Changeset 46297 in vbox for trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

Timestamp:

May 28, 2013 2:38:48 PM (12 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

86045

Message:

VMM: Started HMSVMR0 work. Unify the AMD-V erratum 170 verification code between R0 and R3. General HM tidying.

File:

• trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

@@ -178 +178 @@
 
 /**
+ * Does global AMD-V initialization (called during module initialization).
+ *
+ * @returns VBox status code.
+ */
+VMMR0DECL(int) SVMR0GlobalInit(void)
+{
+    return VINF_SUCCESS;
+}
+
+
+/**
+ * Does global VT-x termination (called during module termination).
+ */
+VMMR0DECL(void) SVMR0GlobalTerm(void)
+{
+}
+
+
+/**
  * Does Ring-0 per VM AMD-V init.
  *
@@ -199 +218 @@
     ASMMemFill32(pVM->hm.s.svm.pvIOBitmap, 3 << PAGE_SHIFT, 0xffffffff);
 
-    /*
-     * Erratum 170 which requires a forced TLB flush for each world switch:
-     * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
-     *
-     * All BH-G1/2 and DH-G1/2 models include a fix:
-     * Athlon X2:   0x6b 1/2
-     *              0x68 1/2
-     * Athlon 64:   0x7f 1
-     *              0x6f 2
-     * Sempron:     0x7f 1/2
-     *              0x6f 2
-     *              0x6c 2
-     *              0x7c 2
-     * Turion 64:   0x68 2
-     */
-    uint32_t u32Dummy;
-    uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
-    ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
-    u32BaseFamily = (u32Version >> 8) & 0xf;
-    u32Family     = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
-    u32Model      = ((u32Version >> 4) & 0xf);
-    u32Model      = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
-    u32Stepping   = u32Version & 0xf;
-    if (    u32Family == 0xf
-        &&  !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) &&  u32Stepping >= 1)
-        &&  !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) &&  u32Stepping >= 2))
+    /* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch. */
+    uint32_t u32Family;
+    uint32_t u32Model;
+    uint32_t u32Stepping;
+    if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
     {
         Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));