Changeset 41727 in vbox for trunk/include/VBox/dis.h
- Timestamp:
- Jun 14, 2012 10:49:03 PM (13 years ago)
- svn:sync-xref-src-repo-rev:
- 78535
- File:
-
- 1 edited
-
trunk/include/VBox/dis.h (modified) (11 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/include/VBox/dis.h
r41706 r41727 192 192 /** @} */ 193 193 194 /** index in {"RAX", "RCX", "RDX", "RBX", "RSP", "RBP", "RSI", "RDI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"} 195 * @{ 196 */ 197 #define USE_REG_RAX 0 198 #define USE_REG_RCX 1 199 #define USE_REG_RDX 2 200 #define USE_REG_RBX 3 201 #define USE_REG_RSP 4 202 #define USE_REG_RBP 5 203 #define USE_REG_RSI 6 204 #define USE_REG_RDI 7 205 #define USE_REG_R8 8 206 #define USE_REG_R9 9 207 #define USE_REG_R10 10 208 #define USE_REG_R11 11 209 #define USE_REG_R12 12 210 #define USE_REG_R13 13 211 #define USE_REG_R14 14 212 #define USE_REG_R15 15 213 /** @} */ 214 215 /** index in {"EAX", "ECX", "EDX", "EBX", "ESP", "EBP", "ESI", "EDI", "R8D", "R9D", "R10D", "R11D", "R12D", "R13D", "R14D", "R15D"} 216 * @{ 217 */ 218 #define USE_REG_EAX 0 219 #define USE_REG_ECX 1 220 #define USE_REG_EDX 2 221 #define USE_REG_EBX 3 222 #define USE_REG_ESP 4 223 #define USE_REG_EBP 5 224 #define USE_REG_ESI 6 225 #define USE_REG_EDI 7 226 #define USE_REG_R8D 8 227 #define USE_REG_R9D 9 228 #define USE_REG_R10D 10 229 #define USE_REG_R11D 11 230 #define USE_REG_R12D 12 231 #define USE_REG_R13D 13 232 #define USE_REG_R14D 14 233 #define USE_REG_R15D 15 234 /** @} */ 235 236 /** index in {"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI", "R8W", "R9W", "R10W", "R11W", "R12W", "R13W", "R14W", "R15W"} 237 * @{ 238 */ 239 #define USE_REG_AX 0 240 #define USE_REG_CX 1 241 #define USE_REG_DX 2 242 #define USE_REG_BX 3 243 #define USE_REG_SP 4 244 #define USE_REG_BP 5 245 #define USE_REG_SI 6 246 #define USE_REG_DI 7 247 #define USE_REG_R8W 8 248 #define USE_REG_R9W 9 249 #define USE_REG_R10W 10 250 #define USE_REG_R11W 11 251 #define USE_REG_R12W 12 252 #define USE_REG_R13W 13 253 #define USE_REG_R14W 14 254 #define USE_REG_R15W 15 255 /** @} */ 256 257 /** index in {"AL", "CL", "DL", "BL", "AH", "CH", "DH", "BH", "R8B", "R9B", "R10B", "R11B", "R12B", "R13B", "R14B", "R15B", "SPL", "BPL", "SIL", "DIL"} 258 * @{ 259 */ 260 #define USE_REG_AL 0 261 #define USE_REG_CL 1 262 #define USE_REG_DL 2 263 #define USE_REG_BL 3 264 #define USE_REG_AH 4 265 #define USE_REG_CH 5 266 #define USE_REG_DH 6 267 #define USE_REG_BH 7 268 #define USE_REG_R8B 8 269 #define USE_REG_R9B 9 270 #define USE_REG_R10B 10 271 #define USE_REG_R11B 11 272 #define USE_REG_R12B 12 273 #define USE_REG_R13B 13 274 #define USE_REG_R14B 14 275 #define USE_REG_R15B 15 276 #define USE_REG_SPL 16 277 #define USE_REG_BPL 17 278 #define USE_REG_SIL 18 279 #define USE_REG_DIL 19 280 281 /** @} */ 282 283 /** index in {ES, CS, SS, DS, FS, GS} 194 /** @name 64-bit general register indexes. 195 * This matches the AMD64 register encoding. It is found used in 196 * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen. 197 * @note Safe to assume same values as the 16-bit and 32-bit general registers. 198 * @{ 199 */ 200 #define DISGREG_RAX UINT8_C(0) 201 #define DISGREG_RCX UINT8_C(1) 202 #define DISGREG_RDX UINT8_C(2) 203 #define DISGREG_RBX UINT8_C(3) 204 #define DISGREG_RSP UINT8_C(4) 205 #define DISGREG_RBP UINT8_C(5) 206 #define DISGREG_RSI UINT8_C(6) 207 #define DISGREG_RDI UINT8_C(7) 208 #define DISGREG_R8 UINT8_C(8) 209 #define DISGREG_R9 UINT8_C(9) 210 #define DISGREG_R10 UINT8_C(10) 211 #define DISGREG_R11 UINT8_C(11) 212 #define DISGREG_R12 UINT8_C(12) 213 #define DISGREG_R13 UINT8_C(13) 214 #define DISGREG_R14 UINT8_C(14) 215 #define DISGREG_R15 UINT8_C(15) 216 /** @} */ 217 218 /** @name 32-bit general register indexes. 219 * This matches the AMD64 register encoding. It is found used in 220 * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen. 221 * @note Safe to assume same values as the 16-bit and 64-bit general registers. 222 * @{ 223 */ 224 #define DISGREG_EAX UINT8_C(0) 225 #define DISGREG_ECX UINT8_C(1) 226 #define DISGREG_EDX UINT8_C(2) 227 #define DISGREG_EBX UINT8_C(3) 228 #define DISGREG_ESP UINT8_C(4) 229 #define DISGREG_EBP UINT8_C(5) 230 #define DISGREG_ESI UINT8_C(6) 231 #define DISGREG_EDI UINT8_C(7) 232 #define DISGREG_R8D UINT8_C(8) 233 #define DISGREG_R9D UINT8_C(9) 234 #define DISGREG_R10D UINT8_C(10) 235 #define DISGREG_R11D UINT8_C(11) 236 #define DISGREG_R12D UINT8_C(12) 237 #define DISGREG_R13D UINT8_C(13) 238 #define DISGREG_R14D UINT8_C(14) 239 #define DISGREG_R15D UINT8_C(15) 240 /** @} */ 241 242 /** @name 16-bit general register indexes. 243 * This matches the AMD64 register encoding. It is found used in 244 * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen. 245 * @note Safe to assume same values as the 32-bit and 64-bit general registers. 246 * @{ 247 */ 248 #define DISGREG_AX UINT8_C(0) 249 #define DISGREG_CX UINT8_C(1) 250 #define DISGREG_DX UINT8_C(2) 251 #define DISGREG_BX UINT8_C(3) 252 #define DISGREG_SP UINT8_C(4) 253 #define DISGREG_BP UINT8_C(5) 254 #define DISGREG_SI UINT8_C(6) 255 #define DISGREG_DI UINT8_C(7) 256 #define DISGREG_R8W UINT8_C(8) 257 #define DISGREG_R9W UINT8_C(9) 258 #define DISGREG_R10W UINT8_C(10) 259 #define DISGREG_R11W UINT8_C(11) 260 #define DISGREG_R12W UINT8_C(12) 261 #define DISGREG_R13W UINT8_C(13) 262 #define DISGREG_R14W UINT8_C(14) 263 #define DISGREG_R15W UINT8_C(15) 264 /** @} */ 265 266 /** @name 8-bit general register indexes. 267 * This mostly (?) matches the AMD64 register encoding. It is found used in 268 * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen. 269 * @{ 270 */ 271 #define DISGREG_AL UINT8_C(0) 272 #define DISGREG_CL UINT8_C(1) 273 #define DISGREG_DL UINT8_C(2) 274 #define DISGREG_BL UINT8_C(3) 275 #define DISGREG_AH UINT8_C(4) 276 #define DISGREG_CH UINT8_C(5) 277 #define DISGREG_DH UINT8_C(6) 278 #define DISGREG_BH UINT8_C(7) 279 #define DISGREG_R8B UINT8_C(8) 280 #define DISGREG_R9B UINT8_C(9) 281 #define DISGREG_R10B UINT8_C(10) 282 #define DISGREG_R11B UINT8_C(11) 283 #define DISGREG_R12B UINT8_C(12) 284 #define DISGREG_R13B UINT8_C(13) 285 #define DISGREG_R14B UINT8_C(14) 286 #define DISGREG_R15B UINT8_C(15) 287 #define DISGREG_SPL UINT8_C(16) 288 #define DISGREG_BPL UINT8_C(17) 289 #define DISGREG_SIL UINT8_C(18) 290 #define DISGREG_DIL UINT8_C(19) 291 /** @} */ 292 293 /** @name Segment registerindexes. 294 * This matches the AMD64 register encoding. It is found used in 295 * DISOPPARAM::base.reg_seg. 284 296 * @{ 285 297 */ 286 298 typedef enum 287 299 { 288 DIS _SELREG_ES = 0,289 DIS _SELREG_CS = 1,290 DIS _SELREG_SS = 2,291 DIS _SELREG_DS = 3,292 DIS _SELREG_FS = 4,293 DIS _SELREG_GS = 5,300 DISSELREG_ES = 0, 301 DISSELREG_CS = 1, 302 DISSELREG_SS = 2, 303 DISSELREG_DS = 3, 304 DISSELREG_FS = 4, 305 DISSELREG_GS = 5, 294 306 /** The usual 32-bit paranoia. */ 295 307 DIS_SEGREG_32BIT_HACK = 0x7fffffff 296 } DIS _SELREG;308 } DISSELREG; 297 309 /** @} */ 298 310 … … 410 422 union 411 423 { 424 /** DISGREG_XXX. */ 412 425 uint8_t reg_gen; 413 426 /** ST(0) - ST(7) */ … … 417 430 /** XMM0 - XMM7 */ 418 431 uint8_t reg_xmm; 419 /** {ES, CS, SS, DS, FS, GS} (DIS _SELREG). */432 /** {ES, CS, SS, DS, FS, GS} (DISSELREG). */ 420 433 uint8_t reg_seg; 421 434 /** TR0-TR7 (?) */ … … 428 441 union 429 442 { 443 /** DISGREG_XXX. */ 430 444 uint8_t reg_gen; 431 445 } index; … … 476 490 477 491 /* off: 0x060 (96) */ 478 /** ModRM fields. */ 492 /** ModRM fields. */ 479 493 union 480 494 { … … 502 516 unsigned u; 503 517 } SIB; 504 int32_t i32SibDisp; 518 int32_t i32SibDisp; 505 519 506 520 /* off: 0x06c (108) */ 507 521 /** The CPU mode (DISCPUMODE). */ 508 uint8_t mode; 522 uint8_t mode; 509 523 /** The addressing mode (DISCPUMODE). */ 510 524 uint8_t addrmode; … … 512 526 uint8_t opmode; 513 527 /** Per instruction prefix settings. */ 514 uint8_t prefix; 528 uint8_t prefix; 515 529 /* off: 0x070 (112) */ 516 530 /** REX prefix value (64 bits only). */ 517 uint8_t prefix_rex; 518 /** Segment prefix value (DIS _SELREG). */531 uint8_t prefix_rex; 532 /** Segment prefix value (DISSELREG). */ 519 533 uint8_t idxSegPrefix; 520 534 /** Last prefix byte (for SSE2 extension tables). */ … … 524 538 /* off: 0x074 (116) */ 525 539 /** The size of the prefix bytes. */ 526 uint8_t cbPrefix; 540 uint8_t cbPrefix; 527 541 /** The instruction size. */ 528 542 uint8_t opsize; … … 567 581 568 582 569 /** 570 * Opcode descriptor. 571 */ 583 /** 584 * Opcode descriptor. 585 */ 572 586 typedef struct DISOPCODE 573 587 { … … 603 617 604 618 DISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, PDISOPPARAM pParam); 605 DISDECL(DIS _SELREG) DISDetectSegReg(PDISCPUSTATE pCpu, PDISOPPARAM pParam);619 DISDECL(DISSELREG) DISDetectSegReg(PDISCPUSTATE pCpu, PDISOPPARAM pParam); 606 620 DISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu); 607 621 … … 613 627 DISDECL(int) DISFetchReg32(PCCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal); 614 628 DISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal); 615 DISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DIS _SELREG sel, RTSEL *pVal);616 DISDECL(int) DISFetchRegSegEx(PCCPUMCTXCORE pCtx, DIS _SELREG sel, RTSEL *pVal, PCPUMSELREGHID *ppSelHidReg);629 DISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal); 630 DISDECL(int) DISFetchRegSegEx(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal, PCPUMSELREGHID *ppSelHidReg); 617 631 DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8); 618 632 DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg32, uint16_t val16); 619 633 DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32); 620 634 DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64); 621 DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DIS _SELREG sel, RTSEL val);635 DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DISSELREG sel, RTSEL val); 622 636 DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg); 623 637 DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg);
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