helper.c@ 12105

Last change on this file since 12105 was 11982, checked in by vboxsync, 17 years ago
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1	/*
2	* i386 helpers
3	*
4	* Copyright (c) 2003 Fabrice Bellard
5	*
6	* This library is free software; you can redistribute it and/or
7	* modify it under the terms of the GNU Lesser General Public
8	* License as published by the Free Software Foundation; either
9	* version 2 of the License, or (at your option) any later version.
10	*
11	* This library is distributed in the hope that it will be useful,
12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14	* Lesser General Public License for more details.
15	*
16	* You should have received a copy of the GNU Lesser General Public
17	* License along with this library; if not, write to the Free Software
18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19	*/
20
21	/*
22	* Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
23	* other than GPL or LGPL is available it will apply instead, Sun elects to use only
24	* the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
25	* a choice of LGPL license versions is made available with the language indicating
26	* that LGPLv2 or any later version may be used, or where a choice of which version
27	* of the LGPL is applied is otherwise unspecified.
28	*/
29	#ifdef VBOX
30	# include <VBox/err.h>
31	#endif
32	#include "exec.h"
33
34	//#define DEBUG_PCALL
35
36	#if 0
37	#define raise_exception_err(a, b)\
38	do {\
39	if (logfile)\
40	fprintf(logfile, "raise_exception line=%d\n", __LINE__);\
41	(raise_exception_err)(a, b);\
42	} while (0)
43	#endif
44
45	const uint8_t parity_table[256] = {
46	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
47	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
48	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
49	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
50	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
51	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
52	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
53	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
54	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
55	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
56	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
57	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
58	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
59	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
60	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
61	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
62	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
63	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
64	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
65	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
66	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
67	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
68	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
69	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
70	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
71	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
72	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
73	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
74	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
75	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
76	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
77	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
78	};
79
80	/* modulo 17 table */
81	const uint8_t rclw_table[32] = {
82	0, 1, 2, 3, 4, 5, 6, 7,
83	8, 9,10,11,12,13,14,15,
84	16, 0, 1, 2, 3, 4, 5, 6,
85	7, 8, 9,10,11,12,13,14,
86	};
87
88	/* modulo 9 table */
89	const uint8_t rclb_table[32] = {
90	0, 1, 2, 3, 4, 5, 6, 7,
91	8, 0, 1, 2, 3, 4, 5, 6,
92	7, 8, 0, 1, 2, 3, 4, 5,
93	6, 7, 8, 0, 1, 2, 3, 4,
94	};
95
96	const CPU86_LDouble f15rk[7] =
97	{
98	0.00000000000000000000L,
99	1.00000000000000000000L,
100	3.14159265358979323851L, /pi/
101	0.30102999566398119523L, /lg2/
102	0.69314718055994530943L, /ln2/
103	1.44269504088896340739L, /l2e/
104	3.32192809488736234781L, /l2t/
105	};
106
107	/* thread support */
108
109	spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
110
111	void cpu_lock(void)
112	{
113	spin_lock(&global_cpu_lock);
114	}
115
116	void cpu_unlock(void)
117	{
118	spin_unlock(&global_cpu_lock);
119	}
120
121	void cpu_loop_exit(void)
122	{
123	/* NOTE: the register at this point must be saved by hand because
124	longjmp restore them */
125	regs_to_env();
126	longjmp(env->jmp_env, 1);
127	}
128
129	/* return non zero if error */
130	static inline int load_segment(uint32_t e1_ptr, uint32_t e2_ptr,
131	int selector)
132	{
133	SegmentCache *dt;
134	int index;
135	target_ulong ptr;
136
137	if (selector & 0x4)
138	dt = &env->ldt;
139	else
140	dt = &env->gdt;
141	index = selector & ~7;
142	if ((index + 7) > dt->limit)
143	return -1;
144	ptr = dt->base + index;
145	*e1_ptr = ldl_kernel(ptr);
146	*e2_ptr = ldl_kernel(ptr + 4);
147	return 0;
148	}
149
150	static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2)
151	{
152	unsigned int limit;
153	limit = (e1 & 0xffff) \| (e2 & 0x000f0000);
154	if (e2 & DESC_G_MASK)
155	limit = (limit << 12) \| 0xfff;
156	return limit;
157	}
158
159	static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2)
160	{
161	return ((e1 >> 16) \| ((e2 & 0xff) << 16) \| (e2 & 0xff000000));
162	}
163
164	static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1, uint32_t e2)
165	{
166	sc->base = get_seg_base(e1, e2);
167	sc->limit = get_seg_limit(e1, e2);
168	sc->flags = e2;
169	}
170
171	/* init the segment cache in vm86 mode. */
172	static inline void load_seg_vm(int seg, int selector)
173	{
174	selector &= 0xffff;
175	cpu_x86_load_seg_cache(env, seg, selector,
176	(selector << 4), 0xffff, 0);
177	}
178
179	static inline void get_ss_esp_from_tss(uint32_t *ss_ptr,
180	uint32_t *esp_ptr, int dpl)
181	{
182	int type, index, shift;
183
184	#if 0
185	{
186	int i;
187	printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit);
188	for(i=0;i<env->tr.limit;i++) {
189	printf("%02x ", env->tr.base[i]);
190	if ((i & 7) == 7) printf("\n");
191	}
192	printf("\n");
193	}
194	#endif
195
196	if (!(env->tr.flags & DESC_P_MASK))
197	cpu_abort(env, "invalid tss");
198	type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
199	if ((type & 7) != 1)
200	cpu_abort(env, "invalid tss type %d", type);
201	shift = type >> 3;
202	index = (dpl * 4 + 2) << shift;
203	if (index + (4 << shift) - 1 > env->tr.limit)
204	raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
205	if (shift == 0) {
206	*esp_ptr = lduw_kernel(env->tr.base + index);
207	*ss_ptr = lduw_kernel(env->tr.base + index + 2);
208	} else {
209	*esp_ptr = ldl_kernel(env->tr.base + index);
210	*ss_ptr = lduw_kernel(env->tr.base + index + 4);
211	}
212	}
213
214	/* XXX: merge with load_seg() */
215	static void tss_load_seg(int seg_reg, int selector)
216	{
217	uint32_t e1, e2;
218	int rpl, dpl, cpl;
219
220	if ((selector & 0xfffc) != 0) {
221	if (load_segment(&e1, &e2, selector) != 0)
222	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
223	if (!(e2 & DESC_S_MASK))
224	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
225	rpl = selector & 3;
226	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
227	cpl = env->hflags & HF_CPL_MASK;
228	if (seg_reg == R_CS) {
229	if (!(e2 & DESC_CS_MASK))
230	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
231	/* XXX: is it correct ? */
232	if (dpl != rpl)
233	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
234	if ((e2 & DESC_C_MASK) && dpl > rpl)
235	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
236	} else if (seg_reg == R_SS) {
237	/* SS must be writable data */
238	if ((e2 & DESC_CS_MASK) \|\| !(e2 & DESC_W_MASK))
239	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
240	if (dpl != cpl \|\| dpl != rpl)
241	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
242	} else {
243	/* not readable code */
244	if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK))
245	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
246	/* if data or non conforming code, checks the rights */
247	if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) {
248	if (dpl < cpl \|\| dpl < rpl)
249	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
250	}
251	}
252	if (!(e2 & DESC_P_MASK))
253	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
254	cpu_x86_load_seg_cache(env, seg_reg, selector,
255	get_seg_base(e1, e2),
256	get_seg_limit(e1, e2),
257	e2);
258	} else {
259	if (seg_reg == R_SS \|\| seg_reg == R_CS)
260	raise_exception_err(EXCP0A_TSS, selector & 0xfffc);
261	}
262	}
263
264	#define SWITCH_TSS_JMP 0
265	#define SWITCH_TSS_IRET 1
266	#define SWITCH_TSS_CALL 2
267
268	/* XXX: restore CPU state in registers (PowerPC case) */
269	static void switch_tss(int tss_selector,
270	uint32_t e1, uint32_t e2, int source,
271	uint32_t next_eip)
272	{
273	int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;
274	target_ulong tss_base;
275	uint32_t new_regs[8], new_segs[6];
276	uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap;
277	uint32_t old_eflags, eflags_mask;
278	SegmentCache *dt;
279	int index;
280	target_ulong ptr;
281
282	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
283	#ifdef DEBUG_PCALL
284	if (loglevel & CPU_LOG_PCALL)
285	fprintf(logfile, "switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type, source);
286	#endif
287
288	#if defined(VBOX) && defined(DEBUG)
289	printf("switch_tss %x %x %x %d %08x\n", tss_selector, e1, e2, source, next_eip);
290	#endif
291
292	/* if task gate, we read the TSS segment and we load it */
293	if (type == 5) {
294	if (!(e2 & DESC_P_MASK))
295	raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
296	tss_selector = e1 >> 16;
297	if (tss_selector & 4)
298	raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
299	if (load_segment(&e1, &e2, tss_selector) != 0)
300	raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
301	if (e2 & DESC_S_MASK)
302	raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
303	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
304	if ((type & 7) != 1)
305	raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);
306	}
307
308	if (!(e2 & DESC_P_MASK))
309	raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);
310
311	if (type & 8)
312	tss_limit_max = 103;
313	else
314	tss_limit_max = 43;
315	tss_limit = get_seg_limit(e1, e2);
316	tss_base = get_seg_base(e1, e2);
317	if ((tss_selector & 4) != 0 \|\|
318	tss_limit < tss_limit_max)
319	raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
320	old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
321	if (old_type & 8)
322	old_tss_limit_max = 103;
323	else
324	old_tss_limit_max = 43;
325
326	/* read all the registers from the new TSS */
327	if (type & 8) {
328	/* 32 bit */
329	new_cr3 = ldl_kernel(tss_base + 0x1c);
330	new_eip = ldl_kernel(tss_base + 0x20);
331	new_eflags = ldl_kernel(tss_base + 0x24);
332	for(i = 0; i < 8; i++)
333	new_regs[i] = ldl_kernel(tss_base + (0x28 + i * 4));
334	for(i = 0; i < 6; i++)
335	new_segs[i] = lduw_kernel(tss_base + (0x48 + i * 4));
336	new_ldt = lduw_kernel(tss_base + 0x60);
337	new_trap = ldl_kernel(tss_base + 0x64);
338	} else {
339	/* 16 bit */
340	new_cr3 = 0;
341	new_eip = lduw_kernel(tss_base + 0x0e);
342	new_eflags = lduw_kernel(tss_base + 0x10);
343	for(i = 0; i < 8; i++)
344	new_regs[i] = lduw_kernel(tss_base + (0x12 + i * 2)) \| 0xffff0000;
345	for(i = 0; i < 4; i++)
346	new_segs[i] = lduw_kernel(tss_base + (0x22 + i * 4));
347	new_ldt = lduw_kernel(tss_base + 0x2a);
348	new_segs[R_FS] = 0;
349	new_segs[R_GS] = 0;
350	new_trap = 0;
351	}
352
353	/* NOTE: we must avoid memory exceptions during the task switch,
354	so we make dummy accesses before */
355	/* XXX: it can still fail in some cases, so a bigger hack is
356	necessary to valid the TLB after having done the accesses */
357
358	v1 = ldub_kernel(env->tr.base);
359	v2 = ldub_kernel(env->tr.base + old_tss_limit_max);
360	stb_kernel(env->tr.base, v1);
361	stb_kernel(env->tr.base + old_tss_limit_max, v2);
362
363	/* clear busy bit (it is restartable) */
364	if (source == SWITCH_TSS_JMP \|\| source == SWITCH_TSS_IRET) {
365	target_ulong ptr;
366	uint32_t e2;
367	ptr = env->gdt.base + (env->tr.selector & ~7);
368	e2 = ldl_kernel(ptr + 4);
369	e2 &= ~DESC_TSS_BUSY_MASK;
370	stl_kernel(ptr + 4, e2);
371	}
372	old_eflags = compute_eflags();
373	if (source == SWITCH_TSS_IRET)
374	old_eflags &= ~NT_MASK;
375
376	/* save the current state in the old TSS */
377	if (type & 8) {
378	/* 32 bit */
379	stl_kernel(env->tr.base + 0x20, next_eip);
380	stl_kernel(env->tr.base + 0x24, old_eflags);
381	stl_kernel(env->tr.base + (0x28 + 0 * 4), EAX);
382	stl_kernel(env->tr.base + (0x28 + 1 * 4), ECX);
383	stl_kernel(env->tr.base + (0x28 + 2 * 4), EDX);
384	stl_kernel(env->tr.base + (0x28 + 3 * 4), EBX);
385	stl_kernel(env->tr.base + (0x28 + 4 * 4), ESP);
386	stl_kernel(env->tr.base + (0x28 + 5 * 4), EBP);
387	stl_kernel(env->tr.base + (0x28 + 6 * 4), ESI);
388	stl_kernel(env->tr.base + (0x28 + 7 * 4), EDI);
389	for(i = 0; i < 6; i++)
390	stw_kernel(env->tr.base + (0x48 + i * 4), env->segs[i].selector);
391	#if defined(VBOX) && defined(DEBUG)
392	printf("TSS 32 bits switch\n");
393	printf("Saving CS=%08X\n", env->segs[R_CS].selector);
394	#endif
395	} else {
396	/* 16 bit */
397	stw_kernel(env->tr.base + 0x0e, next_eip);
398	stw_kernel(env->tr.base + 0x10, old_eflags);
399	stw_kernel(env->tr.base + (0x12 + 0 * 2), EAX);
400	stw_kernel(env->tr.base + (0x12 + 1 * 2), ECX);
401	stw_kernel(env->tr.base + (0x12 + 2 * 2), EDX);
402	stw_kernel(env->tr.base + (0x12 + 3 * 2), EBX);
403	stw_kernel(env->tr.base + (0x12 + 4 * 2), ESP);
404	stw_kernel(env->tr.base + (0x12 + 5 * 2), EBP);
405	stw_kernel(env->tr.base + (0x12 + 6 * 2), ESI);
406	stw_kernel(env->tr.base + (0x12 + 7 * 2), EDI);
407	for(i = 0; i < 4; i++)
408	stw_kernel(env->tr.base + (0x22 + i * 4), env->segs[i].selector);
409	}
410
411	/* now if an exception occurs, it will occurs in the next task
412	context */
413
414	if (source == SWITCH_TSS_CALL) {
415	stw_kernel(tss_base, env->tr.selector);
416	new_eflags \|= NT_MASK;
417	}
418
419	/* set busy bit */
420	if (source == SWITCH_TSS_JMP \|\| source == SWITCH_TSS_CALL) {
421	target_ulong ptr;
422	uint32_t e2;
423	ptr = env->gdt.base + (tss_selector & ~7);
424	e2 = ldl_kernel(ptr + 4);
425	e2 \|= DESC_TSS_BUSY_MASK;
426	stl_kernel(ptr + 4, e2);
427	}
428
429	/* set the new CPU state */
430	/* from this point, any exception which occurs can give problems */
431	env->cr[0] \|= CR0_TS_MASK;
432	env->hflags \|= HF_TS_MASK;
433	env->tr.selector = tss_selector;
434	env->tr.base = tss_base;
435	env->tr.limit = tss_limit;
436	env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK;
437
438	if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) {
439	cpu_x86_update_cr3(env, new_cr3);
440	}
441
442	/* load all registers without an exception, then reload them with
443	possible exception */
444	env->eip = new_eip;
445	eflags_mask = TF_MASK \| AC_MASK \| ID_MASK \|
446	IF_MASK \| IOPL_MASK \| VM_MASK \| RF_MASK \| NT_MASK;
447	if (!(type & 8))
448	eflags_mask &= 0xffff;
449	load_eflags(new_eflags, eflags_mask);
450	/* XXX: what to do in 16 bit case ? */
451	EAX = new_regs[0];
452	ECX = new_regs[1];
453	EDX = new_regs[2];
454	EBX = new_regs[3];
455	ESP = new_regs[4];
456	EBP = new_regs[5];
457	ESI = new_regs[6];
458	EDI = new_regs[7];
459	if (new_eflags & VM_MASK) {
460	for(i = 0; i < 6; i++)
461	load_seg_vm(i, new_segs[i]);
462	/* in vm86, CPL is always 3 */
463	cpu_x86_set_cpl(env, 3);
464	} else {
465	/* CPL is set the RPL of CS */
466	cpu_x86_set_cpl(env, new_segs[R_CS] & 3);
467	/* first just selectors as the rest may trigger exceptions */
468	for(i = 0; i < 6; i++)
469	cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0);
470	}
471
472	env->ldt.selector = new_ldt & ~4;
473	env->ldt.base = 0;
474	env->ldt.limit = 0;
475	env->ldt.flags = 0;
476
477	/* load the LDT */
478	if (new_ldt & 4)
479	raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
480
481	if ((new_ldt & 0xfffc) != 0) {
482	dt = &env->gdt;
483	index = new_ldt & ~7;
484	if ((index + 7) > dt->limit)
485	raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
486	ptr = dt->base + index;
487	e1 = ldl_kernel(ptr);
488	e2 = ldl_kernel(ptr + 4);
489	if ((e2 & DESC_S_MASK) \|\| ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
490	raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
491	if (!(e2 & DESC_P_MASK))
492	raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);
493	load_seg_cache_raw_dt(&env->ldt, e1, e2);
494	}
495
496	/* load the segments */
497	if (!(new_eflags & VM_MASK)) {
498	tss_load_seg(R_CS, new_segs[R_CS]);
499	tss_load_seg(R_SS, new_segs[R_SS]);
500	tss_load_seg(R_ES, new_segs[R_ES]);
501	tss_load_seg(R_DS, new_segs[R_DS]);
502	tss_load_seg(R_FS, new_segs[R_FS]);
503	tss_load_seg(R_GS, new_segs[R_GS]);
504	}
505
506	/* check that EIP is in the CS segment limits */
507	if (new_eip > env->segs[R_CS].limit) {
508	/* XXX: different exception if CALL ? */
509	raise_exception_err(EXCP0D_GPF, 0);
510	}
511	}
512
513	/* check if Port I/O is allowed in TSS */
514	static inline void check_io(int addr, int size)
515	{
516	int io_offset, val, mask;
517
518	/* TSS must be a valid 32 bit one */
519	if (!(env->tr.flags & DESC_P_MASK) \|\|
520	((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 \|\|
521	env->tr.limit < 103)
522	goto fail;
523	io_offset = lduw_kernel(env->tr.base + 0x66);
524	io_offset += (addr >> 3);
525	/* Note: the check needs two bytes */
526	if ((io_offset + 1) > env->tr.limit)
527	goto fail;
528	val = lduw_kernel(env->tr.base + io_offset);
529	val >>= (addr & 7);
530	mask = (1 << size) - 1;
531	/* all bits must be zero to allow the I/O */
532	if ((val & mask) != 0) {
533	fail:
534	raise_exception_err(EXCP0D_GPF, 0);
535	}
536	}
537
538	void check_iob_T0(void)
539	{
540	check_io(T0, 1);
541	}
542
543	void check_iow_T0(void)
544	{
545	check_io(T0, 2);
546	}
547
548	void check_iol_T0(void)
549	{
550	check_io(T0, 4);
551	}
552
553	void check_iob_DX(void)
554	{
555	check_io(EDX & 0xffff, 1);
556	}
557
558	void check_iow_DX(void)
559	{
560	check_io(EDX & 0xffff, 2);
561	}
562
563	void check_iol_DX(void)
564	{
565	check_io(EDX & 0xffff, 4);
566	}
567
568	static inline unsigned int get_sp_mask(unsigned int e2)
569	{
570	if (e2 & DESC_B_MASK)
571	return 0xffffffff;
572	else
573	return 0xffff;
574	}
575
576	#ifdef TARGET_X86_64
577	#define SET_ESP(val, sp_mask)\
578	do {\
579	if ((sp_mask) == 0xffff)\
580	ESP = (ESP & ~0xffff) \| ((val) & 0xffff);\
581	else if ((sp_mask) == 0xffffffffLL)\
582	ESP = (uint32_t)(val);\
583	else\
584	ESP = (val);\
585	} while (0)
586	#else
587	#define SET_ESP(val, sp_mask) ESP = (ESP & ~(sp_mask)) \| ((val) & (sp_mask))
588	#endif
589
590	/* XXX: add a is_user flag to have proper security support */
591	#define PUSHW(ssp, sp, sp_mask, val)\
592	{\
593	sp -= 2;\
594	stw_kernel((ssp) + (sp & (sp_mask)), (val));\
595	}
596
597	#define PUSHL(ssp, sp, sp_mask, val)\
598	{\
599	sp -= 4;\
600	stl_kernel((ssp) + (sp & (sp_mask)), (val));\
601	}
602
603	#define POPW(ssp, sp, sp_mask, val)\
604	{\
605	val = lduw_kernel((ssp) + (sp & (sp_mask)));\
606	sp += 2;\
607	}
608
609	#define POPL(ssp, sp, sp_mask, val)\
610	{\
611	val = (uint32_t)ldl_kernel((ssp) + (sp & (sp_mask)));\
612	sp += 4;\
613	}
614
615	/* protected mode interrupt */
616	static void do_interrupt_protected(int intno, int is_int, int error_code,
617	unsigned int next_eip, int is_hw)
618	{
619	SegmentCache *dt;
620	target_ulong ptr, ssp;
621	int type, dpl, selector, ss_dpl, cpl;
622	int has_error_code, new_stack, shift;
623	uint32_t e1, e2, offset, ss, esp, ss_e1, ss_e2;
624	uint32_t old_eip, sp_mask;
625
626	#ifdef VBOX
627	if (remR3NotifyTrap(env, intno, error_code, next_eip) != VINF_SUCCESS)
628	cpu_loop_exit();
629	#endif
630
631	has_error_code = 0;
632	if (!is_int && !is_hw) {
633	switch(intno) {
634	case 8:
635	case 10:
636	case 11:
637	case 12:
638	case 13:
639	case 14:
640	case 17:
641	has_error_code = 1;
642	break;
643	}
644	}
645	if (is_int)
646	old_eip = next_eip;
647	else
648	old_eip = env->eip;
649
650	dt = &env->idt;
651	if (intno * 8 + 7 > dt->limit)
652	raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
653	ptr = dt->base + intno * 8;
654	e1 = ldl_kernel(ptr);
655	e2 = ldl_kernel(ptr + 4);
656	/* check gate type */
657	type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
658	switch(type) {
659	case 5: /* task gate */
660	/* must do that check here to return the correct error code */
661	if (!(e2 & DESC_P_MASK))
662	raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
663	switch_tss(intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
664	if (has_error_code) {
665	int type;
666	uint32_t mask;
667	/* push the error code */
668	type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
669	shift = type >> 3;
670	if (env->segs[R_SS].flags & DESC_B_MASK)
671	mask = 0xffffffff;
672	else
673	mask = 0xffff;
674	esp = (ESP - (2 << shift)) & mask;
675	ssp = env->segs[R_SS].base + esp;
676	if (shift)
677	stl_kernel(ssp, error_code);
678	else
679	stw_kernel(ssp, error_code);
680	SET_ESP(esp, mask);
681	}
682	return;
683	case 6: /* 286 interrupt gate */
684	case 7: /* 286 trap gate */
685	case 14: /* 386 interrupt gate */
686	case 15: /* 386 trap gate */
687	break;
688	default:
689	raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
690	break;
691	}
692	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
693	cpl = env->hflags & HF_CPL_MASK;
694	/* check privledge if software int */
695	if (is_int && dpl < cpl)
696	raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
697	/* check valid bit */
698	if (!(e2 & DESC_P_MASK))
699	raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);
700	selector = e1 >> 16;
701	offset = (e2 & 0xffff0000) \| (e1 & 0x0000ffff);
702	if ((selector & 0xfffc) == 0)
703	raise_exception_err(EXCP0D_GPF, 0);
704
705	if (load_segment(&e1, &e2, selector) != 0)
706	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
707	if (!(e2 & DESC_S_MASK) \|\| !(e2 & (DESC_CS_MASK)))
708	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
709	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
710	if (dpl > cpl)
711	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
712	if (!(e2 & DESC_P_MASK))
713	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
714	if (!(e2 & DESC_C_MASK) && dpl < cpl) {
715	/* to inner priviledge */
716	get_ss_esp_from_tss(&ss, &esp, dpl);
717	if ((ss & 0xfffc) == 0)
718	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
719	if ((ss & 3) != dpl)
720	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
721	if (load_segment(&ss_e1, &ss_e2, ss) != 0)
722	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
723	ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
724	if (ss_dpl != dpl)
725	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
726	if (!(ss_e2 & DESC_S_MASK) \|\|
727	(ss_e2 & DESC_CS_MASK) \|\|
728	!(ss_e2 & DESC_W_MASK))
729	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
730	if (!(ss_e2 & DESC_P_MASK))
731	#ifdef VBOX /* See page 3-477 of 253666.pdf */
732	raise_exception_err(EXCP0C_STACK, ss & 0xfffc);
733	#else
734	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
735	#endif
736	new_stack = 1;
737	sp_mask = get_sp_mask(ss_e2);
738	ssp = get_seg_base(ss_e1, ss_e2);
739	#if defined(VBOX) && defined(DEBUG)
740	printf("new stack %04X:%08X gate dpl=%d\n", ss, esp, dpl);
741	#endif
742	} else if ((e2 & DESC_C_MASK) \|\| dpl == cpl) {
743	/* to same priviledge */
744	if (env->eflags & VM_MASK)
745	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
746	new_stack = 0;
747	sp_mask = get_sp_mask(env->segs[R_SS].flags);
748	ssp = env->segs[R_SS].base;
749	esp = ESP;
750	dpl = cpl;
751	} else {
752	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
753	new_stack = 0; /* avoid warning */
754	sp_mask = 0; /* avoid warning */
755	ssp = 0; /* avoid warning */
756	esp = 0; /* avoid warning */
757	}
758
759	shift = type >> 3;
760
761	#if 0
762	/* XXX: check that enough room is available */
763	push_size = 6 + (new_stack << 2) + (has_error_code << 1);
764	if (env->eflags & VM_MASK)
765	push_size += 8;
766	push_size <<= shift;
767	#endif
768	if (shift == 1) {
769	if (new_stack) {
770	if (env->eflags & VM_MASK) {
771	PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector);
772	PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector);
773	PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector);
774	PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);
775	}
776	PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
777	PUSHL(ssp, esp, sp_mask, ESP);
778	}
779	PUSHL(ssp, esp, sp_mask, compute_eflags());
780	PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
781	PUSHL(ssp, esp, sp_mask, old_eip);
782	if (has_error_code) {
783	PUSHL(ssp, esp, sp_mask, error_code);
784	}
785	} else {
786	if (new_stack) {
787	if (env->eflags & VM_MASK) {
788	PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector);
789	PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector);
790	PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector);
791	PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);
792	}
793	PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);
794	PUSHW(ssp, esp, sp_mask, ESP);
795	}
796	PUSHW(ssp, esp, sp_mask, compute_eflags());
797	PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
798	PUSHW(ssp, esp, sp_mask, old_eip);
799	if (has_error_code) {
800	PUSHW(ssp, esp, sp_mask, error_code);
801	}
802	}
803
804	if (new_stack) {
805	if (env->eflags & VM_MASK) {
806	cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0);
807	cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0);
808	cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0);
809	cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0);
810	}
811	ss = (ss & ~3) \| dpl;
812	cpu_x86_load_seg_cache(env, R_SS, ss,
813	ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
814	}
815	SET_ESP(esp, sp_mask);
816
817	selector = (selector & ~3) \| dpl;
818	cpu_x86_load_seg_cache(env, R_CS, selector,
819	get_seg_base(e1, e2),
820	get_seg_limit(e1, e2),
821	e2);
822	cpu_x86_set_cpl(env, dpl);
823	env->eip = offset;
824
825	/* interrupt gate clear IF mask */
826	if ((type & 1) == 0) {
827	env->eflags &= ~IF_MASK;
828	}
829	env->eflags &= ~(TF_MASK \| VM_MASK \| RF_MASK \| NT_MASK);
830	}
831
832	#ifdef VBOX
833
834	/* check if VME interrupt redirection is enabled in TSS */
835	static inline bool is_vme_irq_redirected(int intno)
836	{
837	int io_offset, intredir_offset;
838	unsigned char val, mask;
839
840	/* TSS must be a valid 32 bit one */
841	if (!(env->tr.flags & DESC_P_MASK) \|\|
842	((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 \|\|
843	env->tr.limit < 103)
844	goto fail;
845	io_offset = lduw_kernel(env->tr.base + 0x66);
846	/* the virtual interrupt redirection bitmap is located below the io bitmap */
847	intredir_offset = io_offset - 0x20;
848
849	intredir_offset += (intno >> 3);
850	if ((intredir_offset) > env->tr.limit)
851	goto fail;
852
853	val = ldub_kernel(env->tr.base + intredir_offset);
854	mask = 1 << (unsigned char)(intno & 7);
855
856	/* bit set means no redirection. */
857	if ((val & mask) != 0) {
858	return false;
859	}
860	return true;
861
862	fail:
863	raise_exception_err(EXCP0D_GPF, 0);
864	return true;
865	}
866
867	/* V86 mode software interrupt with CR4.VME=1 */
868	static void do_soft_interrupt_vme(int intno, int error_code, unsigned int next_eip)
869	{
870	target_ulong ptr, ssp;
871	int selector;
872	uint32_t offset, esp;
873	uint32_t old_cs, old_eflags;
874	uint32_t iopl;
875
876	iopl = ((env->eflags >> IOPL_SHIFT) & 3);
877
878	if (!is_vme_irq_redirected(intno))
879	{
880	if (iopl == 3)
881	/* normal protected mode handler call */
882	return do_interrupt_protected(intno, 1, error_code, next_eip, 0);
883	else
884	raise_exception_err(EXCP0D_GPF, 0);
885	}
886
887	/* virtual mode idt is at linear address 0 */
888	ptr = 0 + intno * 4;
889	offset = lduw_kernel(ptr);
890	selector = lduw_kernel(ptr + 2);
891	esp = ESP;
892	ssp = env->segs[R_SS].base;
893	old_cs = env->segs[R_CS].selector;
894
895	old_eflags = compute_eflags();
896	if (iopl < 3)
897	{
898	/* copy VIF into IF and set IOPL to 3 */
899	if (env->eflags & VIF_MASK)
900	old_eflags \|= IF_MASK;
901	else
902	old_eflags &= ~IF_MASK;
903
904	old_eflags \|= (3 << IOPL_SHIFT);
905	}
906
907	/* XXX: use SS segment size ? */
908	PUSHW(ssp, esp, 0xffff, old_eflags);
909	PUSHW(ssp, esp, 0xffff, old_cs);
910	PUSHW(ssp, esp, 0xffff, next_eip);
911
912	/* update processor state */
913	ESP = (ESP & ~0xffff) \| (esp & 0xffff);
914	env->eip = offset;
915	env->segs[R_CS].selector = selector;
916	env->segs[R_CS].base = (selector << 4);
917	env->eflags &= ~(TF_MASK \| RF_MASK);
918
919	if (iopl < 3)
920	env->eflags &= ~VIF_MASK;
921	else
922	env->eflags &= ~IF_MASK;
923	}
924	#endif /* VBOX */
925
926	#ifdef TARGET_X86_64
927
928	#define PUSHQ(sp, val)\
929	{\
930	sp -= 8;\
931	stq_kernel(sp, (val));\
932	}
933
934	#define POPQ(sp, val)\
935	{\
936	val = ldq_kernel(sp);\
937	sp += 8;\
938	}
939
940	static inline target_ulong get_rsp_from_tss(int level)
941	{
942	int index;
943
944	#if 0
945	printf("TR: base=" TARGET_FMT_lx " limit=%x\n",
946	env->tr.base, env->tr.limit);
947	#endif
948
949	if (!(env->tr.flags & DESC_P_MASK))
950	cpu_abort(env, "invalid tss");
951	index = 8 * level + 4;
952	if ((index + 7) > env->tr.limit)
953	raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
954	return ldq_kernel(env->tr.base + index);
955	}
956
957	/* 64 bit interrupt */
958	static void do_interrupt64(int intno, int is_int, int error_code,
959	target_ulong next_eip, int is_hw)
960	{
961	SegmentCache *dt;
962	target_ulong ptr;
963	int type, dpl, selector, cpl, ist;
964	int has_error_code, new_stack;
965	uint32_t e1, e2, e3, ss;
966	target_ulong old_eip, esp, offset;
967
968	has_error_code = 0;
969	if (!is_int && !is_hw) {
970	switch(intno) {
971	case 8:
972	case 10:
973	case 11:
974	case 12:
975	case 13:
976	case 14:
977	case 17:
978	has_error_code = 1;
979	break;
980	}
981	}
982	if (is_int)
983	old_eip = next_eip;
984	else
985	old_eip = env->eip;
986
987	dt = &env->idt;
988	if (intno * 16 + 15 > dt->limit)
989	raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
990	ptr = dt->base + intno * 16;
991	e1 = ldl_kernel(ptr);
992	e2 = ldl_kernel(ptr + 4);
993	e3 = ldl_kernel(ptr + 8);
994	/* check gate type */
995	type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
996	switch(type) {
997	case 14: /* 386 interrupt gate */
998	case 15: /* 386 trap gate */
999	break;
1000	default:
1001	raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
1002	break;
1003	}
1004	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1005	cpl = env->hflags & HF_CPL_MASK;
1006	/* check privledge if software int */
1007	if (is_int && dpl < cpl)
1008	raise_exception_err(EXCP0D_GPF, intno * 16 + 2);
1009	/* check valid bit */
1010	if (!(e2 & DESC_P_MASK))
1011	raise_exception_err(EXCP0B_NOSEG, intno * 16 + 2);
1012	selector = e1 >> 16;
1013	offset = ((target_ulong)e3 << 32) \| (e2 & 0xffff0000) \| (e1 & 0x0000ffff);
1014	ist = e2 & 7;
1015	if ((selector & 0xfffc) == 0)
1016	raise_exception_err(EXCP0D_GPF, 0);
1017
1018	if (load_segment(&e1, &e2, selector) != 0)
1019	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1020	if (!(e2 & DESC_S_MASK) \|\| !(e2 & (DESC_CS_MASK)))
1021	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1022	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1023	if (dpl > cpl)
1024	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1025	if (!(e2 & DESC_P_MASK))
1026	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1027	if (!(e2 & DESC_L_MASK) \|\| (e2 & DESC_B_MASK))
1028	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1029	if ((!(e2 & DESC_C_MASK) && dpl < cpl) \|\| ist != 0) {
1030	/* to inner priviledge */
1031	if (ist != 0)
1032	esp = get_rsp_from_tss(ist + 3);
1033	else
1034	esp = get_rsp_from_tss(dpl);
1035	esp &= ~0xfLL; /* align stack */
1036	ss = 0;
1037	new_stack = 1;
1038	} else if ((e2 & DESC_C_MASK) \|\| dpl == cpl) {
1039	/* to same priviledge */
1040	if (env->eflags & VM_MASK)
1041	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1042	new_stack = 0;
1043	if (ist != 0)
1044	esp = get_rsp_from_tss(ist + 3);
1045	else
1046	esp = ESP;
1047	esp &= ~0xfLL; /* align stack */
1048	dpl = cpl;
1049	} else {
1050	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1051	new_stack = 0; /* avoid warning */
1052	esp = 0; /* avoid warning */
1053	}
1054
1055	PUSHQ(esp, env->segs[R_SS].selector);
1056	PUSHQ(esp, ESP);
1057	PUSHQ(esp, compute_eflags());
1058	PUSHQ(esp, env->segs[R_CS].selector);
1059	PUSHQ(esp, old_eip);
1060	if (has_error_code) {
1061	PUSHQ(esp, error_code);
1062	}
1063
1064	if (new_stack) {
1065	ss = 0 \| dpl;
1066	cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);
1067	}
1068	ESP = esp;
1069
1070	selector = (selector & ~3) \| dpl;
1071	cpu_x86_load_seg_cache(env, R_CS, selector,
1072	get_seg_base(e1, e2),
1073	get_seg_limit(e1, e2),
1074	e2);
1075	cpu_x86_set_cpl(env, dpl);
1076	env->eip = offset;
1077
1078	/* interrupt gate clear IF mask */
1079	if ((type & 1) == 0) {
1080	env->eflags &= ~IF_MASK;
1081	}
1082	env->eflags &= ~(TF_MASK \| VM_MASK \| RF_MASK \| NT_MASK);
1083	}
1084	#endif
1085
1086	void helper_syscall(int next_eip_addend)
1087	{
1088	int selector;
1089
1090	if (!(env->efer & MSR_EFER_SCE)) {
1091	raise_exception_err(EXCP06_ILLOP, 0);
1092	}
1093	selector = (env->star >> 32) & 0xffff;
1094	#ifdef TARGET_X86_64
1095	if (env->hflags & HF_LMA_MASK) {
1096	int code64;
1097
1098	ECX = env->eip + next_eip_addend;
1099	env->regs[11] = compute_eflags();
1100
1101	code64 = env->hflags & HF_CS64_MASK;
1102
1103	cpu_x86_set_cpl(env, 0);
1104	cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
1105	0, 0xffffffff,
1106	DESC_G_MASK \| DESC_P_MASK \|
1107	DESC_S_MASK \|
1108	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK \| DESC_L_MASK);
1109	cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
1110	0, 0xffffffff,
1111	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1112	DESC_S_MASK \|
1113	DESC_W_MASK \| DESC_A_MASK);
1114	env->eflags &= ~env->fmask;
1115	if (code64)
1116	env->eip = env->lstar;
1117	else
1118	env->eip = env->cstar;
1119	} else
1120	#endif
1121	{
1122	ECX = (uint32_t)(env->eip + next_eip_addend);
1123
1124	cpu_x86_set_cpl(env, 0);
1125	cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
1126	0, 0xffffffff,
1127	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1128	DESC_S_MASK \|
1129	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK);
1130	cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
1131	0, 0xffffffff,
1132	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1133	DESC_S_MASK \|
1134	DESC_W_MASK \| DESC_A_MASK);
1135	env->eflags &= ~(IF_MASK \| RF_MASK \| VM_MASK);
1136	env->eip = (uint32_t)env->star;
1137	}
1138	}
1139
1140	void helper_sysret(int dflag)
1141	{
1142	int cpl, selector;
1143
1144	if (!(env->efer & MSR_EFER_SCE)) {
1145	raise_exception_err(EXCP06_ILLOP, 0);
1146	}
1147	cpl = env->hflags & HF_CPL_MASK;
1148	if (!(env->cr[0] & CR0_PE_MASK) \|\| cpl != 0) {
1149	raise_exception_err(EXCP0D_GPF, 0);
1150	}
1151	selector = (env->star >> 48) & 0xffff;
1152	#ifdef TARGET_X86_64
1153	if (env->hflags & HF_LMA_MASK) {
1154	if (dflag == 2) {
1155	cpu_x86_load_seg_cache(env, R_CS, (selector + 16) \| 3,
1156	0, 0xffffffff,
1157	DESC_G_MASK \| DESC_P_MASK \|
1158	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
1159	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK \|
1160	DESC_L_MASK);
1161	env->eip = ECX;
1162	} else {
1163	cpu_x86_load_seg_cache(env, R_CS, selector \| 3,
1164	0, 0xffffffff,
1165	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1166	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
1167	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK);
1168	env->eip = (uint32_t)ECX;
1169	}
1170	cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1171	0, 0xffffffff,
1172	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1173	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
1174	DESC_W_MASK \| DESC_A_MASK);
1175	load_eflags((uint32_t)(env->regs[11]), TF_MASK \| AC_MASK \| ID_MASK \|
1176	IF_MASK \| IOPL_MASK \| VM_MASK \| RF_MASK \| NT_MASK);
1177	cpu_x86_set_cpl(env, 3);
1178	} else
1179	#endif
1180	{
1181	cpu_x86_load_seg_cache(env, R_CS, selector \| 3,
1182	0, 0xffffffff,
1183	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1184	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
1185	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK);
1186	env->eip = (uint32_t)ECX;
1187	cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1188	0, 0xffffffff,
1189	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
1190	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
1191	DESC_W_MASK \| DESC_A_MASK);
1192	env->eflags \|= IF_MASK;
1193	cpu_x86_set_cpl(env, 3);
1194	}
1195	#ifdef USE_KQEMU
1196	if (kqemu_is_ok(env)) {
1197	if (env->hflags & HF_LMA_MASK)
1198	CC_OP = CC_OP_EFLAGS;
1199	env->exception_index = -1;
1200	cpu_loop_exit();
1201	}
1202	#endif
1203	}
1204
1205	#ifdef VBOX
1206	/**
1207	* Checks and processes external VMM events.
1208	* Called by op_check_external_event() when any of the flags is set and can be serviced.
1209	*/
1210	void helper_external_event(void)
1211	{
1212	#if defined(RT_OS_DARWIN) && defined(VBOX_STRICT)
1213	uintptr_t uESP;
1214	__asm__ __volatile__("movl %%esp, %0" : "=r" (uESP));
1215	AssertMsg(!(uESP & 15), ("esp=%#p\n", uESP));
1216	#endif
1217	if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_HARD)
1218	{
1219	ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_HARD);
1220	cpu_interrupt(env, CPU_INTERRUPT_HARD);
1221	}
1222	if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_EXIT)
1223	{
1224	ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_EXIT);
1225	cpu_interrupt(env, CPU_INTERRUPT_EXIT);
1226	}
1227	if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_DMA)
1228	{
1229	ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_DMA);
1230	remR3DmaRun(env);
1231	}
1232	if (env->interrupt_request & CPU_INTERRUPT_EXTERNAL_TIMER)
1233	{
1234	ASMAtomicAndS32(&env->interrupt_request, ~CPU_INTERRUPT_EXTERNAL_TIMER);
1235	remR3TimersRun(env);
1236	}
1237	}
1238	/* helper for recording call instruction addresses for later scanning */
1239	void helper_record_call()
1240	{
1241	if ( !(env->state & CPU_RAW_RING0)
1242	&& (env->cr[0] & CR0_PG_MASK)
1243	&& !(env->eflags & X86_EFL_IF))
1244	remR3RecordCall(env);
1245	}
1246	#endif /* VBOX */
1247
1248	/* real mode interrupt */
1249	static void do_interrupt_real(int intno, int is_int, int error_code,
1250	unsigned int next_eip)
1251	{
1252	SegmentCache *dt;
1253	target_ulong ptr, ssp;
1254	int selector;
1255	uint32_t offset, esp;
1256	uint32_t old_cs, old_eip;
1257
1258	/* real mode (simpler !) */
1259	dt = &env->idt;
1260	if (intno * 4 + 3 > dt->limit)
1261	raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
1262	ptr = dt->base + intno * 4;
1263	offset = lduw_kernel(ptr);
1264	selector = lduw_kernel(ptr + 2);
1265	esp = ESP;
1266	ssp = env->segs[R_SS].base;
1267	if (is_int)
1268	old_eip = next_eip;
1269	else
1270	old_eip = env->eip;
1271	old_cs = env->segs[R_CS].selector;
1272	/* XXX: use SS segment size ? */
1273	PUSHW(ssp, esp, 0xffff, compute_eflags());
1274	PUSHW(ssp, esp, 0xffff, old_cs);
1275	PUSHW(ssp, esp, 0xffff, old_eip);
1276
1277	/* update processor state */
1278	ESP = (ESP & ~0xffff) \| (esp & 0xffff);
1279	env->eip = offset;
1280	env->segs[R_CS].selector = selector;
1281	env->segs[R_CS].base = (selector << 4);
1282	env->eflags &= ~(IF_MASK \| TF_MASK \| AC_MASK \| RF_MASK);
1283	}
1284
1285	/* fake user mode interrupt */
1286	void do_interrupt_user(int intno, int is_int, int error_code,
1287	target_ulong next_eip)
1288	{
1289	SegmentCache *dt;
1290	target_ulong ptr;
1291	int dpl, cpl;
1292	uint32_t e2;
1293
1294	dt = &env->idt;
1295	ptr = dt->base + (intno * 8);
1296	e2 = ldl_kernel(ptr + 4);
1297
1298	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1299	cpl = env->hflags & HF_CPL_MASK;
1300	/* check privledge if software int */
1301	if (is_int && dpl < cpl)
1302	raise_exception_err(EXCP0D_GPF, intno * 8 + 2);
1303
1304	/* Since we emulate only user space, we cannot do more than
1305	exiting the emulation with the suitable exception and error
1306	code */
1307	if (is_int)
1308	EIP = next_eip;
1309	}
1310
1311	/*
1312	* Begin execution of an interruption. is_int is TRUE if coming from
1313	* the int instruction. next_eip is the EIP value AFTER the interrupt
1314	* instruction. It is only relevant if is_int is TRUE.
1315	*/
1316	void do_interrupt(int intno, int is_int, int error_code,
1317	target_ulong next_eip, int is_hw)
1318	{
1319	if (loglevel & CPU_LOG_INT) {
1320	if ((env->cr[0] & CR0_PE_MASK)) {
1321	static int count;
1322	fprintf(logfile, "%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx,
1323	count, intno, error_code, is_int,
1324	env->hflags & HF_CPL_MASK,
1325	env->segs[R_CS].selector, EIP,
1326	(int)env->segs[R_CS].base + EIP,
1327	env->segs[R_SS].selector, ESP);
1328	if (intno == 0x0e) {
1329	fprintf(logfile, " CR2=" TARGET_FMT_lx, env->cr[2]);
1330	} else {
1331	fprintf(logfile, " EAX=" TARGET_FMT_lx, EAX);
1332	}
1333	fprintf(logfile, "\n");
1334	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1335	#if 0
1336	{
1337	int i;
1338	uint8_t *ptr;
1339	fprintf(logfile, " code=");
1340	ptr = env->segs[R_CS].base + env->eip;
1341	for(i = 0; i < 16; i++) {
1342	fprintf(logfile, " %02x", ldub(ptr + i));
1343	}
1344	fprintf(logfile, "\n");
1345	}
1346	#endif
1347	count++;
1348	}
1349	}
1350	if (env->cr[0] & CR0_PE_MASK) {
1351	#ifdef TARGET_X86_64
1352	if (env->hflags & HF_LMA_MASK) {
1353	do_interrupt64(intno, is_int, error_code, next_eip, is_hw);
1354	} else
1355	#endif
1356	{
1357	#ifdef VBOX
1358	/* int xx , v86 code and VME enabled? /
1359	if ( (env->eflags & VM_MASK)
1360	&& (env->cr[4] & CR4_VME_MASK)
1361	&& is_int
1362	&& !is_hw
1363	&& env->eip + 1 != next_eip /* single byte int 3 goes straight to the protected mode handler */
1364	)
1365	do_soft_interrupt_vme(intno, error_code, next_eip);
1366	else
1367	#endif /* VBOX */
1368	do_interrupt_protected(intno, is_int, error_code, next_eip, is_hw);
1369	}
1370	} else {
1371	do_interrupt_real(intno, is_int, error_code, next_eip);
1372	}
1373	}
1374
1375	/*
1376	* Signal an interruption. It is executed in the main CPU loop.
1377	* is_int is TRUE if coming from the int instruction. next_eip is the
1378	* EIP value AFTER the interrupt instruction. It is only relevant if
1379	* is_int is TRUE.
1380	*/
1381	void raise_interrupt(int intno, int is_int, int error_code,
1382	int next_eip_addend)
1383	{
1384	#if defined(VBOX) && defined(DEBUG)
1385	NOT_DMIK(Log2(("raise_interrupt: %x %x %x %08x\n", intno, is_int, error_code, env->eip + next_eip_addend)));
1386	#endif
1387	env->exception_index = intno;
1388	env->error_code = error_code;
1389	env->exception_is_int = is_int;
1390	env->exception_next_eip = env->eip + next_eip_addend;
1391	cpu_loop_exit();
1392	}
1393
1394	/* same as raise_exception_err, but do not restore global registers */
1395	static void raise_exception_err_norestore(int exception_index, int error_code)
1396	{
1397	env->exception_index = exception_index;
1398	env->error_code = error_code;
1399	env->exception_is_int = 0;
1400	env->exception_next_eip = 0;
1401	longjmp(env->jmp_env, 1);
1402	}
1403
1404	/* shortcuts to generate exceptions */
1405
1406	void (raise_exception_err)(int exception_index, int error_code)
1407	{
1408	raise_interrupt(exception_index, 0, error_code, 0);
1409	}
1410
1411	void raise_exception(int exception_index)
1412	{
1413	raise_interrupt(exception_index, 0, 0, 0);
1414	}
1415
1416	/* SMM support */
1417
1418	#if defined(CONFIG_USER_ONLY)
1419
1420	void do_smm_enter(void)
1421	{
1422	}
1423
1424	void helper_rsm(void)
1425	{
1426	}
1427
1428	#else
1429
1430	#ifdef TARGET_X86_64
1431	#define SMM_REVISION_ID 0x00020064
1432	#else
1433	#define SMM_REVISION_ID 0x00020000
1434	#endif
1435
1436	void do_smm_enter(void)
1437	{
1438	#ifdef VBOX
1439	cpu_abort(env, "do_ssm_enter");
1440	#else /* !VBOX */
1441	target_ulong sm_state;
1442	SegmentCache *dt;
1443	int i, offset;
1444
1445	if (loglevel & CPU_LOG_INT) {
1446	fprintf(logfile, "SMM: enter\n");
1447	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1448	}
1449
1450	env->hflags \|= HF_SMM_MASK;
1451	cpu_smm_update(env);
1452
1453	sm_state = env->smbase + 0x8000;
1454
1455	#ifdef TARGET_X86_64
1456	for(i = 0; i < 6; i++) {
1457	dt = &env->segs[i];
1458	offset = 0x7e00 + i * 16;
1459	stw_phys(sm_state + offset, dt->selector);
1460	stw_phys(sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
1461	stl_phys(sm_state + offset + 4, dt->limit);
1462	stq_phys(sm_state + offset + 8, dt->base);
1463	}
1464
1465	stq_phys(sm_state + 0x7e68, env->gdt.base);
1466	stl_phys(sm_state + 0x7e64, env->gdt.limit);
1467
1468	stw_phys(sm_state + 0x7e70, env->ldt.selector);
1469	stq_phys(sm_state + 0x7e78, env->ldt.base);
1470	stl_phys(sm_state + 0x7e74, env->ldt.limit);
1471	stw_phys(sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
1472
1473	stq_phys(sm_state + 0x7e88, env->idt.base);
1474	stl_phys(sm_state + 0x7e84, env->idt.limit);
1475
1476	stw_phys(sm_state + 0x7e90, env->tr.selector);
1477	stq_phys(sm_state + 0x7e98, env->tr.base);
1478	stl_phys(sm_state + 0x7e94, env->tr.limit);
1479	stw_phys(sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
1480
1481	stq_phys(sm_state + 0x7ed0, env->efer);
1482
1483	stq_phys(sm_state + 0x7ff8, EAX);
1484	stq_phys(sm_state + 0x7ff0, ECX);
1485	stq_phys(sm_state + 0x7fe8, EDX);
1486	stq_phys(sm_state + 0x7fe0, EBX);
1487	stq_phys(sm_state + 0x7fd8, ESP);
1488	stq_phys(sm_state + 0x7fd0, EBP);
1489	stq_phys(sm_state + 0x7fc8, ESI);
1490	stq_phys(sm_state + 0x7fc0, EDI);
1491	for(i = 8; i < 16; i++)
1492	stq_phys(sm_state + 0x7ff8 - i * 8, env->regs[i]);
1493	stq_phys(sm_state + 0x7f78, env->eip);
1494	stl_phys(sm_state + 0x7f70, compute_eflags());
1495	stl_phys(sm_state + 0x7f68, env->dr[6]);
1496	stl_phys(sm_state + 0x7f60, env->dr[7]);
1497
1498	stl_phys(sm_state + 0x7f48, env->cr[4]);
1499	stl_phys(sm_state + 0x7f50, env->cr[3]);
1500	stl_phys(sm_state + 0x7f58, env->cr[0]);
1501
1502	stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
1503	stl_phys(sm_state + 0x7f00, env->smbase);
1504	#else
1505	stl_phys(sm_state + 0x7ffc, env->cr[0]);
1506	stl_phys(sm_state + 0x7ff8, env->cr[3]);
1507	stl_phys(sm_state + 0x7ff4, compute_eflags());
1508	stl_phys(sm_state + 0x7ff0, env->eip);
1509	stl_phys(sm_state + 0x7fec, EDI);
1510	stl_phys(sm_state + 0x7fe8, ESI);
1511	stl_phys(sm_state + 0x7fe4, EBP);
1512	stl_phys(sm_state + 0x7fe0, ESP);
1513	stl_phys(sm_state + 0x7fdc, EBX);
1514	stl_phys(sm_state + 0x7fd8, EDX);
1515	stl_phys(sm_state + 0x7fd4, ECX);
1516	stl_phys(sm_state + 0x7fd0, EAX);
1517	stl_phys(sm_state + 0x7fcc, env->dr[6]);
1518	stl_phys(sm_state + 0x7fc8, env->dr[7]);
1519
1520	stl_phys(sm_state + 0x7fc4, env->tr.selector);
1521	stl_phys(sm_state + 0x7f64, env->tr.base);
1522	stl_phys(sm_state + 0x7f60, env->tr.limit);
1523	stl_phys(sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
1524
1525	stl_phys(sm_state + 0x7fc0, env->ldt.selector);
1526	stl_phys(sm_state + 0x7f80, env->ldt.base);
1527	stl_phys(sm_state + 0x7f7c, env->ldt.limit);
1528	stl_phys(sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
1529
1530	stl_phys(sm_state + 0x7f74, env->gdt.base);
1531	stl_phys(sm_state + 0x7f70, env->gdt.limit);
1532
1533	stl_phys(sm_state + 0x7f58, env->idt.base);
1534	stl_phys(sm_state + 0x7f54, env->idt.limit);
1535
1536	for(i = 0; i < 6; i++) {
1537	dt = &env->segs[i];
1538	if (i < 3)
1539	offset = 0x7f84 + i * 12;
1540	else
1541	offset = 0x7f2c + (i - 3) * 12;
1542	stl_phys(sm_state + 0x7fa8 + i * 4, dt->selector);
1543	stl_phys(sm_state + offset + 8, dt->base);
1544	stl_phys(sm_state + offset + 4, dt->limit);
1545	stl_phys(sm_state + offset, (dt->flags >> 8) & 0xf0ff);
1546	}
1547	stl_phys(sm_state + 0x7f14, env->cr[4]);
1548
1549	stl_phys(sm_state + 0x7efc, SMM_REVISION_ID);
1550	stl_phys(sm_state + 0x7ef8, env->smbase);
1551	#endif
1552	/* init SMM cpu state */
1553
1554	#ifdef TARGET_X86_64
1555	env->efer = 0;
1556	env->hflags &= ~HF_LMA_MASK;
1557	#endif
1558	load_eflags(0, ~(CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C \| DF_MASK));
1559	env->eip = 0x00008000;
1560	cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
1561	0xffffffff, 0);
1562	cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff, 0);
1563	cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff, 0);
1564	cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff, 0);
1565	cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff, 0);
1566	cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff, 0);
1567
1568	cpu_x86_update_cr0(env,
1569	env->cr[0] & ~(CR0_PE_MASK \| CR0_EM_MASK \| CR0_TS_MASK \| CR0_PG_MASK));
1570	cpu_x86_update_cr4(env, 0);
1571	env->dr[7] = 0x00000400;
1572	CC_OP = CC_OP_EFLAGS;
1573	#endif /* VBOX */
1574	}
1575
1576	void helper_rsm(void)
1577	{
1578	#ifdef VBOX
1579	cpu_abort(env, "helper_rsm");
1580	#else /* !VBOX */
1581	target_ulong sm_state;
1582	int i, offset;
1583	uint32_t val;
1584
1585	sm_state = env->smbase + 0x8000;
1586	#ifdef TARGET_X86_64
1587	env->efer = ldq_phys(sm_state + 0x7ed0);
1588	if (env->efer & MSR_EFER_LMA)
1589	env->hflags \|= HF_LMA_MASK;
1590	else
1591	env->hflags &= ~HF_LMA_MASK;
1592
1593	for(i = 0; i < 6; i++) {
1594	offset = 0x7e00 + i * 16;
1595	cpu_x86_load_seg_cache(env, i,
1596	lduw_phys(sm_state + offset),
1597	ldq_phys(sm_state + offset + 8),
1598	ldl_phys(sm_state + offset + 4),
1599	(lduw_phys(sm_state + offset + 2) & 0xf0ff) << 8);
1600	}
1601
1602	env->gdt.base = ldq_phys(sm_state + 0x7e68);
1603	env->gdt.limit = ldl_phys(sm_state + 0x7e64);
1604
1605	env->ldt.selector = lduw_phys(sm_state + 0x7e70);
1606	env->ldt.base = ldq_phys(sm_state + 0x7e78);
1607	env->ldt.limit = ldl_phys(sm_state + 0x7e74);
1608	env->ldt.flags = (lduw_phys(sm_state + 0x7e72) & 0xf0ff) << 8;
1609
1610	env->idt.base = ldq_phys(sm_state + 0x7e88);
1611	env->idt.limit = ldl_phys(sm_state + 0x7e84);
1612
1613	env->tr.selector = lduw_phys(sm_state + 0x7e90);
1614	env->tr.base = ldq_phys(sm_state + 0x7e98);
1615	env->tr.limit = ldl_phys(sm_state + 0x7e94);
1616	env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8;
1617
1618	EAX = ldq_phys(sm_state + 0x7ff8);
1619	ECX = ldq_phys(sm_state + 0x7ff0);
1620	EDX = ldq_phys(sm_state + 0x7fe8);
1621	EBX = ldq_phys(sm_state + 0x7fe0);
1622	ESP = ldq_phys(sm_state + 0x7fd8);
1623	EBP = ldq_phys(sm_state + 0x7fd0);
1624	ESI = ldq_phys(sm_state + 0x7fc8);
1625	EDI = ldq_phys(sm_state + 0x7fc0);
1626	for(i = 8; i < 16; i++)
1627	env->regs[i] = ldq_phys(sm_state + 0x7ff8 - i * 8);
1628	env->eip = ldq_phys(sm_state + 0x7f78);
1629	load_eflags(ldl_phys(sm_state + 0x7f70),
1630	~(CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C \| DF_MASK));
1631	env->dr[6] = ldl_phys(sm_state + 0x7f68);
1632	env->dr[7] = ldl_phys(sm_state + 0x7f60);
1633
1634	cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f48));
1635	cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7f50));
1636	cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7f58));
1637
1638	val = ldl_phys(sm_state + 0x7efc); /* revision ID */
1639	if (val & 0x20000) {
1640	env->smbase = ldl_phys(sm_state + 0x7f00) & ~0x7fff;
1641	}
1642	#else
1643	cpu_x86_update_cr0(env, ldl_phys(sm_state + 0x7ffc));
1644	cpu_x86_update_cr3(env, ldl_phys(sm_state + 0x7ff8));
1645	load_eflags(ldl_phys(sm_state + 0x7ff4),
1646	~(CC_O \| CC_S \| CC_Z \| CC_A \| CC_P \| CC_C \| DF_MASK));
1647	env->eip = ldl_phys(sm_state + 0x7ff0);
1648	EDI = ldl_phys(sm_state + 0x7fec);
1649	ESI = ldl_phys(sm_state + 0x7fe8);
1650	EBP = ldl_phys(sm_state + 0x7fe4);
1651	ESP = ldl_phys(sm_state + 0x7fe0);
1652	EBX = ldl_phys(sm_state + 0x7fdc);
1653	EDX = ldl_phys(sm_state + 0x7fd8);
1654	ECX = ldl_phys(sm_state + 0x7fd4);
1655	EAX = ldl_phys(sm_state + 0x7fd0);
1656	env->dr[6] = ldl_phys(sm_state + 0x7fcc);
1657	env->dr[7] = ldl_phys(sm_state + 0x7fc8);
1658
1659	env->tr.selector = ldl_phys(sm_state + 0x7fc4) & 0xffff;
1660	env->tr.base = ldl_phys(sm_state + 0x7f64);
1661	env->tr.limit = ldl_phys(sm_state + 0x7f60);
1662	env->tr.flags = (ldl_phys(sm_state + 0x7f5c) & 0xf0ff) << 8;
1663
1664	env->ldt.selector = ldl_phys(sm_state + 0x7fc0) & 0xffff;
1665	env->ldt.base = ldl_phys(sm_state + 0x7f80);
1666	env->ldt.limit = ldl_phys(sm_state + 0x7f7c);
1667	env->ldt.flags = (ldl_phys(sm_state + 0x7f78) & 0xf0ff) << 8;
1668
1669	env->gdt.base = ldl_phys(sm_state + 0x7f74);
1670	env->gdt.limit = ldl_phys(sm_state + 0x7f70);
1671
1672	env->idt.base = ldl_phys(sm_state + 0x7f58);
1673	env->idt.limit = ldl_phys(sm_state + 0x7f54);
1674
1675	for(i = 0; i < 6; i++) {
1676	if (i < 3)
1677	offset = 0x7f84 + i * 12;
1678	else
1679	offset = 0x7f2c + (i - 3) * 12;
1680	cpu_x86_load_seg_cache(env, i,
1681	ldl_phys(sm_state + 0x7fa8 + i * 4) & 0xffff,
1682	ldl_phys(sm_state + offset + 8),
1683	ldl_phys(sm_state + offset + 4),
1684	(ldl_phys(sm_state + offset) & 0xf0ff) << 8);
1685	}
1686	cpu_x86_update_cr4(env, ldl_phys(sm_state + 0x7f14));
1687
1688	val = ldl_phys(sm_state + 0x7efc); /* revision ID */
1689	if (val & 0x20000) {
1690	env->smbase = ldl_phys(sm_state + 0x7ef8) & ~0x7fff;
1691	}
1692	#endif
1693	CC_OP = CC_OP_EFLAGS;
1694	env->hflags &= ~HF_SMM_MASK;
1695	cpu_smm_update(env);
1696
1697	if (loglevel & CPU_LOG_INT) {
1698	fprintf(logfile, "SMM: after RSM\n");
1699	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
1700	}
1701	#endif /* !VBOX */
1702	}
1703
1704	#endif /* !CONFIG_USER_ONLY */
1705
1706
1707	#ifdef BUGGY_GCC_DIV64
1708	/* gcc 2.95.4 on PowerPC does not seem to like using __udivdi3, so we
1709	call it from another function */
1710	uint32_t div32(uint64_t *q_ptr, uint64_t num, uint32_t den)
1711	{
1712	*q_ptr = num / den;
1713	return num % den;
1714	}
1715
1716	int32_t idiv32(int64_t *q_ptr, int64_t num, int32_t den)
1717	{
1718	*q_ptr = num / den;
1719	return num % den;
1720	}
1721	#endif
1722
1723	void helper_divl_EAX_T0(void)
1724	{
1725	unsigned int den, r;
1726	uint64_t num, q;
1727
1728	num = ((uint32_t)EAX) \| ((uint64_t)((uint32_t)EDX) << 32);
1729	den = T0;
1730	if (den == 0) {
1731	raise_exception(EXCP00_DIVZ);
1732	}
1733	#ifdef BUGGY_GCC_DIV64
1734	r = div32(&q, num, den);
1735	#else
1736	q = (num / den);
1737	r = (num % den);
1738	#endif
1739	if (q > 0xffffffff)
1740	raise_exception(EXCP00_DIVZ);
1741	EAX = (uint32_t)q;
1742	EDX = (uint32_t)r;
1743	}
1744
1745	void helper_idivl_EAX_T0(void)
1746	{
1747	int den, r;
1748	int64_t num, q;
1749
1750	num = ((uint32_t)EAX) \| ((uint64_t)((uint32_t)EDX) << 32);
1751	den = T0;
1752	if (den == 0) {
1753	raise_exception(EXCP00_DIVZ);
1754	}
1755	#ifdef BUGGY_GCC_DIV64
1756	r = idiv32(&q, num, den);
1757	#else
1758	q = (num / den);
1759	r = (num % den);
1760	#endif
1761	if (q != (int32_t)q)
1762	raise_exception(EXCP00_DIVZ);
1763	EAX = (uint32_t)q;
1764	EDX = (uint32_t)r;
1765	}
1766
1767	void helper_cmpxchg8b(void)
1768	{
1769	uint64_t d;
1770	int eflags;
1771
1772	eflags = cc_table[CC_OP].compute_all();
1773	d = ldq(A0);
1774	if (d == (((uint64_t)EDX << 32) \| EAX)) {
1775	stq(A0, ((uint64_t)ECX << 32) \| EBX);
1776	eflags \|= CC_Z;
1777	} else {
1778	EDX = d >> 32;
1779	EAX = d;
1780	eflags &= ~CC_Z;
1781	}
1782	CC_SRC = eflags;
1783	}
1784
1785	void helper_single_step()
1786	{
1787	env->dr[6] \|= 0x4000;
1788	raise_exception(EXCP01_SSTP);
1789	}
1790
1791	void helper_cpuid(void)
1792	{
1793	#ifndef VBOX
1794	uint32_t index;
1795	index = (uint32_t)EAX;
1796
1797	/* test if maximum index reached */
1798	if (index & 0x80000000) {
1799	if (index > env->cpuid_xlevel)
1800	index = env->cpuid_level;
1801	} else {
1802	if (index > env->cpuid_level)
1803	index = env->cpuid_level;
1804	}
1805
1806	switch(index) {
1807	case 0:
1808	EAX = env->cpuid_level;
1809	EBX = env->cpuid_vendor1;
1810	EDX = env->cpuid_vendor2;
1811	ECX = env->cpuid_vendor3;
1812	break;
1813	case 1:
1814	EAX = env->cpuid_version;
1815	EBX = 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1816	ECX = env->cpuid_ext_features;
1817	EDX = env->cpuid_features;
1818	break;
1819	case 2:
1820	/* cache info: needed for Pentium Pro compatibility */
1821	EAX = 0x410601;
1822	EBX = 0;
1823	ECX = 0;
1824	EDX = 0;
1825	break;
1826	case 0x80000000:
1827	EAX = env->cpuid_xlevel;
1828	EBX = env->cpuid_vendor1;
1829	EDX = env->cpuid_vendor2;
1830	ECX = env->cpuid_vendor3;
1831	break;
1832	case 0x80000001:
1833	EAX = env->cpuid_features;
1834	EBX = 0;
1835	ECX = 0;
1836	EDX = env->cpuid_ext2_features;
1837	break;
1838	case 0x80000002:
1839	case 0x80000003:
1840	case 0x80000004:
1841	EAX = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1842	EBX = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1843	ECX = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1844	EDX = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1845	break;
1846	case 0x80000005:
1847	/* cache info (L1 cache) */
1848	EAX = 0x01ff01ff;
1849	EBX = 0x01ff01ff;
1850	ECX = 0x40020140;
1851	EDX = 0x40020140;
1852	break;
1853	case 0x80000006:
1854	/* cache info (L2 cache) */
1855	EAX = 0;
1856	EBX = 0x42004200;
1857	ECX = 0x02008140;
1858	EDX = 0;
1859	break;
1860	case 0x80000008:
1861	/* virtual & phys address size in low 2 bytes. */
1862	EAX = 0x00003028;
1863	EBX = 0;
1864	ECX = 0;
1865	EDX = 0;
1866	break;
1867	default:
1868	/* reserved values: zero */
1869	EAX = 0;
1870	EBX = 0;
1871	ECX = 0;
1872	EDX = 0;
1873	break;
1874	}
1875	#else /* VBOX */
1876	remR3CpuId(env, EAX, &EAX, &EBX, &ECX, &EDX);
1877	#endif /* VBOX */
1878	}
1879
1880	void helper_enter_level(int level, int data32)
1881	{
1882	target_ulong ssp;
1883	uint32_t esp_mask, esp, ebp;
1884
1885	esp_mask = get_sp_mask(env->segs[R_SS].flags);
1886	ssp = env->segs[R_SS].base;
1887	ebp = EBP;
1888	esp = ESP;
1889	if (data32) {
1890	/* 32 bit */
1891	esp -= 4;
1892	while (--level) {
1893	esp -= 4;
1894	ebp -= 4;
1895	stl(ssp + (esp & esp_mask), ldl(ssp + (ebp & esp_mask)));
1896	}
1897	esp -= 4;
1898	stl(ssp + (esp & esp_mask), T1);
1899	} else {
1900	/* 16 bit */
1901	esp -= 2;
1902	while (--level) {
1903	esp -= 2;
1904	ebp -= 2;
1905	stw(ssp + (esp & esp_mask), lduw(ssp + (ebp & esp_mask)));
1906	}
1907	esp -= 2;
1908	stw(ssp + (esp & esp_mask), T1);
1909	}
1910	}
1911
1912	#ifdef TARGET_X86_64
1913	void helper_enter64_level(int level, int data64)
1914	{
1915	target_ulong esp, ebp;
1916	ebp = EBP;
1917	esp = ESP;
1918
1919	if (data64) {
1920	/* 64 bit */
1921	esp -= 8;
1922	while (--level) {
1923	esp -= 8;
1924	ebp -= 8;
1925	stq(esp, ldq(ebp));
1926	}
1927	esp -= 8;
1928	stq(esp, T1);
1929	} else {
1930	/* 16 bit */
1931	esp -= 2;
1932	while (--level) {
1933	esp -= 2;
1934	ebp -= 2;
1935	stw(esp, lduw(ebp));
1936	}
1937	esp -= 2;
1938	stw(esp, T1);
1939	}
1940	}
1941	#endif
1942
1943	void helper_lldt_T0(void)
1944	{
1945	int selector;
1946	SegmentCache *dt;
1947	uint32_t e1, e2;
1948	int index, entry_limit;
1949	target_ulong ptr;
1950	#ifdef VBOX
1951	Log(("helper_lldt_T0: old ldtr=%RTsel {.base=%VGv, .limit=%VGv} new=%RTsel\n",
1952	(RTSEL)env->ldt.selector, (RTGCPTR)env->ldt.base, (RTGCPTR)env->ldt.limit, (RTSEL)(T0 & 0xffff)));
1953	#endif
1954
1955	selector = T0 & 0xffff;
1956	if ((selector & 0xfffc) == 0) {
1957	/* XXX: NULL selector case: invalid LDT */
1958	env->ldt.base = 0;
1959	env->ldt.limit = 0;
1960	} else {
1961	if (selector & 0x4)
1962	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1963	dt = &env->gdt;
1964	index = selector & ~7;
1965	#ifdef TARGET_X86_64
1966	if (env->hflags & HF_LMA_MASK)
1967	entry_limit = 15;
1968	else
1969	#endif
1970	entry_limit = 7;
1971	if ((index + entry_limit) > dt->limit)
1972	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1973	ptr = dt->base + index;
1974	e1 = ldl_kernel(ptr);
1975	e2 = ldl_kernel(ptr + 4);
1976	if ((e2 & DESC_S_MASK) \|\| ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)
1977	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
1978	if (!(e2 & DESC_P_MASK))
1979	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
1980	#ifdef TARGET_X86_64
1981	if (env->hflags & HF_LMA_MASK) {
1982	uint32_t e3;
1983	e3 = ldl_kernel(ptr + 8);
1984	load_seg_cache_raw_dt(&env->ldt, e1, e2);
1985	env->ldt.base \|= (target_ulong)e3 << 32;
1986	} else
1987	#endif
1988	{
1989	load_seg_cache_raw_dt(&env->ldt, e1, e2);
1990	}
1991	}
1992	env->ldt.selector = selector;
1993	#ifdef VBOX
1994	Log(("helper_lldt_T0: new ldtr=%RTsel {.base=%VGv, .limit=%VGv}\n",
1995	(RTSEL)env->ldt.selector, (RTGCPTR)env->ldt.base, (RTGCPTR)env->ldt.limit));
1996	#endif
1997	}
1998
1999	void helper_ltr_T0(void)
2000	{
2001	int selector;
2002	SegmentCache *dt;
2003	uint32_t e1, e2;
2004	int index, type, entry_limit;
2005	target_ulong ptr;
2006
2007	#ifdef VBOX
2008	Log(("helper_ltr_T0: old tr=%RTsel {.base=%VGv, .limit=%VGv, .flags=%RX32} new=%RTsel\n",
2009	(RTSEL)env->tr.selector, (RTGCPTR)env->tr.base, (RTGCPTR)env->tr.limit,
2010	env->tr.flags, (RTSEL)(T0 & 0xffff)));
2011	#endif
2012
2013	selector = T0 & 0xffff;
2014	if ((selector & 0xfffc) == 0) {
2015	/* NULL selector case: invalid TR */
2016	env->tr.base = 0;
2017	env->tr.limit = 0;
2018	env->tr.flags = 0;
2019	} else {
2020	if (selector & 0x4)
2021	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2022	dt = &env->gdt;
2023	index = selector & ~7;
2024	#ifdef TARGET_X86_64
2025	if (env->hflags & HF_LMA_MASK)
2026	entry_limit = 15;
2027	else
2028	#endif
2029	entry_limit = 7;
2030	if ((index + entry_limit) > dt->limit)
2031	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2032	ptr = dt->base + index;
2033	e1 = ldl_kernel(ptr);
2034	e2 = ldl_kernel(ptr + 4);
2035	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2036	if ((e2 & DESC_S_MASK) \|\|
2037	(type != 1 && type != 9))
2038	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2039	if (!(e2 & DESC_P_MASK))
2040	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
2041	#ifdef TARGET_X86_64
2042	if (env->hflags & HF_LMA_MASK) {
2043	uint32_t e3;
2044	e3 = ldl_kernel(ptr + 8);
2045	load_seg_cache_raw_dt(&env->tr, e1, e2);
2046	env->tr.base \|= (target_ulong)e3 << 32;
2047	} else
2048	#endif
2049	{
2050	load_seg_cache_raw_dt(&env->tr, e1, e2);
2051	}
2052	e2 \|= DESC_TSS_BUSY_MASK;
2053	stl_kernel(ptr + 4, e2);
2054	}
2055	env->tr.selector = selector;
2056	#ifdef VBOX
2057	Log(("helper_ltr_T0: new tr=%RTsel {.base=%VGv, .limit=%VGv, .flags=%RX32} new=%RTsel\n",
2058	(RTSEL)env->tr.selector, (RTGCPTR)env->tr.base, (RTGCPTR)env->tr.limit,
2059	env->tr.flags, (RTSEL)(T0 & 0xffff)));
2060	#endif
2061	}
2062
2063	/* only works if protected mode and not VM86. seg_reg must be != R_CS */
2064	void load_seg(int seg_reg, int selector)
2065	{
2066	uint32_t e1, e2;
2067	int cpl, dpl, rpl;
2068	SegmentCache *dt;
2069	int index;
2070	target_ulong ptr;
2071
2072	selector &= 0xffff;
2073	cpl = env->hflags & HF_CPL_MASK;
2074
2075	#ifdef VBOX
2076	/* Trying to load a selector with CPL=1? */
2077	if (cpl == 0 && (selector & 3) == 1 && (env->state & CPU_RAW_RING0))
2078	{
2079	Log(("RPL 1 -> sel %04X -> %04X\n", selector, selector & 0xfffc));
2080	selector = selector & 0xfffc;
2081	}
2082	#endif
2083
2084	if ((selector & 0xfffc) == 0) {
2085	/* null selector case */
2086	if (seg_reg == R_SS
2087	#ifdef TARGET_X86_64
2088	&& (!(env->hflags & HF_CS64_MASK) \|\| cpl == 3)
2089	#endif
2090	)
2091	raise_exception_err(EXCP0D_GPF, 0);
2092	cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);
2093	} else {
2094
2095	if (selector & 0x4)
2096	dt = &env->ldt;
2097	else
2098	dt = &env->gdt;
2099	index = selector & ~7;
2100	if ((index + 7) > dt->limit)
2101	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2102	ptr = dt->base + index;
2103	e1 = ldl_kernel(ptr);
2104	e2 = ldl_kernel(ptr + 4);
2105
2106	if (!(e2 & DESC_S_MASK))
2107	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2108	rpl = selector & 3;
2109	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2110	if (seg_reg == R_SS) {
2111	/* must be writable segment */
2112	if ((e2 & DESC_CS_MASK) \|\| !(e2 & DESC_W_MASK))
2113	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2114	if (rpl != cpl \|\| dpl != cpl)
2115	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2116	} else {
2117	/* must be readable segment */
2118	if ((e2 & (DESC_CS_MASK \| DESC_R_MASK)) == DESC_CS_MASK)
2119	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2120
2121	if (!(e2 & DESC_CS_MASK) \|\| !(e2 & DESC_C_MASK)) {
2122	/* if not conforming code, test rights */
2123	if (dpl < cpl \|\| dpl < rpl)
2124	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2125	}
2126	}
2127
2128	if (!(e2 & DESC_P_MASK)) {
2129	if (seg_reg == R_SS)
2130	raise_exception_err(EXCP0C_STACK, selector & 0xfffc);
2131	else
2132	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
2133	}
2134
2135	/* set the access bit if not already set */
2136	if (!(e2 & DESC_A_MASK)) {
2137	e2 \|= DESC_A_MASK;
2138	stl_kernel(ptr + 4, e2);
2139	}
2140
2141	cpu_x86_load_seg_cache(env, seg_reg, selector,
2142	get_seg_base(e1, e2),
2143	get_seg_limit(e1, e2),
2144	e2);
2145	#if 0
2146	fprintf(logfile, "load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
2147	selector, (unsigned long)sc->base, sc->limit, sc->flags);
2148	#endif
2149	}
2150	}
2151
2152	/* protected mode jump */
2153	void helper_ljmp_protected_T0_T1(int next_eip_addend)
2154	{
2155	int new_cs, gate_cs, type;
2156	uint32_t e1, e2, cpl, dpl, rpl, limit;
2157	target_ulong new_eip, next_eip;
2158
2159	new_cs = T0;
2160	new_eip = T1;
2161	if ((new_cs & 0xfffc) == 0)
2162	raise_exception_err(EXCP0D_GPF, 0);
2163	if (load_segment(&e1, &e2, new_cs) != 0)
2164	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2165	cpl = env->hflags & HF_CPL_MASK;
2166	if (e2 & DESC_S_MASK) {
2167	if (!(e2 & DESC_CS_MASK))
2168	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2169	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2170	if (e2 & DESC_C_MASK) {
2171	/* conforming code segment */
2172	if (dpl > cpl)
2173	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2174	} else {
2175	/* non conforming code segment */
2176	rpl = new_cs & 3;
2177	if (rpl > cpl)
2178	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2179	if (dpl != cpl)
2180	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2181	}
2182	if (!(e2 & DESC_P_MASK))
2183	raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2184	limit = get_seg_limit(e1, e2);
2185	if (new_eip > limit &&
2186	!(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK))
2187	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2188	cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) \| cpl,
2189	get_seg_base(e1, e2), limit, e2);
2190	EIP = new_eip;
2191	} else {
2192	/* jump to call or task gate */
2193	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2194	rpl = new_cs & 3;
2195	cpl = env->hflags & HF_CPL_MASK;
2196	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2197	switch(type) {
2198	case 1: /* 286 TSS */
2199	case 9: /* 386 TSS */
2200	case 5: /* task gate */
2201	if (dpl < cpl \|\| dpl < rpl)
2202	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2203	next_eip = env->eip + next_eip_addend;
2204	switch_tss(new_cs, e1, e2, SWITCH_TSS_JMP, next_eip);
2205	CC_OP = CC_OP_EFLAGS;
2206	break;
2207	case 4: /* 286 call gate */
2208	case 12: /* 386 call gate */
2209	if ((dpl < cpl) \|\| (dpl < rpl))
2210	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2211	if (!(e2 & DESC_P_MASK))
2212	raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2213	gate_cs = e1 >> 16;
2214	new_eip = (e1 & 0xffff);
2215	if (type == 12)
2216	new_eip \|= (e2 & 0xffff0000);
2217	if (load_segment(&e1, &e2, gate_cs) != 0)
2218	raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2219	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2220	/* must be code segment */
2221	if (((e2 & (DESC_S_MASK \| DESC_CS_MASK)) !=
2222	(DESC_S_MASK \| DESC_CS_MASK)))
2223	raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2224	if (((e2 & DESC_C_MASK) && (dpl > cpl)) \|\|
2225	(!(e2 & DESC_C_MASK) && (dpl != cpl)))
2226	raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2227	if (!(e2 & DESC_P_MASK))
2228	#ifdef VBOX /* See page 3-514 of 253666.pdf */
2229	raise_exception_err(EXCP0B_NOSEG, gate_cs & 0xfffc);
2230	#else
2231	raise_exception_err(EXCP0D_GPF, gate_cs & 0xfffc);
2232	#endif
2233	limit = get_seg_limit(e1, e2);
2234	if (new_eip > limit)
2235	raise_exception_err(EXCP0D_GPF, 0);
2236	cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) \| cpl,
2237	get_seg_base(e1, e2), limit, e2);
2238	EIP = new_eip;
2239	break;
2240	default:
2241	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2242	break;
2243	}
2244	}
2245	}
2246
2247	/* real mode call */
2248	void helper_lcall_real_T0_T1(int shift, int next_eip)
2249	{
2250	int new_cs, new_eip;
2251	uint32_t esp, esp_mask;
2252	target_ulong ssp;
2253
2254	new_cs = T0;
2255	new_eip = T1;
2256	esp = ESP;
2257	esp_mask = get_sp_mask(env->segs[R_SS].flags);
2258	ssp = env->segs[R_SS].base;
2259	if (shift) {
2260	PUSHL(ssp, esp, esp_mask, env->segs[R_CS].selector);
2261	PUSHL(ssp, esp, esp_mask, next_eip);
2262	} else {
2263	PUSHW(ssp, esp, esp_mask, env->segs[R_CS].selector);
2264	PUSHW(ssp, esp, esp_mask, next_eip);
2265	}
2266
2267	SET_ESP(esp, esp_mask);
2268	env->eip = new_eip;
2269	env->segs[R_CS].selector = new_cs;
2270	env->segs[R_CS].base = (new_cs << 4);
2271	}
2272
2273	/* protected mode call */
2274	void helper_lcall_protected_T0_T1(int shift, int next_eip_addend)
2275	{
2276	int new_cs, new_stack, i;
2277	uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count;
2278	uint32_t ss, ss_e1, ss_e2, sp, type, ss_dpl, sp_mask;
2279	uint32_t val, limit, old_sp_mask;
2280	target_ulong ssp, old_ssp, next_eip, new_eip;
2281
2282	new_cs = T0;
2283	new_eip = T1;
2284	next_eip = env->eip + next_eip_addend;
2285	#ifdef DEBUG_PCALL
2286	if (loglevel & CPU_LOG_PCALL) {
2287	fprintf(logfile, "lcall %04x:%08x s=%d\n",
2288	new_cs, (uint32_t)new_eip, shift);
2289	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
2290	}
2291	#endif
2292	if ((new_cs & 0xfffc) == 0)
2293	raise_exception_err(EXCP0D_GPF, 0);
2294	if (load_segment(&e1, &e2, new_cs) != 0)
2295	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2296	cpl = env->hflags & HF_CPL_MASK;
2297	#ifdef DEBUG_PCALL
2298	if (loglevel & CPU_LOG_PCALL) {
2299	fprintf(logfile, "desc=%08x:%08x\n", e1, e2);
2300	}
2301	#endif
2302	if (e2 & DESC_S_MASK) {
2303	if (!(e2 & DESC_CS_MASK))
2304	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2305	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2306	if (e2 & DESC_C_MASK) {
2307	/* conforming code segment */
2308	if (dpl > cpl)
2309	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2310	} else {
2311	/* non conforming code segment */
2312	rpl = new_cs & 3;
2313	if (rpl > cpl)
2314	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2315	if (dpl != cpl)
2316	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2317	}
2318	if (!(e2 & DESC_P_MASK))
2319	raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2320
2321	#ifdef TARGET_X86_64
2322	/* XXX: check 16/32 bit cases in long mode */
2323	if (shift == 2) {
2324	target_ulong rsp;
2325	/* 64 bit case */
2326	rsp = ESP;
2327	PUSHQ(rsp, env->segs[R_CS].selector);
2328	PUSHQ(rsp, next_eip);
2329	/* from this point, not restartable */
2330	ESP = rsp;
2331	cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) \| cpl,
2332	get_seg_base(e1, e2),
2333	get_seg_limit(e1, e2), e2);
2334	EIP = new_eip;
2335	} else
2336	#endif
2337	{
2338	sp = ESP;
2339	sp_mask = get_sp_mask(env->segs[R_SS].flags);
2340	ssp = env->segs[R_SS].base;
2341	if (shift) {
2342	PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
2343	PUSHL(ssp, sp, sp_mask, next_eip);
2344	} else {
2345	PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
2346	PUSHW(ssp, sp, sp_mask, next_eip);
2347	}
2348
2349	limit = get_seg_limit(e1, e2);
2350	if (new_eip > limit)
2351	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2352	/* from this point, not restartable */
2353	SET_ESP(sp, sp_mask);
2354	cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) \| cpl,
2355	get_seg_base(e1, e2), limit, e2);
2356	EIP = new_eip;
2357	}
2358	} else {
2359	/* check gate type */
2360	type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
2361	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2362	rpl = new_cs & 3;
2363	switch(type) {
2364	case 1: /* available 286 TSS */
2365	case 9: /* available 386 TSS */
2366	case 5: /* task gate */
2367	if (dpl < cpl \|\| dpl < rpl)
2368	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2369	switch_tss(new_cs, e1, e2, SWITCH_TSS_CALL, next_eip);
2370	CC_OP = CC_OP_EFLAGS;
2371	return;
2372	case 4: /* 286 call gate */
2373	case 12: /* 386 call gate */
2374	break;
2375	default:
2376	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2377	break;
2378	}
2379	shift = type >> 3;
2380
2381	if (dpl < cpl \|\| dpl < rpl)
2382	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2383	/* check valid bit */
2384	if (!(e2 & DESC_P_MASK))
2385	raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2386	selector = e1 >> 16;
2387	offset = (e2 & 0xffff0000) \| (e1 & 0x0000ffff);
2388	param_count = e2 & 0x1f;
2389	if ((selector & 0xfffc) == 0)
2390	raise_exception_err(EXCP0D_GPF, 0);
2391
2392	if (load_segment(&e1, &e2, selector) != 0)
2393	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2394	if (!(e2 & DESC_S_MASK) \|\| !(e2 & (DESC_CS_MASK)))
2395	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2396	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2397	if (dpl > cpl)
2398	raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
2399	if (!(e2 & DESC_P_MASK))
2400	raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);
2401
2402	if (!(e2 & DESC_C_MASK) && dpl < cpl) {
2403	/* to inner priviledge */
2404	get_ss_esp_from_tss(&ss, &sp, dpl);
2405	#ifdef DEBUG_PCALL
2406	if (loglevel & CPU_LOG_PCALL)
2407	fprintf(logfile, "new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx "\n",
2408	ss, sp, param_count, ESP);
2409	#endif
2410	if ((ss & 0xfffc) == 0)
2411	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2412	if ((ss & 3) != dpl)
2413	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2414	if (load_segment(&ss_e1, &ss_e2, ss) != 0)
2415	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2416	ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
2417	if (ss_dpl != dpl)
2418	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2419	if (!(ss_e2 & DESC_S_MASK) \|\|
2420	(ss_e2 & DESC_CS_MASK) \|\|
2421	!(ss_e2 & DESC_W_MASK))
2422	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2423	if (!(ss_e2 & DESC_P_MASK))
2424	#ifdef VBOX /* See page 3-99 of 253666.pdf */
2425	raise_exception_err(EXCP0C_STACK, ss & 0xfffc);
2426	#else
2427	raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
2428	#endif
2429
2430	// push_size = ((param_count * 2) + 8) << shift;
2431
2432	old_sp_mask = get_sp_mask(env->segs[R_SS].flags);
2433	old_ssp = env->segs[R_SS].base;
2434
2435	sp_mask = get_sp_mask(ss_e2);
2436	ssp = get_seg_base(ss_e1, ss_e2);
2437	if (shift) {
2438	PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);
2439	PUSHL(ssp, sp, sp_mask, ESP);
2440	for(i = param_count - 1; i >= 0; i--) {
2441	val = ldl_kernel(old_ssp + ((ESP + i * 4) & old_sp_mask));
2442	PUSHL(ssp, sp, sp_mask, val);
2443	}
2444	} else {
2445	PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);
2446	PUSHW(ssp, sp, sp_mask, ESP);
2447	for(i = param_count - 1; i >= 0; i--) {
2448	val = lduw_kernel(old_ssp + ((ESP + i * 2) & old_sp_mask));
2449	PUSHW(ssp, sp, sp_mask, val);
2450	}
2451	}
2452	new_stack = 1;
2453	} else {
2454	/* to same priviledge */
2455	sp = ESP;
2456	sp_mask = get_sp_mask(env->segs[R_SS].flags);
2457	ssp = env->segs[R_SS].base;
2458	// push_size = (4 << shift);
2459	new_stack = 0;
2460	}
2461
2462	if (shift) {
2463	PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
2464	PUSHL(ssp, sp, sp_mask, next_eip);
2465	} else {
2466	PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
2467	PUSHW(ssp, sp, sp_mask, next_eip);
2468	}
2469
2470	/* from this point, not restartable */
2471
2472	if (new_stack) {
2473	ss = (ss & ~3) \| dpl;
2474	cpu_x86_load_seg_cache(env, R_SS, ss,
2475	ssp,
2476	get_seg_limit(ss_e1, ss_e2),
2477	ss_e2);
2478	}
2479
2480	selector = (selector & ~3) \| dpl;
2481	cpu_x86_load_seg_cache(env, R_CS, selector,
2482	get_seg_base(e1, e2),
2483	get_seg_limit(e1, e2),
2484	e2);
2485	cpu_x86_set_cpl(env, dpl);
2486	SET_ESP(sp, sp_mask);
2487	EIP = offset;
2488	}
2489	#ifdef USE_KQEMU
2490	if (kqemu_is_ok(env)) {
2491	env->exception_index = -1;
2492	cpu_loop_exit();
2493	}
2494	#endif
2495	}
2496
2497	/* real and vm86 mode iret */
2498	void helper_iret_real(int shift)
2499	{
2500	uint32_t sp, new_cs, new_eip, new_eflags, sp_mask;
2501	target_ulong ssp;
2502	int eflags_mask;
2503	#ifdef VBOX
2504	bool fVME = false;
2505
2506	remR3TrapClear(env->pVM);
2507	#endif /* VBOX */
2508
2509	sp_mask = 0xffff; /* XXXX: use SS segment size ? */
2510	sp = ESP;
2511	ssp = env->segs[R_SS].base;
2512	if (shift == 1) {
2513	/* 32 bits */
2514	POPL(ssp, sp, sp_mask, new_eip);
2515	POPL(ssp, sp, sp_mask, new_cs);
2516	new_cs &= 0xffff;
2517	POPL(ssp, sp, sp_mask, new_eflags);
2518	} else {
2519	/* 16 bits */
2520	POPW(ssp, sp, sp_mask, new_eip);
2521	POPW(ssp, sp, sp_mask, new_cs);
2522	POPW(ssp, sp, sp_mask, new_eflags);
2523	}
2524	#ifdef VBOX
2525	if ( (env->eflags & VM_MASK)
2526	&& ((env->eflags >> IOPL_SHIFT) & 3) != 3
2527	&& (env->cr[4] & CR4_VME_MASK)) /* implied or else we would fault earlier */
2528	{
2529	fVME = true;
2530	/* if virtual interrupt pending and (virtual) interrupts will be enabled -> #GP */
2531	/* if TF will be set -> #GP */
2532	if ( ((new_eflags & IF_MASK) && (env->eflags & VIP_MASK))
2533	\|\| (new_eflags & TF_MASK))
2534	raise_exception(EXCP0D_GPF);
2535	}
2536	#endif /* VBOX */
2537
2538	ESP = (ESP & ~sp_mask) \| (sp & sp_mask);
2539	load_seg_vm(R_CS, new_cs);
2540	env->eip = new_eip;
2541	#ifdef VBOX
2542	if (fVME)
2543	eflags_mask = TF_MASK \| AC_MASK \| ID_MASK \| RF_MASK \| NT_MASK;
2544	else
2545	#endif
2546	if (env->eflags & VM_MASK)
2547	eflags_mask = TF_MASK \| AC_MASK \| ID_MASK \| IF_MASK \| RF_MASK \| NT_MASK;
2548	else
2549	eflags_mask = TF_MASK \| AC_MASK \| ID_MASK \| IF_MASK \| IOPL_MASK \| RF_MASK \| NT_MASK;
2550	if (shift == 0)
2551	eflags_mask &= 0xffff;
2552	load_eflags(new_eflags, eflags_mask);
2553
2554	#ifdef VBOX
2555	if (fVME)
2556	{
2557	if (new_eflags & IF_MASK)
2558	env->eflags \|= VIF_MASK;
2559	else
2560	env->eflags &= ~VIF_MASK;
2561	}
2562	#endif /* VBOX */
2563	}
2564
2565	static inline void validate_seg(int seg_reg, int cpl)
2566	{
2567	int dpl;
2568	uint32_t e2;
2569
2570	/* XXX: on x86_64, we do not want to nullify FS and GS because
2571	they may still contain a valid base. I would be interested to
2572	know how a real x86_64 CPU behaves */
2573	if ((seg_reg == R_FS \|\| seg_reg == R_GS) &&
2574	(env->segs[seg_reg].selector & 0xfffc) == 0)
2575	return;
2576
2577	e2 = env->segs[seg_reg].flags;
2578	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2579	if (!(e2 & DESC_CS_MASK) \|\| !(e2 & DESC_C_MASK)) {
2580	/* data or non conforming code segment */
2581	if (dpl < cpl) {
2582	cpu_x86_load_seg_cache(env, seg_reg, 0, 0, 0, 0);
2583	}
2584	}
2585	}
2586
2587	/* protected mode iret */
2588	static inline void helper_ret_protected(int shift, int is_iret, int addend)
2589	{
2590	uint32_t new_cs, new_eflags, new_ss;
2591	uint32_t new_es, new_ds, new_fs, new_gs;
2592	uint32_t e1, e2, ss_e1, ss_e2;
2593	int cpl, dpl, rpl, eflags_mask, iopl;
2594	target_ulong ssp, sp, new_eip, new_esp, sp_mask;
2595
2596	#ifdef TARGET_X86_64
2597	if (shift == 2)
2598	sp_mask = -1;
2599	else
2600	#endif
2601	sp_mask = get_sp_mask(env->segs[R_SS].flags);
2602	sp = ESP;
2603	ssp = env->segs[R_SS].base;
2604	new_eflags = 0; /* avoid warning */
2605	#ifdef TARGET_X86_64
2606	if (shift == 2) {
2607	POPQ(sp, new_eip);
2608	POPQ(sp, new_cs);
2609	new_cs &= 0xffff;
2610	if (is_iret) {
2611	POPQ(sp, new_eflags);
2612	}
2613	} else
2614	#endif
2615	if (shift == 1) {
2616	/* 32 bits */
2617	POPL(ssp, sp, sp_mask, new_eip);
2618	POPL(ssp, sp, sp_mask, new_cs);
2619	new_cs &= 0xffff;
2620	if (is_iret) {
2621	POPL(ssp, sp, sp_mask, new_eflags);
2622	#if defined(VBOX) && defined(DEBUG)
2623	printf("iret: new CS %04X\n", new_cs);
2624	printf("iret: new EIP %08X\n", new_eip);
2625	printf("iret: new EFLAGS %08X\n", new_eflags);
2626	printf("iret: EAX=%08x\n", EAX);
2627	#endif
2628
2629	if (new_eflags & VM_MASK)
2630	goto return_to_vm86;
2631	}
2632	#ifdef VBOX
2633	if ((new_cs & 0x3) == 1 && (env->state & CPU_RAW_RING0))
2634	{
2635	#ifdef DEBUG
2636	printf("RPL 1 -> new_cs %04X -> %04X\n", new_cs, new_cs & 0xfffc);
2637	#endif
2638	new_cs = new_cs & 0xfffc;
2639	}
2640	#endif
2641	} else {
2642	/* 16 bits */
2643	POPW(ssp, sp, sp_mask, new_eip);
2644	POPW(ssp, sp, sp_mask, new_cs);
2645	if (is_iret)
2646	POPW(ssp, sp, sp_mask, new_eflags);
2647	}
2648	#ifdef DEBUG_PCALL
2649	if (loglevel & CPU_LOG_PCALL) {
2650	fprintf(logfile, "lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
2651	new_cs, new_eip, shift, addend);
2652	cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
2653	}
2654	#endif
2655	if ((new_cs & 0xfffc) == 0)
2656	{
2657	#if defined(VBOX) && defined(DEBUG)
2658	printf("new_cs & 0xfffc) == 0\n");
2659	#endif
2660	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2661	}
2662	if (load_segment(&e1, &e2, new_cs) != 0)
2663	{
2664	#if defined(VBOX) && defined(DEBUG)
2665	printf("load_segment failed\n");
2666	#endif
2667	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2668	}
2669	if (!(e2 & DESC_S_MASK) \|\|
2670	!(e2 & DESC_CS_MASK))
2671	{
2672	#if defined(VBOX) && defined(DEBUG)
2673	printf("e2 mask %08x\n", e2);
2674	#endif
2675	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2676	}
2677	cpl = env->hflags & HF_CPL_MASK;
2678	rpl = new_cs & 3;
2679	if (rpl < cpl)
2680	{
2681	#if defined(VBOX) && defined(DEBUG)
2682	printf("rpl < cpl (%d vs %d)\n", rpl, cpl);
2683	#endif
2684	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2685	}
2686	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2687	if (e2 & DESC_C_MASK) {
2688	if (dpl > rpl)
2689	{
2690	#if defined(VBOX) && defined(DEBUG)
2691	printf("dpl > rpl (%d vs %d)\n", dpl, rpl);
2692	#endif
2693	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2694	}
2695	} else {
2696	if (dpl != rpl)
2697	{
2698	#if defined(VBOX) && defined(DEBUG)
2699	printf("dpl != rpl (%d vs %d) e1=%x e2=%x\n", dpl, rpl, e1, e2);
2700	#endif
2701	raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
2702	}
2703	}
2704	if (!(e2 & DESC_P_MASK))
2705	{
2706	#if defined(VBOX) && defined(DEBUG)
2707	printf("DESC_P_MASK e2=%08x\n", e2);
2708	#endif
2709	raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
2710	}
2711	sp += addend;
2712	if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) \|\|
2713	((env->hflags & HF_CS64_MASK) && !is_iret))) {
2714	/* return to same priledge level */
2715	cpu_x86_load_seg_cache(env, R_CS, new_cs,
2716	get_seg_base(e1, e2),
2717	get_seg_limit(e1, e2),
2718	e2);
2719	} else {
2720	/* return to different priviledge level */
2721	#ifdef TARGET_X86_64
2722	if (shift == 2) {
2723	POPQ(sp, new_esp);
2724	POPQ(sp, new_ss);
2725	new_ss &= 0xffff;
2726	} else
2727	#endif
2728	if (shift == 1) {
2729	/* 32 bits */
2730	POPL(ssp, sp, sp_mask, new_esp);
2731	POPL(ssp, sp, sp_mask, new_ss);
2732	new_ss &= 0xffff;
2733	} else {
2734	/* 16 bits */
2735	POPW(ssp, sp, sp_mask, new_esp);
2736	POPW(ssp, sp, sp_mask, new_ss);
2737	}
2738	#ifdef DEBUG_PCALL
2739	if (loglevel & CPU_LOG_PCALL) {
2740	fprintf(logfile, "new ss:esp=%04x:" TARGET_FMT_lx "\n",
2741	new_ss, new_esp);
2742	}
2743	#endif
2744	if ((new_ss & 0xfffc) == 0) {
2745	#ifdef TARGET_X86_64
2746	/* NULL ss is allowed in long mode if cpl != 3*/
2747	/* XXX: test CS64 ? */
2748	if ((env->hflags & HF_LMA_MASK) && rpl != 3) {
2749	cpu_x86_load_seg_cache(env, R_SS, new_ss,
2750	0, 0xffffffff,
2751	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
2752	DESC_S_MASK \| (rpl << DESC_DPL_SHIFT) \|
2753	DESC_W_MASK \| DESC_A_MASK);
2754	ss_e2 = DESC_B_MASK; /* XXX: should not be needed ? */
2755	} else
2756	#endif
2757	{
2758	raise_exception_err(EXCP0D_GPF, 0);
2759	}
2760	} else {
2761	if ((new_ss & 3) != rpl)
2762	raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2763	if (load_segment(&ss_e1, &ss_e2, new_ss) != 0)
2764	raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2765	if (!(ss_e2 & DESC_S_MASK) \|\|
2766	(ss_e2 & DESC_CS_MASK) \|\|
2767	!(ss_e2 & DESC_W_MASK))
2768	raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2769	dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
2770	if (dpl != rpl)
2771	raise_exception_err(EXCP0D_GPF, new_ss & 0xfffc);
2772	if (!(ss_e2 & DESC_P_MASK))
2773	raise_exception_err(EXCP0B_NOSEG, new_ss & 0xfffc);
2774	cpu_x86_load_seg_cache(env, R_SS, new_ss,
2775	get_seg_base(ss_e1, ss_e2),
2776	get_seg_limit(ss_e1, ss_e2),
2777	ss_e2);
2778	}
2779
2780	cpu_x86_load_seg_cache(env, R_CS, new_cs,
2781	get_seg_base(e1, e2),
2782	get_seg_limit(e1, e2),
2783	e2);
2784	cpu_x86_set_cpl(env, rpl);
2785	sp = new_esp;
2786	#ifdef TARGET_X86_64
2787	if (env->hflags & HF_CS64_MASK)
2788	sp_mask = -1;
2789	else
2790	#endif
2791	sp_mask = get_sp_mask(ss_e2);
2792
2793	/* validate data segments */
2794	validate_seg(R_ES, rpl);
2795	validate_seg(R_DS, rpl);
2796	validate_seg(R_FS, rpl);
2797	validate_seg(R_GS, rpl);
2798
2799	sp += addend;
2800	}
2801	SET_ESP(sp, sp_mask);
2802	env->eip = new_eip;
2803	if (is_iret) {
2804	/* NOTE: 'cpl' is the _old_ CPL */
2805	eflags_mask = TF_MASK \| AC_MASK \| ID_MASK \| RF_MASK \| NT_MASK;
2806	if (cpl == 0)
2807	#ifdef VBOX
2808	eflags_mask \|= IOPL_MASK \| VIF_MASK \| VIP_MASK;
2809	#else
2810	eflags_mask \|= IOPL_MASK;
2811	#endif
2812	iopl = (env->eflags >> IOPL_SHIFT) & 3;
2813	if (cpl <= iopl)
2814	eflags_mask \|= IF_MASK;
2815	if (shift == 0)
2816	eflags_mask &= 0xffff;
2817	load_eflags(new_eflags, eflags_mask);
2818	}
2819	return;
2820
2821	return_to_vm86:
2822
2823	#if 0 // defined(VBOX) && defined(DEBUG)
2824	printf("V86: new CS %04X\n", new_cs);
2825	printf("V86: Descriptor %08X:%08X\n", e2, e1);
2826	printf("V86: new EIP %08X\n", new_eip);
2827	printf("V86: new EFLAGS %08X\n", new_eflags);
2828	#endif
2829
2830	POPL(ssp, sp, sp_mask, new_esp);
2831	POPL(ssp, sp, sp_mask, new_ss);
2832	POPL(ssp, sp, sp_mask, new_es);
2833	POPL(ssp, sp, sp_mask, new_ds);
2834	POPL(ssp, sp, sp_mask, new_fs);
2835	POPL(ssp, sp, sp_mask, new_gs);
2836
2837	/* modify processor state */
2838	load_eflags(new_eflags, TF_MASK \| AC_MASK \| ID_MASK \|
2839	IF_MASK \| IOPL_MASK \| VM_MASK \| NT_MASK \| VIF_MASK \| VIP_MASK);
2840	load_seg_vm(R_CS, new_cs & 0xffff);
2841	cpu_x86_set_cpl(env, 3);
2842	load_seg_vm(R_SS, new_ss & 0xffff);
2843	load_seg_vm(R_ES, new_es & 0xffff);
2844	load_seg_vm(R_DS, new_ds & 0xffff);
2845	load_seg_vm(R_FS, new_fs & 0xffff);
2846	load_seg_vm(R_GS, new_gs & 0xffff);
2847
2848	env->eip = new_eip & 0xffff;
2849	ESP = new_esp;
2850	}
2851
2852	void helper_iret_protected(int shift, int next_eip)
2853	{
2854	int tss_selector, type;
2855	uint32_t e1, e2;
2856
2857	#ifdef VBOX
2858	remR3TrapClear(env->pVM);
2859	#endif
2860
2861	/* specific case for TSS */
2862	if (env->eflags & NT_MASK) {
2863	#ifdef TARGET_X86_64
2864	if (env->hflags & HF_LMA_MASK)
2865	raise_exception_err(EXCP0D_GPF, 0);
2866	#endif
2867	tss_selector = lduw_kernel(env->tr.base + 0);
2868	if (tss_selector & 4)
2869	raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2870	if (load_segment(&e1, &e2, tss_selector) != 0)
2871	raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2872	type = (e2 >> DESC_TYPE_SHIFT) & 0x17;
2873	/* NOTE: we check both segment and busy TSS */
2874	if (type != 3)
2875	raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);
2876	switch_tss(tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip);
2877	} else {
2878	helper_ret_protected(shift, 1, 0);
2879	}
2880	#ifdef USE_KQEMU
2881	if (kqemu_is_ok(env)) {
2882	CC_OP = CC_OP_EFLAGS;
2883	env->exception_index = -1;
2884	cpu_loop_exit();
2885	}
2886	#endif
2887	}
2888
2889	void helper_lret_protected(int shift, int addend)
2890	{
2891	helper_ret_protected(shift, 0, addend);
2892	#ifdef USE_KQEMU
2893	if (kqemu_is_ok(env)) {
2894	env->exception_index = -1;
2895	cpu_loop_exit();
2896	}
2897	#endif
2898	}
2899
2900	void helper_sysenter(void)
2901	{
2902	if (env->sysenter_cs == 0) {
2903	raise_exception_err(EXCP0D_GPF, 0);
2904	}
2905	env->eflags &= ~(VM_MASK \| IF_MASK \| RF_MASK);
2906	cpu_x86_set_cpl(env, 0);
2907	cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2908	0, 0xffffffff,
2909	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
2910	DESC_S_MASK \|
2911	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK);
2912	cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc,
2913	0, 0xffffffff,
2914	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
2915	DESC_S_MASK \|
2916	DESC_W_MASK \| DESC_A_MASK);
2917	ESP = env->sysenter_esp;
2918	EIP = env->sysenter_eip;
2919	}
2920
2921	void helper_sysexit(void)
2922	{
2923	int cpl;
2924
2925	cpl = env->hflags & HF_CPL_MASK;
2926	if (env->sysenter_cs == 0 \|\| cpl != 0) {
2927	raise_exception_err(EXCP0D_GPF, 0);
2928	}
2929	cpu_x86_set_cpl(env, 3);
2930	cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) \| 3,
2931	0, 0xffffffff,
2932	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
2933	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
2934	DESC_CS_MASK \| DESC_R_MASK \| DESC_A_MASK);
2935	cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) \| 3,
2936	0, 0xffffffff,
2937	DESC_G_MASK \| DESC_B_MASK \| DESC_P_MASK \|
2938	DESC_S_MASK \| (3 << DESC_DPL_SHIFT) \|
2939	DESC_W_MASK \| DESC_A_MASK);
2940	ESP = ECX;
2941	EIP = EDX;
2942	#ifdef USE_KQEMU
2943	if (kqemu_is_ok(env)) {
2944	env->exception_index = -1;
2945	cpu_loop_exit();
2946	}
2947	#endif
2948	}
2949
2950	void helper_movl_crN_T0(int reg)
2951	{
2952	#if !defined(CONFIG_USER_ONLY)
2953	switch(reg) {
2954	case 0:
2955	cpu_x86_update_cr0(env, T0);
2956	break;
2957	case 3:
2958	cpu_x86_update_cr3(env, T0);
2959	break;
2960	case 4:
2961	cpu_x86_update_cr4(env, T0);
2962	break;
2963	case 8:
2964	cpu_set_apic_tpr(env, T0);
2965	break;
2966	default:
2967	env->cr[reg] = T0;
2968	break;
2969	}
2970	#endif
2971	}
2972
2973	/* XXX: do more */
2974	void helper_movl_drN_T0(int reg)
2975	{
2976	env->dr[reg] = T0;
2977	}
2978
2979	void helper_invlpg(target_ulong addr)
2980	{
2981	cpu_x86_flush_tlb(env, addr);
2982	}
2983
2984	void helper_rdtsc(void)
2985	{
2986	uint64_t val;
2987
2988	if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
2989	raise_exception(EXCP0D_GPF);
2990	}
2991	val = cpu_get_tsc(env);
2992	EAX = (uint32_t)(val);
2993	EDX = (uint32_t)(val >> 32);
2994	}
2995
2996	#if defined(CONFIG_USER_ONLY)
2997	void helper_wrmsr(void)
2998	{
2999	}
3000
3001	void helper_rdmsr(void)
3002	{
3003	}
3004	#else
3005	void helper_wrmsr(void)
3006	{
3007	uint64_t val;
3008
3009	val = ((uint32_t)EAX) \| ((uint64_t)((uint32_t)EDX) << 32);
3010
3011	switch((uint32_t)ECX) {
3012	case MSR_IA32_SYSENTER_CS:
3013	env->sysenter_cs = val & 0xffff;
3014	break;
3015	case MSR_IA32_SYSENTER_ESP:
3016	env->sysenter_esp = val;
3017	break;
3018	case MSR_IA32_SYSENTER_EIP:
3019	env->sysenter_eip = val;
3020	break;
3021	case MSR_IA32_APICBASE:
3022	cpu_set_apic_base(env, val);
3023	break;
3024	case MSR_EFER:
3025	{
3026	uint64_t update_mask;
3027	update_mask = 0;
3028	if (env->cpuid_ext2_features & CPUID_EXT2_SYSCALL)
3029	update_mask \|= MSR_EFER_SCE;
3030	if (env->cpuid_ext2_features & CPUID_EXT2_LM)
3031	update_mask \|= MSR_EFER_LME;
3032	if (env->cpuid_ext2_features & CPUID_EXT2_FFXSR)
3033	update_mask \|= MSR_EFER_FFXSR;
3034	if (env->cpuid_ext2_features & CPUID_EXT2_NX)
3035	update_mask \|= MSR_EFER_NXE;
3036	env->efer = (env->efer & ~update_mask) \|
3037	(val & update_mask);
3038	}
3039	break;
3040	case MSR_STAR:
3041	env->star = val;
3042	break;
3043	case MSR_PAT:
3044	env->pat = val;
3045	break;
3046	#ifdef TARGET_X86_64
3047	case MSR_LSTAR:
3048	env->lstar = val;
3049	break;
3050	case MSR_CSTAR:
3051	env->cstar = val;
3052	break;
3053	case MSR_FMASK:
3054	env->fmask = val;
3055	break;
3056	case MSR_FSBASE:
3057	env->segs[R_FS].base = val;
3058	break;
3059	case MSR_GSBASE:
3060	env->segs[R_GS].base = val;
3061	break;
3062	case MSR_KERNELGSBASE:
3063	env->kernelgsbase = val;
3064	break;
3065	#endif
3066	default:
3067	/* XXX: exception ? */
3068	break;
3069	}
3070	}
3071
3072	void helper_rdmsr(void)
3073	{
3074	uint64_t val;
3075	switch((uint32_t)ECX) {
3076	case MSR_IA32_SYSENTER_CS:
3077	val = env->sysenter_cs;
3078	break;
3079	case MSR_IA32_SYSENTER_ESP:
3080	val = env->sysenter_esp;
3081	break;
3082	case MSR_IA32_SYSENTER_EIP:
3083	val = env->sysenter_eip;
3084	break;
3085	case MSR_IA32_APICBASE:
3086	val = cpu_get_apic_base(env);
3087	break;
3088	case MSR_EFER:
3089	val = env->efer;
3090	break;
3091	case MSR_STAR:
3092	val = env->star;
3093	break;
3094	case MSR_PAT:
3095	val = env->pat;
3096	break;
3097	#ifdef TARGET_X86_64
3098	case MSR_LSTAR:
3099	val = env->lstar;
3100	break;
3101	case MSR_CSTAR:
3102	val = env->cstar;
3103	break;
3104	case MSR_FMASK:
3105	val = env->fmask;
3106	break;
3107	case MSR_FSBASE:
3108	val = env->segs[R_FS].base;
3109	break;
3110	case MSR_GSBASE:
3111	val = env->segs[R_GS].base;
3112	break;
3113	case MSR_KERNELGSBASE:
3114	val = env->kernelgsbase;
3115	break;
3116	#endif
3117	default:
3118	/* XXX: exception ? */
3119	val = 0;
3120	break;
3121	}
3122	EAX = (uint32_t)(val);
3123	EDX = (uint32_t)(val >> 32);
3124	}
3125	#endif
3126
3127	void helper_lsl(void)
3128	{
3129	unsigned int selector, limit;
3130	uint32_t e1, e2, eflags;
3131	int rpl, dpl, cpl, type;
3132
3133	eflags = cc_table[CC_OP].compute_all();
3134	selector = T0 & 0xffff;
3135	if (load_segment(&e1, &e2, selector) != 0)
3136	goto fail;
3137	rpl = selector & 3;
3138	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
3139	cpl = env->hflags & HF_CPL_MASK;
3140	if (e2 & DESC_S_MASK) {
3141	if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
3142	/* conforming */
3143	} else {
3144	if (dpl < cpl \|\| dpl < rpl)
3145	goto fail;
3146	}
3147	} else {
3148	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
3149	switch(type) {
3150	case 1:
3151	case 2:
3152	case 3:
3153	case 9:
3154	case 11:
3155	break;
3156	default:
3157	goto fail;
3158	}
3159	if (dpl < cpl \|\| dpl < rpl) {
3160	fail:
3161	CC_SRC = eflags & ~CC_Z;
3162	return;
3163	}
3164	}
3165	limit = get_seg_limit(e1, e2);
3166	T1 = limit;
3167	CC_SRC = eflags \| CC_Z;
3168	}
3169
3170	void helper_lar(void)
3171	{
3172	unsigned int selector;
3173	uint32_t e1, e2, eflags;
3174	int rpl, dpl, cpl, type;
3175
3176	eflags = cc_table[CC_OP].compute_all();
3177	selector = T0 & 0xffff;
3178	if ((selector & 0xfffc) == 0)
3179	goto fail;
3180	if (load_segment(&e1, &e2, selector) != 0)
3181	goto fail;
3182	rpl = selector & 3;
3183	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
3184	cpl = env->hflags & HF_CPL_MASK;
3185	if (e2 & DESC_S_MASK) {
3186	if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
3187	/* conforming */
3188	} else {
3189	if (dpl < cpl \|\| dpl < rpl)
3190	goto fail;
3191	}
3192	} else {
3193	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
3194	switch(type) {
3195	case 1:
3196	case 2:
3197	case 3:
3198	case 4:
3199	case 5:
3200	case 9:
3201	case 11:
3202	case 12:
3203	break;
3204	default:
3205	goto fail;
3206	}
3207	if (dpl < cpl \|\| dpl < rpl) {
3208	fail:
3209	CC_SRC = eflags & ~CC_Z;
3210	return;
3211	}
3212	}
3213	T1 = e2 & 0x00f0ff00;
3214	CC_SRC = eflags \| CC_Z;
3215	}
3216
3217	void helper_verr(void)
3218	{
3219	unsigned int selector;
3220	uint32_t e1, e2, eflags;
3221	int rpl, dpl, cpl;
3222
3223	eflags = cc_table[CC_OP].compute_all();
3224	selector = T0 & 0xffff;
3225	if ((selector & 0xfffc) == 0)
3226	goto fail;
3227	if (load_segment(&e1, &e2, selector) != 0)
3228	goto fail;
3229	if (!(e2 & DESC_S_MASK))
3230	goto fail;
3231	rpl = selector & 3;
3232	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
3233	cpl = env->hflags & HF_CPL_MASK;
3234	if (e2 & DESC_CS_MASK) {
3235	if (!(e2 & DESC_R_MASK))
3236	goto fail;
3237	if (!(e2 & DESC_C_MASK)) {
3238	if (dpl < cpl \|\| dpl < rpl)
3239	goto fail;
3240	}
3241	} else {
3242	if (dpl < cpl \|\| dpl < rpl) {
3243	fail:
3244	CC_SRC = eflags & ~CC_Z;
3245	return;
3246	}
3247	}
3248	CC_SRC = eflags \| CC_Z;
3249	}
3250
3251	void helper_verw(void)
3252	{
3253	unsigned int selector;
3254	uint32_t e1, e2, eflags;
3255	int rpl, dpl, cpl;
3256
3257	eflags = cc_table[CC_OP].compute_all();
3258	selector = T0 & 0xffff;
3259	if ((selector & 0xfffc) == 0)
3260	goto fail;
3261	if (load_segment(&e1, &e2, selector) != 0)
3262	goto fail;
3263	if (!(e2 & DESC_S_MASK))
3264	goto fail;
3265	rpl = selector & 3;
3266	dpl = (e2 >> DESC_DPL_SHIFT) & 3;
3267	cpl = env->hflags & HF_CPL_MASK;
3268	if (e2 & DESC_CS_MASK) {
3269	goto fail;
3270	} else {
3271	if (dpl < cpl \|\| dpl < rpl)
3272	goto fail;
3273	if (!(e2 & DESC_W_MASK)) {
3274	fail:
3275	CC_SRC = eflags & ~CC_Z;
3276	return;
3277	}
3278	}
3279	CC_SRC = eflags \| CC_Z;
3280	}
3281
3282	/* FPU helpers */
3283
3284	void helper_fldt_ST0_A0(void)
3285	{
3286	int new_fpstt;
3287	new_fpstt = (env->fpstt - 1) & 7;
3288	env->fpregs[new_fpstt].d = helper_fldt(A0);
3289	env->fpstt = new_fpstt;
3290	env->fptags[new_fpstt] = 0; /* validate stack entry */
3291	}
3292
3293	void helper_fstt_ST0_A0(void)
3294	{
3295	helper_fstt(ST0, A0);
3296	}
3297
3298	void fpu_set_exception(int mask)
3299	{
3300	env->fpus \|= mask;
3301	if (env->fpus & (~env->fpuc & FPUC_EM))
3302	env->fpus \|= FPUS_SE \| FPUS_B;
3303	}
3304
3305	CPU86_LDouble helper_fdiv(CPU86_LDouble a, CPU86_LDouble b)
3306	{
3307	if (b == 0.0)
3308	fpu_set_exception(FPUS_ZE);
3309	return a / b;
3310	}
3311
3312	void fpu_raise_exception(void)
3313	{
3314	if (env->cr[0] & CR0_NE_MASK) {
3315	raise_exception(EXCP10_COPR);
3316	}
3317	#if !defined(CONFIG_USER_ONLY)
3318	else {
3319	cpu_set_ferr(env);
3320	}
3321	#endif
3322	}
3323
3324	/* BCD ops */
3325
3326	void helper_fbld_ST0_A0(void)
3327	{
3328	CPU86_LDouble tmp;
3329	uint64_t val;
3330	unsigned int v;
3331	int i;
3332
3333	val = 0;
3334	for(i = 8; i >= 0; i--) {
3335	v = ldub(A0 + i);
3336	val = (val * 100) + ((v >> 4) * 10) + (v & 0xf);
3337	}
3338	tmp = val;
3339	if (ldub(A0 + 9) & 0x80)
3340	tmp = -tmp;
3341	fpush();
3342	ST0 = tmp;
3343	}
3344
3345	void helper_fbst_ST0_A0(void)
3346	{
3347	int v;
3348	target_ulong mem_ref, mem_end;
3349	int64_t val;
3350
3351	val = floatx_to_int64(ST0, &env->fp_status);
3352	mem_ref = A0;
3353	mem_end = mem_ref + 9;
3354	if (val < 0) {
3355	stb(mem_end, 0x80);
3356	val = -val;
3357	} else {
3358	stb(mem_end, 0x00);
3359	}
3360	while (mem_ref < mem_end) {
3361	if (val == 0)
3362	break;
3363	v = val % 100;
3364	val = val / 100;
3365	v = ((v / 10) << 4) \| (v % 10);
3366	stb(mem_ref++, v);
3367	}
3368	while (mem_ref < mem_end) {
3369	stb(mem_ref++, 0);
3370	}
3371	}
3372
3373	void helper_f2xm1(void)
3374	{
3375	ST0 = pow(2.0,ST0) - 1.0;
3376	}
3377
3378	void helper_fyl2x(void)
3379	{
3380	CPU86_LDouble fptemp;
3381
3382	fptemp = ST0;
3383	if (fptemp>0.0){
3384	fptemp = log(fptemp)/log(2.0); /* log2(ST) */
3385	ST1 *= fptemp;
3386	fpop();
3387	} else {
3388	env->fpus &= (~0x4700);
3389	env->fpus \|= 0x400;
3390	}
3391	}
3392
3393	void helper_fptan(void)
3394	{
3395	CPU86_LDouble fptemp;
3396
3397	fptemp = ST0;
3398	if((fptemp > MAXTAN)\|\|(fptemp < -MAXTAN)) {
3399	env->fpus \|= 0x400;
3400	} else {
3401	ST0 = tan(fptemp);
3402	fpush();
3403	ST0 = 1.0;
3404	env->fpus &= (~0x400); /* C2 <-- 0 */
3405	/* the above code is for \|arg\| < 2*52 only /
3406	}
3407	}
3408
3409	void helper_fpatan(void)
3410	{
3411	CPU86_LDouble fptemp, fpsrcop;
3412
3413	fpsrcop = ST1;
3414	fptemp = ST0;
3415	ST1 = atan2(fpsrcop,fptemp);
3416	fpop();
3417	}
3418
3419	void helper_fxtract(void)
3420	{
3421	CPU86_LDoubleU temp;
3422	unsigned int expdif;
3423
3424	temp.d = ST0;
3425	expdif = EXPD(temp) - EXPBIAS;
3426	/DP exponent bias/
3427	ST0 = expdif;
3428	fpush();
3429	BIASEXPONENT(temp);
3430	ST0 = temp.d;
3431	}
3432
3433	void helper_fprem1(void)
3434	{
3435	CPU86_LDouble dblq, fpsrcop, fptemp;
3436	CPU86_LDoubleU fpsrcop1, fptemp1;
3437	int expdif;
3438	int q;
3439
3440	fpsrcop = ST0;
3441	fptemp = ST1;
3442	fpsrcop1.d = fpsrcop;
3443	fptemp1.d = fptemp;
3444	expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
3445	if (expdif < 53) {
3446	dblq = fpsrcop / fptemp;
3447	dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
3448	ST0 = fpsrcop - fptemp*dblq;
3449	q = (int)dblq; /* cutting off top bits is assumed here */
3450	env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3451	/* (C0,C1,C3) <-- (q2,q1,q0) */
3452	env->fpus \|= (q&0x4) << 6; /* (C0) <-- q2 */
3453	env->fpus \|= (q&0x2) << 8; /* (C1) <-- q1 */
3454	env->fpus \|= (q&0x1) << 14; /* (C3) <-- q0 */
3455	} else {
3456	env->fpus \|= 0x400; /* C2 <-- 1 */
3457	fptemp = pow(2.0, expdif-50);
3458	fpsrcop = (ST0 / ST1) / fptemp;
3459	/* fpsrcop = integer obtained by rounding to the nearest */
3460	fpsrcop = (fpsrcop-floor(fpsrcop) < ceil(fpsrcop)-fpsrcop)?
3461	floor(fpsrcop): ceil(fpsrcop);
3462	ST0 -= (ST1 * fpsrcop * fptemp);
3463	}
3464	}
3465
3466	void helper_fprem(void)
3467	{
3468	CPU86_LDouble dblq, fpsrcop, fptemp;
3469	CPU86_LDoubleU fpsrcop1, fptemp1;
3470	int expdif;
3471	int q;
3472
3473	fpsrcop = ST0;
3474	fptemp = ST1;
3475	fpsrcop1.d = fpsrcop;
3476	fptemp1.d = fptemp;
3477	expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
3478	if ( expdif < 53 ) {
3479	dblq = fpsrcop / fptemp;
3480	dblq = (dblq < 0.0)? ceil(dblq): floor(dblq);
3481	ST0 = fpsrcop - fptemp*dblq;
3482	q = (int)dblq; /* cutting off top bits is assumed here */
3483	env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3484	/* (C0,C1,C3) <-- (q2,q1,q0) */
3485	env->fpus \|= (q&0x4) << 6; /* (C0) <-- q2 */
3486	env->fpus \|= (q&0x2) << 8; /* (C1) <-- q1 */
3487	env->fpus \|= (q&0x1) << 14; /* (C3) <-- q0 */
3488	} else {
3489	env->fpus \|= 0x400; /* C2 <-- 1 */
3490	fptemp = pow(2.0, expdif-50);
3491	fpsrcop = (ST0 / ST1) / fptemp;
3492	/* fpsrcop = integer obtained by chopping */
3493	fpsrcop = (fpsrcop < 0.0)?
3494	-(floor(fabs(fpsrcop))): floor(fpsrcop);
3495	ST0 -= (ST1 * fpsrcop * fptemp);
3496	}
3497	}
3498
3499	void helper_fyl2xp1(void)
3500	{
3501	CPU86_LDouble fptemp;
3502
3503	fptemp = ST0;
3504	if ((fptemp+1.0)>0.0) {
3505	fptemp = log(fptemp+1.0) / log(2.0); /* log2(ST+1.0) */
3506	ST1 *= fptemp;
3507	fpop();
3508	} else {
3509	env->fpus &= (~0x4700);
3510	env->fpus \|= 0x400;
3511	}
3512	}
3513
3514	void helper_fsqrt(void)
3515	{
3516	CPU86_LDouble fptemp;
3517
3518	fptemp = ST0;
3519	if (fptemp<0.0) {
3520	env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3521	env->fpus \|= 0x400;
3522	}
3523	ST0 = sqrt(fptemp);
3524	}
3525
3526	void helper_fsincos(void)
3527	{
3528	CPU86_LDouble fptemp;
3529
3530	fptemp = ST0;
3531	if ((fptemp > MAXTAN)\|\|(fptemp < -MAXTAN)) {
3532	env->fpus \|= 0x400;
3533	} else {
3534	ST0 = sin(fptemp);
3535	fpush();
3536	ST0 = cos(fptemp);
3537	env->fpus &= (~0x400); /* C2 <-- 0 */
3538	/* the above code is for \|arg\| < 2*63 only /
3539	}
3540	}
3541
3542	void helper_frndint(void)
3543	{
3544	ST0 = floatx_round_to_int(ST0, &env->fp_status);
3545	}
3546
3547	void helper_fscale(void)
3548	{
3549	ST0 = ldexp (ST0, (int)(ST1));
3550	}
3551
3552	void helper_fsin(void)
3553	{
3554	CPU86_LDouble fptemp;
3555
3556	fptemp = ST0;
3557	if ((fptemp > MAXTAN)\|\|(fptemp < -MAXTAN)) {
3558	env->fpus \|= 0x400;
3559	} else {
3560	ST0 = sin(fptemp);
3561	env->fpus &= (~0x400); /* C2 <-- 0 */
3562	/* the above code is for \|arg\| < 2*53 only /
3563	}
3564	}
3565
3566	void helper_fcos(void)
3567	{
3568	CPU86_LDouble fptemp;
3569
3570	fptemp = ST0;
3571	if((fptemp > MAXTAN)\|\|(fptemp < -MAXTAN)) {
3572	env->fpus \|= 0x400;
3573	} else {
3574	ST0 = cos(fptemp);
3575	env->fpus &= (~0x400); /* C2 <-- 0 */
3576	/* the above code is for \|arg5 < 2*63 only /
3577	}
3578	}
3579
3580	void helper_fxam_ST0(void)
3581	{
3582	CPU86_LDoubleU temp;
3583	int expdif;
3584
3585	temp.d = ST0;
3586
3587	env->fpus &= (~0x4700); /* (C3,C2,C1,C0) <-- 0000 */
3588	if (SIGND(temp))
3589	env->fpus \|= 0x200; /* C1 <-- 1 */
3590
3591	/* XXX: test fptags too */
3592	expdif = EXPD(temp);
3593	if (expdif == MAXEXPD) {
3594	#ifdef USE_X86LDOUBLE
3595	if (MANTD(temp) == 0x8000000000000000ULL)
3596	#else
3597	if (MANTD(temp) == 0)
3598	#endif
3599	env->fpus \|= 0x500 /Infinity/;
3600	else
3601	env->fpus \|= 0x100 /NaN/;
3602	} else if (expdif == 0) {
3603	if (MANTD(temp) == 0)
3604	env->fpus \|= 0x4000 /Zero/;
3605	else
3606	env->fpus \|= 0x4400 /Denormal/;
3607	} else {
3608	env->fpus \|= 0x400;
3609	}
3610	}
3611
3612	void helper_fstenv(target_ulong ptr, int data32)
3613	{
3614	int fpus, fptag, exp, i;
3615	uint64_t mant;
3616	CPU86_LDoubleU tmp;
3617
3618	fpus = (env->fpus & ~0x3800) \| (env->fpstt & 0x7) << 11;
3619	fptag = 0;
3620	for (i=7; i>=0; i--) {
3621	fptag <<= 2;
3622	if (env->fptags[i]) {
3623	fptag \|= 3;
3624	} else {
3625	tmp.d = env->fpregs[i].d;
3626	exp = EXPD(tmp);
3627	mant = MANTD(tmp);
3628	if (exp == 0 && mant == 0) {
3629	/* zero */
3630	fptag \|= 1;
3631	} else if (exp == 0 \|\| exp == MAXEXPD
3632	#ifdef USE_X86LDOUBLE
3633	\|\| (mant & (1LL << 63)) == 0
3634	#endif
3635	) {
3636	/* NaNs, infinity, denormal */
3637	fptag \|= 2;
3638	}
3639	}
3640	}
3641	if (data32) {
3642	/* 32 bit */
3643	stl(ptr, env->fpuc);
3644	stl(ptr + 4, fpus);
3645	stl(ptr + 8, fptag);
3646	stl(ptr + 12, 0); /* fpip */
3647	stl(ptr + 16, 0); /* fpcs */
3648	stl(ptr + 20, 0); /* fpoo */
3649	stl(ptr + 24, 0); /* fpos */
3650	} else {
3651	/* 16 bit */
3652	stw(ptr, env->fpuc);
3653	stw(ptr + 2, fpus);
3654	stw(ptr + 4, fptag);
3655	stw(ptr + 6, 0);
3656	stw(ptr + 8, 0);
3657	stw(ptr + 10, 0);
3658	stw(ptr + 12, 0);
3659	}
3660	}
3661
3662	void helper_fldenv(target_ulong ptr, int data32)
3663	{
3664	int i, fpus, fptag;
3665
3666	if (data32) {
3667	env->fpuc = lduw(ptr);
3668	fpus = lduw(ptr + 4);
3669	fptag = lduw(ptr + 8);
3670	}
3671	else {
3672	env->fpuc = lduw(ptr);
3673	fpus = lduw(ptr + 2);
3674	fptag = lduw(ptr + 4);
3675	}
3676	env->fpstt = (fpus >> 11) & 7;
3677	env->fpus = fpus & ~0x3800;
3678	for(i = 0;i < 8; i++) {
3679	env->fptags[i] = ((fptag & 3) == 3);
3680	fptag >>= 2;
3681	}
3682	}
3683
3684	void helper_fsave(target_ulong ptr, int data32)
3685	{
3686	CPU86_LDouble tmp;
3687	int i;
3688
3689	helper_fstenv(ptr, data32);
3690
3691	ptr += (14 << data32);
3692	for(i = 0;i < 8; i++) {
3693	tmp = ST(i);
3694	helper_fstt(tmp, ptr);
3695	ptr += 10;
3696	}
3697
3698	/* fninit */
3699	env->fpus = 0;
3700	env->fpstt = 0;
3701	env->fpuc = 0x37f;
3702	env->fptags[0] = 1;
3703	env->fptags[1] = 1;
3704	env->fptags[2] = 1;
3705	env->fptags[3] = 1;
3706	env->fptags[4] = 1;
3707	env->fptags[5] = 1;
3708	env->fptags[6] = 1;
3709	env->fptags[7] = 1;
3710	}
3711
3712	void helper_frstor(target_ulong ptr, int data32)
3713	{
3714	CPU86_LDouble tmp;
3715	int i;
3716
3717	helper_fldenv(ptr, data32);
3718	ptr += (14 << data32);
3719
3720	for(i = 0;i < 8; i++) {
3721	tmp = helper_fldt(ptr);
3722	ST(i) = tmp;
3723	ptr += 10;
3724	}
3725	}
3726
3727	void helper_fxsave(target_ulong ptr, int data64)
3728	{
3729	int fpus, fptag, i, nb_xmm_regs;
3730	CPU86_LDouble tmp;
3731	target_ulong addr;
3732
3733	fpus = (env->fpus & ~0x3800) \| (env->fpstt & 0x7) << 11;
3734	fptag = 0;
3735	for(i = 0; i < 8; i++) {
3736	fptag \|= (env->fptags[i] << i);
3737	}
3738	stw(ptr, env->fpuc);
3739	stw(ptr + 2, fpus);
3740	stw(ptr + 4, fptag ^ 0xff);
3741
3742	addr = ptr + 0x20;
3743	for(i = 0;i < 8; i++) {
3744	tmp = ST(i);
3745	helper_fstt(tmp, addr);
3746	addr += 16;
3747	}
3748
3749	if (env->cr[4] & CR4_OSFXSR_MASK) {
3750	/* XXX: finish it */
3751	stl(ptr + 0x18, env->mxcsr); /* mxcsr */
3752	stl(ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
3753	nb_xmm_regs = 8 << data64;
3754	addr = ptr + 0xa0;
3755	for(i = 0; i < nb_xmm_regs; i++) {
3756	stq(addr, env->xmm_regs[i].XMM_Q(0));
3757	stq(addr + 8, env->xmm_regs[i].XMM_Q(1));
3758	addr += 16;
3759	}
3760	}
3761	}
3762
3763	void helper_fxrstor(target_ulong ptr, int data64)
3764	{
3765	int i, fpus, fptag, nb_xmm_regs;
3766	CPU86_LDouble tmp;
3767	target_ulong addr;
3768
3769	env->fpuc = lduw(ptr);
3770	fpus = lduw(ptr + 2);
3771	fptag = lduw(ptr + 4);
3772	env->fpstt = (fpus >> 11) & 7;
3773	env->fpus = fpus & ~0x3800;
3774	fptag ^= 0xff;
3775	for(i = 0;i < 8; i++) {
3776	env->fptags[i] = ((fptag >> i) & 1);
3777	}
3778
3779	addr = ptr + 0x20;
3780	for(i = 0;i < 8; i++) {
3781	tmp = helper_fldt(addr);
3782	ST(i) = tmp;
3783	addr += 16;
3784	}
3785
3786	if (env->cr[4] & CR4_OSFXSR_MASK) {
3787	/* XXX: finish it */
3788	env->mxcsr = ldl(ptr + 0x18);
3789	//ldl(ptr + 0x1c);
3790	nb_xmm_regs = 8 << data64;
3791	addr = ptr + 0xa0;
3792	for(i = 0; i < nb_xmm_regs; i++) {
3793	#if !defined(VBOX) \|\| __GNUC__ < 4
3794	env->xmm_regs[i].XMM_Q(0) = ldq(addr);
3795	env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8);
3796	#else /* VBOX + __GNUC__ >= 4: gcc 4.x compiler bug - it runs out of registers for the 64-bit value. */
3797	# if 1
3798	env->xmm_regs[i].XMM_L(0) = ldl(addr);
3799	env->xmm_regs[i].XMM_L(1) = ldl(addr + 4);
3800	env->xmm_regs[i].XMM_L(2) = ldl(addr + 8);
3801	env->xmm_regs[i].XMM_L(3) = ldl(addr + 12);
3802	# else
3803	/* this works fine on Mac OS X, gcc 4.0.1 */
3804	uint64_t u64 = ldq(addr);
3805	env->xmm_regs[i].XMM_Q(0);
3806	u64 = ldq(addr + 4);
3807	env->xmm_regs[i].XMM_Q(1) = u64;
3808	# endif
3809	#endif
3810	addr += 16;
3811	}
3812	}
3813	}
3814
3815	#ifndef USE_X86LDOUBLE
3816
3817	void cpu_get_fp80(uint64_t pmant, uint16_t pexp, CPU86_LDouble f)
3818	{
3819	CPU86_LDoubleU temp;
3820	int e;
3821
3822	temp.d = f;
3823	/* mantissa */
3824	*pmant = (MANTD(temp) << 11) \| (1LL << 63);
3825	/* exponent + sign */
3826	e = EXPD(temp) - EXPBIAS + 16383;
3827	e \|= SIGND(temp) >> 16;
3828	*pexp = e;
3829	}
3830
3831	CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper)
3832	{
3833	CPU86_LDoubleU temp;
3834	int e;
3835	uint64_t ll;
3836
3837	/* XXX: handle overflow ? */
3838	e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */
3839	e \|= (upper >> 4) & 0x800; /* sign */
3840	ll = (mant >> 11) & ((1LL << 52) - 1);
3841	#ifdef __arm__
3842	temp.l.upper = (e << 20) \| (ll >> 32);
3843	temp.l.lower = ll;
3844	#else
3845	temp.ll = ll \| ((uint64_t)e << 52);
3846	#endif
3847	return temp.d;
3848	}
3849
3850	#else
3851
3852	void cpu_get_fp80(uint64_t pmant, uint16_t pexp, CPU86_LDouble f)
3853	{
3854	CPU86_LDoubleU temp;
3855
3856	temp.d = f;
3857	*pmant = temp.l.lower;
3858	*pexp = temp.l.upper;
3859	}
3860
3861	CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper)
3862	{
3863	CPU86_LDoubleU temp;
3864
3865	temp.l.upper = upper;
3866	temp.l.lower = mant;
3867	return temp.d;
3868	}
3869	#endif
3870
3871	#ifdef TARGET_X86_64
3872
3873	//#define DEBUG_MULDIV
3874
3875	static void add128(uint64_t plow, uint64_t phigh, uint64_t a, uint64_t b)
3876	{
3877	*plow += a;
3878	/* carry test */
3879	if (*plow < a)
3880	(*phigh)++;
3881	*phigh += b;
3882	}
3883
3884	static void neg128(uint64_t plow, uint64_t phigh)
3885	{
3886	plow = ~ plow;
3887	phigh = ~ phigh;
3888	add128(plow, phigh, 1, 0);
3889	}
3890
3891	static void mul64(uint64_t plow, uint64_t phigh, uint64_t a, uint64_t b)
3892	{
3893	uint32_t a0, a1, b0, b1;
3894	uint64_t v;
3895
3896	a0 = a;
3897	a1 = a >> 32;
3898
3899	b0 = b;
3900	b1 = b >> 32;
3901
3902	v = (uint64_t)a0 * (uint64_t)b0;
3903	*plow = v;
3904	*phigh = 0;
3905
3906	v = (uint64_t)a0 * (uint64_t)b1;
3907	add128(plow, phigh, v << 32, v >> 32);
3908
3909	v = (uint64_t)a1 * (uint64_t)b0;
3910	add128(plow, phigh, v << 32, v >> 32);
3911
3912	v = (uint64_t)a1 * (uint64_t)b1;
3913	*phigh += v;
3914	#ifdef DEBUG_MULDIV
3915	printf("mul: 0x%016" PRIx64 " * 0x%016" PRIx64 " = 0x%016" PRIx64 "%016" PRIx64 "\n",
3916	a, b, phigh, plow);
3917	#endif
3918	}
3919
3920	static void imul64(uint64_t plow, uint64_t phigh, int64_t a, int64_t b)
3921	{
3922	int sa, sb;
3923	sa = (a < 0);
3924	if (sa)
3925	a = -a;
3926	sb = (b < 0);
3927	if (sb)
3928	b = -b;
3929	mul64(plow, phigh, a, b);
3930	if (sa ^ sb) {
3931	neg128(plow, phigh);
3932	}
3933	}
3934
3935	/* return TRUE if overflow */
3936	static int div64(uint64_t plow, uint64_t phigh, uint64_t b)
3937	{
3938	uint64_t q, r, a1, a0;
3939	int i, qb, ab;
3940
3941	a0 = *plow;
3942	a1 = *phigh;
3943	if (a1 == 0) {
3944	q = a0 / b;
3945	r = a0 % b;
3946	*plow = q;
3947	*phigh = r;
3948	} else {
3949	if (a1 >= b)
3950	return 1;
3951	/* XXX: use a better algorithm */
3952	for(i = 0; i < 64; i++) {
3953	ab = a1 >> 63;
3954	a1 = (a1 << 1) \| (a0 >> 63);
3955	if (ab \|\| a1 >= b) {
3956	a1 -= b;
3957	qb = 1;
3958	} else {
3959	qb = 0;
3960	}
3961	a0 = (a0 << 1) \| qb;
3962	}
3963	#if defined(DEBUG_MULDIV)
3964	printf("div: 0x%016" PRIx64 "%016" PRIx64 " / 0x%016" PRIx64 ": q=0x%016" PRIx64 " r=0x%016" PRIx64 "\n",
3965	phigh, plow, b, a0, a1);
3966	#endif
3967	*plow = a0;
3968	*phigh = a1;
3969	}
3970	return 0;
3971	}
3972
3973	/* return TRUE if overflow */
3974	static int idiv64(uint64_t plow, uint64_t phigh, int64_t b)
3975	{
3976	int sa, sb;
3977	sa = ((int64_t)*phigh < 0);
3978	if (sa)
3979	neg128(plow, phigh);
3980	sb = (b < 0);
3981	if (sb)
3982	b = -b;
3983	if (div64(plow, phigh, b) != 0)
3984	return 1;
3985	if (sa ^ sb) {
3986	if (*plow > (1ULL << 63))
3987	return 1;
3988	plow = - plow;
3989	} else {
3990	if (*plow >= (1ULL << 63))
3991	return 1;
3992	}
3993	if (sa)
3994	phigh = - phigh;
3995	return 0;
3996	}
3997
3998	void helper_mulq_EAX_T0(void)
3999	{
4000	uint64_t r0, r1;
4001
4002	mul64(&r0, &r1, EAX, T0);
4003	EAX = r0;
4004	EDX = r1;
4005	CC_DST = r0;
4006	CC_SRC = r1;
4007	}
4008
4009	void helper_imulq_EAX_T0(void)
4010	{
4011	uint64_t r0, r1;
4012
4013	imul64(&r0, &r1, EAX, T0);
4014	EAX = r0;
4015	EDX = r1;
4016	CC_DST = r0;
4017	CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63));
4018	}
4019
4020	void helper_imulq_T0_T1(void)
4021	{
4022	uint64_t r0, r1;
4023
4024	imul64(&r0, &r1, T0, T1);
4025	T0 = r0;
4026	CC_DST = r0;
4027	CC_SRC = ((int64_t)r1 != ((int64_t)r0 >> 63));
4028	}
4029
4030	void helper_divq_EAX_T0(void)
4031	{
4032	uint64_t r0, r1;
4033	if (T0 == 0) {
4034	raise_exception(EXCP00_DIVZ);
4035	}
4036	r0 = EAX;
4037	r1 = EDX;
4038	if (div64(&r0, &r1, T0))
4039	raise_exception(EXCP00_DIVZ);
4040	EAX = r0;
4041	EDX = r1;
4042	}
4043
4044	void helper_idivq_EAX_T0(void)
4045	{
4046	uint64_t r0, r1;
4047	if (T0 == 0) {
4048	raise_exception(EXCP00_DIVZ);
4049	}
4050	r0 = EAX;
4051	r1 = EDX;
4052	if (idiv64(&r0, &r1, T0))
4053	raise_exception(EXCP00_DIVZ);
4054	EAX = r0;
4055	EDX = r1;
4056	}
4057
4058	void helper_bswapq_T0(void)
4059	{
4060	T0 = bswap64(T0);
4061	}
4062	#endif
4063
4064	void helper_hlt(void)
4065	{
4066	env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
4067	env->hflags \|= HF_HALTED_MASK;
4068	env->exception_index = EXCP_HLT;
4069	cpu_loop_exit();
4070	}
4071
4072	void helper_monitor(void)
4073	{
4074	if ((uint32_t)ECX != 0)
4075	raise_exception(EXCP0D_GPF);
4076	/* XXX: store address ? */
4077	}
4078
4079	void helper_mwait(void)
4080	{
4081	if ((uint32_t)ECX != 0)
4082	raise_exception(EXCP0D_GPF);
4083	#ifdef VBOX
4084	helper_hlt();
4085	#else
4086	/* XXX: not complete but not completely erroneous */
4087	if (env->cpu_index != 0 \|\| env->next_cpu != NULL) {
4088	/* more than one CPU: do not sleep because another CPU may
4089	wake this one */
4090	} else {
4091	helper_hlt();
4092	}
4093	#endif
4094	}
4095
4096	float approx_rsqrt(float a)
4097	{
4098	return 1.0 / sqrt(a);
4099	}
4100
4101	float approx_rcp(float a)
4102	{
4103	return 1.0 / a;
4104	}
4105
4106	void update_fp_status(void)
4107	{
4108	int rnd_type;
4109
4110	/* set rounding mode */
4111	switch(env->fpuc & RC_MASK) {
4112	default:
4113	case RC_NEAR:
4114	rnd_type = float_round_nearest_even;
4115	break;
4116	case RC_DOWN:
4117	rnd_type = float_round_down;
4118	break;
4119	case RC_UP:
4120	rnd_type = float_round_up;
4121	break;
4122	case RC_CHOP:
4123	rnd_type = float_round_to_zero;
4124	break;
4125	}
4126	set_float_rounding_mode(rnd_type, &env->fp_status);
4127	#ifdef FLOATX80
4128	switch((env->fpuc >> 8) & 3) {
4129	case 0:
4130	rnd_type = 32;
4131	break;
4132	case 2:
4133	rnd_type = 64;
4134	break;
4135	case 3:
4136	default:
4137	rnd_type = 80;
4138	break;
4139	}
4140	set_floatx80_rounding_precision(rnd_type, &env->fp_status);
4141	#endif
4142	}
4143
4144	#if !defined(CONFIG_USER_ONLY)
4145
4146	#define MMUSUFFIX _mmu
4147	#define GETPC() (__builtin_return_address(0))
4148
4149	#define SHIFT 0
4150	#include "softmmu_template.h"
4151
4152	#define SHIFT 1
4153	#include "softmmu_template.h"
4154
4155	#define SHIFT 2
4156	#include "softmmu_template.h"
4157
4158	#define SHIFT 3
4159	#include "softmmu_template.h"
4160
4161	#endif
4162
4163	/* try to fill the TLB and return an exception if error. If retaddr is
4164	NULL, it means that the function was called in C code (i.e. not
4165	from generated code or from helper.c) */
4166	/* XXX: fix it to restore all registers */
4167	void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
4168	{
4169	TranslationBlock *tb;
4170	int ret;
4171	unsigned long pc;
4172	CPUX86State *saved_env;
4173
4174	/* XXX: hack to restore env in all cases, even if not called from
4175	generated code */
4176	saved_env = env;
4177	env = cpu_single_env;
4178
4179	ret = cpu_x86_handle_mmu_fault(env, addr, is_write, is_user, 1);
4180	if (ret) {
4181	if (retaddr) {
4182	/* now we have a real cpu fault */
4183	pc = (unsigned long)retaddr;
4184	tb = tb_find_pc(pc);
4185	if (tb) {
4186	/* the PC is inside the translated code. It means that we have
4187	a virtual CPU fault */
4188	cpu_restore_state(tb, env, pc, NULL);
4189	}
4190	}
4191	if (retaddr)
4192	raise_exception_err(env->exception_index, env->error_code);
4193	else
4194	raise_exception_err_norestore(env->exception_index, env->error_code);
4195	}
4196	env = saved_env;
4197	}
4198
4199	#ifdef VBOX
4200
4201	/**
4202	* Correctly computes the eflags.
4203	* @returns eflags.
4204	* @param env1 CPU environment.
4205	*/
4206	uint32_t raw_compute_eflags(CPUX86State *env1)
4207	{
4208	CPUX86State *savedenv = env;
4209	env = env1;
4210	uint32_t efl = compute_eflags();
4211	env = savedenv;
4212	return efl;
4213	}
4214
4215	/**
4216	* Reads byte from virtual address in guest memory area.
4217	* XXX: is it working for any addresses? swapped out pages?
4218	* @returns readed data byte.
4219	* @param env1 CPU environment.
4220	* @param pvAddr GC Virtual address.
4221	*/
4222	uint8_t read_byte(CPUX86State *env1, target_ulong addr)
4223	{
4224	CPUX86State *savedenv = env;
4225	env = env1;
4226	uint8_t u8 = ldub_kernel(addr);
4227	env = savedenv;
4228	return u8;
4229	}
4230
4231	/**
4232	* Reads byte from virtual address in guest memory area.
4233	* XXX: is it working for any addresses? swapped out pages?
4234	* @returns readed data byte.
4235	* @param env1 CPU environment.
4236	* @param pvAddr GC Virtual address.
4237	*/
4238	uint16_t read_word(CPUX86State *env1, target_ulong addr)
4239	{
4240	CPUX86State *savedenv = env;
4241	env = env1;
4242	uint16_t u16 = lduw_kernel(addr);
4243	env = savedenv;
4244	return u16;
4245	}
4246
4247	/**
4248	* Reads byte from virtual address in guest memory area.
4249	* XXX: is it working for any addresses? swapped out pages?
4250	* @returns readed data byte.
4251	* @param env1 CPU environment.
4252	* @param pvAddr GC Virtual address.
4253	*/
4254	uint32_t read_dword(CPUX86State *env1, target_ulong addr)
4255	{
4256	CPUX86State *savedenv = env;
4257	env = env1;
4258	uint32_t u32 = ldl_kernel(addr);
4259	env = savedenv;
4260	return u32;
4261	}
4262
4263	/**
4264	* Writes byte to virtual address in guest memory area.
4265	* XXX: is it working for any addresses? swapped out pages?
4266	* @returns readed data byte.
4267	* @param env1 CPU environment.
4268	* @param pvAddr GC Virtual address.
4269	* @param val byte value
4270	*/
4271	void write_byte(CPUX86State *env1, target_ulong addr, uint8_t val)
4272	{
4273	CPUX86State *savedenv = env;
4274	env = env1;
4275	stb(addr, val);
4276	env = savedenv;
4277	}
4278
4279	void write_word(CPUX86State *env1, target_ulong addr, uint16_t val)
4280	{
4281	CPUX86State *savedenv = env;
4282	env = env1;
4283	stw(addr, val);
4284	env = savedenv;
4285	}
4286
4287	void write_dword(CPUX86State *env1, target_ulong addr, uint32_t val)
4288	{
4289	CPUX86State *savedenv = env;
4290	env = env1;
4291	stl(addr, val);
4292	env = savedenv;
4293	}
4294
4295	/**
4296	* Correctly loads selector into segment register with updating internal
4297	* qemu data/caches.
4298	* @param env1 CPU environment.
4299	* @param seg_reg Segment register.
4300	* @param selector Selector to load.
4301	*/
4302	void sync_seg(CPUX86State *env1, int seg_reg, int selector)
4303	{
4304	CPUX86State *savedenv = env;
4305	env = env1;
4306
4307	if ( env->eflags & X86_EFL_VM
4308	\|\| !(env->cr[0] & X86_CR0_PE))
4309	{
4310	load_seg_vm(seg_reg, selector);
4311
4312	env = savedenv;
4313
4314	/* Successful sync. */
4315	env1->segs[seg_reg].newselector = 0;
4316	}
4317	else
4318	{
4319	if (setjmp(env1->jmp_env) == 0)
4320	{
4321	if (seg_reg == R_CS)
4322	{
4323	uint32_t e1, e2;
4324	load_segment(&e1, &e2, selector);
4325	cpu_x86_load_seg_cache(env, R_CS, selector,
4326	get_seg_base(e1, e2),
4327	get_seg_limit(e1, e2),
4328	e2);
4329	}
4330	else
4331	load_seg(seg_reg, selector);
4332	env = savedenv;
4333
4334	/* Successful sync. */
4335	env1->segs[seg_reg].newselector = 0;
4336	}
4337	else
4338	{
4339	env = savedenv;
4340
4341	/* Postpone sync until the guest uses the selector. */
4342	env1->segs[seg_reg].selector = selector; /* hidden values are now incorrect, but will be resynced when this register is accessed. */
4343	env1->segs[seg_reg].newselector = selector;
4344	Log(("sync_seg: out of sync seg_reg=%d selector=%#x\n", seg_reg, selector));
4345	}
4346	}
4347
4348	}
4349
4350
4351	/**
4352	* Correctly loads a new ldtr selector.
4353	*
4354	* @param env1 CPU environment.
4355	* @param selector Selector to load.
4356	*/
4357	void sync_ldtr(CPUX86State *env1, int selector)
4358	{
4359	CPUX86State *saved_env = env;
4360	target_ulong saved_T0 = T0;
4361	if (setjmp(env1->jmp_env) == 0)
4362	{
4363	env = env1;
4364	T0 = selector;
4365	helper_lldt_T0();
4366	T0 = saved_T0;
4367	env = saved_env;
4368	}
4369	else
4370	{
4371	T0 = saved_T0;
4372	env = saved_env;
4373	#ifdef VBOX_STRICT
4374	cpu_abort(env1, "sync_ldtr: selector=%#x\n", selector);
4375	#endif
4376	}
4377	}
4378
4379	/**
4380	* Correctly loads a new tr selector.
4381	*
4382	* @param env1 CPU environment.
4383	* @param selector Selector to load.
4384	*/
4385	int sync_tr(CPUX86State *env1, int selector)
4386	{
4387	/* ARG! this was going to call helper_ltr_T0 but that won't work because of busy flag. */
4388	SegmentCache *dt;
4389	uint32_t e1, e2;
4390	int index, type, entry_limit;
4391	target_ulong ptr;
4392	CPUX86State *saved_env = env;
4393	env = env1;
4394
4395	selector &= 0xffff;
4396	if ((selector & 0xfffc) == 0) {
4397	/* NULL selector case: invalid TR */
4398	env->tr.base = 0;
4399	env->tr.limit = 0;
4400	env->tr.flags = 0;
4401	} else {
4402	if (selector & 0x4)
4403	goto l_failure;
4404	dt = &env->gdt;
4405	index = selector & ~7;
4406	#ifdef TARGET_X86_64
4407	if (env->hflags & HF_LMA_MASK)
4408	entry_limit = 15;
4409	else
4410	#endif
4411	entry_limit = 7;
4412	if ((index + entry_limit) > dt->limit)
4413	goto l_failure;
4414	ptr = dt->base + index;
4415	e1 = ldl_kernel(ptr);
4416	e2 = ldl_kernel(ptr + 4);
4417	type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
4418	if ((e2 & DESC_S_MASK) /*\|\|
4419	(type != 1 && type != 9)*/)
4420	goto l_failure;
4421	if (!(e2 & DESC_P_MASK))
4422	goto l_failure;
4423	#ifdef TARGET_X86_64
4424	if (env->hflags & HF_LMA_MASK) {
4425	uint32_t e3;
4426	e3 = ldl_kernel(ptr + 8);
4427	load_seg_cache_raw_dt(&env->tr, e1, e2);
4428	env->tr.base \|= (target_ulong)e3 << 32;
4429	} else
4430	#endif
4431	{
4432	load_seg_cache_raw_dt(&env->tr, e1, e2);
4433	}
4434	e2 \|= DESC_TSS_BUSY_MASK;
4435	stl_kernel(ptr + 4, e2);
4436	}
4437	env->tr.selector = selector;
4438
4439	env = saved_env;
4440	return 0;
4441	l_failure:
4442	AssertMsgFailed(("selector=%d\n", selector));
4443	return -1;
4444	}
4445
4446	int emulate_single_instr(CPUX86State *env1)
4447	{
4448	#if 1 /* single stepping is broken when using a static tb... feel free to figure out why. :-) */
4449	/* This has to be static because it needs to be addressible
4450	using 32-bit immediate addresses on 64-bit machines. This
4451	is dictated by the gcc code model used when building this
4452	module / op.o. Using a static here pushes the problem
4453	onto the module loader. */
4454	static TranslationBlock tb_temp;
4455	#endif
4456	TranslationBlock *tb;
4457	TranslationBlock *current;
4458	int csize;
4459	void (*gen_func)(void);
4460	uint8_t *tc_ptr;
4461	target_ulong old_eip;
4462
4463	/* ensures env is loaded in ebp! */
4464	CPUX86State *savedenv = env;
4465	env = env1;
4466
4467	RAWEx_ProfileStart(env, STATS_EMULATE_SINGLE_INSTR);
4468
4469	#if 1 /* see above */
4470	tc_ptr = env->pvCodeBuffer;
4471	#else
4472	tc_ptr = code_gen_ptr;
4473	#endif
4474
4475	/*
4476	* Setup temporary translation block.
4477	*/
4478	/* tb_alloc: */
4479	#if 1 /* see above */
4480	tb = &tb_temp;
4481	tb->pc = env->segs[R_CS].base + env->eip;
4482	tb->cflags = 0;
4483	#else
4484	tb = tb_alloc(env->segs[R_CS].base + env->eip);
4485	if (!tb)
4486	{
4487	tb_flush(env);
4488	tb = tb_alloc(env->segs[R_CS].base + env->eip);
4489	}
4490	#endif
4491
4492	/* tb_find_slow: */
4493	tb->tc_ptr = tc_ptr;
4494	tb->cs_base = env->segs[R_CS].base;
4495	tb->flags = env->hflags \| (env->eflags & (IOPL_MASK \| TF_MASK \| VM_MASK));
4496
4497	/* Initialize the rest with sensible values. */
4498	tb->size = 0;
4499	tb->phys_hash_next = NULL;
4500	tb->page_next[0] = NULL;
4501	tb->page_next[1] = NULL;
4502	tb->page_addr[0] = 0;
4503	tb->page_addr[1] = 0;
4504	tb->tb_next_offset[0] = 0xffff;
4505	tb->tb_next_offset[1] = 0xffff;
4506	tb->tb_next[0] = 0xffff;
4507	tb->tb_next[1] = 0xffff;
4508	tb->jmp_next[0] = NULL;
4509	tb->jmp_next[1] = NULL;
4510	tb->jmp_first = NULL;
4511
4512	current = env->current_tb;
4513	env->current_tb = NULL;
4514
4515	/*
4516	* Translate only one instruction.
4517	*/
4518	ASMAtomicOrU32(&env->state, CPU_EMULATE_SINGLE_INSTR);
4519	if (cpu_gen_code(env, tb, env->cbCodeBuffer, &csize) < 0)
4520	{
4521	AssertFailed();
4522	RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
4523	ASMAtomicAndU32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
4524	env = savedenv;
4525	return -1;
4526	}
4527	#ifdef DEBUG
4528	if(csize > env->cbCodeBuffer)
4529	{
4530	RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
4531	AssertFailed();
4532	ASMAtomicAndU32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
4533	env = savedenv;
4534	return -1;
4535	}
4536	if (tb->tc_ptr != tc_ptr)
4537	{
4538	RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
4539	AssertFailed();
4540	ASMAtomicAndU32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
4541	env = savedenv;
4542	return -1;
4543	}
4544	#endif
4545	ASMAtomicAndU32(&env->state, ~CPU_EMULATE_SINGLE_INSTR);
4546
4547	/* tb_link_phys: */
4548	tb->jmp_first = (TranslationBlock *)((intptr_t)tb \| 2);
4549	Assert(tb->jmp_next[0] == NULL); Assert(tb->jmp_next[1] == NULL);
4550	if (tb->tb_next_offset[0] != 0xffff)
4551	tb_set_jmp_target(tb, 0, (uintptr_t)(tb->tc_ptr + tb->tb_next_offset[0]));
4552	if (tb->tb_next_offset[1] != 0xffff)
4553	tb_set_jmp_target(tb, 1, (uintptr_t)(tb->tc_ptr + tb->tb_next_offset[1]));
4554
4555	/*
4556	* Execute it using emulation
4557	*/
4558	old_eip = env->eip;
4559	gen_func = (void *)tb->tc_ptr;
4560	env->current_tb = tb;
4561
4562	// eip remains the same for repeated instructions; no idea why qemu doesn't do a jump inside the generated code
4563	// perhaps not a very safe hack
4564	while(old_eip == env->eip)
4565	{
4566	gen_func();
4567	/*
4568	* Exit once we detect an external interrupt and interrupts are enabled
4569	*/
4570	if( (env->interrupt_request & (CPU_INTERRUPT_EXTERNAL_EXIT\|CPU_INTERRUPT_EXTERNAL_TIMER)) \|\|
4571	( (env->eflags & IF_MASK) &&
4572	!(env->hflags & HF_INHIBIT_IRQ_MASK) &&
4573	(env->interrupt_request & CPU_INTERRUPT_EXTERNAL_HARD) ) )
4574	{
4575	break;
4576	}
4577	}
4578	env->current_tb = current;
4579
4580	Assert(tb->phys_hash_next == NULL);
4581	Assert(tb->page_next[0] == NULL);
4582	Assert(tb->page_next[1] == NULL);
4583	Assert(tb->page_addr[0] == 0);
4584	Assert(tb->page_addr[1] == 0);
4585	/*
4586	Assert(tb->tb_next_offset[0] == 0xffff);
4587	Assert(tb->tb_next_offset[1] == 0xffff);
4588	Assert(tb->tb_next[0] == 0xffff);
4589	Assert(tb->tb_next[1] == 0xffff);
4590	Assert(tb->jmp_next[0] == NULL);
4591	Assert(tb->jmp_next[1] == NULL);
4592	Assert(tb->jmp_first == NULL); */
4593
4594	RAWEx_ProfileStop(env, STATS_EMULATE_SINGLE_INSTR);
4595
4596	/*
4597	* Execute the next instruction when we encounter instruction fusing.
4598	*/
4599	if (env->hflags & HF_INHIBIT_IRQ_MASK)
4600	{
4601	Log(("REM: Emulating next instruction due to instruction fusing (HF_INHIBIT_IRQ_MASK) at %VGv\n", env->eip));
4602	env->hflags &= ~HF_INHIBIT_IRQ_MASK;
4603	emulate_single_instr(env);
4604	}
4605
4606	env = savedenv;
4607	return 0;
4608	}
4609
4610	int get_ss_esp_from_tss_raw(CPUX86State env1, uint32_t ss_ptr,
4611	uint32_t *esp_ptr, int dpl)
4612	{
4613	int type, index, shift;
4614
4615	CPUX86State *savedenv = env;
4616	env = env1;
4617
4618	if (!(env->tr.flags & DESC_P_MASK))
4619	cpu_abort(env, "invalid tss");
4620	type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
4621	if ((type & 7) != 1)
4622	cpu_abort(env, "invalid tss type %d", type);
4623	shift = type >> 3;
4624	index = (dpl * 4 + 2) << shift;
4625	if (index + (4 << shift) - 1 > env->tr.limit)
4626	{
4627	env = savedenv;
4628	return 0;
4629	}
4630	//raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);
4631
4632	if (shift == 0) {
4633	*esp_ptr = lduw_kernel(env->tr.base + index);
4634	*ss_ptr = lduw_kernel(env->tr.base + index + 2);
4635	} else {
4636	*esp_ptr = ldl_kernel(env->tr.base + index);
4637	*ss_ptr = lduw_kernel(env->tr.base + index + 4);
4638	}
4639
4640	env = savedenv;
4641	return 1;
4642	}
4643
4644	//*****************************************************************************
4645	// Needs to be at the bottom of the file (overriding macros)
4646
4647	static inline CPU86_LDouble helper_fldt_raw(uint8_t *ptr)
4648	{
4649	return (CPU86_LDouble )ptr;
4650	}
4651
4652	static inline void helper_fstt_raw(CPU86_LDouble f, uint8_t *ptr)
4653	{
4654	(CPU86_LDouble )ptr = f;
4655	}
4656
4657	#undef stw
4658	#undef stl
4659	#undef stq
4660	#define stw(a,b) (uint16_t )(a) = (uint16_t)(b)
4661	#define stl(a,b) (uint32_t )(a) = (uint32_t)(b)
4662	#define stq(a,b) (uint64_t )(a) = (uint64_t)(b)
4663	#define data64 0
4664
4665	//*****************************************************************************
4666	void restore_raw_fp_state(CPUX86State env, uint8_t ptr)
4667	{
4668	int fpus, fptag, i, nb_xmm_regs;
4669	CPU86_LDouble tmp;
4670	uint8_t *addr;
4671
4672	if (env->cpuid_features & CPUID_FXSR)
4673	{
4674	fpus = (env->fpus & ~0x3800) \| (env->fpstt & 0x7) << 11;
4675	fptag = 0;
4676	for(i = 0; i < 8; i++) {
4677	fptag \|= (env->fptags[i] << i);
4678	}
4679	stw(ptr, env->fpuc);
4680	stw(ptr + 2, fpus);
4681	stw(ptr + 4, fptag ^ 0xff);
4682
4683	addr = ptr + 0x20;
4684	for(i = 0;i < 8; i++) {
4685	tmp = ST(i);
4686	helper_fstt_raw(tmp, addr);
4687	addr += 16;
4688	}
4689
4690	if (env->cr[4] & CR4_OSFXSR_MASK) {
4691	/* XXX: finish it */
4692	stl(ptr + 0x18, env->mxcsr); /* mxcsr */
4693	stl(ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
4694	nb_xmm_regs = 8 << data64;
4695	addr = ptr + 0xa0;
4696	for(i = 0; i < nb_xmm_regs; i++) {
4697	#if __GNUC__ < 4
4698	stq(addr, env->xmm_regs[i].XMM_Q(0));
4699	stq(addr + 8, env->xmm_regs[i].XMM_Q(1));
4700	#else /* VBOX + __GNUC__ >= 4: gcc 4.x compiler bug - it runs out of registers for the 64-bit value. */
4701	stl(addr, env->xmm_regs[i].XMM_L(0));
4702	stl(addr + 4, env->xmm_regs[i].XMM_L(1));
4703	stl(addr + 8, env->xmm_regs[i].XMM_L(2));
4704	stl(addr + 12, env->xmm_regs[i].XMM_L(3));
4705	#endif
4706	addr += 16;
4707	}
4708	}
4709	}
4710	else
4711	{
4712	PX86FPUSTATE fp = (PX86FPUSTATE)ptr;
4713	int fptag;
4714
4715	fp->FCW = env->fpuc;
4716	fp->FSW = (env->fpus & ~0x3800) \| (env->fpstt & 0x7) << 11;
4717	fptag = 0;
4718	for (i=7; i>=0; i--) {
4719	fptag <<= 2;
4720	if (env->fptags[i]) {
4721	fptag \|= 3;
4722	} else {
4723	/* the FPU automatically computes it */
4724	}
4725	}
4726	fp->FTW = fptag;
4727
4728	for(i = 0;i < 8; i++) {
4729	tmp = ST(i);
4730	helper_fstt_raw(tmp, &fp->regs[i].reg[0]);
4731	}
4732	}
4733	}
4734
4735	//*****************************************************************************
4736	#undef lduw
4737	#undef ldl
4738	#undef ldq
4739	#define lduw(a) (uint16_t )(a)
4740	#define ldl(a) (uint32_t )(a)
4741	#define ldq(a) (uint64_t )(a)
4742	//*****************************************************************************
4743	void save_raw_fp_state(CPUX86State env, uint8_t ptr)
4744	{
4745	int i, fpus, fptag, nb_xmm_regs;
4746	CPU86_LDouble tmp;
4747	uint8_t *addr;
4748
4749	if (env->cpuid_features & CPUID_FXSR)
4750	{
4751	env->fpuc = lduw(ptr);
4752	fpus = lduw(ptr + 2);
4753	fptag = lduw(ptr + 4);
4754	env->fpstt = (fpus >> 11) & 7;
4755	env->fpus = fpus & ~0x3800;
4756	fptag ^= 0xff;
4757	for(i = 0;i < 8; i++) {
4758	env->fptags[i] = ((fptag >> i) & 1);
4759	}
4760
4761	addr = ptr + 0x20;
4762	for(i = 0;i < 8; i++) {
4763	tmp = helper_fldt_raw(addr);
4764	ST(i) = tmp;
4765	addr += 16;
4766	}
4767
4768	if (env->cr[4] & CR4_OSFXSR_MASK) {
4769	/* XXX: finish it, endianness */
4770	env->mxcsr = ldl(ptr + 0x18);
4771	//ldl(ptr + 0x1c);
4772	nb_xmm_regs = 8 << data64;
4773	addr = ptr + 0xa0;
4774	for(i = 0; i < nb_xmm_regs; i++) {
4775	#if HC_ARCH_BITS == 32
4776	/* this is a workaround for http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35135 */
4777	env->xmm_regs[i].XMM_L(0) = ldl(addr);
4778	env->xmm_regs[i].XMM_L(1) = ldl(addr + 4);
4779	env->xmm_regs[i].XMM_L(2) = ldl(addr + 8);
4780	env->xmm_regs[i].XMM_L(3) = ldl(addr + 12);
4781	#else
4782	env->xmm_regs[i].XMM_Q(0) = ldq(addr);
4783	env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8);
4784	#endif
4785	addr += 16;
4786	}
4787	}
4788	}
4789	else
4790	{
4791	PX86FPUSTATE fp = (PX86FPUSTATE)ptr;
4792	int fptag, j;
4793
4794	env->fpuc = fp->FCW;
4795	env->fpstt = (fp->FSW >> 11) & 7;
4796	env->fpus = fp->FSW & ~0x3800;
4797	fptag = fp->FTW;
4798	for(i = 0;i < 8; i++) {
4799	env->fptags[i] = ((fptag & 3) == 3);
4800	fptag >>= 2;
4801	}
4802	j = env->fpstt;
4803	for(i = 0;i < 8; i++) {
4804	tmp = helper_fldt_raw(&fp->regs[i].reg[0]);
4805	ST(i) = tmp;
4806	}
4807	}
4808	}
4809	//*****************************************************************************
4810	//*****************************************************************************
4811
4812	#endif /* VBOX */
4813

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source: vbox/trunk/src/recompiler/target-i386/helper.c@ 12105

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