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source: vbox/trunk/src/recompiler/target-i386/exec.h@ 36140

Last change on this file since 36140 was 36140, checked in by vboxsync, 14 years ago

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1/*
2 * i386 execution defines
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/*
22 * Oracle LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
23 * other than GPL or LGPL is available it will apply instead, Oracle elects to use only
24 * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
25 * a choice of LGPL license versions is made available with the language indicating
26 * that LGPLv2 or any later version may be used, or where a choice of which version
27 * of the LGPL is applied is otherwise unspecified.
28 */
29
30#include "config.h"
31#include "dyngen-exec.h"
32
33/* XXX: factorize this mess */
34#ifdef TARGET_X86_64
35#define TARGET_LONG_BITS 64
36#else
37#define TARGET_LONG_BITS 32
38#endif
39
40#include "cpu-defs.h"
41
42register struct CPUX86State *env asm(AREG0);
43
44#include "qemu-log.h"
45
46#define EAX (env->regs[R_EAX])
47#define ECX (env->regs[R_ECX])
48#define EDX (env->regs[R_EDX])
49#define EBX (env->regs[R_EBX])
50#define ESP (env->regs[R_ESP])
51#define EBP (env->regs[R_EBP])
52#define ESI (env->regs[R_ESI])
53#define EDI (env->regs[R_EDI])
54#define EIP (env->eip)
55#define DF (env->df)
56
57#define CC_SRC (env->cc_src)
58#define CC_DST (env->cc_dst)
59#define CC_OP (env->cc_op)
60
61/* float macros */
62#define FT0 (env->ft0)
63#define ST0 (env->fpregs[env->fpstt].d)
64#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
65#define ST1 ST(1)
66
67#include "cpu.h"
68#include "exec-all.h"
69
70void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
71void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
72int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
73 int is_write, int mmu_idx, int is_softmmu);
74void __hidden cpu_lock(void);
75void __hidden cpu_unlock(void);
76void do_interrupt(int intno, int is_int, int error_code,
77 target_ulong next_eip, int is_hw);
78void do_interrupt_user(int intno, int is_int, int error_code,
79 target_ulong next_eip);
80void raise_interrupt(int intno, int is_int, int error_code,
81 int next_eip_addend);
82void raise_exception_err(int exception_index, int error_code);
83void raise_exception(int exception_index);
84void do_smm_enter(void);
85void __hidden cpu_loop_exit(void);
86
87void OPPROTO op_movl_eflags_T0(void);
88void OPPROTO op_movl_T0_eflags(void);
89#ifdef VBOX
90void OPPROTO op_movl_T0_eflags_vme(void);
91void OPPROTO op_movw_eflags_T0_vme(void);
92void OPPROTO op_cli_vme(void);
93void OPPROTO op_sti_vme(void);
94#endif
95
96/* n must be a constant to be efficient */
97static inline target_long lshift(target_long x, int n)
98{
99 if (n >= 0)
100 return x << n;
101 else
102 return x >> (-n);
103}
104
105#include "helper.h"
106
107static inline void svm_check_intercept(uint32_t type)
108{
109 helper_svm_check_intercept_param(type, 0);
110}
111
112#if !defined(CONFIG_USER_ONLY)
113
114#include "softmmu_exec.h"
115
116#endif /* !defined(CONFIG_USER_ONLY) */
117
118#ifdef USE_X86LDOUBLE
119/* use long double functions */
120#define floatx_to_int32 floatx80_to_int32
121#define floatx_to_int64 floatx80_to_int64
122#define floatx_to_int32_round_to_zero floatx80_to_int32_round_to_zero
123#define floatx_to_int64_round_to_zero floatx80_to_int64_round_to_zero
124#define int32_to_floatx int32_to_floatx80
125#define int64_to_floatx int64_to_floatx80
126#define float32_to_floatx float32_to_floatx80
127#define float64_to_floatx float64_to_floatx80
128#define floatx_to_float32 floatx80_to_float32
129#define floatx_to_float64 floatx80_to_float64
130#define floatx_abs floatx80_abs
131#define floatx_chs floatx80_chs
132#define floatx_round_to_int floatx80_round_to_int
133#define floatx_compare floatx80_compare
134#define floatx_compare_quiet floatx80_compare_quiet
135#ifdef VBOX
136#undef sin
137#undef cos
138#undef sqrt
139#undef pow
140#undef log
141#undef tan
142#undef atan2
143#undef floor
144#undef ceil
145#undef ldexp
146#endif /* !VBOX */
147#if !defined(VBOX) || !defined(_MSC_VER)
148#define sin sinl
149#define cos cosl
150#define sqrt sqrtl
151#define pow powl
152#define log logl
153#define tan tanl
154#define atan2 atan2l
155#define floor floorl
156#define ceil ceill
157#define ldexp ldexpl
158#endif
159#else
160#define floatx_to_int32 float64_to_int32
161#define floatx_to_int64 float64_to_int64
162#define floatx_to_int32_round_to_zero float64_to_int32_round_to_zero
163#define floatx_to_int64_round_to_zero float64_to_int64_round_to_zero
164#define int32_to_floatx int32_to_float64
165#define int64_to_floatx int64_to_float64
166#define float32_to_floatx float32_to_float64
167#define float64_to_floatx(x, e) (x)
168#define floatx_to_float32 float64_to_float32
169#define floatx_to_float64(x, e) (x)
170#define floatx_abs float64_abs
171#define floatx_chs float64_chs
172#define floatx_round_to_int float64_round_to_int
173#define floatx_compare float64_compare
174#define floatx_compare_quiet float64_compare_quiet
175#endif
176
177#ifdef VBOX
178extern CPU86_LDouble sin(CPU86_LDouble x);
179extern CPU86_LDouble cos(CPU86_LDouble x);
180extern CPU86_LDouble sqrt(CPU86_LDouble x);
181extern CPU86_LDouble pow(CPU86_LDouble, CPU86_LDouble);
182extern CPU86_LDouble log(CPU86_LDouble x);
183extern CPU86_LDouble tan(CPU86_LDouble x);
184extern CPU86_LDouble atan2(CPU86_LDouble, CPU86_LDouble);
185extern CPU86_LDouble floor(CPU86_LDouble x);
186extern CPU86_LDouble ceil(CPU86_LDouble x);
187#endif /* VBOX */
188
189#define RC_MASK 0xc00
190#define RC_NEAR 0x000
191#define RC_DOWN 0x400
192#define RC_UP 0x800
193#define RC_CHOP 0xc00
194
195#define MAXTAN 9223372036854775808.0
196
197#ifdef USE_X86LDOUBLE
198
199/* only for x86 */
200typedef union {
201 long double d;
202 struct {
203 unsigned long long lower;
204 unsigned short upper;
205 } l;
206} CPU86_LDoubleU;
207
208/* the following deal with x86 long double-precision numbers */
209#define MAXEXPD 0x7fff
210#define EXPBIAS 16383
211#define EXPD(fp) (fp.l.upper & 0x7fff)
212#define SIGND(fp) ((fp.l.upper) & 0x8000)
213#define MANTD(fp) (fp.l.lower)
214#define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS
215
216#else
217
218/* NOTE: arm is horrible as double 32 bit words are stored in big endian ! */
219typedef union {
220 double d;
221#if !defined(WORDS_BIGENDIAN) && !defined(__arm__)
222 struct {
223 uint32_t lower;
224 int32_t upper;
225 } l;
226#else
227 struct {
228 int32_t upper;
229 uint32_t lower;
230 } l;
231#endif
232#ifndef __arm__
233 int64_t ll;
234#endif
235} CPU86_LDoubleU;
236
237/* the following deal with IEEE double-precision numbers */
238#define MAXEXPD 0x7ff
239#define EXPBIAS 1023
240#define EXPD(fp) (((fp.l.upper) >> 20) & 0x7FF)
241#define SIGND(fp) ((fp.l.upper) & 0x80000000)
242#ifdef __arm__
243#define MANTD(fp) (fp.l.lower | ((uint64_t)(fp.l.upper & ((1 << 20) - 1)) << 32))
244#else
245#define MANTD(fp) (fp.ll & ((1LL << 52) - 1))
246#endif
247#define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7ff << 20)) | (EXPBIAS << 20)
248#endif
249
250static inline void fpush(void)
251{
252 env->fpstt = (env->fpstt - 1) & 7;
253 env->fptags[env->fpstt] = 0; /* validate stack entry */
254}
255
256static inline void fpop(void)
257{
258 env->fptags[env->fpstt] = 1; /* invvalidate stack entry */
259 env->fpstt = (env->fpstt + 1) & 7;
260}
261
262#ifndef USE_X86LDOUBLE
263static inline CPU86_LDouble helper_fldt(target_ulong ptr)
264{
265 CPU86_LDoubleU temp;
266 int upper, e;
267 uint64_t ll;
268
269 /* mantissa */
270 upper = lduw(ptr + 8);
271 /* XXX: handle overflow ? */
272 e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */
273 e |= (upper >> 4) & 0x800; /* sign */
274 ll = (ldq(ptr) >> 11) & ((1LL << 52) - 1);
275#ifdef __arm__
276 temp.l.upper = (e << 20) | (ll >> 32);
277 temp.l.lower = ll;
278#else
279 temp.ll = ll | ((uint64_t)e << 52);
280#endif
281 return temp.d;
282}
283
284static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
285{
286 CPU86_LDoubleU temp;
287 int e;
288
289 temp.d = f;
290 /* mantissa */
291 stq(ptr, (MANTD(temp) << 11) | (1LL << 63));
292 /* exponent + sign */
293 e = EXPD(temp) - EXPBIAS + 16383;
294 e |= SIGND(temp) >> 16;
295 stw(ptr + 8, e);
296}
297#else
298
299/* we use memory access macros */
300
301static inline CPU86_LDouble helper_fldt(target_ulong ptr)
302{
303 CPU86_LDoubleU temp;
304
305 temp.l.lower = ldq(ptr);
306 temp.l.upper = lduw(ptr + 8);
307 return temp.d;
308}
309
310static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
311{
312 CPU86_LDoubleU temp;
313
314 temp.d = f;
315 stq(ptr, temp.l.lower);
316 stw(ptr + 8, temp.l.upper);
317}
318
319#endif /* USE_X86LDOUBLE */
320
321#define FPUS_IE (1 << 0)
322#define FPUS_DE (1 << 1)
323#define FPUS_ZE (1 << 2)
324#define FPUS_OE (1 << 3)
325#define FPUS_UE (1 << 4)
326#define FPUS_PE (1 << 5)
327#define FPUS_SF (1 << 6)
328#define FPUS_SE (1 << 7)
329#define FPUS_B (1 << 15)
330
331#define FPUC_EM 0x3f
332
333extern const CPU86_LDouble f15rk[7];
334
335void fpu_raise_exception(void);
336void restore_native_fp_state(CPUState *env);
337void save_native_fp_state(CPUState *env);
338
339extern const uint8_t parity_table[256];
340extern const uint8_t rclw_table[32];
341extern const uint8_t rclb_table[32];
342
343static inline uint32_t compute_eflags(void)
344{
345 return env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
346}
347
348/* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */
349static inline void load_eflags(int eflags, int update_mask)
350{
351 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
352 DF = 1 - (2 * ((eflags >> 10) & 1));
353 env->eflags = (env->eflags & ~update_mask) |
354 (eflags & update_mask) | 0x2;
355}
356
357static inline void env_to_regs(void)
358{
359#ifdef reg_EAX
360 EAX = env->regs[R_EAX];
361#endif
362#ifdef reg_ECX
363 ECX = env->regs[R_ECX];
364#endif
365#ifdef reg_EDX
366 EDX = env->regs[R_EDX];
367#endif
368#ifdef reg_EBX
369 EBX = env->regs[R_EBX];
370#endif
371#ifdef reg_ESP
372 ESP = env->regs[R_ESP];
373#endif
374#ifdef reg_EBP
375 EBP = env->regs[R_EBP];
376#endif
377#ifdef reg_ESI
378 ESI = env->regs[R_ESI];
379#endif
380#ifdef reg_EDI
381 EDI = env->regs[R_EDI];
382#endif
383}
384
385static inline void regs_to_env(void)
386{
387#ifdef reg_EAX
388 env->regs[R_EAX] = EAX;
389#endif
390#ifdef reg_ECX
391 env->regs[R_ECX] = ECX;
392#endif
393#ifdef reg_EDX
394 env->regs[R_EDX] = EDX;
395#endif
396#ifdef reg_EBX
397 env->regs[R_EBX] = EBX;
398#endif
399#ifdef reg_ESP
400 env->regs[R_ESP] = ESP;
401#endif
402#ifdef reg_EBP
403 env->regs[R_EBP] = EBP;
404#endif
405#ifdef reg_ESI
406 env->regs[R_ESI] = ESI;
407#endif
408#ifdef reg_EDI
409 env->regs[R_EDI] = EDI;
410#endif
411}
412
413static inline int cpu_halted(CPUState *env) {
414 /* handle exit of HALTED state */
415 if (!env->halted)
416 return 0;
417 /* disable halt condition */
418 if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
419 (env->eflags & IF_MASK)) ||
420 (env->interrupt_request & CPU_INTERRUPT_NMI)) {
421 env->halted = 0;
422 return 0;
423 }
424 return EXCP_HALTED;
425}
426
427/* load efer and update the corresponding hflags. XXX: do consistency
428 checks with cpuid bits ? */
429static inline void cpu_load_efer(CPUState *env, uint64_t val)
430{
431 env->efer = val;
432 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
433 if (env->efer & MSR_EFER_LMA)
434 env->hflags |= HF_LMA_MASK;
435 if (env->efer & MSR_EFER_SVME)
436 env->hflags |= HF_SVME_MASK;
437}
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