bs3-cpu-generated-1.h@ 66744

Last change on this file since 66744 was 66744, checked in by vboxsync, 8 years ago
IEM: Implemented movupd Vpd,Wpd (0x66 0x0f 0x10).
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 17.5 KB

Line
1	/* $Id: bs3-cpu-generated-1.h 66744 2017-05-02 11:28:41Z vboxsync $ */
2	/** @file
3	* BS3Kit - bs3-cpu-generated-1, common header file.
4	*/
5
6	/*
7	* Copyright (C) 2007-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.215389.xyz. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27
28	#ifndef ___bs3_cpu_generated_1_h___
29	#define ___bs3_cpu_generated_1_h___
30
31	#include <bs3kit.h>
32	#include <iprt/assert.h>
33
34
35	/**
36	* Operand details.
37	*
38	* Currently simply using the encoding from the reference manuals.
39	*/
40	typedef enum BS3CG1OP
41	{
42	BS3CG1OP_INVALID = 0,
43
44	BS3CG1OP_Eb,
45	BS3CG1OP_Ev,
46	BS3CG1OP_Wss,
47	BS3CG1OP_Wsd,
48	BS3CG1OP_Wps,
49	BS3CG1OP_Wpd,
50	BS3CG1OP_Wdq,
51	BS3CG1OP_WqZxReg,
52
53	BS3CG1OP_Gb,
54	BS3CG1OP_Gv,
55	BS3CG1OP_Uq,
56	BS3CG1OP_UqHi,
57	BS3CG1OP_Vss,
58	BS3CG1OP_VssZxReg,
59	BS3CG1OP_Vsd,
60	BS3CG1OP_Vps,
61	BS3CG1OP_Vpd,
62	BS3CG1OP_Vq,
63	BS3CG1OP_Vdq,
64
65	BS3CG1OP_Ib,
66	BS3CG1OP_Iz,
67
68	BS3CG1OP_AL,
69	BS3CG1OP_rAX,
70
71	BS3CG1OP_Ma,
72	BS3CG1OP_MbRO,
73	BS3CG1OP_MdRO,
74	BS3CG1OP_MdWO,
75	BS3CG1OP_Mq,
76
77	BS3CG1OP_END
78	} BS3CG1OP;
79	/** Pointer to a const operand enum. */
80	typedef const BS3CG1OP BS3_FAR *PCBS3CG1OP;
81
82
83	/**
84	* Instruction encoding format.
85	*
86	* This duplicates some of the info in the operand array, however it makes it
87	* easier to figure out encoding variations.
88	*/
89	typedef enum BS3CG1ENC
90	{
91	BS3CG1ENC_INVALID = 0,
92
93	BS3CG1ENC_MODRM_Eb_Gb,
94	BS3CG1ENC_MODRM_Ev_Gv,
95	BS3CG1ENC_MODRM_Wss_Vss,
96	BS3CG1ENC_MODRM_Wsd_Vsd,
97	BS3CG1ENC_MODRM_Wps_Vps,
98	BS3CG1ENC_MODRM_Wpd_Vpd,
99	BS3CG1ENC_MODRM_WqZxReg_Vq,
100
101	BS3CG1ENC_MODRM_Gb_Eb,
102	BS3CG1ENC_MODRM_Gv_Ev,
103	BS3CG1ENC_MODRM_Gv_Ma, /*< bound instruction /
104	BS3CG1ENC_MODRM_Vq_UqHi,
105	BS3CG1ENC_MODRM_Vq_Mq,
106	BS3CG1ENC_MODRM_Vdq_Wdq,
107	BS3CG1ENC_MODRM_Vpd_Wpd,
108	BS3CG1ENC_MODRM_Vps_Wps,
109	BS3CG1ENC_MODRM_VssZxReg_Wss,
110	BS3CG1ENC_MODRM_MbRO,
111	BS3CG1ENC_MODRM_MdRO,
112	BS3CG1ENC_MODRM_MdWO,
113
114	BS3CG1ENC_VEX_MODRM_MdWO,
115
116	BS3CG1ENC_FIXED,
117	BS3CG1ENC_FIXED_AL_Ib,
118	BS3CG1ENC_FIXED_rAX_Iz,
119
120	BS3CG1ENC_MODRM_MOD_EQ_3, /*< Unused or invalid instruction. /
121	BS3CG1ENC_MODRM_MOD_NE_3, /*< Unused or invalid instruction. /
122
123	BS3CG1ENC_END
124	} BS3CG1ENC;
125
126
127	/**
128	* Prefix sensitivitiy kind.
129	*/
130	typedef enum BS3CG1PFXKIND
131	{
132	BS3CG1PFXKIND_INVALID = 0,
133
134	BS3CG1PFXKIND_NO_F2_F3_66, /*< No 66, F2 or F3 prefixes allowed as that would alter the meaning. /
135	BS3CG1PFXKIND_REQ_F2, /*< Requires F2 (REPNE) prefix as part of the instr encoding. /
136	BS3CG1PFXKIND_REQ_F3, /*< Requires F3 (REPE) prefix as part of the instr encoding. /
137	BS3CG1PFXKIND_REQ_66, /*< Requires 66 (OP SIZE) prefix as part of the instr encoding. /
138
139	/** @todo more work to be done here... */
140	BS3CG1PFXKIND_MODRM,
141	BS3CG1PFXKIND_MODRM_NO_OP_SIZES,
142
143	BS3CG1PFXKIND_END
144	} BS3CG1PFXKIND;
145
146	/**
147	* CPU selection or CPU ID.
148	*/
149	typedef enum BS3CG1CPU
150	{
151	/** Works with an CPU. */
152	BS3CG1CPU_ANY = 0,
153	BS3CG1CPU_GE_80186,
154	BS3CG1CPU_GE_80286,
155	BS3CG1CPU_GE_80386,
156	BS3CG1CPU_GE_80486,
157	BS3CG1CPU_GE_Pentium,
158
159	BS3CG1CPU_SSE,
160	BS3CG1CPU_SSE2,
161	BS3CG1CPU_SSE3,
162	BS3CG1CPU_AVX,
163	BS3CG1CPU_AVX2,
164	BS3CG1CPU_CLFSH,
165	BS3CG1CPU_CLFLUSHOPT,
166
167	BS3CG1CPU_END
168	} BS3CG1CPU;
169
170
171	/**
172	* SSE & AVX exception types.
173	*/
174	typedef enum BS3CG1XCPTTYPE
175	{
176	BS3CG1XCPTTYPE_NONE = 0,
177	/* SSE: */
178	BS3CG1XCPTTYPE_1,
179	BS3CG1XCPTTYPE_2,
180	BS3CG1XCPTTYPE_3,
181	BS3CG1XCPTTYPE_4,
182	BS3CG1XCPTTYPE_4UA,
183	BS3CG1XCPTTYPE_5,
184	BS3CG1XCPTTYPE_6,
185	BS3CG1XCPTTYPE_7,
186	BS3CG1XCPTTYPE_8,
187	BS3CG1XCPTTYPE_11,
188	BS3CG1XCPTTYPE_12,
189	/* EVEX: */
190	BS3CG1XCPTTYPE_E1,
191	BS3CG1XCPTTYPE_E1NF,
192	BS3CG1XCPTTYPE_E2,
193	BS3CG1XCPTTYPE_E3,
194	BS3CG1XCPTTYPE_E3NF,
195	BS3CG1XCPTTYPE_E4,
196	BS3CG1XCPTTYPE_E4NF,
197	BS3CG1XCPTTYPE_E5,
198	BS3CG1XCPTTYPE_E5NF,
199	BS3CG1XCPTTYPE_E6,
200	BS3CG1XCPTTYPE_E6NF,
201	BS3CG1XCPTTYPE_E7NF,
202	BS3CG1XCPTTYPE_E9,
203	BS3CG1XCPTTYPE_E9NF,
204	BS3CG1XCPTTYPE_E10,
205	BS3CG1XCPTTYPE_E11,
206	BS3CG1XCPTTYPE_E12,
207	BS3CG1XCPTTYPE_E12NF,
208	BS3CG1XCPTTYPE_END
209	} BS3CG1XCPTTYPE;
210	AssertCompile(BS3CG1XCPTTYPE_END <= 32);
211
212
213	/**
214	* Generated instruction info.
215	*/
216	typedef struct BS3CG1INSTR
217	{
218	/** The opcode size. */
219	uint32_t cbOpcodes : 2;
220	/** The number of operands. */
221	uint32_t cOperands : 2;
222	/** The length of the mnemonic. */
223	uint32_t cchMnemonic : 4;
224	/** Whether to advance the mnemonic array pointer. */
225	uint32_t fAdvanceMnemonic : 1;
226	/** Offset into g_abBs3Cg1Tests of the first test. */
227	uint32_t offTests : 23;
228	/** BS3CG1ENC values. */
229	uint32_t enmEncoding : 10;
230	/** BS3CG1PFXKIND values. */
231	uint32_t enmPrefixKind : 4;
232	/** CPU test / CPU ID bit test (BS3CG1CPU). */
233	uint32_t enmCpuTest : 6;
234	/** Exception type (BS3CG1XCPTTYPE) */
235	uint32_t enmXcptType : 5;
236	/** Currently unused bits. */
237	uint32_t uUnused : 6;
238	/** BS3CG1INSTR_F_XXX. */
239	uint32_t fFlags;
240	} BS3CG1INSTR;
241	AssertCompileSize(BS3CG1INSTR, 12);
242	/** Pointer to a const instruction. */
243	typedef BS3CG1INSTR const BS3_FAR *PCBS3CG1INSTR;
244
245
246	/** @name BS3CG1INSTR_F_XXX
247	* @{ */
248	/** Defaults to SS rather than DS. */
249	#define BS3CG1INSTR_F_DEF_SS UINT32_C(0x00000001)
250	/** Invalid instruction in 64-bit mode. */
251	#define BS3CG1INSTR_F_INVALID_64BIT UINT32_C(0x00000002)
252	/** Unused instruction. */
253	#define BS3CG1INSTR_F_UNUSED UINT32_C(0x00000004)
254	/** Invalid instruction. */
255	#define BS3CG1INSTR_F_INVALID UINT32_C(0x00000008)
256	/** Only intel does full ModR/M(, ++) decoding for invalid instruction.
257	* Always used with BS3CG1INSTR_F_INVALID or BS3CG1INSTR_F_UNUSED. */
258	#define BS3CG1INSTR_F_INTEL_DECODES_INVALID UINT32_C(0x00000010)
259	/** @} */
260
261
262	/**
263	* Test header.
264	*/
265	typedef struct BS3CG1TESTHDR
266	{
267	/** The size of the selector program in bytes.
268	* This is also the offset of the input context modification program. */
269	uint32_t cbSelector : 8;
270	/** The size of the input context modification program in bytes.
271	* This immediately follows the selector program. */
272	uint32_t cbInput : 12;
273	/** The size of the output context modification program in bytes.
274	* This immediately follows the input context modification program. The
275	* program takes the result of the input program as starting point. */
276	uint32_t cbOutput : 11;
277	/** Indicates whether this is the last test or not. */
278	uint32_t fLast : 1;
279	} BS3CG1TESTHDR;
280	AssertCompileSize(BS3CG1TESTHDR, 4);
281	/** Pointer to a const test header. */
282	typedef BS3CG1TESTHDR const BS3_FAR *PCBS3CG1TESTHDR;
283
284	/** @name Opcode format for the BS3CG1 context modifier.
285	*
286	* Used by both the input and output context programs.
287	*
288	* The most common operations are encoded as a single byte opcode followed by
289	* one or more immediate bytes with data.
290	*
291	* @{ */
292	#define BS3CG1_CTXOP_SIZE_MASK UINT8_C(0x07)
293	#define BS3CG1_CTXOP_1_BYTE UINT8_C(0x00)
294	#define BS3CG1_CTXOP_2_BYTES UINT8_C(0x01)
295	#define BS3CG1_CTXOP_4_BYTES UINT8_C(0x02)
296	#define BS3CG1_CTXOP_8_BYTES UINT8_C(0x03)
297	#define BS3CG1_CTXOP_16_BYTES UINT8_C(0x04)
298	#define BS3CG1_CTXOP_32_BYTES UINT8_C(0x05)
299	#define BS3CG1_CTXOP_12_BYTES UINT8_C(0x06)
300	#define BS3CG1_CTXOP_SIZE_ESC UINT8_C(0x07) /*< Separate byte encoding the value size following any destination escape byte. /
301
302	#define BS3CG1_CTXOP_DST_MASK UINT8_C(0x18)
303	#define BS3CG1_CTXOP_OP1 UINT8_C(0x00)
304	#define BS3CG1_CTXOP_OP2 UINT8_C(0x08)
305	#define BS3CG1_CTXOP_EFL UINT8_C(0x10)
306	#define BS3CG1_CTXOP_DST_ESC UINT8_C(0x18) /*< Separate byte giving the destination follows immediately. /
307
308	#define BS3CG1_CTXOP_SIGN_EXT UINT8_C(0x20) /*< Whether to sign-extend (set) the immediate value. /
309
310	#define BS3CG1_CTXOP_OPERATOR_MASK UINT8_C(0xc0)
311	#define BS3CG1_CTXOP_ASSIGN UINT8_C(0x00) /*< Simple assignment operator (=) /
312	#define BS3CG1_CTXOP_OR UINT8_C(0x40) /*< OR assignment operator (\|=). /
313	#define BS3CG1_CTXOP_AND UINT8_C(0x80) /*< AND assignment operator (&=). /
314	#define BS3CG1_CTXOP_AND_INV UINT8_C(0xc0) /*< AND assignment operator of the inverted value (&~=). /
315	/** @} */
316
317	/**
318	* Escaped destination values
319	*
320	* These are just uppercased versions of TestInOut.kdFields, where dots are
321	* replaced by underscores.
322	*/
323	typedef enum BS3CG1DST
324	{
325	BS3CG1DST_INVALID = 0,
326	/* Operands. */
327	BS3CG1DST_OP1,
328	BS3CG1DST_OP2,
329	BS3CG1DST_OP3,
330	BS3CG1DST_OP4,
331	/* Flags. */
332	BS3CG1DST_EFL,
333	BS3CG1DST_EFL_UNDEF, /*< Special field only valid in output context modifiers: EFLAGS \|= Value & Ouput.EFLAGS; /
334	/* 8-bit GPRs. */
335	BS3CG1DST_AL,
336	BS3CG1DST_CL,
337	BS3CG1DST_DL,
338	BS3CG1DST_BL,
339	BS3CG1DST_AH,
340	BS3CG1DST_CH,
341	BS3CG1DST_DH,
342	BS3CG1DST_BH,
343	BS3CG1DST_SPL,
344	BS3CG1DST_BPL,
345	BS3CG1DST_SIL,
346	BS3CG1DST_DIL,
347	BS3CG1DST_R8L,
348	BS3CG1DST_R9L,
349	BS3CG1DST_R10L,
350	BS3CG1DST_R11L,
351	BS3CG1DST_R12L,
352	BS3CG1DST_R13L,
353	BS3CG1DST_R14L,
354	BS3CG1DST_R15L,
355	/* 16-bit GPRs. */
356	BS3CG1DST_AX,
357	BS3CG1DST_CX,
358	BS3CG1DST_DX,
359	BS3CG1DST_BX,
360	BS3CG1DST_SP,
361	BS3CG1DST_BP,
362	BS3CG1DST_SI,
363	BS3CG1DST_DI,
364	BS3CG1DST_R8W,
365	BS3CG1DST_R9W,
366	BS3CG1DST_R10W,
367	BS3CG1DST_R11W,
368	BS3CG1DST_R12W,
369	BS3CG1DST_R13W,
370	BS3CG1DST_R14W,
371	BS3CG1DST_R15W,
372	/* 32-bit GPRs. */
373	BS3CG1DST_EAX,
374	BS3CG1DST_ECX,
375	BS3CG1DST_EDX,
376	BS3CG1DST_EBX,
377	BS3CG1DST_ESP,
378	BS3CG1DST_EBP,
379	BS3CG1DST_ESI,
380	BS3CG1DST_EDI,
381	BS3CG1DST_R8D,
382	BS3CG1DST_R9D,
383	BS3CG1DST_R10D,
384	BS3CG1DST_R11D,
385	BS3CG1DST_R12D,
386	BS3CG1DST_R13D,
387	BS3CG1DST_R14D,
388	BS3CG1DST_R15D,
389	/* 64-bit GPRs. */
390	BS3CG1DST_RAX,
391	BS3CG1DST_RCX,
392	BS3CG1DST_RDX,
393	BS3CG1DST_RBX,
394	BS3CG1DST_RSP,
395	BS3CG1DST_RBP,
396	BS3CG1DST_RSI,
397	BS3CG1DST_RDI,
398	BS3CG1DST_R8,
399	BS3CG1DST_R9,
400	BS3CG1DST_R10,
401	BS3CG1DST_R11,
402	BS3CG1DST_R12,
403	BS3CG1DST_R13,
404	BS3CG1DST_R14,
405	BS3CG1DST_R15,
406	/* 16-bit, 32-bit or 64-bit registers according to operand size. */
407	BS3CG1DST_OZ_RAX,
408	BS3CG1DST_OZ_RCX,
409	BS3CG1DST_OZ_RDX,
410	BS3CG1DST_OZ_RBX,
411	BS3CG1DST_OZ_RSP,
412	BS3CG1DST_OZ_RBP,
413	BS3CG1DST_OZ_RSI,
414	BS3CG1DST_OZ_RDI,
415	BS3CG1DST_OZ_R8,
416	BS3CG1DST_OZ_R9,
417	BS3CG1DST_OZ_R10,
418	BS3CG1DST_OZ_R11,
419	BS3CG1DST_OZ_R12,
420	BS3CG1DST_OZ_R13,
421	BS3CG1DST_OZ_R14,
422	BS3CG1DST_OZ_R15,
423
424	/* Control registers.*/
425	BS3CG1DST_CR0,
426	BS3CG1DST_CR4,
427	BS3CG1DST_XCR0,
428
429	/* FPU registers. */
430	BS3CG1DST_FPU_FIRST,
431	BS3CG1DST_FCW = BS3CG1DST_FPU_FIRST,
432	BS3CG1DST_FSW,
433	BS3CG1DST_FTW,
434	BS3CG1DST_FOP,
435	BS3CG1DST_FPUIP,
436	BS3CG1DST_FPUCS,
437	BS3CG1DST_FPUDP,
438	BS3CG1DST_FPUDS,
439	BS3CG1DST_MXCSR,
440	BS3CG1DST_ST0,
441	BS3CG1DST_ST1,
442	BS3CG1DST_ST2,
443	BS3CG1DST_ST3,
444	BS3CG1DST_ST4,
445	BS3CG1DST_ST5,
446	BS3CG1DST_ST6,
447	BS3CG1DST_ST7,
448	/* MMX registers. */
449	BS3CG1DST_MM0,
450	BS3CG1DST_MM1,
451	BS3CG1DST_MM2,
452	BS3CG1DST_MM3,
453	BS3CG1DST_MM4,
454	BS3CG1DST_MM5,
455	BS3CG1DST_MM6,
456	BS3CG1DST_MM7,
457	/* SSE registers. */
458	BS3CG1DST_XMM0,
459	BS3CG1DST_XMM1,
460	BS3CG1DST_XMM2,
461	BS3CG1DST_XMM3,
462	BS3CG1DST_XMM4,
463	BS3CG1DST_XMM5,
464	BS3CG1DST_XMM6,
465	BS3CG1DST_XMM7,
466	BS3CG1DST_XMM8,
467	BS3CG1DST_XMM9,
468	BS3CG1DST_XMM10,
469	BS3CG1DST_XMM11,
470	BS3CG1DST_XMM12,
471	BS3CG1DST_XMM13,
472	BS3CG1DST_XMM14,
473	BS3CG1DST_XMM15,
474	BS3CG1DST_XMM0_LO,
475	BS3CG1DST_XMM1_LO,
476	BS3CG1DST_XMM2_LO,
477	BS3CG1DST_XMM3_LO,
478	BS3CG1DST_XMM4_LO,
479	BS3CG1DST_XMM5_LO,
480	BS3CG1DST_XMM6_LO,
481	BS3CG1DST_XMM7_LO,
482	BS3CG1DST_XMM8_LO,
483	BS3CG1DST_XMM9_LO,
484	BS3CG1DST_XMM10_LO,
485	BS3CG1DST_XMM11_LO,
486	BS3CG1DST_XMM12_LO,
487	BS3CG1DST_XMM13_LO,
488	BS3CG1DST_XMM14_LO,
489	BS3CG1DST_XMM15_LO,
490	BS3CG1DST_XMM0_HI,
491	BS3CG1DST_XMM1_HI,
492	BS3CG1DST_XMM2_HI,
493	BS3CG1DST_XMM3_HI,
494	BS3CG1DST_XMM4_HI,
495	BS3CG1DST_XMM5_HI,
496	BS3CG1DST_XMM6_HI,
497	BS3CG1DST_XMM7_HI,
498	BS3CG1DST_XMM8_HI,
499	BS3CG1DST_XMM9_HI,
500	BS3CG1DST_XMM10_HI,
501	BS3CG1DST_XMM11_HI,
502	BS3CG1DST_XMM12_HI,
503	BS3CG1DST_XMM13_HI,
504	BS3CG1DST_XMM14_HI,
505	BS3CG1DST_XMM15_HI,
506	BS3CG1DST_XMM0_LO_ZX,
507	BS3CG1DST_XMM1_LO_ZX,
508	BS3CG1DST_XMM2_LO_ZX,
509	BS3CG1DST_XMM3_LO_ZX,
510	BS3CG1DST_XMM4_LO_ZX,
511	BS3CG1DST_XMM5_LO_ZX,
512	BS3CG1DST_XMM6_LO_ZX,
513	BS3CG1DST_XMM7_LO_ZX,
514	BS3CG1DST_XMM8_LO_ZX,
515	BS3CG1DST_XMM9_LO_ZX,
516	BS3CG1DST_XMM10_LO_ZX,
517	BS3CG1DST_XMM11_LO_ZX,
518	BS3CG1DST_XMM12_LO_ZX,
519	BS3CG1DST_XMM13_LO_ZX,
520	BS3CG1DST_XMM14_LO_ZX,
521	BS3CG1DST_XMM15_LO_ZX,
522	BS3CG1DST_XMM0_DW0,
523	BS3CG1DST_XMM1_DW0,
524	BS3CG1DST_XMM2_DW0,
525	BS3CG1DST_XMM3_DW0,
526	BS3CG1DST_XMM4_DW0,
527	BS3CG1DST_XMM5_DW0,
528	BS3CG1DST_XMM6_DW0,
529	BS3CG1DST_XMM7_DW0,
530	BS3CG1DST_XMM8_DW0,
531	BS3CG1DST_XMM9_DW0,
532	BS3CG1DST_XMM10_DW0,
533	BS3CG1DST_XMM11_DW0,
534	BS3CG1DST_XMM12_DW0,
535	BS3CG1DST_XMM13_DW0,
536	BS3CG1DST_XMM14_DW0,
537	BS3CG1DST_XMM15_DW0,
538	BS3CG1DST_XMM0_DW0_ZX,
539	BS3CG1DST_XMM1_DW0_ZX,
540	BS3CG1DST_XMM2_DW0_ZX,
541	BS3CG1DST_XMM3_DW0_ZX,
542	BS3CG1DST_XMM4_DW0_ZX,
543	BS3CG1DST_XMM5_DW0_ZX,
544	BS3CG1DST_XMM6_DW0_ZX,
545	BS3CG1DST_XMM7_DW0_ZX,
546	BS3CG1DST_XMM8_DW0_ZX,
547	BS3CG1DST_XMM9_DW0_ZX,
548	BS3CG1DST_XMM10_DW0_ZX,
549	BS3CG1DST_XMM11_DW0_ZX,
550	BS3CG1DST_XMM12_DW0_ZX,
551	BS3CG1DST_XMM13_DW0_ZX,
552	BS3CG1DST_XMM14_DW0_ZX,
553	BS3CG1DST_XMM15_DW0_ZX,
554	/* AVX registers. */
555	BS3CG1DST_YMM0,
556	BS3CG1DST_YMM1,
557	BS3CG1DST_YMM2,
558	BS3CG1DST_YMM3,
559	BS3CG1DST_YMM4,
560	BS3CG1DST_YMM5,
561	BS3CG1DST_YMM6,
562	BS3CG1DST_YMM7,
563	BS3CG1DST_YMM8,
564	BS3CG1DST_YMM9,
565	BS3CG1DST_YMM10,
566	BS3CG1DST_YMM11,
567	BS3CG1DST_YMM12,
568	BS3CG1DST_YMM13,
569	BS3CG1DST_YMM14,
570	BS3CG1DST_YMM15,
571
572	/* Special fields: */
573	BS3CG1DST_SPECIAL_START,
574	BS3CG1DST_VALUE_XCPT = BS3CG1DST_SPECIAL_START, /*< Expected exception based on input or result. /
575
576	BS3CG1DST_END
577	} BS3CG1DST;
578	AssertCompile(BS3CG1DST_END <= 256);
579
580	/** @name Selector opcode definitions.
581	*
582	* Selector programs are very simple, they are zero or more predicate tests
583	* that are ANDed together. If a predicate test fails, the test is skipped.
584	*
585	* One instruction is encoded as byte, where the first bit indicates what kind
586	* of test and the 7 remaining bits indicates which predicate to check.
587	*
588	* @{ */
589	#define BS3CG1SEL_OP_KIND_MASK UINT8_C(0x01) /*< The operator part (put in lower bit to reduce switch value range). /
590	#define BS3CG1SEL_OP_IS_TRUE UINT8_C(0x00) /*< Check that the predicate is true. /
591	#define BS3CG1SEL_OP_IS_FALSE UINT8_C(0x01) /*< Check that the predicate is false. /
592	#define BS3CG1SEL_OP_PRED_SHIFT 1 /*< Shift factor for getting/putting a BS3CG1PRED value into/from a byte. /
593	/** @} */
594
595	/**
596	* Test selector predicates (values are shifted by BS3CG1SEL_OP_PRED_SHIFT).
597	*/
598	typedef enum BS3CG1PRED
599	{
600	BS3CG1PRED_INVALID = 0,
601
602	/* Operand size. */
603	BS3CG1PRED_SIZE_O16,
604	BS3CG1PRED_SIZE_O32,
605	BS3CG1PRED_SIZE_O64,
606	/* Execution ring. */
607	BS3CG1PRED_RING_0,
608	BS3CG1PRED_RING_1,
609	BS3CG1PRED_RING_2,
610	BS3CG1PRED_RING_3,
611	BS3CG1PRED_RING_0_THRU_2,
612	BS3CG1PRED_RING_1_THRU_3,
613	/* Basic code mode. */
614	BS3CG1PRED_CODE_64BIT,
615	BS3CG1PRED_CODE_32BIT,
616	BS3CG1PRED_CODE_16BIT,
617	/* CPU modes. */
618	BS3CG1PRED_MODE_REAL,
619	BS3CG1PRED_MODE_PROT,
620	BS3CG1PRED_MODE_LONG,
621	BS3CG1PRED_MODE_V86,
622	BS3CG1PRED_MODE_SMM,
623	BS3CG1PRED_MODE_VMX,
624	BS3CG1PRED_MODE_SVM,
625	/* Paging on/off */
626	BS3CG1PRED_PAGING_ON,
627	BS3CG1PRED_PAGING_OFF,
628	/* CPU Vendors. */
629	BS3CG1PRED_VENDOR_AMD,
630	BS3CG1PRED_VENDOR_INTEL,
631	BS3CG1PRED_VENDOR_VIA,
632
633	BS3CG1PRED_END
634	} BS3CG1PRED;
635
636
637	/** The test instructions (generated). */
638	extern const BS3CG1INSTR BS3_FAR_DATA g_aBs3Cg1Instructions[];
639	/** The number of test instructions (generated). */
640	extern const uint16_t BS3_FAR_DATA g_cBs3Cg1Instructions;
641	/** The mnemonics (generated).
642	* Variable length sequence of mnemonics that runs in parallel to
643	* g_aBs3Cg1Instructions. */
644	extern const char BS3_FAR_DATA g_achBs3Cg1Mnemonics[];
645	/** The opcodes (generated).
646	* Variable length sequence of opcode bytes that runs in parallel to
647	* g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cbOpcodes each time. */
648	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Opcodes[];
649	/** The operands (generated).
650	* Variable length sequence of opcode values (BS3CG1OP) that runs in
651	* parallel to g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cOperands. */
652	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Operands[];
653	/** The test data that BS3CG1INSTR.
654	* In order to simplify generating these, we use a byte array. */
655	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Tests[];
656
657
658	#endif
659

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h@ 66744

Download in other formats: