bs3-cpu-generated-1.h@ 66462

Last change on this file since 66462 was 66462, checked in by vboxsync, 8 years ago
IEM,bs3-cpu-generated-1: Made the current testcases pass on AMD.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 16.9 KB

Line
1	/* $Id: bs3-cpu-generated-1.h 66462 2017-04-06 13:38:13Z vboxsync $ */
2	/** @file
3	* BS3Kit - bs3-cpu-generated-1, common header file.
4	*/
5
6	/*
7	* Copyright (C) 2007-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.215389.xyz. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27
28	#ifndef ___bs3_cpu_generated_1_h___
29	#define ___bs3_cpu_generated_1_h___
30
31	#include <bs3kit.h>
32	#include <iprt/assert.h>
33
34
35	/**
36	* Operand details.
37	*
38	* Currently simply using the encoding from the reference manuals.
39	*/
40	typedef enum BS3CG1OP
41	{
42	BS3CG1OP_INVALID = 0,
43
44	BS3CG1OP_Eb,
45	BS3CG1OP_Ev,
46	BS3CG1OP_Wss,
47	BS3CG1OP_Wsd,
48	BS3CG1OP_Wps,
49	BS3CG1OP_Wpd,
50	BS3CG1OP_Wdq,
51	BS3CG1OP_WqZxReg,
52
53	BS3CG1OP_Gb,
54	BS3CG1OP_Gv,
55	BS3CG1OP_Uq,
56	BS3CG1OP_UqHi,
57	BS3CG1OP_Vss,
58	BS3CG1OP_Vsd,
59	BS3CG1OP_Vps,
60	BS3CG1OP_Vpd,
61	BS3CG1OP_Vq,
62	BS3CG1OP_Vdq,
63
64	BS3CG1OP_Ib,
65	BS3CG1OP_Iz,
66
67	BS3CG1OP_AL,
68	BS3CG1OP_rAX,
69
70	BS3CG1OP_Ma,
71	BS3CG1OP_MbRO,
72	BS3CG1OP_MdRO,
73	BS3CG1OP_MdWO,
74	BS3CG1OP_Mq,
75
76	BS3CG1OP_END
77	} BS3CG1OP;
78	/** Pointer to a const operand enum. */
79	typedef const BS3CG1OP BS3_FAR *PCBS3CG1OP;
80
81
82	/**
83	* Instruction encoding format.
84	*
85	* This duplicates some of the info in the operand array, however it makes it
86	* easier to figure out encoding variations.
87	*/
88	typedef enum BS3CG1ENC
89	{
90	BS3CG1ENC_INVALID = 0,
91
92	BS3CG1ENC_MODRM_Eb_Gb,
93	BS3CG1ENC_MODRM_Ev_Gv,
94	BS3CG1ENC_MODRM_Wss_Vss,
95	BS3CG1ENC_MODRM_Wsd_Vsd,
96	BS3CG1ENC_MODRM_Wps_Vps,
97	BS3CG1ENC_MODRM_Wpd_Vpd,
98	BS3CG1ENC_MODRM_WqZxReg_Vq,
99
100	BS3CG1ENC_MODRM_Gb_Eb,
101	BS3CG1ENC_MODRM_Gv_Ev,
102	BS3CG1ENC_MODRM_Gv_Ma, /*< bound instruction /
103	BS3CG1ENC_MODRM_Vq_UqHi,
104	BS3CG1ENC_MODRM_Vq_Mq,
105	BS3CG1ENC_MODRM_Vdq_Wdq,
106	BS3CG1ENC_MODRM_MbRO,
107	BS3CG1ENC_MODRM_MdRO,
108	BS3CG1ENC_MODRM_MdWO,
109
110	BS3CG1ENC_VEX_MODRM_MdWO,
111
112	BS3CG1ENC_FIXED,
113	BS3CG1ENC_FIXED_AL_Ib,
114	BS3CG1ENC_FIXED_rAX_Iz,
115
116	BS3CG1ENC_MODRM_MOD_EQ_3, /*< Unused or invalid instruction. /
117	BS3CG1ENC_MODRM_MOD_NE_3, /*< Unused or invalid instruction. /
118
119	BS3CG1ENC_END
120	} BS3CG1ENC;
121
122
123	/**
124	* Prefix sensitivitiy kind.
125	*/
126	typedef enum BS3CG1PFXKIND
127	{
128	BS3CG1PFXKIND_INVALID = 0,
129
130	BS3CG1PFXKIND_NO_F2_F3_66, /*< No 66, F2 or F3 prefixes allowed as that would alter the meaning. /
131	BS3CG1PFXKIND_REQ_F2, /*< Requires F2 (REPNE) prefix as part of the instr encoding. /
132	BS3CG1PFXKIND_REQ_F3, /*< Requires F3 (REPE) prefix as part of the instr encoding. /
133	BS3CG1PFXKIND_REQ_66, /*< Requires 66 (OP SIZE) prefix as part of the instr encoding. /
134
135	/** @todo more work to be done here... */
136	BS3CG1PFXKIND_MODRM,
137	BS3CG1PFXKIND_MODRM_NO_OP_SIZES,
138
139	BS3CG1PFXKIND_END
140	} BS3CG1PFXKIND;
141
142	/**
143	* CPU selection or CPU ID.
144	*/
145	typedef enum BS3CG1CPU
146	{
147	/** Works with an CPU. */
148	BS3CG1CPU_ANY = 0,
149	BS3CG1CPU_GE_80186,
150	BS3CG1CPU_GE_80286,
151	BS3CG1CPU_GE_80386,
152	BS3CG1CPU_GE_80486,
153	BS3CG1CPU_GE_Pentium,
154
155	BS3CG1CPU_SSE,
156	BS3CG1CPU_SSE2,
157	BS3CG1CPU_SSE3,
158	BS3CG1CPU_AVX,
159	BS3CG1CPU_AVX2,
160	BS3CG1CPU_CLFSH,
161	BS3CG1CPU_CLFLUSHOPT,
162
163	BS3CG1CPU_END
164	} BS3CG1CPU;
165
166
167	/**
168	* SSE & AVX exception types.
169	*/
170	typedef enum BS3CG1XCPTTYPE
171	{
172	BS3CG1XCPTTYPE_NONE = 0,
173	/* SSE: */
174	BS3CG1XCPTTYPE_1,
175	BS3CG1XCPTTYPE_2,
176	BS3CG1XCPTTYPE_3,
177	BS3CG1XCPTTYPE_4,
178	BS3CG1XCPTTYPE_4UA,
179	BS3CG1XCPTTYPE_5,
180	BS3CG1XCPTTYPE_6,
181	BS3CG1XCPTTYPE_7,
182	BS3CG1XCPTTYPE_8,
183	BS3CG1XCPTTYPE_11,
184	BS3CG1XCPTTYPE_12,
185	/* EVEX: */
186	BS3CG1XCPTTYPE_E1,
187	BS3CG1XCPTTYPE_E1NF,
188	BS3CG1XCPTTYPE_E2,
189	BS3CG1XCPTTYPE_E3,
190	BS3CG1XCPTTYPE_E3NF,
191	BS3CG1XCPTTYPE_E4,
192	BS3CG1XCPTTYPE_E4NF,
193	BS3CG1XCPTTYPE_E5,
194	BS3CG1XCPTTYPE_E5NF,
195	BS3CG1XCPTTYPE_E6,
196	BS3CG1XCPTTYPE_E6NF,
197	BS3CG1XCPTTYPE_E7NF,
198	BS3CG1XCPTTYPE_E9,
199	BS3CG1XCPTTYPE_E9NF,
200	BS3CG1XCPTTYPE_E10,
201	BS3CG1XCPTTYPE_E11,
202	BS3CG1XCPTTYPE_E12,
203	BS3CG1XCPTTYPE_E12NF,
204	BS3CG1XCPTTYPE_END
205	} BS3CG1XCPTTYPE;
206	AssertCompile(BS3CG1XCPTTYPE_END <= 32);
207
208
209	/**
210	* Generated instruction info.
211	*/
212	typedef struct BS3CG1INSTR
213	{
214	/** The opcode size. */
215	uint32_t cbOpcodes : 2;
216	/** The number of operands. */
217	uint32_t cOperands : 2;
218	/** The length of the mnemonic. */
219	uint32_t cchMnemonic : 4;
220	/** Whether to advance the mnemonic array pointer. */
221	uint32_t fAdvanceMnemonic : 1;
222	/** Offset into g_abBs3Cg1Tests of the first test. */
223	uint32_t offTests : 23;
224	/** BS3CG1ENC values. */
225	uint32_t enmEncoding : 10;
226	/** BS3CG1PFXKIND values. */
227	uint32_t enmPrefixKind : 4;
228	/** CPU test / CPU ID bit test (BS3CG1CPU). */
229	uint32_t enmCpuTest : 6;
230	/** Exception type (BS3CG1XCPTTYPE) */
231	uint32_t enmXcptType : 5;
232	/** Currently unused bits. */
233	uint32_t uUnused : 6;
234	/** BS3CG1INSTR_F_XXX. */
235	uint32_t fFlags;
236	} BS3CG1INSTR;
237	AssertCompileSize(BS3CG1INSTR, 12);
238	/** Pointer to a const instruction. */
239	typedef BS3CG1INSTR const BS3_FAR *PCBS3CG1INSTR;
240
241
242	/** @name BS3CG1INSTR_F_XXX
243	* @{ */
244	/** Defaults to SS rather than DS. */
245	#define BS3CG1INSTR_F_DEF_SS UINT32_C(0x00000001)
246	/** Invalid instruction in 64-bit mode. */
247	#define BS3CG1INSTR_F_INVALID_64BIT UINT32_C(0x00000002)
248	/** Unused instruction. */
249	#define BS3CG1INSTR_F_UNUSED UINT32_C(0x00000004)
250	/** Invalid instruction. */
251	#define BS3CG1INSTR_F_INVALID UINT32_C(0x00000008)
252	/** Only intel does full ModR/M(, ++) decoding for invalid instruction.
253	* Always used with BS3CG1INSTR_F_INVALID or BS3CG1INSTR_F_UNUSED. */
254	#define BS3CG1INSTR_F_INTEL_DECODES_INVALID UINT32_C(0x00000010)
255	/** @} */
256
257
258	/**
259	* Test header.
260	*/
261	typedef struct BS3CG1TESTHDR
262	{
263	/** The size of the selector program in bytes.
264	* This is also the offset of the input context modification program. */
265	uint32_t cbSelector : 8;
266	/** The size of the input context modification program in bytes.
267	* This immediately follows the selector program. */
268	uint32_t cbInput : 12;
269	/** The size of the output context modification program in bytes.
270	* This immediately follows the input context modification program. The
271	* program takes the result of the input program as starting point. */
272	uint32_t cbOutput : 11;
273	/** Indicates whether this is the last test or not. */
274	uint32_t fLast : 1;
275	} BS3CG1TESTHDR;
276	AssertCompileSize(BS3CG1TESTHDR, 4);
277	/** Pointer to a const test header. */
278	typedef BS3CG1TESTHDR const BS3_FAR *PCBS3CG1TESTHDR;
279
280	/** @name Opcode format for the BS3CG1 context modifier.
281	*
282	* Used by both the input and output context programs.
283	*
284	* The most common operations are encoded as a single byte opcode followed by
285	* one or more immediate bytes with data.
286	*
287	* @{ */
288	#define BS3CG1_CTXOP_SIZE_MASK UINT8_C(0x07)
289	#define BS3CG1_CTXOP_1_BYTE UINT8_C(0x00)
290	#define BS3CG1_CTXOP_2_BYTES UINT8_C(0x01)
291	#define BS3CG1_CTXOP_4_BYTES UINT8_C(0x02)
292	#define BS3CG1_CTXOP_8_BYTES UINT8_C(0x03)
293	#define BS3CG1_CTXOP_16_BYTES UINT8_C(0x04)
294	#define BS3CG1_CTXOP_32_BYTES UINT8_C(0x05)
295	#define BS3CG1_CTXOP_12_BYTES UINT8_C(0x06)
296	#define BS3CG1_CTXOP_SIZE_ESC UINT8_C(0x07) /*< Separate byte encoding the value size following any destination escape byte. /
297
298	#define BS3CG1_CTXOP_DST_MASK UINT8_C(0x18)
299	#define BS3CG1_CTXOP_OP1 UINT8_C(0x00)
300	#define BS3CG1_CTXOP_OP2 UINT8_C(0x08)
301	#define BS3CG1_CTXOP_EFL UINT8_C(0x10)
302	#define BS3CG1_CTXOP_DST_ESC UINT8_C(0x18) /*< Separate byte giving the destination follows immediately. /
303
304	#define BS3CG1_CTXOP_SIGN_EXT UINT8_C(0x20) /*< Whether to sign-extend (set) the immediate value. /
305
306	#define BS3CG1_CTXOP_OPERATOR_MASK UINT8_C(0xc0)
307	#define BS3CG1_CTXOP_ASSIGN UINT8_C(0x00) /*< Simple assignment operator (=) /
308	#define BS3CG1_CTXOP_OR UINT8_C(0x40) /*< OR assignment operator (\|=). /
309	#define BS3CG1_CTXOP_AND UINT8_C(0x80) /*< AND assignment operator (&=). /
310	#define BS3CG1_CTXOP_AND_INV UINT8_C(0xc0) /*< AND assignment operator of the inverted value (&~=). /
311	/** @} */
312
313	/**
314	* Escaped destination values
315	*
316	* These are just uppercased versions of TestInOut.kdFields, where dots are
317	* replaced by underscores.
318	*/
319	typedef enum BS3CG1DST
320	{
321	BS3CG1DST_INVALID = 0,
322	/* Operands. */
323	BS3CG1DST_OP1,
324	BS3CG1DST_OP2,
325	BS3CG1DST_OP3,
326	BS3CG1DST_OP4,
327	/* Flags. */
328	BS3CG1DST_EFL,
329	BS3CG1DST_EFL_UNDEF, /*< Special field only valid in output context modifiers: EFLAGS \|= Value & Ouput.EFLAGS; /
330	/* 8-bit GPRs. */
331	BS3CG1DST_AL,
332	BS3CG1DST_CL,
333	BS3CG1DST_DL,
334	BS3CG1DST_BL,
335	BS3CG1DST_AH,
336	BS3CG1DST_CH,
337	BS3CG1DST_DH,
338	BS3CG1DST_BH,
339	BS3CG1DST_SPL,
340	BS3CG1DST_BPL,
341	BS3CG1DST_SIL,
342	BS3CG1DST_DIL,
343	BS3CG1DST_R8L,
344	BS3CG1DST_R9L,
345	BS3CG1DST_R10L,
346	BS3CG1DST_R11L,
347	BS3CG1DST_R12L,
348	BS3CG1DST_R13L,
349	BS3CG1DST_R14L,
350	BS3CG1DST_R15L,
351	/* 16-bit GPRs. */
352	BS3CG1DST_AX,
353	BS3CG1DST_CX,
354	BS3CG1DST_DX,
355	BS3CG1DST_BX,
356	BS3CG1DST_SP,
357	BS3CG1DST_BP,
358	BS3CG1DST_SI,
359	BS3CG1DST_DI,
360	BS3CG1DST_R8W,
361	BS3CG1DST_R9W,
362	BS3CG1DST_R10W,
363	BS3CG1DST_R11W,
364	BS3CG1DST_R12W,
365	BS3CG1DST_R13W,
366	BS3CG1DST_R14W,
367	BS3CG1DST_R15W,
368	/* 32-bit GPRs. */
369	BS3CG1DST_EAX,
370	BS3CG1DST_ECX,
371	BS3CG1DST_EDX,
372	BS3CG1DST_EBX,
373	BS3CG1DST_ESP,
374	BS3CG1DST_EBP,
375	BS3CG1DST_ESI,
376	BS3CG1DST_EDI,
377	BS3CG1DST_R8D,
378	BS3CG1DST_R9D,
379	BS3CG1DST_R10D,
380	BS3CG1DST_R11D,
381	BS3CG1DST_R12D,
382	BS3CG1DST_R13D,
383	BS3CG1DST_R14D,
384	BS3CG1DST_R15D,
385	/* 64-bit GPRs. */
386	BS3CG1DST_RAX,
387	BS3CG1DST_RCX,
388	BS3CG1DST_RDX,
389	BS3CG1DST_RBX,
390	BS3CG1DST_RSP,
391	BS3CG1DST_RBP,
392	BS3CG1DST_RSI,
393	BS3CG1DST_RDI,
394	BS3CG1DST_R8,
395	BS3CG1DST_R9,
396	BS3CG1DST_R10,
397	BS3CG1DST_R11,
398	BS3CG1DST_R12,
399	BS3CG1DST_R13,
400	BS3CG1DST_R14,
401	BS3CG1DST_R15,
402	/* 16-bit, 32-bit or 64-bit registers according to operand size. */
403	BS3CG1DST_OZ_RAX,
404	BS3CG1DST_OZ_RCX,
405	BS3CG1DST_OZ_RDX,
406	BS3CG1DST_OZ_RBX,
407	BS3CG1DST_OZ_RSP,
408	BS3CG1DST_OZ_RBP,
409	BS3CG1DST_OZ_RSI,
410	BS3CG1DST_OZ_RDI,
411	BS3CG1DST_OZ_R8,
412	BS3CG1DST_OZ_R9,
413	BS3CG1DST_OZ_R10,
414	BS3CG1DST_OZ_R11,
415	BS3CG1DST_OZ_R12,
416	BS3CG1DST_OZ_R13,
417	BS3CG1DST_OZ_R14,
418	BS3CG1DST_OZ_R15,
419
420	/* Control registers.*/
421	BS3CG1DST_CR0,
422	BS3CG1DST_CR4,
423	BS3CG1DST_XCR0,
424
425	/* FPU registers. */
426	BS3CG1DST_FPU_FIRST,
427	BS3CG1DST_FCW = BS3CG1DST_FPU_FIRST,
428	BS3CG1DST_FSW,
429	BS3CG1DST_FTW,
430	BS3CG1DST_FOP,
431	BS3CG1DST_FPUIP,
432	BS3CG1DST_FPUCS,
433	BS3CG1DST_FPUDP,
434	BS3CG1DST_FPUDS,
435	BS3CG1DST_MXCSR,
436	BS3CG1DST_ST0,
437	BS3CG1DST_ST1,
438	BS3CG1DST_ST2,
439	BS3CG1DST_ST3,
440	BS3CG1DST_ST4,
441	BS3CG1DST_ST5,
442	BS3CG1DST_ST6,
443	BS3CG1DST_ST7,
444	/* MMX registers. */
445	BS3CG1DST_MM0,
446	BS3CG1DST_MM1,
447	BS3CG1DST_MM2,
448	BS3CG1DST_MM3,
449	BS3CG1DST_MM4,
450	BS3CG1DST_MM5,
451	BS3CG1DST_MM6,
452	BS3CG1DST_MM7,
453	/* SSE registers. */
454	BS3CG1DST_XMM0,
455	BS3CG1DST_XMM1,
456	BS3CG1DST_XMM2,
457	BS3CG1DST_XMM3,
458	BS3CG1DST_XMM4,
459	BS3CG1DST_XMM5,
460	BS3CG1DST_XMM6,
461	BS3CG1DST_XMM7,
462	BS3CG1DST_XMM8,
463	BS3CG1DST_XMM9,
464	BS3CG1DST_XMM10,
465	BS3CG1DST_XMM11,
466	BS3CG1DST_XMM12,
467	BS3CG1DST_XMM13,
468	BS3CG1DST_XMM14,
469	BS3CG1DST_XMM15,
470	BS3CG1DST_XMM0_LO,
471	BS3CG1DST_XMM1_LO,
472	BS3CG1DST_XMM2_LO,
473	BS3CG1DST_XMM3_LO,
474	BS3CG1DST_XMM4_LO,
475	BS3CG1DST_XMM5_LO,
476	BS3CG1DST_XMM6_LO,
477	BS3CG1DST_XMM7_LO,
478	BS3CG1DST_XMM8_LO,
479	BS3CG1DST_XMM9_LO,
480	BS3CG1DST_XMM10_LO,
481	BS3CG1DST_XMM11_LO,
482	BS3CG1DST_XMM12_LO,
483	BS3CG1DST_XMM13_LO,
484	BS3CG1DST_XMM14_LO,
485	BS3CG1DST_XMM15_LO,
486	BS3CG1DST_XMM0_HI,
487	BS3CG1DST_XMM1_HI,
488	BS3CG1DST_XMM2_HI,
489	BS3CG1DST_XMM3_HI,
490	BS3CG1DST_XMM4_HI,
491	BS3CG1DST_XMM5_HI,
492	BS3CG1DST_XMM6_HI,
493	BS3CG1DST_XMM7_HI,
494	BS3CG1DST_XMM8_HI,
495	BS3CG1DST_XMM9_HI,
496	BS3CG1DST_XMM10_HI,
497	BS3CG1DST_XMM11_HI,
498	BS3CG1DST_XMM12_HI,
499	BS3CG1DST_XMM13_HI,
500	BS3CG1DST_XMM14_HI,
501	BS3CG1DST_XMM15_HI,
502	BS3CG1DST_XMM0_LO_ZX,
503	BS3CG1DST_XMM1_LO_ZX,
504	BS3CG1DST_XMM2_LO_ZX,
505	BS3CG1DST_XMM3_LO_ZX,
506	BS3CG1DST_XMM4_LO_ZX,
507	BS3CG1DST_XMM5_LO_ZX,
508	BS3CG1DST_XMM6_LO_ZX,
509	BS3CG1DST_XMM7_LO_ZX,
510	BS3CG1DST_XMM8_LO_ZX,
511	BS3CG1DST_XMM9_LO_ZX,
512	BS3CG1DST_XMM10_LO_ZX,
513	BS3CG1DST_XMM11_LO_ZX,
514	BS3CG1DST_XMM12_LO_ZX,
515	BS3CG1DST_XMM13_LO_ZX,
516	BS3CG1DST_XMM14_LO_ZX,
517	BS3CG1DST_XMM15_LO_ZX,
518	BS3CG1DST_XMM0_DW0,
519	BS3CG1DST_XMM1_DW0,
520	BS3CG1DST_XMM2_DW0,
521	BS3CG1DST_XMM3_DW0,
522	BS3CG1DST_XMM4_DW0,
523	BS3CG1DST_XMM5_DW0,
524	BS3CG1DST_XMM6_DW0,
525	BS3CG1DST_XMM7_DW0,
526	BS3CG1DST_XMM8_DW0,
527	BS3CG1DST_XMM9_DW0,
528	BS3CG1DST_XMM10_DW0,
529	BS3CG1DST_XMM11_DW0,
530	BS3CG1DST_XMM12_DW0,
531	BS3CG1DST_XMM13_DW0,
532	BS3CG1DST_XMM14_DW0,
533	BS3CG1DST_XMM15_DW0,
534	/* AVX registers. */
535	BS3CG1DST_YMM0,
536	BS3CG1DST_YMM1,
537	BS3CG1DST_YMM2,
538	BS3CG1DST_YMM3,
539	BS3CG1DST_YMM4,
540	BS3CG1DST_YMM5,
541	BS3CG1DST_YMM6,
542	BS3CG1DST_YMM7,
543	BS3CG1DST_YMM8,
544	BS3CG1DST_YMM9,
545	BS3CG1DST_YMM10,
546	BS3CG1DST_YMM11,
547	BS3CG1DST_YMM12,
548	BS3CG1DST_YMM13,
549	BS3CG1DST_YMM14,
550	BS3CG1DST_YMM15,
551
552	/* Special fields: */
553	BS3CG1DST_SPECIAL_START,
554	BS3CG1DST_VALUE_XCPT = BS3CG1DST_SPECIAL_START, /*< Expected exception based on input or result. /
555
556	BS3CG1DST_END
557	} BS3CG1DST;
558	AssertCompile(BS3CG1DST_END <= 256);
559
560	/** @name Selector opcode definitions.
561	*
562	* Selector programs are very simple, they are zero or more predicate tests
563	* that are ANDed together. If a predicate test fails, the test is skipped.
564	*
565	* One instruction is encoded as byte, where the first bit indicates what kind
566	* of test and the 7 remaining bits indicates which predicate to check.
567	*
568	* @{ */
569	#define BS3CG1SEL_OP_KIND_MASK UINT8_C(0x01) /*< The operator part (put in lower bit to reduce switch value range). /
570	#define BS3CG1SEL_OP_IS_TRUE UINT8_C(0x00) /*< Check that the predicate is true. /
571	#define BS3CG1SEL_OP_IS_FALSE UINT8_C(0x01) /*< Check that the predicate is false. /
572	#define BS3CG1SEL_OP_PRED_SHIFT 1 /*< Shift factor for getting/putting a BS3CG1PRED value into/from a byte. /
573	/** @} */
574
575	/**
576	* Test selector predicates (values are shifted by BS3CG1SEL_OP_PRED_SHIFT).
577	*/
578	typedef enum BS3CG1PRED
579	{
580	BS3CG1PRED_INVALID = 0,
581
582	/* Operand size. */
583	BS3CG1PRED_SIZE_O16,
584	BS3CG1PRED_SIZE_O32,
585	BS3CG1PRED_SIZE_O64,
586	/* Execution ring. */
587	BS3CG1PRED_RING_0,
588	BS3CG1PRED_RING_1,
589	BS3CG1PRED_RING_2,
590	BS3CG1PRED_RING_3,
591	BS3CG1PRED_RING_0_THRU_2,
592	BS3CG1PRED_RING_1_THRU_3,
593	/* Basic code mode. */
594	BS3CG1PRED_CODE_64BIT,
595	BS3CG1PRED_CODE_32BIT,
596	BS3CG1PRED_CODE_16BIT,
597	/* CPU modes. */
598	BS3CG1PRED_MODE_REAL,
599	BS3CG1PRED_MODE_PROT,
600	BS3CG1PRED_MODE_LONG,
601	BS3CG1PRED_MODE_V86,
602	BS3CG1PRED_MODE_SMM,
603	BS3CG1PRED_MODE_VMX,
604	BS3CG1PRED_MODE_SVM,
605	/* Paging on/off */
606	BS3CG1PRED_PAGING_ON,
607	BS3CG1PRED_PAGING_OFF,
608	/* CPU Vendors. */
609	BS3CG1PRED_VENDOR_AMD,
610	BS3CG1PRED_VENDOR_INTEL,
611	BS3CG1PRED_VENDOR_VIA,
612
613	BS3CG1PRED_END
614	} BS3CG1PRED;
615
616
617	/** The test instructions (generated). */
618	extern const BS3CG1INSTR BS3_FAR_DATA g_aBs3Cg1Instructions[];
619	/** The number of test instructions (generated). */
620	extern const uint16_t BS3_FAR_DATA g_cBs3Cg1Instructions;
621	/** The mnemonics (generated).
622	* Variable length sequence of mnemonics that runs in parallel to
623	* g_aBs3Cg1Instructions. */
624	extern const char BS3_FAR_DATA g_achBs3Cg1Mnemonics[];
625	/** The opcodes (generated).
626	* Variable length sequence of opcode bytes that runs in parallel to
627	* g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cbOpcodes each time. */
628	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Opcodes[];
629	/** The operands (generated).
630	* Variable length sequence of opcode values (BS3CG1OP) that runs in
631	* parallel to g_aBs3Cg1Instructions, advancing by BS3CG1INSTR::cOperands. */
632	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Operands[];
633	/** The test data that BS3CG1INSTR.
634	* In order to simplify generating these, we use a byte array. */
635	extern const uint8_t BS3_FAR_DATA g_abBs3Cg1Tests[];
636
637
638	#endif
639

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h@ 66462

Download in other formats: