bs3-cpu-decoding-1.c32@ 65527

Last change on this file since 65527 was 65527, checked in by vboxsync, 8 years ago
bs3-cpu-decoding-1: Working on testing undefined areas since these may include ModR/M and immediate decoding as well as unused 3-byte escapes.
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1	/* $Id: bs3-cpu-decoding-1.c32 65527 2017-01-30 22:58:31Z vboxsync $ */
2	/** @file
3	* BS3Kit - bs3-cpu-decoding-1, 32-bit C code.
4	*/
5
6	/*
7	* Copyright (C) 2007-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.215389.xyz. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27
28	/*********************************************************************************************************************************
29	* Header Files *
30	*********************************************************************************************************************************/
31	#include <bs3kit.h>
32	#include <iprt/asm-amd64-x86.h>
33
34
35	/*********************************************************************************************************************************
36	* Structures and Typedefs *
37	*********************************************************************************************************************************/
38	/**
39	* Simple test.
40	*/
41	typedef struct CPUDECODE1TST
42	{
43	uint16_t fFlags;
44	uint8_t cbOpcodes;
45	uint8_t abOpcodes[20];
46	uint8_t cbUd;
47	} CPUDECODE1TST;
48	typedef CPUDECODE1TST BS3_FAR *PCPUDECODE1TST;
49
50	#define P_CS X86_OP_PRF_CS
51	#define P_SS X86_OP_PRF_SS
52	#define P_DS X86_OP_PRF_DS
53	#define P_ES X86_OP_PRF_ES
54	#define P_FS X86_OP_PRF_FS
55	#define P_GS X86_OP_PRF_GS
56	#define P_OZ X86_OP_PRF_SIZE_OP
57	#define P_AZ X86_OP_PRF_SIZE_ADDR
58	#define P_LK X86_OP_PRF_LOCK
59	#define P_RZ X86_OP_PRF_REPZ
60	#define P_RN X86_OP_PRF_REPNZ
61
62	#define RM_EAX_EAX ((3 << X86_MODRM_MOD_SHIFT) \| (X86_GREG_xAX << X86_MODRM_REG_SHIFT) \| (X86_GREG_xAX))
63	#define RM_EAX_DEREF_EBX ((0 << X86_MODRM_MOD_SHIFT) \| (X86_GREG_xAX << X86_MODRM_REG_SHIFT) \| (X86_GREG_xBX))
64	#define RM_EAX_DEREF_EBX_DISP8 ((1 << X86_MODRM_MOD_SHIFT) \| (X86_GREG_xAX << X86_MODRM_REG_SHIFT) \| (X86_GREG_xBX))
65	#define RM_EAX_DEREF_EBX_DISP32 ((2 << X86_MODRM_MOD_SHIFT) \| (X86_GREG_xAX << X86_MODRM_REG_SHIFT) \| (X86_GREG_xBX))
66	#define RM_EAX_SIB ((0 << X86_MODRM_MOD_SHIFT) \| (X86_GREG_xAX << X86_MODRM_REG_SHIFT) \| 4)
67	#define RM_EAX_SIB_DISP8 ((1 << X86_MODRM_MOD_SHIFT) \| (X86_GREG_xAX << X86_MODRM_REG_SHIFT) \| 4)
68	#define RM_EAX_SIB_DISP32 ((2 << X86_MODRM_MOD_SHIFT) \| (X86_GREG_xAX << X86_MODRM_REG_SHIFT) \| 4)
69
70	#define SIB_EBX_X1_NONE ((0 << X86_SIB_SCALE_SHIFT) \| (4 << X86_SIB_INDEX_SHIFT) \| (X86_GREG_xBX))
71	#define SIB_EBX_X2_NONE ((1 << X86_SIB_SCALE_SHIFT) \| (4 << X86_SIB_INDEX_SHIFT) \| (X86_GREG_xBX))
72	#define SIB_EBX_X4_NONE ((2 << X86_SIB_SCALE_SHIFT) \| (4 << X86_SIB_INDEX_SHIFT) \| (X86_GREG_xBX))
73	#define SIB_EBX_X8_NONE ((3 << X86_SIB_SCALE_SHIFT) \| (4 << X86_SIB_INDEX_SHIFT) \| (X86_GREG_xBX))
74
75	#define F_486 UINT16_C(0x0000)
76	#define F_SSE2 UINT16_C(0x0001)
77	#define F_SSE3 UINT16_C(0x0002)
78	#define F_SSE42 UINT16_C(0x0004)
79	#define F_MOVBE UINT16_C(0x0080)
80	#define F_CBUD UINT16_C(0x4000)
81	#define F_UD UINT16_C(0x8000)
82	#define F_OK UINT16_C(0x0000)
83
84
85	/**
86	* This is an exploratory testcase. It tries to figure out how exactly the
87	* different Intel and AMD CPUs implements SSE and similar instructions that
88	* uses the size, repz, repnz and lock prefixes in the encoding.
89	*/
90	CPUDECODE1TST const g_aSimpleTests[] =
91	{
92	/*
93	* fFlags, cbUd, cbOpcodes, abOpcodes
94	*/
95	#if 0
96	/* Using currently undefined 0x0f 0x7a sequences. */
97	{ F_UD, 3, { 0x0f, 0x7a, RM_EAX_EAX, } },
98	{ F_UD, 3+1, { P_LK, 0x0f, 0x7a, RM_EAX_EAX, } },
99	{ F_UD, 3+1, { P_RN, 0x0f, 0x7a, RM_EAX_EAX, } },
100	{ F_UD, 3+1, { P_RZ, 0x0f, 0x7a, RM_EAX_EAX, } },
101	{ F_UD, 3+2, { P_LK, P_LK, 0x0f, 0x7a, RM_EAX_EAX, } },
102	{ F_UD, 4, { 0x0f, 0x7a, RM_EAX_DEREF_EBX_DISP8, 0 } },
103	{ F_UD, 4+1, { P_LK, 0x0f, 0x7a, RM_EAX_DEREF_EBX_DISP8, 0 } },
104	{ F_UD, 4+1, { P_RN, 0x0f, 0x7a, RM_EAX_DEREF_EBX_DISP8, 0 } },
105	{ F_UD, 4+1, { P_RZ, 0x0f, 0x7a, RM_EAX_DEREF_EBX_DISP8, 0 } },
106	{ F_UD, 4+2, { P_LK, P_LK, 0x0f, 0x7a, RM_EAX_DEREF_EBX_DISP8, 0 } },
107	{ F_UD, 7, { 0x0f, 0x7a, RM_EAX_DEREF_EBX_DISP32, 0, 0, 0, 0 } },
108	{ F_UD, 7+1, { P_LK, 0x0f, 0x7a, RM_EAX_DEREF_EBX_DISP32, 0, 0, 0, 0 } },
109	{ F_UD, 7+1, { P_RN, 0x0f, 0x7a, RM_EAX_DEREF_EBX_DISP32, 0, 0, 0, 0 } },
110	{ F_UD, 7+1, { P_RZ, 0x0f, 0x7a, RM_EAX_DEREF_EBX_DISP32, 0, 0, 0, 0 } },
111	{ F_UD, 7+2, { P_LK, P_LK, 0x0f, 0x7a, RM_EAX_DEREF_EBX_DISP32, 0, 0, 0, 0 } },
112	#endif
113	#if 0
114	/* Ditto for currently undefined sequence: 0x0f 0x7b */
115	{ F_UD, 3, { 0x0f, 0x7b, RM_EAX_EAX, } },
116	{ F_UD, 3+1, { P_LK, 0x0f, 0x7b, RM_EAX_EAX, } },
117	{ F_UD, 3+1, { P_RN, 0x0f, 0x7b, RM_EAX_EAX, } },
118	{ F_UD, 3+1, { P_RZ, 0x0f, 0x7b, RM_EAX_EAX, } },
119	{ F_UD, 3+2, { P_LK, P_LK, 0x0f, 0x7b, RM_EAX_EAX, } },
120	#endif
121	#if 1
122	/* Ditto for currently undefined sequence: 0x0f 0x24 */
123	{ F_UD, 3, { 0x0f, 0x24, RM_EAX_EAX, } },
124	{ F_UD, 3+1, { P_LK, 0x0f, 0x24, RM_EAX_EAX, } },
125	{ F_UD, 3+1, { P_RN, 0x0f, 0x24, RM_EAX_EAX, } },
126	{ F_UD, 3+1, { P_RZ, 0x0f, 0x24, RM_EAX_EAX, } },
127	{ F_UD, 3+2, { P_LK, P_LK, 0x0f, 0x24, RM_EAX_EAX, } },
128	#endif
129	#if 0
130	/* The XADD instruction has empty lines for 66, f3 and f2 prefixes.
131	AMD doesn't do anything special for XADD Ev,Gv as the intel table would indicate. */
132	{ F_486 \| F_OK, 3, { 0x0f, 0xc1, RM_EAX_EAX, } },
133	{ F_486 \| F_OK, 4, { P_OZ, 0x0f, 0xc1, RM_EAX_EAX, } },
134	{ F_486 \| F_OK, 4, { P_RN, 0x0f, 0xc1, RM_EAX_EAX, } },
135	{ F_486 \| F_OK, 5, { P_OZ, P_RN, 0x0f, 0xc1, RM_EAX_EAX, } },
136	{ F_486 \| F_OK, 5, { P_RN, P_OZ, 0x0f, 0xc1, RM_EAX_EAX, } },
137	{ F_486 \| F_OK, 4, { P_RZ, 0x0f, 0xc1, RM_EAX_EAX, } },
138	{ F_486 \| F_OK, 5, { P_OZ, P_RZ, 0x0f, 0xc1, RM_EAX_EAX, } },
139	{ F_486 \| F_OK, 5, { P_RZ, P_OZ, 0x0f, 0xc1, RM_EAX_EAX, } },
140	#endif
141	#if 0
142	/* The movnti instruction is confined to the unprefixed lined in the intel manuals. Check how the other lines work. */
143	{ F_SSE2 \| F_UD, 3, { 0x0f, 0xc3, RM_EAX_EAX, } }, /* invalid - reg,reg */
144	{ F_SSE2 \| F_OK, 3, { 0x0f, 0xc3, RM_EAX_DEREF_EBX, } },
145	{ F_SSE2 \| F_UD, 4, { P_OZ, 0x0f, 0xc3, RM_EAX_DEREF_EBX, } }, /* invalid */
146	{ F_SSE2 \| F_UD, 4, { P_RN, 0x0f, 0xc3, RM_EAX_DEREF_EBX, } }, /* invalid */
147	{ F_SSE2 \| F_UD, 4, { P_RZ, 0x0f, 0xc3, RM_EAX_DEREF_EBX, } }, /* invalid */
148	{ F_SSE2 \| F_UD, 4, { P_LK, 0x0f, 0xc3, RM_EAX_DEREF_EBX, } }, /* invalid */
149	{ F_SSE2 \| F_UD, 5, { P_RZ, P_LK, 0x0f, 0xc3, RM_EAX_DEREF_EBX, } }, /* invalid */
150	#endif
151	#if 0
152	/* The lddqu instruction requires a 0xf2 prefix, intel only lists 0x66 and empty
153	prefix for it. Check what they really mean by that*/
154	{ F_SSE3 \| F_UD, 4, { P_RZ, 0x0f, 0xf0, RM_EAX_EAX, } }, /* invalid - reg, reg */
155	{ F_SSE3 \| F_OK, 4, { P_RZ, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } },
156	{ F_SSE3 \| F_OK, 5, { P_RZ, P_RZ, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } },
157	{ F_SSE3 \| F_UD, 3, { 0x0f, 0xf0, RM_EAX_DEREF_EBX, } },
158	{ F_SSE3 \| F_UD, 4, { P_RN, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } },
159	{ F_SSE3 \| F_UD, 4, { P_OZ, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } },
160	{ F_SSE3 \| F_UD, 4, { P_LK, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } },
161	{ F_SSE3 \| F_UD, 5, { P_RZ, P_RN, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } },
162	{ F_SSE3 \| F_OK, 5, { P_RZ, P_OZ, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } }, // AMD,why?
163	{ F_SSE3 \| F_UD, 5, { P_RZ, P_LK, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } },
164	{ F_SSE3 \| F_OK, 5, { P_RN, P_RZ, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } },
165	{ F_SSE3 \| F_OK, 5, { P_OZ, P_RZ, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } },
166	{ F_SSE3 \| F_UD, 5, { P_LK, P_RZ, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } },
167	{ F_SSE3 \| F_OK, 5, { P_OZ, P_RZ, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } },
168	{ F_SSE3 \| F_OK, 6,{ P_OZ, P_RN, P_RZ, 0x0f, 0xf0, RM_EAX_DEREF_EBX, } },
169	#endif
170	#if 0
171	{ F_SSE2 \| F_OK, 3, { 0x0f, 0x7e, RM_EAX_EAX, } },
172	{ F_SSE2 \| F_OK, 4, { P_OZ, 0x0f, 0x7e, RM_EAX_EAX, } },
173	{ F_SSE2 \| F_UD, 5,{ P_RZ, P_OZ, 0x0f, 0x7e, RM_EAX_EAX, } }, // WTF?
174	{ F_SSE2 \| F_UD, 5,{ P_OZ, P_RZ, 0x0f, 0x7e, RM_EAX_EAX, } },
175	{ F_SSE2 \| F_OK, 5,{ P_RN, P_OZ, 0x0f, 0x7e, RM_EAX_EAX, } },
176	{ F_SSE2 \| F_OK, 4, { P_RN, 0x0f, 0x7e, RM_EAX_EAX, } },
177	{ F_SSE2 \| F_UD, 4, { P_RZ, 0x0f, 0x7e, RM_EAX_EAX, } },
178	#endif
179	/** @todo crc32 / movbe */
180	};
181
182	void DecodeEdgeTest(void)
183	{
184	/*
185	* Allocate and initialize a page pair
186	*/
187	uint8_t BS3_FAR *pbPages;
188	pbPages = Bs3MemGuardedTestPageAlloc(BS3MEMKIND_FLAT32);
189	if (pbPages)
190	{
191	unsigned i;
192	BS3REGCTX Ctx;
193	BS3TRAPFRAME TrapFrame;
194
195	Bs3MemZero(&Ctx, sizeof(Ctx));
196	Bs3MemZero(&TrapFrame, sizeof(TrapFrame));
197
198	ASMSetCR0((ASMGetCR0() & ~(X86_CR0_EM \| X86_CR0_TS)) \| X86_CR0_MP);
199	ASMSetCR4(ASMGetCR4() \| X86_CR4_OSFXSR);
200
201	Bs3RegCtxSaveEx(&Ctx, BS3_MODE_CODE_32, 512);
202	Ctx.rbx.u64 = (uintptr_t)pbPages;
203
204	for (i = 0; i < RT_ELEMENTS(g_aSimpleTests); i++)
205	{
206	unsigned const cbOpcodes = g_aSimpleTests[i].cbOpcodes;
207	uint16_t const fFlags = g_aSimpleTests[i].fFlags;
208	unsigned cb;
209	/** @todo check if supported. */
210
211	/*
212	* Place the instruction exactly at the page boundrary and proceed to
213	* move it across it and check that we get #PFs then.
214	*/
215	cb = cbOpcodes;
216	while (cb >= 1)
217	{
218	unsigned const cErrorsBefore = Bs3TestSubErrorCount();
219	uint8_t BS3_FAR *pbRip = &pbPages[X86_PAGE_SIZE - cb];
220	Bs3MemCpy(pbRip, &g_aSimpleTests[i].abOpcodes[0], cb);
221	Bs3RegCtxSetRipCsFromFlat(&Ctx, (uintptr_t)pbRip);
222	Bs3TrapSetJmpAndRestore(&Ctx, &TrapFrame);
223	#if 1
224	Bs3TestPrintf("\ni=%d cb=%#x (cbOpcodes=%#x fFlags=%#x)\n", i, cb, cbOpcodes, fFlags);
225	// Bs3TrapPrintFrame(&TrapFrame);
226	#endif
227	if (cb >= cbOpcodes && (g_aSimpleTests[i].fFlags & F_UD))
228	{
229	if (TrapFrame.bXcpt != X86_XCPT_UD)
230	Bs3TestFailedF("i=%d cb=%d cbOp=%d fFlags=%#x: expected #UD got %#x at %RX32\n",
231	i, cb, cbOpcodes, fFlags, TrapFrame.bXcpt, TrapFrame.Ctx.rip.u32);
232	}
233	else if (cb < cbOpcodes)
234	{
235	if (TrapFrame.bXcpt != X86_XCPT_PF)
236	Bs3TestFailedF("i=%d cb=%d cbOp=%d fFlags=%#x: expected #PF (on) got %#x at %RX32\n",
237	i, cb, cbOpcodes, fFlags, TrapFrame.bXcpt, TrapFrame.Ctx.rip.u32);
238	else if (TrapFrame.Ctx.rip.u32 != (uintptr_t)pbRip)
239	Bs3TestFailedF("i=%d cb=%d cbOp=%d fFlags=%#x: expected #PF rip of %p (on) got %#RX32\n",
240	i, cb, cbOpcodes, fFlags, pbRip, TrapFrame.Ctx.rip.u32);
241	}
242	else
243	{
244	if (TrapFrame.bXcpt != X86_XCPT_PF)
245	Bs3TestFailedF("i=%d cb=%d cbOp=%d fFlags=%#x: expected #PF (after) got %#x at %RX32\n",
246	i, cb, cbOpcodes, fFlags, TrapFrame.bXcpt, TrapFrame.Ctx.rip.u32);
247	else if (TrapFrame.Ctx.rip.u32 != (uintptr_t)&pbPages[X86_PAGE_SIZE])
248	Bs3TestFailedF("i=%d cb=%d cbOp=%d fFlags=%#x: expected #PF rip of %p (after) got %#RX32\n",
249	i, cb, cbOpcodes, fFlags, &pbPages[X86_PAGE_SIZE], TrapFrame.Ctx.rip.u32);
250	}
251	if (Bs3TestSubErrorCount() != cErrorsBefore)
252	{
253	Bs3TestPrintf(" %.*Rhxs", cb, &g_aSimpleTests[i].abOpcodes[0]);
254	if (cb < cbOpcodes)
255	Bs3TestPrintf("[%.*Rhxs]", cbOpcodes - cb, &g_aSimpleTests[i].abOpcodes[cb]);
256	Bs3TestPrintf("\n");
257	}
258
259	/* next */
260	cb--;
261	}
262	}
263
264	Bs3MemGuardedTestPageFree(pbPages);
265	}
266	else
267	Bs3TestFailed("Failed to allocate two pages!\n");
268
269	/*
270	* Test instruction sequences.
271	*/
272
273
274	}
275
276
277	/**
278	* Undefined opcode test.
279	*/
280	typedef struct CPUDECODE1UDTST
281	{
282	/** Type of undefined opcode decoding logic - UD_T_XXX. */
283	uint8_t enmType;
284	/** Core opcodes length. */
285	uint8_t cbOpcodes;
286	/** Core opcodes. */
287	uint8_t abOpcodes[5];
288	/** UD_F_XXX. */
289	uint8_t fFlags;
290	} CPUDECODE1UDTST;
291	typedef CPUDECODE1UDTST const BS3_FAR *PCCPUDECODE1UDTST;
292
293	#define UD_T_EXACT 0
294	#define UD_T_MODRM 1
295	#define UD_T_MODRM_IMM8 2
296
297	#define UD_F_ANY_PFX 0
298	#define UD_F_NOT_NO_PFX UINT8_C(0x01) /*< Must have some kind of prefix to be \#UD. /
299	#define UD_F_NOT_OZ_PFX UINT8_C(0x02) /*< Skip the size prefix. /
300	#define UD_F_NOT_RZ_PFX UINT8_C(0x04) /*< Skip the REPZ prefix. /
301	#define UD_F_NOT_RN_PFX UINT8_C(0x08) /*< Skip the REPNZ prefix. /
302	#define UD_F_NOT_LK_PFX UINT8_C(0x10) /*< Skip the LOCK prefix. /
303	#define UD_F_3BYTE_ESC UINT8_C(0x20) /*< Unused 3 byte escape table. Test all 256 entries /
304
305	CPUDECODE1UDTST const g_aUdTest[] =
306	{
307	/* Two byte opcodes. */
308	{ UD_T_EXACT, 2, { 0x0f, 0x04 }, UD_F_ANY_PFX },
309	{ UD_T_EXACT, 2, { 0x0f, 0x0a }, UD_F_ANY_PFX },
310	{ UD_T_EXACT, 2, { 0x0f, 0x0c }, UD_F_ANY_PFX },
311	{ UD_T_EXACT, 2, { 0x0f, 0x0e }, UD_F_ANY_PFX },
312	{ UD_T_EXACT, 2, { 0x0f, 0x0f }, UD_F_ANY_PFX },
313	{ UD_T_MODRM, 2, { 0x0f, 0x13 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
314	{ UD_T_MODRM, 2, { 0x0f, 0x14 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
315	{ UD_T_MODRM, 2, { 0x0f, 0x15 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
316	{ UD_T_MODRM, 2, { 0x0f, 0x16 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX \| UD_F_NOT_RN_PFX },
317	{ UD_T_MODRM, 2, { 0x0f, 0x17 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
318	/** @todo figure when 0f 019 and 0f 0c-0f were made into NOPs. */
319	{ UD_T_EXACT, 2, { 0x0f, 0x24 }, UD_F_ANY_PFX },
320	{ UD_T_EXACT, 2, { 0x0f, 0x25 }, UD_F_ANY_PFX },
321	{ UD_T_EXACT, 2, { 0x0f, 0x26 }, UD_F_ANY_PFX },
322	{ UD_T_EXACT, 2, { 0x0f, 0x27 }, UD_F_ANY_PFX },
323	{ UD_T_MODRM, 2, { 0x0f, 0x28 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
324	{ UD_T_MODRM, 2, { 0x0f, 0x29 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
325	{ UD_T_MODRM, 2, { 0x0f, 0x2b }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
326	{ UD_T_MODRM, 2, { 0x0f, 0x2e }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
327	{ UD_T_MODRM, 2, { 0x0f, 0x2f }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
328	{ UD_T_EXACT, 2, { 0x0f, 0x36 }, UD_F_ANY_PFX },
329	{ UD_T_MODRM, 3, { 0x0f, 0x39, 0x00 }, UD_F_3BYTE_ESC \| UD_F_ANY_PFX }, /* Three byte escape table, just unused. */
330	{ UD_T_MODRM_IMM8, 3, { 0x0f, 0x3b, 0x00 }, UD_F_3BYTE_ESC \| UD_F_ANY_PFX }, /* Three byte escape table, just unused. */
331	{ UD_T_MODRM, 3, { 0x0f, 0x3c, 0x00 }, UD_F_3BYTE_ESC \| UD_F_ANY_PFX }, /* Three byte escape table, just unused. */
332	{ UD_T_MODRM, 3, { 0x0f, 0x3d, 0x00 }, UD_F_3BYTE_ESC \| UD_F_ANY_PFX }, /* Three byte escape table, just unused. */
333	{ UD_T_MODRM_IMM8, 3, { 0x0f, 0x3e, 0x00 }, UD_F_3BYTE_ESC \| UD_F_ANY_PFX }, /* Three byte escape table, just unused. */
334	{ UD_T_MODRM_IMM8, 3, { 0x0f, 0x3f, 0x00 }, UD_F_3BYTE_ESC \| UD_F_ANY_PFX }, /* Three byte escape table, just unused. */
335	{ UD_T_MODRM, 2, { 0x0f, 0x50 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
336	{ UD_T_MODRM, 2, { 0x0f, 0x52 }, UD_F_NOT_NO_PFX \| UD_F_NOT_RN_PFX },
337	{ UD_T_MODRM, 2, { 0x0f, 0x53 }, UD_F_NOT_NO_PFX \| UD_F_NOT_RN_PFX },
338	{ UD_T_MODRM, 2, { 0x0f, 0x54 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
339	{ UD_T_MODRM, 2, { 0x0f, 0x55 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
340	{ UD_T_MODRM, 2, { 0x0f, 0x56 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
341	{ UD_T_MODRM, 2, { 0x0f, 0x57 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
342	{ UD_T_MODRM, 2, { 0x0f, 0x5b }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX \| UD_F_NOT_RN_PFX },
343	{ UD_T_MODRM, 2, { 0x0f, 0x60 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
344	{ UD_T_MODRM, 2, { 0x0f, 0x61 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
345	{ UD_T_MODRM, 2, { 0x0f, 0x62 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
346	{ UD_T_MODRM, 2, { 0x0f, 0x63 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
347	{ UD_T_MODRM, 2, { 0x0f, 0x64 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
348	{ UD_T_MODRM, 2, { 0x0f, 0x65 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
349	{ UD_T_MODRM, 2, { 0x0f, 0x66 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
350	{ UD_T_MODRM, 2, { 0x0f, 0x67 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
351	{ UD_T_MODRM, 2, { 0x0f, 0x68 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
352	{ UD_T_MODRM, 2, { 0x0f, 0x69 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
353	{ UD_T_MODRM, 2, { 0x0f, 0x6a }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
354	{ UD_T_MODRM, 2, { 0x0f, 0x6b }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
355	{ UD_T_MODRM, 2, { 0x0f, 0x6c }, UD_F_NOT_OZ_PFX },
356	{ UD_T_MODRM, 2, { 0x0f, 0x6d }, UD_F_NOT_OZ_PFX },
357	{ UD_T_MODRM, 2, { 0x0f, 0x6e }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
358	{ UD_T_MODRM, 2, { 0x0f, 0x6f }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX \| UD_F_NOT_RN_PFX },
359	{ UD_T_MODRM, 2, { 0x0f, 0x74 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
360	{ UD_T_MODRM, 2, { 0x0f, 0x75 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
361	{ UD_T_MODRM, 2, { 0x0f, 0x76 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
362	/* 0f 77: WTF? OZ, RZ and RN are all empty in the intel tables and LK isn't metnioned at all: */
363	{ UD_T_MODRM, 2, { 0x0f, 0x77 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX \| UD_F_NOT_RZ_PFX \| UD_F_NOT_RN_PFX \| UD_F_NOT_LK_PFX },
364	{ UD_T_MODRM, 2, { 0x0f, 0x78 }, UD_F_NOT_NO_PFX },
365	{ UD_T_MODRM, 2, { 0x0f, 0x79 }, UD_F_NOT_NO_PFX },
366	{ UD_T_MODRM, 2, { 0x0f, 0x7a }, UD_F_ANY_PFX },
367	{ UD_T_MODRM, 2, { 0x0f, 0x7b }, UD_F_ANY_PFX },
368	{ UD_T_MODRM, 2, { 0x0f, 0x7c }, UD_F_NOT_OZ_PFX \| UD_F_NOT_RZ_PFX },
369	{ UD_T_MODRM, 2, { 0x0f, 0x7d }, UD_F_NOT_OZ_PFX \| UD_F_NOT_RZ_PFX },
370	{ UD_T_MODRM, 2, { 0x0f, 0x7e }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX \| UD_F_NOT_RN_PFX },
371	{ UD_T_MODRM, 2, { 0x0f, 0x7f }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX \| UD_F_NOT_RN_PFX },
372	{ UD_T_MODRM, 2, { 0x0f, 0xa6 }, UD_F_ANY_PFX },
373	{ UD_T_MODRM, 2, { 0x0f, 0xa7 }, UD_F_ANY_PFX },
374	{ UD_T_MODRM, 2, { 0x0f, 0xb8 }, UD_F_NOT_RN_PFX },
375	/** @todo f3 0f bb rm and f2 0f bb rm does stuff on skylake even if their are blank in intel and AMD tables! */
376	//{ UD_T_MODRM, 2, { 0x0f, 0xbb }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
377	/** @todo AMD tables indicates that f2 0f bc rm is invalid, but on skylake it works differently (BSF?) */
378	{ UD_T_MODRM, 2, { 0x0f, 0xbc }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX \| UD_F_NOT_RN_PFX /* figure: */ \| UD_F_NOT_RZ_PFX },
379	/** @todo AMD tables indicates that f3 0f bc rm is invalid, but on skylake it works differently (BSR?) */
380	{ UD_T_MODRM, 2, { 0x0f, 0xbd }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX \| UD_F_NOT_RN_PFX /* figure: */ \| UD_F_NOT_RZ_PFX },
381	/* Note! Intel incorrectly states that XADD (0f c0 and 0f c1) are sensitive to OZ, RN and RZ. AMD and skylake hw disagrees. */
382	{ UD_T_MODRM, 2, { 0x0f, 0xc3 }, UD_F_NOT_NO_PFX },
383	{ UD_T_MODRM_IMM8, 2, { 0x0f, 0xc4 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
384	{ UD_T_MODRM_IMM8, 2, { 0x0f, 0xc5 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
385	{ UD_T_MODRM_IMM8, 2, { 0x0f, 0xc6 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
386	{ UD_T_MODRM, 2, { 0x0f, 0xd0 }, UD_F_NOT_OZ_PFX \| UD_F_NOT_RZ_PFX },
387	{ UD_T_MODRM, 2, { 0x0f, 0xd1 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
388	{ UD_T_MODRM, 2, { 0x0f, 0xd2 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
389	{ UD_T_MODRM, 2, { 0x0f, 0xd3 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
390	{ UD_T_MODRM, 2, { 0x0f, 0xd4 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
391	{ UD_T_MODRM, 2, { 0x0f, 0xd5 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
392	{ UD_T_MODRM, 2, { 0x0f, 0xd6 }, UD_F_NOT_OZ_PFX \| UD_F_NOT_RZ_PFX \| UD_F_NOT_RN_PFX },
393	{ UD_T_MODRM, 2, { 0x0f, 0xd7 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
394	{ UD_T_MODRM, 2, { 0x0f, 0xd8 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
395	{ UD_T_MODRM, 2, { 0x0f, 0xd9 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
396	{ UD_T_MODRM, 2, { 0x0f, 0xda }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
397	{ UD_T_MODRM, 2, { 0x0f, 0xdb }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
398	{ UD_T_MODRM, 2, { 0x0f, 0xdc }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
399	{ UD_T_MODRM, 2, { 0x0f, 0xdd }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
400	{ UD_T_MODRM, 2, { 0x0f, 0xde }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
401	{ UD_T_MODRM, 2, { 0x0f, 0xdf }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
402	{ UD_T_MODRM, 2, { 0x0f, 0xe0 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
403	{ UD_T_MODRM, 2, { 0x0f, 0xe1 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
404	{ UD_T_MODRM, 2, { 0x0f, 0xe2 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
405	{ UD_T_MODRM, 2, { 0x0f, 0xe3 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
406	{ UD_T_MODRM, 2, { 0x0f, 0xe4 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
407	{ UD_T_MODRM, 2, { 0x0f, 0xe5 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
408	{ UD_T_MODRM, 2, { 0x0f, 0xe6 }, UD_F_NOT_OZ_PFX \| UD_F_NOT_RZ_PFX \| UD_F_NOT_RN_PFX },
409	{ UD_T_MODRM, 2, { 0x0f, 0xe7 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
410	{ UD_T_MODRM, 2, { 0x0f, 0xe8 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
411	{ UD_T_MODRM, 2, { 0x0f, 0xe9 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
412	{ UD_T_MODRM, 2, { 0x0f, 0xea }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
413	{ UD_T_MODRM, 2, { 0x0f, 0xeb }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
414	{ UD_T_MODRM, 2, { 0x0f, 0xec }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
415	{ UD_T_MODRM, 2, { 0x0f, 0xed }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
416	{ UD_T_MODRM, 2, { 0x0f, 0xee }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
417	{ UD_T_MODRM, 2, { 0x0f, 0xef }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
418	{ UD_T_MODRM, 2, { 0x0f, 0xf0 }, UD_F_NOT_RZ_PFX },
419	{ UD_T_MODRM, 2, { 0x0f, 0xf1 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
420	{ UD_T_MODRM, 2, { 0x0f, 0xf2 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
421	{ UD_T_MODRM, 2, { 0x0f, 0xf3 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
422	{ UD_T_MODRM, 2, { 0x0f, 0xf4 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
423	{ UD_T_MODRM, 2, { 0x0f, 0xf5 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
424	{ UD_T_MODRM, 2, { 0x0f, 0xf6 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
425	{ UD_T_MODRM, 2, { 0x0f, 0xf7 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
426	{ UD_T_MODRM, 2, { 0x0f, 0xf8 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
427	{ UD_T_MODRM, 2, { 0x0f, 0xf9 }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
428	{ UD_T_MODRM, 2, { 0x0f, 0xfa }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
429	{ UD_T_MODRM, 2, { 0x0f, 0xfb }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
430	{ UD_T_MODRM, 2, { 0x0f, 0xfc }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
431	{ UD_T_MODRM, 2, { 0x0f, 0xfd }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
432	{ UD_T_MODRM, 2, { 0x0f, 0xfe }, UD_F_NOT_NO_PFX \| UD_F_NOT_OZ_PFX },
433	{ UD_T_MODRM, 2, { 0x0f, 0xff }, UD_F_ANY_PFX },
434	};
435
436
437	void DecodeUdEdgeTest(PCCPUDECODE1UDTST paTests, unsigned cTests)
438	{
439	/*
440	* Allocate and initialize a page pair
441	*/
442	uint8_t BS3_FAR *pbPages;
443	pbPages = Bs3MemGuardedTestPageAlloc(BS3MEMKIND_FLAT32);
444	if (pbPages)
445	{
446	unsigned iTest;
447	BS3REGCTX Ctx;
448	BS3REGCTX ExpectCtx;
449	BS3TRAPFRAME TrapFrame;
450	uint32_t iStep;
451
452	Bs3MemZero(&Ctx, sizeof(Ctx));
453	Bs3MemZero(&ExpectCtx, sizeof(ExpectCtx));
454	Bs3MemZero(&TrapFrame, sizeof(TrapFrame));
455
456	/* Enable SSE. */
457	ASMSetCR0((ASMGetCR0() & ~(X86_CR0_EM \| X86_CR0_TS)) \| X86_CR0_MP);
458	ASMSetCR4(ASMGetCR4() \| X86_CR4_OSFXSR);
459
460	/* Create a test context. */
461	Bs3RegCtxSaveEx(&Ctx, BS3_MODE_CODE_32, 512);
462	Ctx.rbx.u = (uintptr_t)pbPages;
463	Ctx.rcx.u = (uintptr_t)pbPages;
464	Ctx.rdx.u = (uintptr_t)pbPages;
465	Ctx.rax.u = (uintptr_t)pbPages;
466	Ctx.rbp.u = (uintptr_t)pbPages;
467	Ctx.rsi.u = (uintptr_t)pbPages;
468	Ctx.rdi.u = (uintptr_t)pbPages;
469
470	Bs3MemCpy(&ExpectCtx, &Ctx, sizeof(ExpectCtx));
471	ExpectCtx.rflags.u32 \|= X86_EFL_RF;
472
473	/* Loop thru the tests. */
474	iStep = g_usBs3TestStep = 0;
475	for (iTest = 0; iTest < cTests; iTest++)
476	{
477	typedef struct CPUDECODE1UDSEQ
478	{
479	uint8_t cb;
480	uint8_t ab[10];
481	uint8_t fIncompatible;
482	} CPUDECODE1UDSEQ;
483	typedef CPUDECODE1UDSEQ const BS3_FAR *PCCPUDECODE1UDSEQ;
484
485	static CPUDECODE1UDSEQ const s_aPrefixes[] =
486	{
487	{ 0, { 0 }, UD_F_NOT_NO_PFX },
488	{ 1, { P_OZ }, UD_F_NOT_OZ_PFX },
489	{ 1, { P_RZ }, UD_F_NOT_RZ_PFX },
490	{ 1, { P_RN }, UD_F_NOT_RN_PFX },
491	{ 1, { P_LK }, UD_F_NOT_LK_PFX },
492	{ 2, { P_OZ, P_OZ }, UD_F_NOT_OZ_PFX \| UD_F_NOT_OZ_PFX },
493	{ 2, { P_RZ, P_OZ }, UD_F_NOT_RZ_PFX \| UD_F_NOT_OZ_PFX },
494	{ 2, { P_RN, P_OZ }, UD_F_NOT_RN_PFX \| UD_F_NOT_OZ_PFX },
495	{ 2, { P_LK, P_OZ }, UD_F_NOT_LK_PFX \| UD_F_NOT_OZ_PFX },
496	{ 2, { P_OZ, P_RZ }, UD_F_NOT_OZ_PFX \| UD_F_NOT_RZ_PFX },
497	{ 2, { P_RZ, P_RZ }, UD_F_NOT_RZ_PFX \| UD_F_NOT_RZ_PFX },
498	{ 2, { P_RN, P_RZ }, UD_F_NOT_RN_PFX \| UD_F_NOT_RZ_PFX },
499	{ 2, { P_LK, P_RZ }, UD_F_NOT_LK_PFX \| UD_F_NOT_RZ_PFX },
500	{ 2, { P_OZ, P_RN }, UD_F_NOT_OZ_PFX \| UD_F_NOT_RN_PFX },
501	{ 2, { P_RZ, P_RN }, UD_F_NOT_RZ_PFX \| UD_F_NOT_RN_PFX },
502	{ 2, { P_RN, P_RN }, UD_F_NOT_RN_PFX \| UD_F_NOT_RN_PFX },
503	{ 2, { P_LK, P_RN }, UD_F_NOT_LK_PFX \| UD_F_NOT_RN_PFX },
504	{ 2, { P_OZ, P_LK }, UD_F_NOT_OZ_PFX \| UD_F_NOT_LK_PFX },
505	{ 2, { P_RZ, P_LK }, UD_F_NOT_RZ_PFX \| UD_F_NOT_LK_PFX },
506	{ 2, { P_RN, P_LK }, UD_F_NOT_RN_PFX \| UD_F_NOT_LK_PFX },
507	{ 2, { P_LK, P_LK }, UD_F_NOT_LK_PFX \| UD_F_NOT_LK_PFX },
508	};
509
510	static CPUDECODE1UDSEQ const s_aExact[] = { { 0, { 0 }, 0 } };
511	static CPUDECODE1UDSEQ const s_aModRm[] =
512	{
513	{ 1, { RM_EAX_EAX, }, 0 },
514	{ 2, { RM_EAX_DEREF_EBX_DISP8, 0 }, 0 },
515	{ 5, { RM_EAX_DEREF_EBX_DISP32, 0, 0, 0, 0 }, 0 },
516	{ 2, { RM_EAX_SIB, SIB_EBX_X1_NONE, }, 0 },
517	{ 3, { RM_EAX_SIB_DISP8, SIB_EBX_X1_NONE, 0 }, 0 },
518	{ 6, { RM_EAX_SIB_DISP32, SIB_EBX_X1_NONE, 0, 0, 0, 0 }, 0 },
519	};
520	static CPUDECODE1UDSEQ const s_aModRmImm8[] =
521	{
522	{ 1 + 1, { RM_EAX_EAX, 0x11 }, 0 },
523	{ 2 + 1, { RM_EAX_DEREF_EBX_DISP8, 0, 0x11 }, 0 },
524	{ 5 + 1, { RM_EAX_DEREF_EBX_DISP32, 0, 0, 0, 0, 0x11 }, 0 },
525	{ 2 + 1, { RM_EAX_SIB, SIB_EBX_X1_NONE, 0x11 }, 0 },
526	{ 3 + 1, { RM_EAX_SIB_DISP8, SIB_EBX_X1_NONE, 0, 0x11 }, 0 },
527	{ 6 + 1, { RM_EAX_SIB_DISP32, SIB_EBX_X1_NONE, 0, 0, 0, 0, 0x11 }, 0 },
528	};
529	unsigned iPrefix;
530	unsigned cSuffixes;
531	PCCPUDECODE1UDSEQ paSuffixes;
532	unsigned const cSubTabEntries = paTests[iTest].fFlags & UD_F_3BYTE_ESC ? 256 : 1;
533	unsigned cImmEntries = 1;
534
535	/*
536	* Skip if implemented.
537	*/
538
539	/*
540	* Produce a number of opcode sequences by varying the prefixes and
541	* ModR/M parts. Each opcode sequence is then treated to the edge test.
542	*/
543	switch (paTests[iTest].enmType)
544	{
545	case UD_T_EXACT:
546	cSuffixes = RT_ELEMENTS(s_aExact);
547	paSuffixes = s_aExact;
548	break;
549	case UD_T_MODRM:
550	cSuffixes = RT_ELEMENTS(s_aModRm);
551	paSuffixes = s_aModRm;
552	break;
553	case UD_T_MODRM_IMM8:
554	cSuffixes = RT_ELEMENTS(s_aModRmImm8);
555	paSuffixes = s_aModRmImm8;
556	cImmEntries = 256;
557	break;
558	default:
559	Bs3TestPrintf("#%u: enmType=%d\n", paTests[iTest].enmType);
560	continue;
561	}
562
563	for (iPrefix = 0; iPrefix < RT_ELEMENTS(s_aPrefixes); iPrefix++)
564	if (!(s_aPrefixes[iPrefix].fIncompatible & paTests[iTest].fFlags))
565	{
566	unsigned iSubTab;
567	unsigned cbOpcodesLead;
568	uint8_t abOpcodes[32];
569
570	Bs3MemCpy(&abOpcodes[0], &s_aPrefixes[iPrefix].ab[0], s_aPrefixes[iPrefix].cb);
571	cbOpcodesLead = s_aPrefixes[iPrefix].cb;
572	Bs3MemCpy(&abOpcodes[cbOpcodesLead], &paTests[iTest].abOpcodes[0], paTests[iTest].cbOpcodes);
573	cbOpcodesLead += paTests[iTest].cbOpcodes;
574
575	for (iSubTab = 0; iSubTab < cSubTabEntries; iSubTab++)
576	{
577	unsigned iSuffix;
578
579	if (cSubTabEntries > 1)
580	abOpcodes[cbOpcodesLead - 1] = iSubTab;
581
582	for (iSuffix = 0; iSuffix < cSuffixes; iSuffix++)
583	if (!(paSuffixes[iSuffix].fIncompatible & paTests[iTest].fFlags))
584	{
585	unsigned const cbOpcodes = cbOpcodesLead + paSuffixes[iSuffix].cb;
586	unsigned cbOpcodesMin = 1;
587	unsigned iImm;
588	Bs3MemCpy(&abOpcodes[cbOpcodesLead], paSuffixes[iSuffix].ab, paSuffixes[iSuffix].cb);
589
590	for (iImm = 0; iImm < cImmEntries; iImm++)
591	{
592	unsigned cb;
593
594	if (cImmEntries > 1)
595	abOpcodes[cbOpcodes - 1] = iImm;
596
597	/*
598	* Do the edge thing.
599	*/
600	cb = cbOpcodes;
601	while (cb >= cbOpcodesMin)
602	{
603	uint8_t BS3_FAR *pbRip = &pbPages[X86_PAGE_SIZE - cb];
604	uint8_t bXcptExpected;
605
606	Bs3RegCtxSetRipCsFromFlat(&Ctx, (uintptr_t)pbRip);
607	ExpectCtx.rip = Ctx.rip;
608	ExpectCtx.cs = Ctx.cs;
609	if (cb >= cbOpcodes)
610	{
611	ExpectCtx.cr2 = Ctx.cr2;
612	bXcptExpected = X86_XCPT_UD;
613	}
614	else
615	{
616	ExpectCtx.cr2.u = (uintptr_t)&pbPages[X86_PAGE_SIZE];
617	bXcptExpected = X86_XCPT_PF;
618	}
619
620	Bs3MemCpy(pbRip, &abOpcodes[0], cb);
621	Bs3TrapSetJmpAndRestore(&Ctx, &TrapFrame);
622	#if 0
623	Bs3TestPrintf("iTest=%d iPrefix=%d (%d/%#x) iSubTab=%d iSuffix=%d (%d/%#x) iImm=%d cb=%d cbOp=%d: %.*Rhxs\n",
624	iTest, iPrefix, s_aPrefixes[iPrefix].cb, s_aPrefixes[iPrefix].fIncompatible,
625	iSubTab, iSuffix, paSuffixes[iSuffix].cb, paSuffixes[iSuffix].fIncompatible, iImm,
626	cb, cbOpcodes,
627	cbOpcodes, abOpcodes);
628	#endif
629
630	if ( !Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &ExpectCtx, 0 /cbPcAdjust/,
631	0 /cbSpAdjust/, 0 /fExtraEfl/, "mode", 0)
632	\|\| TrapFrame.bXcpt != bXcptExpected)
633	{
634	Bs3TestFailedF("iTest=%d iPrefix=%d (%d/%#x) iSubTab=%u iSuffix=%d (%d/%#x) cb=%d cbOp=%d: %.*Rhxs\n",
635	iTest, iPrefix, s_aPrefixes[iPrefix].cb, s_aPrefixes[iPrefix].fIncompatible,
636	iSubTab, iSuffix, paSuffixes[iSuffix].cb, paSuffixes[iSuffix].fIncompatible,
637	cb, cbOpcodes,
638	cbOpcodes, abOpcodes);
639	if (TrapFrame.bXcpt != bXcptExpected)
640	Bs3TestFailedF("Expected bXcpt=%#x got %#x\n", bXcptExpected, TrapFrame.bXcpt);
641	Bs3TrapPrintFrame(&TrapFrame);
642	Bs3Shutdown();
643	}
644
645	/* next */
646	g_usBs3TestStep++;
647	iStep++;
648	cb--;
649	}
650
651	/* For iImm > 0 only test cb == cbOpcode since the byte isn't included when cb < cbOpcode. */
652	cbOpcodesMin = cbOpcodes;
653	}
654	}
655	}
656	}
657	}
658	Bs3TestPrintf("%RI32 (%#RX32) test steps\n", iStep, iStep);
659
660	Bs3MemGuardedTestPageFree(pbPages);
661	}
662	else
663	Bs3TestFailed("Failed to allocate two pages!\n");
664	}
665
666
667
668
669	BS3_DECL(void) Main_pp32()
670	{
671	Bs3TestInit("bs3-cpu-decoding-1");
672	Bs3TestPrintf("g_uBs3CpuDetected=%#x\n", g_uBs3CpuDetected);
673
674	//DecodeEdgeTest();
675	Bs3TestSub("undefined opcodes");
676	DecodeUdEdgeTest(g_aUdTest, RT_ELEMENTS(g_aUdTest));
677
678	Bs3TestTerm();
679
680	//for (;;) ASMHalt();
681	}
682

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