bs3-cpu-basic-2-template.c@ 60311

Last change on this file since 60311 was 60311, checked in by vboxsync, 9 years ago
bs3kit: Use \#define with BS3_DATA_NM to map data symbols to names accessible in all context. (Underscores in 16-bit and 32-bit, no underscores in 64-bit.) Detect PSE.
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1	/* $Id: bs3-cpu-basic-2-template.c 60311 2016-04-04 17:01:14Z vboxsync $ */
2	/** @file
3	* BS3Kit - bs3-cpu-basic-2, C code template.
4	*/
5
6	/*
7	* Copyright (C) 2007-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.215389.xyz. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27
28	#ifdef BS3_INSTANTIATING_MODE
29
30	/*********************************************************************************************************************************
31	* Header Files *
32	*********************************************************************************************************************************/
33	#include <iprt/asm.h>
34	#include <iprt/asm-amd64-x86.h>
35
36
37	/*********************************************************************************************************************************
38	* Defined Constants And Macros *
39	*********************************************************************************************************************************/
40	# undef MyBs3Idt
41	# undef MY_SYS_SEL_R0_CS
42	# undef MY_SYS_SEL_R0_CS_CNF
43	# undef MY_SYS_SEL_R0_DS
44	# undef MY_SYS_SEL_R0_SS
45	# if BS3_MODE_IS_16BIT_SYS(TMPL_MODE)
46	# define MyBs3Idt Bs3Idt16
47	# define MY_SYS_SEL_R0_CS BS3_SEL_R0_CS16
48	# define MY_SYS_SEL_R0_CS_CNF BS3_SEL_R0_CS16_CNF
49	# define MY_SYS_SEL_R0_DS BS3_SEL_R0_DS16
50	# define MY_SYS_SEL_R0_SS BS3_SEL_R0_SS16
51	# elif BS3_MODE_IS_32BIT_SYS(TMPL_MODE)
52	# define MyBs3Idt Bs3Idt32
53	# define MY_SYS_SEL_R0_CS BS3_SEL_R0_CS32
54	# define MY_SYS_SEL_R0_CS_CNF BS3_SEL_R0_CS32_CNF
55	# define MY_SYS_SEL_R0_DS BS3_SEL_R0_DS32
56	# define MY_SYS_SEL_R0_SS BS3_SEL_R0_SS32
57	# elif BS3_MODE_IS_64BIT_SYS(TMPL_MODE)
58	# define MyBs3Idt Bs3Idt64
59	# define MY_SYS_SEL_R0_CS BS3_SEL_R0_CS64
60	# define MY_SYS_SEL_R0_CS_CNF BS3_SEL_R0_CS64_CNF
61	# define MY_SYS_SEL_R0_DS BS3_SEL_R0_DS64
62	# define MY_SYS_SEL_R0_SS BS3_SEL_R0_DS64
63	# else
64	# error "TMPL_MODE"
65	# endif
66	#undef CHECK_MEMBER
67	#define CHECK_MEMBER(a_szName, a_szFmt, a_Actual, a_Expected) \
68	do \
69	{ \
70	if ((a_Actual) == (a_Expected)) { /* likely */ } \
71	else bs3CpuBasic2_FailedF(a_szName "=" a_szFmt " expected " a_szFmt, (a_Actual), (a_Expected)); \
72	} while (0)
73
74
75	/*********************************************************************************************************************************
76	* Structures and Typedefs *
77	*********************************************************************************************************************************/
78	#ifndef DONE_MODE_TYPES
79	#define DONE_MODE_TYPES
80	typedef struct BS3CB2INVLDESCTYPE
81	{
82	uint8_t u4Type;
83	uint8_t u1DescType;
84	} BS3CB2INVLDESCTYPE;
85	#endif
86
87
88	/*********************************************************************************************************************************
89	* External Symbols *
90	*********************************************************************************************************************************/
91	extern BS3_DECL(void) TMPL_NM(bs3CpuBasic2_Int80)(void);
92	extern BS3_DECL(void) TMPL_NM(bs3CpuBasic2_Int81)(void);
93	extern BS3_DECL(void) TMPL_NM(bs3CpuBasic2_Int82)(void);
94	extern BS3_DECL(void) TMPL_NM(bs3CpuBasic2_Int83)(void);
95	extern BS3_DECL(void) TMPL_NM(bs3CpuBasic2_ud2)(void);
96	#ifndef DOXYGEN_RUNNING
97	# define g_bs3CpuBasic2_ud2_FlatAddr BS3_DATA_NM(g_bs3CpuBasic2_ud2_FlatAddr)
98	#endif
99	extern uint32_t g_bs3CpuBasic2_ud2_FlatAddr;
100
101
102	/*********************************************************************************************************************************
103	* Global Variables *
104	*********************************************************************************************************************************/
105	#if TMPL_MODE == BS3_MODE_RM \|\| TMPL_MODE == BS3_MODE_PE16_32 \|\| TMPL_MODE == BS3_MODE_LM64
106	#define g_pszTestMode BS3_CMN_NM(g_pszTestMode)
107	static const char BS3_FAR g_pszTestMode = (const char )1;
108	#define g_bTestMode BS3_CMN_NM(g_bTestMode)
109	static uint8_t g_bTestMode = 1;
110	#define g_f16BitSys BS3_CMN_NM(g_f16BitSys)
111	static bool g_f16BitSys = 1;
112
113	/** Table containing invalid CS selector types. */
114	static const BS3CB2INVLDESCTYPE g_aInvalidCsTypes[] =
115	{
116	{ X86_SEL_TYPE_RO, 1 },
117	{ X86_SEL_TYPE_RO_ACC, 1 },
118	{ X86_SEL_TYPE_RW, 1 },
119	{ X86_SEL_TYPE_RW_ACC, 1 },
120	{ X86_SEL_TYPE_RO_DOWN, 1 },
121	{ X86_SEL_TYPE_RO_DOWN_ACC, 1 },
122	{ X86_SEL_TYPE_RW_DOWN, 1 },
123	{ X86_SEL_TYPE_RW_DOWN_ACC, 1 },
124	{ 0, 0 },
125	{ 1, 0 },
126	{ 2, 0 },
127	{ 3, 0 },
128	{ 4, 0 },
129	{ 5, 0 },
130	{ 6, 0 },
131	{ 7, 0 },
132	{ 8, 0 },
133	{ 9, 0 },
134	{ 10, 0 },
135	{ 11, 0 },
136	{ 12, 0 },
137	{ 13, 0 },
138	{ 14, 0 },
139	{ 15, 0 },
140	};
141
142	/** Table containing invalid SS selector types. */
143	static const BS3CB2INVLDESCTYPE g_aInvalidSsTypes[] =
144	{
145	{ X86_SEL_TYPE_EO, 1 },
146	{ X86_SEL_TYPE_EO_ACC, 1 },
147	{ X86_SEL_TYPE_ER, 1 },
148	{ X86_SEL_TYPE_ER_ACC, 1 },
149	{ X86_SEL_TYPE_EO_CONF, 1 },
150	{ X86_SEL_TYPE_EO_CONF_ACC, 1 },
151	{ X86_SEL_TYPE_ER_CONF, 1 },
152	{ X86_SEL_TYPE_ER_CONF_ACC, 1 },
153	{ 0, 0 },
154	{ 1, 0 },
155	{ 2, 0 },
156	{ 3, 0 },
157	{ 4, 0 },
158	{ 5, 0 },
159	{ 6, 0 },
160	{ 7, 0 },
161	{ 8, 0 },
162	{ 9, 0 },
163	{ 10, 0 },
164	{ 11, 0 },
165	{ 12, 0 },
166	{ 13, 0 },
167	{ 14, 0 },
168	{ 15, 0 },
169	};
170
171	#endif
172
173	#if TMPL_MODE == BS3_MODE_RM \|\| TMPL_MODE == BS3_MODE_PE16_32 \|\| TMPL_MODE == BS3_MODE_LM64
174
175	/**
176	* Wrapper around Bs3TestFailedF that prefixes the error with g_usBs3TestStep
177	* and g_pszTestMode.
178	*/
179	#define bs3CpuBasic2_FailedF BS3_CMN_NM(bs3CpuBasic2_FailedF)
180	void bs3CpuBasic2_FailedF(const char *pszFormat, ...)
181	{
182	va_list va;
183
184	char szTmp[168];
185	va_start(va, pszFormat);
186	Bs3StrPrintfV(szTmp, sizeof(szTmp), pszFormat, va);
187	va_end(va);
188
189	Bs3TestFailedF("%u - %s: %s", g_usBs3TestStep, g_pszTestMode, szTmp);
190	}
191
192
193	/**
194	* Compares trap stuff.
195	*/
196	#define bs3CpuBasic2_CompareIntCtx1 BS3_CMN_NM(bs3CpuBasic2_CompareIntCtx1)
197	void bs3CpuBasic2_CompareIntCtx1(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint8_t bXcpt)
198	{
199	uint16_t const cErrorsBefore = Bs3TestSubErrorCount();
200	CHECK_MEMBER("bXcpt", "%#04x", pTrapCtx->bXcpt, bXcpt);
201	CHECK_MEMBER("bErrCd", "%#06RX64", pTrapCtx->uErrCd, 0);
202	Bs3TestCheckRegCtxEx(&pTrapCtx->Ctx, pStartCtx, 2 /int xx/, 0 /cbSpAdjust/, 0 /fExtraEfl/, g_pszTestMode, g_usBs3TestStep);
203	if (Bs3TestSubErrorCount() != cErrorsBefore)
204	{
205	Bs3TrapPrintFrame(pTrapCtx);
206	#if 1
207	Bs3TestPrintf("Halting: g_uBs3CpuDetected=%#x\n", g_uBs3CpuDetected);
208	Bs3TestPrintf("Halting in CompareTrapCtx1: bXcpt=%#x\n", bXcpt);
209	ASMHalt();
210	#endif
211	}
212	}
213
214
215	/**
216	* Compares trap stuff.
217	*/
218	#define bs3CpuBasic2_CompareTrapCtx2 BS3_CMN_NM(bs3CpuBasic2_CompareTrapCtx2)
219	void bs3CpuBasic2_CompareTrapCtx2(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint16_t cbIpAdjust, uint8_t bXcpt,
220	uint16_t uHandlerCs)
221	{
222	uint16_t const cErrorsBefore = Bs3TestSubErrorCount();
223	CHECK_MEMBER("bXcpt", "%#04x", pTrapCtx->bXcpt, bXcpt);
224	CHECK_MEMBER("bErrCd", "%#06RX64", pTrapCtx->uErrCd, 0);
225	CHECK_MEMBER("uHandlerCs", "%#06x", pTrapCtx->uHandlerCs, uHandlerCs);
226	Bs3TestCheckRegCtxEx(&pTrapCtx->Ctx, pStartCtx, cbIpAdjust, 0 /cbSpAdjust/, 0 /fExtraEfl/, g_pszTestMode, g_usBs3TestStep);
227	if (Bs3TestSubErrorCount() != cErrorsBefore)
228	{
229	Bs3TrapPrintFrame(pTrapCtx);
230	#if 1
231	Bs3TestPrintf("Halting: g_uBs3CpuDetected=%#x\n", g_uBs3CpuDetected);
232	Bs3TestPrintf("Halting in CompareTrapCtx2: bXcpt=%#x\n", bXcpt);
233	ASMHalt();
234	#endif
235	}
236	}
237
238	/**
239	* Compares a CPU trap.
240	*/
241	#define bs3CpuBasic2_CompareCpuTrapCtx BS3_CMN_NM(bs3CpuBasic2_CompareCpuTrapCtx)
242	BS3_DECL(void) bs3CpuBasic2_CompareCpuTrapCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint16_t uErrCd, uint8_t bXcpt,
243	bool f486ResumeFlagHint)
244	{
245	uint16_t const cErrorsBefore = Bs3TestSubErrorCount();
246	uint32_t fExtraEfl;
247
248	CHECK_MEMBER("bXcpt", "%#04x", pTrapCtx->bXcpt, bXcpt);
249	CHECK_MEMBER("bErrCd", "%#06RX16", (uint16_t)pTrapCtx->uErrCd, (uint16_t)uErrCd); /* 486 only writes a word */
250
251	fExtraEfl = X86_EFL_RF;
252	if ( g_f16BitSys
253	\|\| ( !f486ResumeFlagHint
254	&& (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) <= BS3CPU_80486 ) )
255	fExtraEfl = 0;
256	else
257	fExtraEfl = X86_EFL_RF;
258	Bs3TestCheckRegCtxEx(&pTrapCtx->Ctx, pStartCtx, 0 /cbIpAdjust/, 0 /cbSpAdjust/, fExtraEfl, g_pszTestMode, g_usBs3TestStep);
259	if (Bs3TestSubErrorCount() != cErrorsBefore)
260	{
261	Bs3TrapPrintFrame(pTrapCtx);
262	#if 1
263	Bs3TestPrintf("Halting: g_uBs3CpuDetected=%#x\n", g_uBs3CpuDetected);
264	Bs3TestPrintf("Halting: bXcpt=%#x uErrCd=%#x\n", bXcpt, uErrCd);
265	ASMHalt();
266	#endif
267	}
268	}
269
270
271	/**
272	* Compares \#GP trap.
273	*/
274	#define bs3CpuBasic2_CompareGpCtx BS3_CMN_NM(bs3CpuBasic2_CompareGpCtx)
275	void bs3CpuBasic2_CompareGpCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint16_t uErrCd)
276	{
277	bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, uErrCd, X86_XCPT_GP, true /f486ResumeFlagHint/);
278	}
279
280	/**
281	* Compares \#NP trap.
282	*/
283	#define bs3CpuBasic2_CompareNpCtx BS3_CMN_NM(bs3CpuBasic2_CompareNpCtx)
284	void bs3CpuBasic2_CompareNpCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint16_t uErrCd)
285	{
286	bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, uErrCd, X86_XCPT_NP, true /f486ResumeFlagHint/);
287	}
288
289	/**
290	* Compares \#SS trap.
291	*/
292	#define bs3CpuBasic2_CompareSsCtx BS3_CMN_NM(bs3CpuBasic2_CompareSsCtx)
293	void bs3CpuBasic2_CompareSsCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint16_t uErrCd, bool f486ResumeFlagHint)
294	{
295	bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, uErrCd, X86_XCPT_SS, f486ResumeFlagHint);
296	}
297
298	/**
299	* Compares \#TS trap.
300	*/
301	#define bs3CpuBasic2_CompareTsCtx BS3_CMN_NM(bs3CpuBasic2_CompareTsCtx)
302	void bs3CpuBasic2_CompareTsCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx, uint16_t uErrCd)
303	{
304	bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, uErrCd, X86_XCPT_TS, false /f486ResumeFlagHint/);
305	}
306
307	/**
308	* Compares \#PF trap.
309	*/
310	#define bs3CpuBasic2_ComparePfCtx BS3_CMN_NM(bs3CpuBasic2_ComparePfCtx)
311	void bs3CpuBasic2_ComparePfCtx(PCBS3TRAPFRAME pTrapCtx, PBS3REGCTX pStartCtx, uint16_t uErrCd, uint64_t uCr2Expected)
312	{
313	uint64_t const uCr2Saved = pStartCtx->cr2.u;
314	pStartCtx->cr2.u = uCr2Expected;
315	bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, uErrCd, X86_XCPT_PF, true /f486ResumeFlagHint/);
316	pStartCtx->cr2.u = uCr2Saved;
317	}
318
319	/**
320	* Compares \#UD trap.
321	*/
322	#define bs3CpuBasic2_CompareUdCtx BS3_CMN_NM(bs3CpuBasic2_CompareUdCtx)
323	void bs3CpuBasic2_CompareUdCtx(PCBS3TRAPFRAME pTrapCtx, PCBS3REGCTX pStartCtx)
324	{
325	bs3CpuBasic2_CompareCpuTrapCtx(pTrapCtx, pStartCtx, 0 /no error code/, X86_XCPT_UD, true /f486ResumeFlagHint/);
326	}
327
328
329	#define bs3CpuBasic2_RaiseXcpt1Common BS3_CMN_NM(bs3CpuBasic2_RaiseXcpt1Common)
330	static void bs3CpuBasic2_RaiseXcpt1Common(bool const g_f16BitSys,
331	uint16_t const uSysR0Cs, uint16_t const uSysR0CsConf, uint16_t const uSysR0Ss,
332	PX86DESC const paIdt, unsigned const cIdteShift)
333	{
334	BS3TRAPFRAME TrapCtx;
335	BS3REGCTX Ctx80;
336	BS3REGCTX Ctx81;
337	BS3REGCTX Ctx82;
338	BS3REGCTX Ctx83;
339	BS3REGCTX CtxTmp;
340	BS3REGCTX CtxTmp2;
341	PBS3REGCTX apCtx8x[4];
342	unsigned iCtx;
343	unsigned iRing;
344	unsigned iDpl;
345	unsigned iRpl;
346	unsigned i, j, k;
347	uint32_t uExpected;
348	# if TMPL_BITS == 16
349	bool const f386Plus = (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386;
350	# else
351	bool const f386Plus = true;
352	int rc;
353	uint8_t *pbIdtCopyAlloc;
354	PX86DESC pIdtCopy;
355	const unsigned cbIdte = 1 << (3 + cIdteShift);
356	RTCCUINTXREG uCr0Saved = ASMGetCR0();
357	RTGDTR GdtrSaved;
358	# endif
359	RTIDTR IdtrSaved;
360	RTIDTR Idtr;
361
362	ASMGetIDTR(&IdtrSaved);
363	# if TMPL_BITS != 16
364	ASMGetGDTR(&GdtrSaved);
365	# endif
366
367	/* make sure they're allocated */
368	Bs3MemZero(&TrapCtx, sizeof(TrapCtx));
369	Bs3MemZero(&Ctx80, sizeof(Ctx80));
370	Bs3MemZero(&Ctx81, sizeof(Ctx81));
371	Bs3MemZero(&Ctx82, sizeof(Ctx82));
372	Bs3MemZero(&Ctx83, sizeof(Ctx83));
373	Bs3MemZero(&CtxTmp, sizeof(CtxTmp));
374	Bs3MemZero(&CtxTmp2, sizeof(CtxTmp2));
375
376	/* Context array. */
377	apCtx8x[0] = &Ctx80;
378	apCtx8x[1] = &Ctx81;
379	apCtx8x[2] = &Ctx82;
380	apCtx8x[3] = &Ctx83;
381
382	# if TMPL_BITS != 16
383	/* Allocate memory for playing around with the IDT. */
384	pbIdtCopyAlloc = NULL;
385	if (BS3_MODE_IS_PAGED(g_bTestMode))
386	pbIdtCopyAlloc = Bs3MemAlloc(BS3MEMKIND_FLAT32, 12*_1K);
387	# endif
388
389	/*
390	* IDT entry 80 thru 83 are assigned DPLs according to the number.
391	* (We'll be useing more, but this'll do for now.)
392	*/
393	paIdt[0x80 << cIdteShift].Gate.u2Dpl = 0;
394	paIdt[0x81 << cIdteShift].Gate.u2Dpl = 1;
395	paIdt[0x82 << cIdteShift].Gate.u2Dpl = 2;
396	paIdt[0x83 << cIdteShift].Gate.u2Dpl = 3;
397
398	Bs3RegCtxSave(&Ctx80);
399	Ctx80.rsp.u -= 0x300;
400	Ctx80.rip.u = (uintptr_t)BS3_FP_OFF(&TMPL_NM(bs3CpuBasic2_Int80));
401	# if TMPL_BITS == 32
402	g_uBs3TrapEipHint = Ctx80.rip.u32;
403	# endif
404	Bs3MemCpy(&Ctx81, &Ctx80, sizeof(Ctx80));
405	Ctx81.rip.u = (uintptr_t)BS3_FP_OFF(&TMPL_NM(bs3CpuBasic2_Int81));
406	Bs3MemCpy(&Ctx82, &Ctx80, sizeof(Ctx80));
407	Ctx82.rip.u = (uintptr_t)BS3_FP_OFF(&TMPL_NM(bs3CpuBasic2_Int82));
408	Bs3MemCpy(&Ctx83, &Ctx80, sizeof(Ctx80));
409	Ctx83.rip.u = (uintptr_t)BS3_FP_OFF(&TMPL_NM(bs3CpuBasic2_Int83));
410
411	/*
412	* Check that all the above gates work from ring-0.
413	*/
414	for (iCtx = 0; iCtx < RT_ELEMENTS(apCtx8x); iCtx++)
415	{
416	g_usBs3TestStep = iCtx;
417	# if TMPL_BITS == 32
418	g_uBs3TrapEipHint = apCtx8x[iCtx]->rip.u32;
419	# endif
420	Bs3TrapSetJmpAndRestore(apCtx8x[iCtx], &TrapCtx);
421	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, apCtx8x[iCtx], 0x80+iCtx /bXcpt/);
422	}
423
424	/*
425	* Check that the gate DPL checks works.
426	*/
427	g_usBs3TestStep = 100;
428	for (iRing = 0; iRing <= 3; iRing++)
429	{
430	for (iCtx = 0; iCtx < RT_ELEMENTS(apCtx8x); iCtx++)
431	{
432	Bs3MemCpy(&CtxTmp, apCtx8x[iCtx], sizeof(CtxTmp));
433	Bs3RegCtxConvertToRingX(&CtxTmp, iRing);
434	# if TMPL_BITS == 32
435	g_uBs3TrapEipHint = CtxTmp.rip.u32;
436	# endif
437	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
438	if (iCtx < iRing)
439	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
440	else
441	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x80 + iCtx /bXcpt/);
442	g_usBs3TestStep++;
443	}
444	}
445
446	/*
447	* Modify the gate CS value and run the handler at a different CPL.
448	* Throw RPL variations into the mix (completely ignored) together
449	* with gate presence.
450	* 1. CPL <= GATE.DPL
451	* 2. GATE.P
452	* 3. GATE.CS.DPL <= CPL (non-conforming segments)
453	*/
454	g_usBs3TestStep = 1000;
455	for (i = 0; i <= 3; i++)
456	{
457	for (iRing = 0; iRing <= 3; iRing++)
458	{
459	for (iCtx = 0; iCtx < RT_ELEMENTS(apCtx8x); iCtx++)
460	{
461	# if TMPL_BITS == 32
462	g_uBs3TrapEipHint = apCtx8x[iCtx]->rip.u32;
463	# endif
464	Bs3MemCpy(&CtxTmp, apCtx8x[iCtx], sizeof(CtxTmp));
465	Bs3RegCtxConvertToRingX(&CtxTmp, iRing);
466
467	for (j = 0; j <= 3; j++)
468	{
469	uint16_t const uCs = (uSysR0Cs \| j) + (i << BS3_SEL_RING_SHIFT);
470	for (k = 0; k < 2; k++)
471	{
472	g_usBs3TestStep++;
473	/Bs3TestPrintf("g_usBs3TestStep=%u iCtx=%u iRing=%u i=%u uCs=%04x\n", g_usBs3TestStep, iCtx, iRing, i, uCs);/
474	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u16Sel = uCs;
475	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u1Present = k;
476	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
477	/Bs3TrapPrintFrame(&TrapCtx);/
478	if (iCtx < iRing)
479	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
480	else if (k == 0)
481	bs3CpuBasic2_CompareNpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
482	else if (i > iRing)
483	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, uCs & X86_SEL_MASK_OFF_RPL);
484	else
485	{
486	uint16_t uExpectedCs = uCs & X86_SEL_MASK_OFF_RPL;
487	if (i <= iCtx && i <= iRing)
488	uExpectedCs \|= i;
489	bs3CpuBasic2_CompareTrapCtx2(&TrapCtx, &CtxTmp, 2 /int 8xh/, 0x80 + iCtx /bXcpt/, uExpectedCs);
490	}
491	}
492	}
493
494	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u16Sel = uSysR0Cs;
495	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u1Present = 1;
496	}
497	}
498	}
499	BS3_ASSERT(g_usBs3TestStep < 1600);
500
501	/*
502	* Various CS and SS related faults
503	*
504	* We temporarily reconfigure gate 80 and 83 with new CS selectors, the
505	* latter have a CS.DPL of 2 for testing ring transisions and SS loading
506	* without making it impossible to handle faults.
507	*/
508	g_usBs3TestStep = 1600;
509	Bs3GdteTestPage00 = Bs3Gdt[uSysR0Cs >> X86_SEL_SHIFT];
510	Bs3GdteTestPage00.Gen.u1Present = 0;
511	Bs3GdteTestPage00.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
512	paIdt[0x80 << cIdteShift].Gate.u16Sel = BS3_SEL_TEST_PAGE_00;
513
514	/* CS.PRESENT = 0 */
515	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
516	bs3CpuBasic2_CompareNpCtx(&TrapCtx, &Ctx80, BS3_SEL_TEST_PAGE_00);
517	if (Bs3GdteTestPage00.Gen.u4Type & X86_SEL_TYPE_ACCESSED)
518	bs3CpuBasic2_FailedF("selector was accessed");
519	g_usBs3TestStep++;
520
521	/* Check that GATE.DPL is checked before CS.PRESENT. */
522	for (iRing = 1; iRing < 4; iRing++)
523	{
524	Bs3MemCpy(&CtxTmp, &Ctx80, sizeof(CtxTmp));
525	Bs3RegCtxConvertToRingX(&CtxTmp, iRing);
526	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
527	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, (0x80 << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
528	if (Bs3GdteTestPage00.Gen.u4Type & X86_SEL_TYPE_ACCESSED)
529	bs3CpuBasic2_FailedF("selector was accessed");
530	g_usBs3TestStep++;
531	}
532
533	/* CS.DPL mismatch takes precedence over CS.PRESENT = 0. */
534	Bs3GdteTestPage00.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
535	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
536	bs3CpuBasic2_CompareNpCtx(&TrapCtx, &Ctx80, BS3_SEL_TEST_PAGE_00);
537	if (Bs3GdteTestPage00.Gen.u4Type & X86_SEL_TYPE_ACCESSED)
538	bs3CpuBasic2_FailedF("CS selector was accessed");
539	g_usBs3TestStep++;
540	for (iDpl = 1; iDpl < 4; iDpl++)
541	{
542	Bs3GdteTestPage00.Gen.u2Dpl = iDpl;
543	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
544	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx80, BS3_SEL_TEST_PAGE_00);
545	if (Bs3GdteTestPage00.Gen.u4Type & X86_SEL_TYPE_ACCESSED)
546	bs3CpuBasic2_FailedF("CS selector was accessed");
547	g_usBs3TestStep++;
548	}
549
550	/* 1608: Check all the invalid CS selector types alone. */
551	Bs3GdteTestPage00 = Bs3Gdt[uSysR0Cs >> X86_SEL_SHIFT];
552	for (i = 0; i < RT_ELEMENTS(g_aInvalidCsTypes); i++)
553	{
554	Bs3GdteTestPage00.Gen.u4Type = g_aInvalidCsTypes[i].u4Type;
555	Bs3GdteTestPage00.Gen.u1DescType = g_aInvalidCsTypes[i].u1DescType;
556	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
557	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx80, BS3_SEL_TEST_PAGE_00);
558	if (Bs3GdteTestPage00.Gen.u4Type != g_aInvalidCsTypes[i].u4Type)
559	bs3CpuBasic2_FailedF("Invalid CS type %#x/%u -> %#x/%u\n",
560	g_aInvalidCsTypes[i].u4Type, g_aInvalidCsTypes[i].u1DescType,
561	Bs3GdteTestPage00.Gen.u4Type, Bs3GdteTestPage00.Gen.u1DescType);
562	g_usBs3TestStep++;
563
564	/* Incorrect CS.TYPE takes precedence over CS.PRESENT = 0. */
565	Bs3GdteTestPage00.Gen.u1Present = 0;
566	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
567	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx80, BS3_SEL_TEST_PAGE_00);
568	Bs3GdteTestPage00.Gen.u1Present = 1;
569	g_usBs3TestStep++;
570	}
571
572	/* Fix CS again. */
573	Bs3GdteTestPage00 = Bs3Gdt[uSysR0Cs >> X86_SEL_SHIFT];
574
575	/* 1632: Test SS. */
576	if (!BS3_MODE_IS_64BIT_SYS(g_bTestMode))
577	{
578	uint16_t BS3_FAR *puTssSs2 = BS3_MODE_IS_16BIT_SYS(g_bTestMode) ? &Bs3Tss16.ss2 : &Bs3Tss32.ss2;
579	uint16_t const uSavedSs2 = *puTssSs2;
580	X86DESC const SavedGate83 = paIdt[0x83 << cIdteShift];
581
582	/* Make the handler execute in ring-2. */
583	Bs3GdteTestPage02 = Bs3Gdt[(uSysR0Cs + (2 << BS3_SEL_RING_SHIFT)) >> X86_SEL_SHIFT];
584	Bs3GdteTestPage02.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
585	paIdt[0x83 << cIdteShift].Gate.u16Sel = BS3_SEL_TEST_PAGE_02 \| 2;
586
587	Bs3MemCpy(&CtxTmp, &Ctx83, sizeof(CtxTmp));
588	Bs3RegCtxConvertToRingX(&CtxTmp, 3); /* yeah, from 3 so SS:xSP is reloaded. */
589	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
590	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x83);
591	if (!(Bs3GdteTestPage02.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
592	bs3CpuBasic2_FailedF("CS selector was not access");
593	g_usBs3TestStep++;
594
595	/* Create a SS.DPL=2 stack segment and check that SS2.RPL matters and
596	that we get #SS if the selector isn't present. */
597	i = 0; /* used for cycling thru invalid CS types */
598	for (k = 0; k < 10; k++)
599	{
600	/* k=0: present,
601	k=1: not-present,
602	k=2: present but very low limit,
603	k=3: not-present, low limit.
604	k=4: present, read-only.
605	k=5: not-present, read-only.
606	k=6: present, code-selector.
607	k=7: not-present, code-selector.
608	k=8: present, read-write / no access + system (=LDT).
609	k=9: not-present, read-write / no access + system (=LDT).
610	*/
611	Bs3GdteTestPage03 = Bs3Gdt[(uSysR0Ss + (2 << BS3_SEL_RING_SHIFT)) >> X86_SEL_SHIFT];
612	Bs3GdteTestPage03.Gen.u1Present = !(k & 1);
613	if (k >= 8)
614	{
615	Bs3GdteTestPage03.Gen.u1DescType = 0; /* system */
616	Bs3GdteTestPage03.Gen.u4Type = X86_SEL_TYPE_RW; /* = LDT */
617	}
618	else if (k >= 6)
619	Bs3GdteTestPage03.Gen.u4Type = X86_SEL_TYPE_ER;
620	else if (k >= 4)
621	Bs3GdteTestPage03.Gen.u4Type = X86_SEL_TYPE_RO;
622	else if (k >= 2)
623	{
624	Bs3GdteTestPage03.Gen.u16LimitLow = 0x400;
625	Bs3GdteTestPage03.Gen.u4LimitHigh = 0;
626	Bs3GdteTestPage03.Gen.u1Granularity = 0;
627	}
628
629	for (iDpl = 0; iDpl < 4; iDpl++)
630	{
631	Bs3GdteTestPage03.Gen.u2Dpl = iDpl;
632
633	for (iRpl = 0; iRpl < 4; iRpl++)
634	{
635	*puTssSs2 = BS3_SEL_TEST_PAGE_03 \| iRpl;
636	//Bs3TestPrintf("k=%u iDpl=%u iRpl=%u step=%u\n", k, iDpl, iRpl, g_usBs3TestStep);
637	Bs3GdteTestPage02.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
638	Bs3GdteTestPage03.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
639	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
640	if (iRpl != 2 \|\| iRpl != iDpl \|\| k >= 4)
641	bs3CpuBasic2_CompareTsCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_03);
642	else if (k != 0)
643	bs3CpuBasic2_CompareSsCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_03,
644	k == 2 /f486ResumeFlagHint/);
645	else
646	{
647	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x83);
648	if (TrapCtx.uHandlerSs != (BS3_SEL_TEST_PAGE_03 \| 2))
649	bs3CpuBasic2_FailedF("uHandlerSs=%#x expected %#x\n", TrapCtx.uHandlerSs, BS3_SEL_TEST_PAGE_03 \| 2);
650	}
651	if (!(Bs3GdteTestPage02.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
652	bs3CpuBasic2_FailedF("CS selector was not access");
653	if ( TrapCtx.bXcpt == 0x83
654	\|\| (TrapCtx.bXcpt == X86_XCPT_SS && k == 2) )
655	{
656	if (!(Bs3GdteTestPage03.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
657	bs3CpuBasic2_FailedF("SS selector was not accessed");
658	}
659	else if (Bs3GdteTestPage03.Gen.u4Type & X86_SEL_TYPE_ACCESSED)
660	bs3CpuBasic2_FailedF("SS selector was accessed");
661	g_usBs3TestStep++;
662
663	/* Modify the gate DPL to check that this is checked before SS.DPL and SS.PRESENT. */
664	paIdt[0x83 << cIdteShift].Gate.u2Dpl = 2;
665	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
666	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, (0x83 << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
667	paIdt[0x83 << cIdteShift].Gate.u2Dpl = 3;
668	g_usBs3TestStep++;
669
670	/* Check the the CS.DPL check is done before the SS ones. Restoring the ring-0 INT 83
671	context triggers the CS.DPL < CPL check. */
672	Bs3TrapSetJmpAndRestore(&Ctx83, &TrapCtx);
673	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx83, BS3_SEL_TEST_PAGE_02);
674	g_usBs3TestStep++;
675
676	/* Now mark the CS selector not present and check that that also triggers before SS stuff. */
677	Bs3GdteTestPage02.Gen.u1Present = 0;
678	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
679	bs3CpuBasic2_CompareNpCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_02);
680	Bs3GdteTestPage02.Gen.u1Present = 1;
681	g_usBs3TestStep++;
682
683	/* Make the CS selector some invalid type and check it triggers before SS stuff. */
684	Bs3GdteTestPage02.Gen.u4Type = g_aInvalidCsTypes[i].u4Type;
685	Bs3GdteTestPage02.Gen.u1DescType = g_aInvalidCsTypes[i].u1DescType;
686	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
687	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_02);
688	Bs3GdteTestPage02.Gen.u4Type = X86_SEL_TYPE_ER_ACC;
689	Bs3GdteTestPage02.Gen.u1DescType = 1;
690	g_usBs3TestStep++;
691
692	/* Now, make the CS selector limit too small and that it triggers after SS trouble. */
693	Bs3GdteTestPage02.Gen.u16LimitLow = 0;
694	Bs3GdteTestPage02.Gen.u4LimitHigh = 0;
695	Bs3GdteTestPage02.Gen.u1Granularity = 0;
696	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
697	if (iRpl != 2 \|\| iRpl != iDpl \|\| k >= 4)
698	bs3CpuBasic2_CompareTsCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_03);
699	else if (k != 0)
700	bs3CpuBasic2_CompareSsCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_03, k == 2 /f486ResumeFlagHint/);
701	else
702	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, 0 /uErrCd/);
703	Bs3GdteTestPage02 = Bs3Gdt[(uSysR0Cs + (2 << BS3_SEL_RING_SHIFT)) >> X86_SEL_SHIFT];
704	g_usBs3TestStep++;
705	}
706	}
707	}
708
709	/* Check all the invalid SS selector types alone. */
710	Bs3GdteTestPage02 = Bs3Gdt[(uSysR0Cs + (2 << BS3_SEL_RING_SHIFT)) >> X86_SEL_SHIFT];
711	Bs3GdteTestPage03 = Bs3Gdt[(uSysR0Ss + (2 << BS3_SEL_RING_SHIFT)) >> X86_SEL_SHIFT];
712	*puTssSs2 = BS3_SEL_TEST_PAGE_03 \| 2;
713	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
714	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x83);
715	g_usBs3TestStep++;
716	for (i = 0; i < RT_ELEMENTS(g_aInvalidSsTypes); i++)
717	{
718	Bs3GdteTestPage03.Gen.u4Type = g_aInvalidSsTypes[i].u4Type;
719	Bs3GdteTestPage03.Gen.u1DescType = g_aInvalidSsTypes[i].u1DescType;
720	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
721	bs3CpuBasic2_CompareTsCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_03);
722	if (Bs3GdteTestPage03.Gen.u4Type != g_aInvalidSsTypes[i].u4Type)
723	bs3CpuBasic2_FailedF("Invalid SS type %#x/%u -> %#x/%u\n",
724	g_aInvalidSsTypes[i].u4Type, g_aInvalidSsTypes[i].u1DescType,
725	Bs3GdteTestPage03.Gen.u4Type, Bs3GdteTestPage03.Gen.u1DescType);
726	g_usBs3TestStep++;
727	}
728
729	/*
730	* Continue the SS experiments with a expand down segment. We'll use
731	* the same setup as we already have with gate 83h being DPL and
732	* having CS.DPL=2.
733	*
734	* Expand down segments are weird. The valid area is practically speaking
735	* reversed. So, a 16-bit segment with a limit of 0x6000 will have valid
736	* addresses from 0xffff thru 0x6001.
737	*
738	* So, with expand down segments we can more easily cut partially into the
739	* pushing of the iret frame and trigger more interesting behavior than
740	* with regular "expand up" segments where the whole pushing area is either
741	* all fine or not not fine.
742	*/
743	Bs3GdteTestPage02 = Bs3Gdt[(uSysR0Cs + (2 << BS3_SEL_RING_SHIFT)) >> X86_SEL_SHIFT];
744	Bs3GdteTestPage03 = Bs3Gdt[(uSysR0Ss + (2 << BS3_SEL_RING_SHIFT)) >> X86_SEL_SHIFT];
745	Bs3GdteTestPage03.Gen.u2Dpl = 2;
746	Bs3GdteTestPage03.Gen.u4Type = X86_SEL_TYPE_RW_DOWN;
747	*puTssSs2 = BS3_SEL_TEST_PAGE_03 \| 2;
748
749	/* First test, limit = max --> no bytes accessible --> #GP */
750	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
751	bs3CpuBasic2_CompareSsCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_03, true /f486ResumeFlagHint/);
752
753	/* Second test, limit = 0 --> all by zero byte accessible --> works */
754	Bs3GdteTestPage03.Gen.u16LimitLow = 0;
755	Bs3GdteTestPage03.Gen.u4LimitHigh = 0;
756	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
757	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x83);
758
759	/* Modify the gate handler to be a dummy that immediately does UD2
760	and triggers #UD, then advance the limit down till we get the #UD. */
761	Bs3GdteTestPage03.Gen.u1Granularity = 0;
762
763	Bs3MemCpy(&CtxTmp2, &CtxTmp, sizeof(CtxTmp2)); /* #UD result context */
764	if (g_f16BitSys)
765	{
766	CtxTmp2.rip.u = g_bs3CpuBasic2_ud2_FlatAddr - BS3_ADDR_BS3TEXT16;
767	Bs3Trap16SetGate(0x83, X86_SEL_TYPE_SYS_286_INT_GATE, 3, BS3_SEL_TEST_PAGE_02, CtxTmp2.rip.u16, 0 /cParams/);
768	CtxTmp2.rsp.u = Bs3Tss16.sp2 - 2*5;
769	}
770	else
771	{
772	CtxTmp2.rip.u = g_bs3CpuBasic2_ud2_FlatAddr;
773	Bs3Trap32SetGate(0x83, X86_SEL_TYPE_SYS_386_INT_GATE, 3, BS3_SEL_TEST_PAGE_02, CtxTmp2.rip.u32, 0 /cParams/);
774	CtxTmp2.rsp.u = Bs3Tss32.esp2 - 4*5;
775	}
776	CtxTmp2.bMode = g_bTestMode; /* g_bBs3CurrentMode not changed by the UD2 handler. */
777	CtxTmp2.cs = BS3_SEL_TEST_PAGE_02 \| 2;
778	CtxTmp2.ss = BS3_SEL_TEST_PAGE_03 \| 2;
779	CtxTmp2.bCpl = 2;
780
781	/* test run. */
782	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
783	bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxTmp2);
784	g_usBs3TestStep++;
785
786	/* Real run. */
787	i = (g_f16BitSys ? 2 : 4) * 6 + 1;
788	while (i-- > 0)
789	{
790	Bs3GdteTestPage03.Gen.u16LimitLow = CtxTmp2.rsp.u16 + i - 1;
791	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
792	if (i > 0)
793	bs3CpuBasic2_CompareSsCtx(&TrapCtx, &CtxTmp, BS3_SEL_TEST_PAGE_03, true /f486ResumeFlagHint/);
794	else
795	bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxTmp2);
796	g_usBs3TestStep++;
797	}
798
799	/* Do a run where we do the same-ring kind of access. */
800	Bs3RegCtxConvertToRingX(&CtxTmp, 2);
801	if (g_f16BitSys)
802	{
803	CtxTmp2.rsp.u32 = CtxTmp.rsp.u32 - 2*3;
804	i = 2*3 - 1;
805	}
806	else
807	{
808	CtxTmp2.rsp.u32 = CtxTmp.rsp.u32 - 4*3;
809	i = 4*3 - 1;
810	}
811	CtxTmp.ss = BS3_SEL_TEST_PAGE_03 \| 2;
812	CtxTmp2.ds = CtxTmp.ds;
813	CtxTmp2.es = CtxTmp.es;
814	CtxTmp2.fs = CtxTmp.fs;
815	CtxTmp2.gs = CtxTmp.gs;
816	while (i-- > 0)
817	{
818	Bs3GdteTestPage03.Gen.u16LimitLow = CtxTmp2.rsp.u16 + i - 1;
819	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
820	if (i > 0)
821	bs3CpuBasic2_CompareSsCtx(&TrapCtx, &CtxTmp, 0 /BS3_SEL_TEST_PAGE_03/, true /f486ResumeFlagHint/);
822	else
823	bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxTmp2);
824	g_usBs3TestStep++;
825	}
826
827	*puTssSs2 = uSavedSs2;
828	paIdt[0x83 << cIdteShift] = SavedGate83;
829	}
830	paIdt[0x80 << cIdteShift].Gate.u16Sel = uSysR0Cs;
831	BS3_ASSERT(g_usBs3TestStep < 3000);
832
833	/*
834	* Modify the gate CS value with a conforming segment.
835	*/
836	g_usBs3TestStep = 3000;
837	for (i = 0; i <= 3; i++) /* cs.dpl */
838	{
839	for (iRing = 0; iRing <= 3; iRing++)
840	{
841	for (iCtx = 0; iCtx < RT_ELEMENTS(apCtx8x); iCtx++)
842	{
843	Bs3MemCpy(&CtxTmp, apCtx8x[iCtx], sizeof(CtxTmp));
844	Bs3RegCtxConvertToRingX(&CtxTmp, iRing);
845	# if TMPL_BITS == 32
846	g_uBs3TrapEipHint = CtxTmp.rip.u32;
847	# endif
848
849	for (j = 0; j <= 3; j++) /* rpl */
850	{
851	uint16_t const uCs = (uSysR0CsConf \| j) + (i << BS3_SEL_RING_SHIFT);
852	/Bs3TestPrintf("g_usBs3TestStep=%u iCtx=%u iRing=%u i=%u uCs=%04x\n", g_usBs3TestStep, iCtx, iRing, i, uCs);/
853	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u16Sel = uCs;
854	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
855	//Bs3TestPrintf("%u/%u/%u/%u: cs=%04x hcs=%04x xcpt=%02x\n", i, iRing, iCtx, j, uCs, TrapCtx.uHandlerCs, TrapCtx.bXcpt);
856	/Bs3TrapPrintFrame(&TrapCtx);/
857	g_usBs3TestStep++;
858	if (iCtx < iRing)
859	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
860	else if (i > iRing)
861	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, uCs & X86_SEL_MASK_OFF_RPL);
862	else
863	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x80 + iCtx /bXcpt/);
864	}
865	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u16Sel = uSysR0Cs;
866	}
867	}
868	}
869	BS3_ASSERT(g_usBs3TestStep < 3500);
870
871	/*
872	* The gates must be 64-bit in long mode.
873	*/
874	if (cIdteShift != 0)
875	{
876	g_usBs3TestStep = 3500;
877	for (i = 0; i <= 3; i++)
878	{
879	for (iRing = 0; iRing <= 3; iRing++)
880	{
881	for (iCtx = 0; iCtx < RT_ELEMENTS(apCtx8x); iCtx++)
882	{
883	Bs3MemCpy(&CtxTmp, apCtx8x[iCtx], sizeof(CtxTmp));
884	Bs3RegCtxConvertToRingX(&CtxTmp, iRing);
885
886	for (j = 0; j < 2; j++)
887	{
888	static const uint16_t s_auCSes[2] = { BS3_SEL_R0_CS16, BS3_SEL_R0_CS32 };
889	uint16_t uCs = (s_auCSes[j] \| i) + (i << BS3_SEL_RING_SHIFT);
890	g_usBs3TestStep++;
891	/Bs3TestPrintf("g_usBs3TestStep=%u iCtx=%u iRing=%u i=%u uCs=%04x\n", g_usBs3TestStep, iCtx, iRing, i, uCs);/
892	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u16Sel = uCs;
893	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
894	/Bs3TrapPrintFrame(&TrapCtx);/
895	if (iCtx < iRing)
896	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
897	else
898	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, uCs & X86_SEL_MASK_OFF_RPL);
899	}
900	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u16Sel = uSysR0Cs;
901	}
902	}
903	}
904	BS3_ASSERT(g_usBs3TestStep < 4000);
905	}
906
907	/*
908	* IDT limit check.
909	*/
910	g_usBs3TestStep = 5000;
911	i = (0x80 << (cIdteShift + 3)) - 1;
912	j = (0x82 << (cIdteShift + 3)) - 1;
913	k = (0x83 << (cIdteShift + 3)) - 1;
914	for (; i <= k; i++, g_usBs3TestStep++)
915	{
916	Idtr = IdtrSaved;
917	Idtr.cbIdt = i;
918	ASMSetIDTR(&Idtr);
919	Bs3TrapSetJmpAndRestore(&Ctx81, &TrapCtx);
920	if (i < j)
921	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &Ctx81, (0x81 << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
922	else
923	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx81, 0x81 /bXcpt/);
924	}
925	ASMSetIDTR(&IdtrSaved);
926	BS3_ASSERT(g_usBs3TestStep < 5100);
927
928	# if TMPL_BITS != 16 /* Only do the paging related stuff in 32-bit and 64-bit modes. */
929
930	/*
931	* IDT page not present. Placing the IDT copy such that 0x80 is on the
932	* first page and 0x81 is on the second page. We need proceed to move
933	* it down byte by byte to check that any inaccessible byte means #PF.
934	*
935	* Note! We must reload the alternative IDTR for each run as any kind of
936	* printing to the string (like error reporting) will cause a switch
937	* to real mode and back, reloading the default IDTR.
938	*/
939	g_usBs3TestStep = 5200;
940	if (BS3_MODE_IS_PAGED(g_bTestMode) && pbIdtCopyAlloc)
941	{
942	uint32_t const uCr2Expected = Bs3SelPtrToFlat(pbIdtCopyAlloc) + _4K;
943	for (j = 0; j < cbIdte; j++)
944	{
945	pIdtCopy = (PX86DESC)&pbIdtCopyAlloc[_4K - cbIdte * 0x81 - j];
946	Bs3MemCpy(pIdtCopy, paIdt, cbIdte * 256);
947
948	Idtr.cbIdt = IdtrSaved.cbIdt;
949	Idtr.pIdt = Bs3SelPtrToFlat(pIdtCopy);
950
951	ASMSetIDTR(&Idtr);
952	Bs3TrapSetJmpAndRestore(&Ctx81, &TrapCtx);
953	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx81, 0x81 /bXcpt/);
954	g_usBs3TestStep++;
955
956	ASMSetIDTR(&Idtr);
957	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
958	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx80, 0x80 /bXcpt/);
959	g_usBs3TestStep++;
960
961	rc = Bs3PagingProtect(uCr2Expected, _4K, 0 /fSet/, X86_PTE_P /fClear/);
962	if (RT_SUCCESS(rc))
963	{
964	ASMSetIDTR(&Idtr);
965	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
966	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx80, 0x80 /bXcpt/);
967	g_usBs3TestStep++;
968
969	ASMSetIDTR(&Idtr);
970	Bs3TrapSetJmpAndRestore(&Ctx81, &TrapCtx);
971	bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx81, 0 /uErrCd/, uCr2Expected);
972	g_usBs3TestStep++;
973
974	Bs3PagingProtect(uCr2Expected, _4K, X86_PTE_P /fSet/, 0 /fClear/);
975
976	/* Check if that the entry type is checked after the whole IDTE has been cleared for #PF. */
977	pIdtCopy[0x80 << cIdteShift].Gate.u4Type = 0;
978	rc = Bs3PagingProtect(uCr2Expected, _4K, 0 /fSet/, X86_PTE_P /fClear/);
979	if (RT_SUCCESS(rc))
980	{
981	ASMSetIDTR(&Idtr);
982	Bs3TrapSetJmpAndRestore(&Ctx81, &TrapCtx);
983	bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx81, 0 /uErrCd/, uCr2Expected);
984	g_usBs3TestStep++;
985
986	Bs3PagingProtect(uCr2Expected, _4K, X86_PTE_P /fSet/, 0 /fClear/);
987	}
988	}
989	else
990	Bs3TestPrintf("Bs3PagingProtectPtr: %d\n", i);
991
992	ASMSetIDTR(&IdtrSaved);
993	}
994	}
995
996	/*
997	* The read/write and user/supervisor bits the IDT PTEs are irrelevant.
998	*/
999	g_usBs3TestStep = 5300;
1000	if (BS3_MODE_IS_PAGED(g_bTestMode) && pbIdtCopyAlloc)
1001	{
1002	Bs3MemCpy(pbIdtCopyAlloc, paIdt, cbIdte * 256);
1003	Idtr.cbIdt = IdtrSaved.cbIdt;
1004	Idtr.pIdt = Bs3SelPtrToFlat(pbIdtCopyAlloc);
1005
1006	ASMSetIDTR(&Idtr);
1007	Bs3TrapSetJmpAndRestore(&Ctx81, &TrapCtx);
1008	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx81, 0x81 /bXcpt/);
1009	g_usBs3TestStep++;
1010
1011	rc = Bs3PagingProtect(Idtr.pIdt, _4K, 0 /fSet/, X86_PTE_RW \| X86_PTE_US /fClear/);
1012	if (RT_SUCCESS(rc))
1013	{
1014	ASMSetIDTR(&Idtr);
1015	Bs3TrapSetJmpAndRestore(&Ctx81, &TrapCtx);
1016	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx81, 0x81 /bXcpt/);
1017	g_usBs3TestStep++;
1018
1019	Bs3PagingProtect(Idtr.pIdt, _4K, X86_PTE_RW \| X86_PTE_US /fSet/, 0 /fClear/);
1020	}
1021	ASMSetIDTR(&IdtrSaved);
1022	}
1023
1024	/*
1025	* Check that CS.u1Accessed is set to 1. Use the test page selector #0 and #3 together
1026	* with interrupt gates 80h and 83h, respectively.
1027	*/
1028	/** @todo Throw in SS.u1Accessed too. */
1029	g_usBs3TestStep = 5400;
1030	if (BS3_MODE_IS_PAGED(g_bTestMode) && pbIdtCopyAlloc)
1031	{
1032	Bs3GdteTestPage00 = Bs3Gdt[uSysR0Cs >> X86_SEL_SHIFT];
1033	Bs3GdteTestPage00.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
1034	paIdt[0x80 << cIdteShift].Gate.u16Sel = BS3_SEL_TEST_PAGE_00;
1035
1036	Bs3GdteTestPage03 = Bs3Gdt[(uSysR0Cs + (3 << BS3_SEL_RING_SHIFT)) >> X86_SEL_SHIFT];
1037	Bs3GdteTestPage03.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
1038	paIdt[0x83 << cIdteShift].Gate.u16Sel = BS3_SEL_TEST_PAGE_03; /* rpl is ignored, so leave it as zero. */
1039
1040	/* Check that the CS.A bit is being set on a general basis and that
1041	the special CS values work with out generic handler code. */
1042	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
1043	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx80, 0x80 /bXcpt/);
1044	if (!(Bs3GdteTestPage00.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1045	bs3CpuBasic2_FailedF("u4Type=%#x, not accessed", Bs3GdteTestPage00.Gen.u4Type);
1046	g_usBs3TestStep++;
1047
1048	Bs3MemCpy(&CtxTmp, &Ctx83, sizeof(CtxTmp));
1049	Bs3RegCtxConvertToRingX(&CtxTmp, 3);
1050	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
1051	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x83 /bXcpt/);
1052	if (!(Bs3GdteTestPage03.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1053	bs3CpuBasic2_FailedF("u4Type=%#x, not accessed!", Bs3GdteTestPage00.Gen.u4Type);
1054	if (TrapCtx.uHandlerCs != (BS3_SEL_TEST_PAGE_03 \| 3))
1055	bs3CpuBasic2_FailedF("uHandlerCs=%#x, expected %#x", TrapCtx.uHandlerCs, (BS3_SEL_TEST_PAGE_03 \| 3));
1056	g_usBs3TestStep++;
1057
1058	/*
1059	* Now check that setting CS.u1Access to 1 does __NOT__ trigger a page
1060	* fault due to the RW bit being zero.
1061	* (We check both with with and without the WP bit if 80486.)
1062	*/
1063	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80486)
1064	ASMSetCR0(uCr0Saved \| X86_CR0_WP);
1065
1066	Bs3GdteTestPage00.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
1067	Bs3GdteTestPage03.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
1068	rc = Bs3PagingProtect(GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_00, 8, 0 /fSet/, X86_PTE_RW /fClear/);
1069	if (RT_SUCCESS(rc))
1070	{
1071	/* ring-0 handler */
1072	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
1073	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx80, 0x80 /bXcpt/);
1074	if (!(Bs3GdteTestPage00.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1075	bs3CpuBasic2_FailedF("u4Type=%#x, not accessed!", Bs3GdteTestPage00.Gen.u4Type);
1076	g_usBs3TestStep++;
1077
1078	/* ring-3 handler */
1079	Bs3MemCpy(&CtxTmp, &Ctx83, sizeof(CtxTmp));
1080	Bs3RegCtxConvertToRingX(&CtxTmp, 3);
1081	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
1082	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x83 /bXcpt/);
1083	if (!(Bs3GdteTestPage03.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1084	bs3CpuBasic2_FailedF("u4Type=%#x, not accessed!", Bs3GdteTestPage00.Gen.u4Type);
1085	g_usBs3TestStep++;
1086
1087	/* clear WP and repeat the above. */
1088	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80486)
1089	ASMSetCR0(uCr0Saved & ~X86_CR0_WP);
1090	Bs3GdteTestPage00.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED; /* (No need to RW the page - ring-0, WP=0.) */
1091	Bs3GdteTestPage03.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED; /* (No need to RW the page - ring-0, WP=0.) */
1092
1093	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
1094	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx80, 0x80 /bXcpt/);
1095	if (!(Bs3GdteTestPage00.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1096	bs3CpuBasic2_FailedF("u4Type=%#x, not accessed!", Bs3GdteTestPage00.Gen.u4Type);
1097	g_usBs3TestStep++;
1098
1099	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
1100	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x83 /bXcpt/);
1101	if (!(Bs3GdteTestPage03.Gen.u4Type & X86_SEL_TYPE_ACCESSED))
1102	bs3CpuBasic2_FailedF("u4Type=%#x, not accessed!n", Bs3GdteTestPage03.Gen.u4Type);
1103	g_usBs3TestStep++;
1104
1105	Bs3PagingProtect(GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_00, 8, X86_PTE_RW /fSet/, 0 /fClear/);
1106	}
1107
1108	ASMSetCR0(uCr0Saved);
1109
1110	/*
1111	* While we're here, check that if the CS GDT entry is a non-present
1112	* page we do get a #PF with the rigth error code and CR2.
1113	*/
1114	Bs3GdteTestPage00.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED; /* Just for fun, really a pointless gesture. */
1115	Bs3GdteTestPage03.Gen.u4Type &= ~X86_SEL_TYPE_ACCESSED;
1116	rc = Bs3PagingProtect(GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_00, 8, 0 /fSet/, X86_PTE_P /fClear/);
1117	if (RT_SUCCESS(rc))
1118	{
1119	Bs3TrapSetJmpAndRestore(&Ctx80, &TrapCtx);
1120	bs3CpuBasic2_ComparePfCtx(&TrapCtx, &Ctx80, 0 /uErrCd/, GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_00);
1121	g_usBs3TestStep++;
1122
1123	/* Do it from ring-3 to check ErrCd, which doesn't set X86_TRAP_PF_US it turns out. */
1124	Bs3MemCpy(&CtxTmp, &Ctx83, sizeof(CtxTmp));
1125	Bs3RegCtxConvertToRingX(&CtxTmp, 3);
1126	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
1127
1128	bs3CpuBasic2_ComparePfCtx(&TrapCtx, &CtxTmp, 0 /uErrCd/, GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_03);
1129	g_usBs3TestStep++;
1130
1131	Bs3PagingProtect(GdtrSaved.pGdt + BS3_SEL_TEST_PAGE_00, 8, X86_PTE_P /fSet/, 0 /fClear/);
1132	if (Bs3GdteTestPage00.Gen.u4Type & X86_SEL_TYPE_ACCESSED)
1133	bs3CpuBasic2_FailedF("u4Type=%#x, accessed! #1", Bs3GdteTestPage00.Gen.u4Type);
1134	if (Bs3GdteTestPage03.Gen.u4Type & X86_SEL_TYPE_ACCESSED)
1135	bs3CpuBasic2_FailedF("u4Type=%#x, accessed! #2", Bs3GdteTestPage03.Gen.u4Type);
1136	}
1137
1138	/* restore */
1139	paIdt[0x80 << cIdteShift].Gate.u16Sel = uSysR0Cs;
1140	paIdt[0x83 << cIdteShift].Gate.u16Sel = uSysR0Cs;// + (3 << BS3_SEL_RING_SHIFT) + 3;
1141	}
1142
1143	# endif /* 32 \|\| 64*/
1144
1145	/*
1146	* Check broad EFLAGS effects.
1147	*/
1148	g_usBs3TestStep = 5600;
1149	for (iCtx = 0; iCtx < RT_ELEMENTS(apCtx8x); iCtx++)
1150	{
1151	for (iRing = 0; iRing < 4; iRing++)
1152	{
1153	Bs3MemCpy(&CtxTmp, apCtx8x[iCtx], sizeof(CtxTmp));
1154	Bs3RegCtxConvertToRingX(&CtxTmp, iRing);
1155
1156	/* all set */
1157	CtxTmp.rflags.u32 &= X86_EFL_VM \| X86_EFL_1;
1158	CtxTmp.rflags.u32 \|= X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF /* \| X86_EFL_TF / /\| X86_EFL_IF*/
1159	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL /* \| X86_EFL_NT*/;
1160	if (f386Plus)
1161	CtxTmp.rflags.u32 \|= /X86_EFL_VM \|/ X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP;
1162	if (f386Plus && !g_f16BitSys)
1163	CtxTmp.rflags.u32 \|= X86_EFL_RF;
1164	if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
1165	CtxTmp.rflags.u32 \|= X86_EFL_ID;
1166	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
1167	CtxTmp.rflags.u32 &= ~X86_EFL_RF;
1168
1169	if (iCtx >= iRing)
1170	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x80 + iCtx /bXcpt/);
1171	else
1172	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
1173	uExpected = CtxTmp.rflags.u32
1174	& ( X86_EFL_1 \| X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_DF
1175	\| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_VM \| X86_EFL_AC \| X86_EFL_VIF \| X86_EFL_VIP
1176	\| X86_EFL_ID /\| X86_EFL_TF/ /\| X86_EFL_IF/ /\| X86_EFL_RF/ );
1177	if (TrapCtx.fHandlerRfl != uExpected)
1178	bs3CpuBasic2_FailedF("unexpected handler rflags value: %RX64 expected %RX32; CtxTmp.rflags=%RX64 Ctx.rflags=%RX64\n",
1179	TrapCtx.fHandlerRfl, uExpected, CtxTmp.rflags.u, TrapCtx.Ctx.rflags.u);
1180	g_usBs3TestStep++;
1181
1182	/* all cleared */
1183	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) < BS3CPU_80286)
1184	CtxTmp.rflags.u32 = apCtx8x[iCtx]->rflags.u32 & (X86_EFL_RA1_MASK \| UINT16_C(0xf000));
1185	else
1186	CtxTmp.rflags.u32 = apCtx8x[iCtx]->rflags.u32 & (X86_EFL_VM \| X86_EFL_RA1_MASK);
1187	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
1188	if (iCtx >= iRing)
1189	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &CtxTmp, 0x80 + iCtx /bXcpt/);
1190	else
1191	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
1192	uExpected = CtxTmp.rflags.u32;
1193	if (TrapCtx.fHandlerRfl != uExpected)
1194	bs3CpuBasic2_FailedF("unexpected handler rflags value: %RX64 expected %RX32; CtxTmp.rflags=%RX64 Ctx.rflags=%RX64\n",
1195	TrapCtx.fHandlerRfl, uExpected, CtxTmp.rflags.u, TrapCtx.Ctx.rflags.u);
1196	g_usBs3TestStep++;
1197	}
1198	}
1199
1200	/** @todo CS.LIMIT / canonical(CS) */
1201
1202
1203	/*
1204	* Check invalid gate types.
1205	*/
1206	g_usBs3TestStep = 32000;
1207	for (iRing = 0; iRing <= 3; iRing++)
1208	{
1209	static const uint16_t s_auCSes[] = { BS3_SEL_R0_CS16, BS3_SEL_R0_CS32, BS3_SEL_R0_CS64,
1210	BS3_SEL_TSS16, BS3_SEL_TSS32, BS3_SEL_TSS64, 0, BS3_SEL_SPARE_1f };
1211	static uint16_t const s_auInvlTypes64[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
1212	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
1213	0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f };
1214	static uint16_t const s_auInvlTypes32[] = { 0, 1, 2, 3, 8, 9, 10, 11, 13,
1215	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
1216	0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
1217	/286:/ 12, 14, 15 };
1218	uint16_t const * const pauInvTypes = cIdteShift != 0 ? s_auInvlTypes64 : s_auInvlTypes32;
1219	uint16_t const cInvTypes = cIdteShift != 0 ? RT_ELEMENTS(s_auInvlTypes64)
1220	: f386Plus ? RT_ELEMENTS(s_auInvlTypes32) - 3 : RT_ELEMENTS(s_auInvlTypes32);
1221
1222
1223	for (iCtx = 0; iCtx < RT_ELEMENTS(apCtx8x); iCtx++)
1224	{
1225	unsigned iType;
1226
1227	Bs3MemCpy(&CtxTmp, apCtx8x[iCtx], sizeof(CtxTmp));
1228	Bs3RegCtxConvertToRingX(&CtxTmp, iRing);
1229	# if TMPL_BITS == 32
1230	g_uBs3TrapEipHint = CtxTmp.rip.u32;
1231	# endif
1232	for (iType = 0; iType < cInvTypes; iType++)
1233	{
1234	uint8_t const bSavedType = paIdt[(0x80 + iCtx) << cIdteShift].Gate.u4Type;
1235	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u1DescType = pauInvTypes[iType] >> 4;
1236	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u4Type = pauInvTypes[iType] & 0xf;
1237
1238	for (i = 0; i < 4; i++)
1239	{
1240	for (j = 0; j < RT_ELEMENTS(s_auCSes); j++)
1241	{
1242	uint16_t uCs = (unsigned)(s_auCSes[j] - BS3_SEL_R0_FIRST) < (unsigned)(4 << BS3_SEL_RING_SHIFT)
1243	? (s_auCSes[j] \| i) + (i << BS3_SEL_RING_SHIFT)
1244	: s_auCSes[j] \| i;
1245	/Bs3TestPrintf("g_usBs3TestStep=%u iCtx=%u iRing=%u i=%u uCs=%04x type=%#x\n", g_usBs3TestStep, iCtx, iRing, i, uCs, pauInvTypes[iType]);/
1246	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u16Sel = uCs;
1247	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
1248	g_usBs3TestStep++;
1249	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
1250
1251	/* Mark it not-present to check that invalid type takes precedence. */
1252	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u1Present = 0;
1253	Bs3TrapSetJmpAndRestore(&CtxTmp, &TrapCtx);
1254	g_usBs3TestStep++;
1255	bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxTmp, ((0x80 + iCtx) << X86_TRAP_ERR_SEL_SHIFT) \| X86_TRAP_ERR_IDT);
1256	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u1Present = 1;
1257	}
1258	}
1259
1260	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u16Sel = MY_SYS_SEL_R0_CS;
1261	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u4Type = bSavedType;
1262	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u1DescType = 0;
1263	paIdt[(0x80 + iCtx) << cIdteShift].Gate.u1Present = 1;
1264	}
1265	}
1266	}
1267	BS3_ASSERT(g_usBs3TestStep < 62000U && g_usBs3TestStep > 32000U);
1268
1269
1270	/** @todo
1271	* - Run \#PF and \#GP (and others?) at CPLs other than zero.
1272	* - Quickly generate all faults.
1273	* - All the peculiarities v8086.
1274	*/
1275
1276	# if TMPL_BITS != 16
1277	Bs3MemFree(pbIdtCopyAlloc, 12*_1K);
1278	# endif
1279	}
1280
1281	#endif /* once for each bitcount */
1282
1283
1284	#if TMPL_MODE == BS3_MODE_PE16 \|\| TMPL_MODE == BS3_MODE_PE16_32
1285
1286	/**
1287	* Worker for bs3CpuBasic2_TssGateEsp that tests the INT 80 from outer rings.
1288	*/
1289	#define bs3CpuBasic2_TssGateEsp_AltStackOuterRing BS3_CMN_NM(bs3CpuBasic2_TssGateEsp_AltStackOuterRing)
1290	void bs3CpuBasic2_TssGateEsp_AltStackOuterRing(PCBS3REGCTX pCtx, uint8_t bRing, uint8_t *pbAltStack, size_t cbAltStack,
1291	bool f16BitStack, bool f16BitTss, bool f16BitHandler, unsigned uLine)
1292	{
1293	uint8_t const cbIretFrame = f16BitHandler ? 52 : 54;
1294	BS3REGCTX Ctx2;
1295	BS3TRAPFRAME TrapCtx;
1296	uint8_t *pbTmp;
1297	g_usBs3TestStep = uLine;
1298
1299	Bs3MemCpy(&Ctx2, pCtx, sizeof(Ctx2));
1300	Bs3RegCtxConvertToRingX(&Ctx2, bRing);
1301
1302	if (pbAltStack)
1303	{
1304	Ctx2.rsp.u = Bs3SelPtrToFlat(pbAltStack + 0x1980);
1305	Bs3MemZero(pbAltStack, cbAltStack);
1306	}
1307
1308	Bs3TrapSetJmpAndRestore(&Ctx2, &TrapCtx);
1309
1310	if (!f16BitStack && f16BitTss)
1311	Ctx2.rsp.u &= UINT16_MAX;
1312
1313	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx2, 0x80 /bXcpt/);
1314	CHECK_MEMBER("bCpl", "%u", TrapCtx.Ctx.bCpl, bRing);
1315	CHECK_MEMBER("cbIretFrame", "%#x", TrapCtx.cbIretFrame, cbIretFrame);
1316
1317	if (pbAltStack)
1318	{
1319	uint64_t uExpectedRsp = (f16BitTss ? Bs3Tss16.sp0 : Bs3Tss32.esp0) - cbIretFrame;
1320	if (f16BitStack)
1321	{
1322	uExpectedRsp &= UINT16_MAX;
1323	uExpectedRsp \|= Ctx2.rsp.u & ~(uint64_t)UINT16_MAX;
1324	}
1325	if ( TrapCtx.uHandlerRsp != uExpectedRsp
1326	\|\| TrapCtx.uHandlerSs != (f16BitTss ? Bs3Tss16.ss0 : Bs3Tss32.ss0))
1327	bs3CpuBasic2_FailedF("handler SS:ESP=%04x:%08RX64, expected %04x:%08RX16",
1328	TrapCtx.uHandlerSs, TrapCtx.uHandlerRsp, Bs3Tss16.ss0, uExpectedRsp);
1329
1330	pbTmp = (uint8_t *)ASMMemFirstNonZero(pbAltStack, cbAltStack);
1331	if ((f16BitStack \|\| TrapCtx.uHandlerRsp <= UINT16_MAX) && pbTmp != NULL)
1332	bs3CpuBasic2_FailedF("someone touched the alt stack (%p) with SS:ESP=%04x:%#RX32: %p=%02x",
1333	pbAltStack, Ctx2.ss, Ctx2.rsp.u32, pbTmp, *pbTmp);
1334	else if (!f16BitStack && TrapCtx.uHandlerRsp > UINT16_MAX && pbTmp == NULL)
1335	bs3CpuBasic2_FailedF("the alt stack (%p) was not used SS:ESP=%04x:%#RX32\n", pbAltStack, Ctx2.ss, Ctx2.rsp.u32);
1336	}
1337	}
1338
1339	#define bs3CpuBasic2_TssGateEspCommon BS3_CMN_NM(bs3CpuBasic2_TssGateEspCommon)
1340	void bs3CpuBasic2_TssGateEspCommon(bool const g_f16BitSys, PX86DESC const paIdt, unsigned const cIdteShift)
1341	{
1342	BS3TRAPFRAME TrapCtx;
1343	BS3REGCTX Ctx;
1344	BS3REGCTX Ctx2;
1345	# if TMPL_BITS == 16
1346	uint8_t *pbTmp;
1347	# endif
1348
1349	/* make sure they're allocated */
1350	Bs3MemZero(&Ctx, sizeof(Ctx));
1351	Bs3MemZero(&Ctx2, sizeof(Ctx2));
1352	Bs3MemZero(&TrapCtx, sizeof(TrapCtx));
1353
1354	Bs3RegCtxSave(&Ctx);
1355	Ctx.rsp.u -= 0x80;
1356	Ctx.rip.u = (uintptr_t)BS3_FP_OFF(&TMPL_NM(bs3CpuBasic2_Int80));
1357	# if TMPL_BITS == 32
1358	g_uBs3TrapEipHint = Ctx.rip.u32;
1359	# endif
1360
1361	/*
1362	* We'll be using IDT entry 80 and 81 here. The first one will be
1363	* accessible from all DPLs, the latter not. So, start with setting
1364	* the DPLs.
1365	*/
1366	paIdt[0x80 << cIdteShift].Gate.u2Dpl = 3;
1367	paIdt[0x81 << cIdteShift].Gate.u2Dpl = 0;
1368
1369	/*
1370	* Check that the basic stuff works first.
1371	*/
1372	Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx);
1373	g_usBs3TestStep = __LINE__;
1374	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx, 0x80 /bXcpt/);
1375
1376	bs3CpuBasic2_TssGateEsp_AltStackOuterRing(&Ctx, 1, NULL, 0, g_f16BitSys, g_f16BitSys, g_f16BitSys, __LINE__);
1377	bs3CpuBasic2_TssGateEsp_AltStackOuterRing(&Ctx, 2, NULL, 0, g_f16BitSys, g_f16BitSys, g_f16BitSys, __LINE__);
1378	bs3CpuBasic2_TssGateEsp_AltStackOuterRing(&Ctx, 3, NULL, 0, g_f16BitSys, g_f16BitSys, g_f16BitSys, __LINE__);
1379
1380	/*
1381	* Check that the upper part of ESP is preserved when doing .
1382	*/
1383	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
1384	{
1385	size_t const cbAltStack = _8K;
1386	uint8_t *pbAltStack = Bs3MemAllocZ(BS3MEMKIND_TILED, cbAltStack);
1387	if (pbAltStack)
1388	{
1389	/* same ring */
1390	g_usBs3TestStep = __LINE__;
1391	Bs3MemCpy(&Ctx2, &Ctx, sizeof(Ctx2));
1392	Ctx2.rsp.u = Bs3SelPtrToFlat(pbAltStack + 0x1980);
1393	if (Bs3TrapSetJmp(&TrapCtx))
1394	Bs3RegCtxRestore(&Ctx2, 0); /* (does not return) */
1395	bs3CpuBasic2_CompareIntCtx1(&TrapCtx, &Ctx2, 0x80 /bXcpt/);
1396	# if TMPL_BITS == 16
1397	if ((pbTmp = (uint8_t *)ASMMemFirstNonZero(pbAltStack, cbAltStack)) != NULL)
1398	bs3CpuBasic2_FailedF("someone touched the alt stack (%p) with SS:ESP=%04x:%#RX32: %p=%02x\n",
1399	pbAltStack, Ctx2.ss, Ctx2.rsp.u32, pbTmp, *pbTmp);
1400	# else
1401	if (ASMMemIsZero(pbAltStack, cbAltStack))
1402	bs3CpuBasic2_FailedF("alt stack wasn't used despite SS:ESP=%04x:%#RX32\n", Ctx2.ss, Ctx2.rsp.u32);
1403	# endif
1404
1405	/* Different rings (load SS0:SP0 from TSS). */
1406	bs3CpuBasic2_TssGateEsp_AltStackOuterRing(&Ctx, 1, pbAltStack, cbAltStack,
1407	g_f16BitSys, g_f16BitSys, g_f16BitSys, __LINE__);
1408	bs3CpuBasic2_TssGateEsp_AltStackOuterRing(&Ctx, 2, pbAltStack, cbAltStack,
1409	g_f16BitSys, g_f16BitSys, g_f16BitSys, __LINE__);
1410	bs3CpuBasic2_TssGateEsp_AltStackOuterRing(&Ctx, 3, pbAltStack, cbAltStack,
1411	g_f16BitSys, g_f16BitSys, g_f16BitSys, __LINE__);
1412
1413	/* Different rings but switch the SS bitness in the TSS. */
1414	if (g_f16BitSys)
1415	{
1416	Bs3Tss16.ss0 = BS3_SEL_R0_SS32;
1417	bs3CpuBasic2_TssGateEsp_AltStackOuterRing(&Ctx, 1, pbAltStack, cbAltStack,
1418	false, g_f16BitSys, g_f16BitSys, __LINE__);
1419	Bs3Tss16.ss0 = BS3_SEL_R0_SS16;
1420	}
1421	else
1422	{
1423	Bs3Tss32.ss0 = BS3_SEL_R0_SS16;
1424	bs3CpuBasic2_TssGateEsp_AltStackOuterRing(&Ctx, 1, pbAltStack, cbAltStack,
1425	true, g_f16BitSys, g_f16BitSys, __LINE__);
1426	Bs3Tss32.ss0 = BS3_SEL_R0_SS32;
1427	}
1428
1429	Bs3MemFree(pbAltStack, cbAltStack);
1430	}
1431	else
1432	Bs3TestPrintf("%s: Skipping ESP check, alloc failed\n", g_pszTestMode);
1433	}
1434	else
1435	Bs3TestPrintf("%s: Skipping ESP check, CPU too old\n", g_pszTestMode);
1436	}
1437
1438	#endif
1439
1440
1441	BS3_DECL(uint8_t) TMPL_NM(bs3CpuBasic2_TssGateEsp)(uint8_t bMode)
1442	{
1443	uint8_t bRet = 0;
1444
1445	g_pszTestMode = TMPL_NM(g_szBs3ModeName);
1446	g_bTestMode = bMode;
1447	g_f16BitSys = BS3_MODE_IS_16BIT_SYS(TMPL_MODE);
1448
1449	#if TMPL_MODE == BS3_MODE_PE16 \
1450	\|\| TMPL_MODE == BS3_MODE_PE16_32 \
1451	\|\| TMPL_MODE == BS3_MODE_PP16 \
1452	\|\| TMPL_MODE == BS3_MODE_PP16_32 \
1453	\|\| TMPL_MODE == BS3_MODE_PAE16 \
1454	\|\| TMPL_MODE == BS3_MODE_PAE16_32 \
1455	\|\| TMPL_MODE == BS3_MODE_PE32
1456	bs3CpuBasic2_TssGateEspCommon(BS3_MODE_IS_16BIT_SYS(TMPL_MODE),
1457	(PX86DESC)MyBs3Idt,
1458	BS3_MODE_IS_64BIT_SYS(TMPL_MODE) ? 1 : 0);
1459	#else
1460	bRet = BS3TESTDOMODE_SKIPPED;
1461	#endif
1462
1463	/*
1464	* Re-initialize the IDT.
1465	*/
1466	TMPL_NM(Bs3TrapInit)();
1467	return bRet;
1468	}
1469
1470
1471	BS3_DECL(uint8_t) TMPL_NM(bs3CpuBasic2_RaiseXcpt1)(uint8_t bMode)
1472	{
1473	g_pszTestMode = TMPL_NM(g_szBs3ModeName);
1474	g_bTestMode = bMode;
1475	g_f16BitSys = BS3_MODE_IS_16BIT_SYS(TMPL_MODE);
1476
1477	#if !BS3_MODE_IS_RM_OR_V86(TMPL_MODE)
1478
1479	/*
1480	* Pass to common worker which is only compiled once per mode.
1481	*/
1482	bs3CpuBasic2_RaiseXcpt1Common(BS3_MODE_IS_16BIT_SYS(TMPL_MODE),
1483	MY_SYS_SEL_R0_CS,
1484	MY_SYS_SEL_R0_CS_CNF,
1485	MY_SYS_SEL_R0_SS,
1486	(PX86DESC)MyBs3Idt,
1487	BS3_MODE_IS_64BIT_SYS(TMPL_MODE) ? 1 : 0);
1488
1489	/*
1490	* Re-initialize the IDT.
1491	*/
1492	TMPL_NM(Bs3TrapInit)();
1493	return 0;
1494	#elif TMPL_MODE == BS3_MODE_RM
1495
1496	/*
1497	* Check
1498	*/
1499	/** @todo check */
1500	return BS3TESTDOMODE_SKIPPED;
1501
1502	#else
1503	return BS3TESTDOMODE_SKIPPED;
1504	#endif
1505	}
1506
1507
1508
1509
1510	BS3_DECL(uint8_t) TMPL_NM(bs3CpuBasic2_iret)(uint8_t bMode)
1511	{
1512	g_pszTestMode = TMPL_NM(g_szBs3ModeName);
1513	g_bTestMode = bMode;
1514	g_f16BitSys = BS3_MODE_IS_16BIT_SYS(TMPL_MODE);
1515
1516	return BS3TESTDOMODE_SKIPPED;
1517	}
1518
1519
1520	#endif /* BS3_INSTANTIATING_MODE */
1521

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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2-template.c@ 60311

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