PGMAllPool.cpp@ 20136

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1	/* $Id: PGMAllPool.cpp 20136 2009-05-29 08:12:12Z vboxsync $ */
2	/** @file
3	* PGM Shadow Page Pool.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.215389.xyz. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM_POOL
27	#include <VBox/pgm.h>
28	#include <VBox/mm.h>
29	#include <VBox/em.h>
30	#include <VBox/cpum.h>
31	#ifdef IN_RC
32	# include <VBox/patm.h>
33	#endif
34	#include "PGMInternal.h"
35	#include <VBox/vm.h>
36	#include <VBox/disopcode.h>
37	#include <VBox/hwacc_vmx.h>
38
39	#include <VBox/log.h>
40	#include <VBox/err.h>
41	#include <iprt/asm.h>
42	#include <iprt/string.h>
43
44
45	/*******************************************************************************
46	* Internal Functions *
47	*******************************************************************************/
48	__BEGIN_DECLS
49	static void pgmPoolFlushAllInt(PPGMPOOL pPool);
50	#ifdef PGMPOOL_WITH_USER_TRACKING
51	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind);
52	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind);
53	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
54	#endif
55	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
56	static void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint);
57	#endif
58	#ifdef PGMPOOL_WITH_CACHE
59	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
60	#endif
61	#ifdef PGMPOOL_WITH_MONITORING
62	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
63	#endif
64	#ifndef IN_RING3
65	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
66	#endif
67	#ifdef LOG_ENABLED
68	static const char *pgmPoolPoolKindToStr(uint8_t enmKind);
69	#endif
70
71	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
72	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
73	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
74	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
75	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
76	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
77
78	__END_DECLS
79
80
81	/**
82	* Checks if the specified page pool kind is for a 4MB or 2MB guest page.
83	*
84	* @returns true if it's the shadow of a 4MB or 2MB guest page, otherwise false.
85	* @param enmKind The page kind.
86	*/
87	DECLINLINE(bool) pgmPoolIsBigPage(PGMPOOLKIND enmKind)
88	{
89	switch (enmKind)
90	{
91	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
92	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
93	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
94	return true;
95	default:
96	return false;
97	}
98	}
99
100	/** @def PGMPOOL_PAGE_2_LOCKED_PTR
101	* Maps a pool page pool into the current context and lock it (RC only).
102	*
103	* @returns VBox status code.
104	* @param pVM The VM handle.
105	* @param pPage The pool page.
106	*
107	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
108	* small page window employeed by that function. Be careful.
109	* @remark There is no need to assert on the result.
110	*/
111	#if defined(IN_RC)
112	DECLINLINE(void *) PGMPOOL_PAGE_2_LOCKED_PTR(PVM pVM, PPGMPOOLPAGE pPage)
113	{
114	void *pv = pgmPoolMapPageInlined(&pVM->pgm.s, pPage);
115
116	/* Make sure the dynamic mapping will not be reused. */
117	if (pv)
118	PGMDynLockHCPage(pVM, (uint8_t *)pv);
119
120	return pv;
121	}
122	#else
123	# define PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage) PGMPOOL_PAGE_2_PTR(pVM, pPage)
124	#endif
125
126	/** @def PGMPOOL_UNLOCK_PTR
127	* Unlock a previously locked dynamic caching (RC only).
128	*
129	* @returns VBox status code.
130	* @param pVM The VM handle.
131	* @param pPage The pool page.
132	*
133	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
134	* small page window employeed by that function. Be careful.
135	* @remark There is no need to assert on the result.
136	*/
137	#if defined(IN_RC)
138	DECLINLINE(void) PGMPOOL_UNLOCK_PTR(PVM pVM, void *pvPage)
139	{
140	if (pvPage)
141	PGMDynUnlockHCPage(pVM, (uint8_t *)pvPage);
142	}
143	#else
144	# define PGMPOOL_UNLOCK_PTR(pVM, pPage) do {} while (0)
145	#endif
146
147
148	#ifdef PGMPOOL_WITH_MONITORING
149	/**
150	* Determin the size of a write instruction.
151	* @returns number of bytes written.
152	* @param pDis The disassembler state.
153	*/
154	static unsigned pgmPoolDisasWriteSize(PDISCPUSTATE pDis)
155	{
156	/*
157	* This is very crude and possibly wrong for some opcodes,
158	* but since it's not really supposed to be called we can
159	* probably live with that.
160	*/
161	return DISGetParamSize(pDis, &pDis->param1);
162	}
163
164
165	/**
166	* Flushes a chain of pages sharing the same access monitor.
167	*
168	* @returns VBox status code suitable for scheduling.
169	* @param pPool The pool.
170	* @param pPage A page in the chain.
171	*/
172	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
173	{
174	LogFlow(("pgmPoolMonitorChainFlush: Flush page %RGp type=%d\n", pPage->GCPhys, pPage->enmKind));
175
176	/*
177	* Find the list head.
178	*/
179	uint16_t idx = pPage->idx;
180	if (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
181	{
182	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
183	{
184	idx = pPage->iMonitoredPrev;
185	Assert(idx != pPage->idx);
186	pPage = &pPool->aPages[idx];
187	}
188	}
189
190	/*
191	* Iterate the list flushing each shadow page.
192	*/
193	int rc = VINF_SUCCESS;
194	for (;;)
195	{
196	idx = pPage->iMonitoredNext;
197	Assert(idx != pPage->idx);
198	if (pPage->idx >= PGMPOOL_IDX_FIRST)
199	{
200	int rc2 = pgmPoolFlushPage(pPool, pPage);
201	AssertRC(rc2);
202	}
203	/* next */
204	if (idx == NIL_PGMPOOL_IDX)
205	break;
206	pPage = &pPool->aPages[idx];
207	}
208	return rc;
209	}
210
211
212	/**
213	* Wrapper for getting the current context pointer to the entry being modified.
214	*
215	* @returns VBox status code suitable for scheduling.
216	* @param pVM VM Handle.
217	* @param pvDst Destination address
218	* @param pvSrc Source guest virtual address.
219	* @param GCPhysSrc The source guest physical address.
220	* @param cb Size of data to read
221	*/
222	DECLINLINE(int) pgmPoolPhysSimpleReadGCPhys(PVM pVM, void *pvDst, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvSrc, RTGCPHYS GCPhysSrc, size_t cb)
223	{
224	#if defined(IN_RING3)
225	memcpy(pvDst, (RTHCPTR)((uintptr_t)pvSrc & ~(RTHCUINTPTR)(cb - 1)), cb);
226	return VINF_SUCCESS;
227	#else
228	/* @todo in RC we could attempt to use the virtual address, although this can cause many faults (PAE Windows XP guest). */
229	return PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysSrc & ~(RTGCPHYS)(cb - 1), cb);
230	#endif
231	}
232
233	/**
234	* Process shadow entries before they are changed by the guest.
235	*
236	* For PT entries we will clear them. For PD entries, we'll simply check
237	* for mapping conflicts and set the SyncCR3 FF if found.
238	*
239	* @param pVCpu VMCPU handle
240	* @param pPool The pool.
241	* @param pPage The head page.
242	* @param GCPhysFault The guest physical fault address.
243	* @param uAddress In R0 and GC this is the guest context fault address (flat).
244	* In R3 this is the host context 'fault' address.
245	* @param pCpu The disassembler state for figuring out the write size.
246	* This need not be specified if the caller knows we won't do cross entry accesses.
247	*/
248	void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu)
249	{
250	Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
251	const unsigned off = GCPhysFault & PAGE_OFFSET_MASK;
252	const unsigned cbWrite = (pCpu) ? pgmPoolDisasWriteSize(pCpu) : 0;
253	PVM pVM = pPool->CTX_SUFF(pVM);
254
255	LogFlow(("pgmPoolMonitorChainChanging: %RGv phys=%RGp kind=%s cbWrite=%d\n", (RTGCPTR)pvAddress, GCPhysFault, pgmPoolPoolKindToStr(pPage->enmKind), cbWrite));
256	for (;;)
257	{
258	union
259	{
260	void *pv;
261	PX86PT pPT;
262	PX86PTPAE pPTPae;
263	PX86PD pPD;
264	PX86PDPAE pPDPae;
265	PX86PDPT pPDPT;
266	PX86PML4 pPML4;
267	} uShw;
268
269	uShw.pv = NULL;
270	switch (pPage->enmKind)
271	{
272	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
273	{
274	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
275	const unsigned iShw = off / sizeof(X86PTE);
276	LogFlow(("PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT iShw=%x\n", iShw));
277	if (uShw.pPT->a[iShw].n.u1Present)
278	{
279	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
280	X86PTE GstPte;
281
282	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
283	AssertRC(rc);
284	Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
285	pgmPoolTracDerefGCPhysHint(pPool, pPage,
286	uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK,
287	GstPte.u & X86_PTE_PG_MASK);
288	# endif
289	ASMAtomicWriteSize(&uShw.pPT->a[iShw], 0);
290	}
291	break;
292	}
293
294	/* page/2 sized */
295	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
296	{
297	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
298	if (!((off ^ pPage->GCPhys) & (PAGE_SIZE / 2)))
299	{
300	const unsigned iShw = (off / sizeof(X86PTE)) & (X86_PG_PAE_ENTRIES - 1);
301	LogFlow(("PGMPOOLKIND_PAE_PT_FOR_32BIT_PT iShw=%x\n", iShw));
302	if (uShw.pPTPae->a[iShw].n.u1Present)
303	{
304	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
305	X86PTE GstPte;
306	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
307	AssertRC(rc);
308
309	Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
310	pgmPoolTracDerefGCPhysHint(pPool, pPage,
311	uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
312	GstPte.u & X86_PTE_PG_MASK);
313	# endif
314	ASMAtomicWriteSize(&uShw.pPTPae->a[iShw], 0);
315	}
316	}
317	break;
318	}
319
320	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
321	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
322	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
323	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
324	{
325	unsigned iGst = off / sizeof(X86PDE);
326	unsigned iShwPdpt = iGst / 256;
327	unsigned iShw = (iGst % 256) * 2;
328	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
329
330	LogFlow(("pgmPoolMonitorChainChanging PAE for 32 bits: iGst=%x iShw=%x idx = %d page idx=%d\n", iGst, iShw, iShwPdpt, pPage->enmKind - PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD));
331	if (iShwPdpt == pPage->enmKind - (unsigned)PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD)
332	{
333	for (unsigned i = 0; i < 2; i++)
334	{
335	# ifndef IN_RING0
336	if ((uShw.pPDPae->a[iShw + i].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
337	{
338	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
339	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
340	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw=%#x!\n", iShwPdpt, iShw+i));
341	break;
342	}
343	else
344	# endif /* !IN_RING0 */
345	if (uShw.pPDPae->a[iShw+i].n.u1Present)
346	{
347	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw+i, uShw.pPDPae->a[iShw+i].u));
348	pgmPoolFree(pVM,
349	uShw.pPDPae->a[iShw+i].u & X86_PDE_PAE_PG_MASK,
350	pPage->idx,
351	iShw + i);
352	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw+i], 0);
353	}
354
355	/* paranoia / a bit assumptive. */
356	if ( pCpu
357	&& (off & 3)
358	&& (off & 3) + cbWrite > 4)
359	{
360	const unsigned iShw2 = iShw + 2 + i;
361	if (iShw2 < RT_ELEMENTS(uShw.pPDPae->a))
362	{
363	# ifndef IN_RING0
364	if ((uShw.pPDPae->a[iShw2].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
365	{
366	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
367	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
368	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw2=%#x!\n", iShwPdpt, iShw2));
369	break;
370	}
371	else
372	# endif /* !IN_RING0 */
373	if (uShw.pPDPae->a[iShw2].n.u1Present)
374	{
375	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
376	pgmPoolFree(pVM,
377	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
378	pPage->idx,
379	iShw2);
380	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
381	}
382	}
383	}
384	}
385	}
386	break;
387	}
388
389	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
390	{
391	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
392	const unsigned iShw = off / sizeof(X86PTEPAE);
393	if (uShw.pPTPae->a[iShw].n.u1Present)
394	{
395	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
396	X86PTEPAE GstPte;
397	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
398	AssertRC(rc);
399
400	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
401	pgmPoolTracDerefGCPhysHint(pPool, pPage,
402	uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
403	GstPte.u & X86_PTE_PAE_PG_MASK);
404	# endif
405	ASMAtomicWriteSize(&uShw.pPTPae->a[iShw].u, 0);
406	}
407
408	/* paranoia / a bit assumptive. */
409	if ( pCpu
410	&& (off & 7)
411	&& (off & 7) + cbWrite > sizeof(X86PTEPAE))
412	{
413	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTEPAE);
414	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPTPae->a));
415
416	if (uShw.pPTPae->a[iShw2].n.u1Present)
417	{
418	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
419	X86PTEPAE GstPte;
420	# ifdef IN_RING3
421	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, (RTHCPTR)((RTHCUINTPTR)pvAddress + sizeof(GstPte)), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
422	# else
423	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress + sizeof(GstPte), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
424	# endif
425	AssertRC(rc);
426	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
427	pgmPoolTracDerefGCPhysHint(pPool, pPage,
428	uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK,
429	GstPte.u & X86_PTE_PAE_PG_MASK);
430	# endif
431	ASMAtomicWriteSize(&uShw.pPTPae->a[iShw2].u ,0);
432	}
433	}
434	break;
435	}
436
437	case PGMPOOLKIND_32BIT_PD:
438	{
439	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
440	const unsigned iShw = off / sizeof(X86PTE); // ASSUMING 32-bit guest paging!
441
442	LogFlow(("pgmPoolMonitorChainChanging: PGMPOOLKIND_32BIT_PD %x\n", iShw));
443	# ifndef IN_RING0
444	if (uShw.pPD->a[iShw].u & PGM_PDFLAGS_MAPPING)
445	{
446	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
447	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
448	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
449	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
450	break;
451	}
452	# endif /* !IN_RING0 */
453	# ifndef IN_RING0
454	else
455	# endif /* !IN_RING0 */
456	{
457	if (uShw.pPD->a[iShw].n.u1Present)
458	{
459	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
460	pgmPoolFree(pVM,
461	uShw.pPD->a[iShw].u & X86_PDE_PAE_PG_MASK,
462	pPage->idx,
463	iShw);
464	ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
465	}
466	}
467	/* paranoia / a bit assumptive. */
468	if ( pCpu
469	&& (off & 3)
470	&& (off & 3) + cbWrite > sizeof(X86PTE))
471	{
472	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTE);
473	if ( iShw2 != iShw
474	&& iShw2 < RT_ELEMENTS(uShw.pPD->a))
475	{
476	# ifndef IN_RING0
477	if (uShw.pPD->a[iShw2].u & PGM_PDFLAGS_MAPPING)
478	{
479	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
480	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
481	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
482	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
483	break;
484	}
485	# endif /* !IN_RING0 */
486	# ifndef IN_RING0
487	else
488	# endif /* !IN_RING0 */
489	{
490	if (uShw.pPD->a[iShw2].n.u1Present)
491	{
492	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPD->a[iShw2].u));
493	pgmPoolFree(pVM,
494	uShw.pPD->a[iShw2].u & X86_PDE_PAE_PG_MASK,
495	pPage->idx,
496	iShw2);
497	ASMAtomicWriteSize(&uShw.pPD->a[iShw2].u, 0);
498	}
499	}
500	}
501	}
502	#if 0 /* useful when running PGMAssertCR3(), a bit too troublesome for general use (TLBs). */
503	if ( uShw.pPD->a[iShw].n.u1Present
504	&& !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
505	{
506	LogFlow(("pgmPoolMonitorChainChanging: iShw=%#x: %RX32 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
507	# ifdef IN_RC /* TLB load - we're pushing things a bit... */
508	ASMProbeReadByte(pvAddress);
509	# endif
510	pgmPoolFree(pVM, uShw.pPD->a[iShw].u & X86_PDE_PG_MASK, pPage->idx, iShw);
511	ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
512	}
513	#endif
514	break;
515	}
516
517	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
518	{
519	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
520	const unsigned iShw = off / sizeof(X86PDEPAE);
521	#ifndef IN_RING0
522	if (uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING)
523	{
524	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
525	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
526	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
527	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
528	break;
529	}
530	#endif /* !IN_RING0 */
531	/*
532	* Causes trouble when the guest uses a PDE to refer to the whole page table level
533	* structure. (Invalidate here; faults later on when it tries to change the page
534	* table entries -> recheck; probably only applies to the RC case.)
535	*/
536	# ifndef IN_RING0
537	else
538	# endif /* !IN_RING0 */
539	{
540	if (uShw.pPDPae->a[iShw].n.u1Present)
541	{
542	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
543	pgmPoolFree(pVM,
544	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
545	pPage->idx,
546	iShw);
547	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
548	}
549	}
550	/* paranoia / a bit assumptive. */
551	if ( pCpu
552	&& (off & 7)
553	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
554	{
555	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
556	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
557
558	#ifndef IN_RING0
559	if ( iShw2 != iShw
560	&& uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING)
561	{
562	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
563	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
564	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
565	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
566	break;
567	}
568	#endif /* !IN_RING0 */
569	# ifndef IN_RING0
570	else
571	# endif /* !IN_RING0 */
572	if (uShw.pPDPae->a[iShw2].n.u1Present)
573	{
574	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
575	pgmPoolFree(pVM,
576	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
577	pPage->idx,
578	iShw2);
579	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
580	}
581	}
582	break;
583	}
584
585	case PGMPOOLKIND_PAE_PDPT:
586	{
587	/*
588	* Hopefully this doesn't happen very often:
589	* - touching unused parts of the page
590	* - messing with the bits of pd pointers without changing the physical address
591	*/
592	/* PDPT roots are not page aligned; 32 byte only! */
593	const unsigned offPdpt = GCPhysFault - pPage->GCPhys;
594
595	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
596	const unsigned iShw = offPdpt / sizeof(X86PDPE);
597	if (iShw < X86_PG_PAE_PDPE_ENTRIES) /* don't use RT_ELEMENTS(uShw.pPDPT->a), because that's for long mode only */
598	{
599	# ifndef IN_RING0
600	if (uShw.pPDPT->a[iShw].u & PGM_PLXFLAGS_MAPPING)
601	{
602	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
603	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
604	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
605	LogFlow(("pgmPoolMonitorChainChanging: Detected pdpt conflict at iShw=%#x!\n", iShw));
606	break;
607	}
608	# endif /* !IN_RING0 */
609	# ifndef IN_RING0
610	else
611	# endif /* !IN_RING0 */
612	if (uShw.pPDPT->a[iShw].n.u1Present)
613	{
614	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
615	pgmPoolFree(pVM,
616	uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK,
617	pPage->idx,
618	iShw);
619	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
620	}
621
622	/* paranoia / a bit assumptive. */
623	if ( pCpu
624	&& (offPdpt & 7)
625	&& (offPdpt & 7) + cbWrite > sizeof(X86PDPE))
626	{
627	const unsigned iShw2 = (offPdpt + cbWrite - 1) / sizeof(X86PDPE);
628	if ( iShw2 != iShw
629	&& iShw2 < X86_PG_PAE_PDPE_ENTRIES)
630	{
631	# ifndef IN_RING0
632	if (uShw.pPDPT->a[iShw2].u & PGM_PLXFLAGS_MAPPING)
633	{
634	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
635	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
636	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
637	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
638	break;
639	}
640	# endif /* !IN_RING0 */
641	# ifndef IN_RING0
642	else
643	# endif /* !IN_RING0 */
644	if (uShw.pPDPT->a[iShw2].n.u1Present)
645	{
646	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
647	pgmPoolFree(pVM,
648	uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK,
649	pPage->idx,
650	iShw2);
651	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
652	}
653	}
654	}
655	}
656	break;
657	}
658
659	#ifndef IN_RC
660	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
661	{
662	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
663	const unsigned iShw = off / sizeof(X86PDEPAE);
664	Assert(!(uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING));
665	if (uShw.pPDPae->a[iShw].n.u1Present)
666	{
667	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
668	pgmPoolFree(pVM,
669	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
670	pPage->idx,
671	iShw);
672	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
673	}
674	/* paranoia / a bit assumptive. */
675	if ( pCpu
676	&& (off & 7)
677	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
678	{
679	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
680	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
681
682	Assert(!(uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING));
683	if (uShw.pPDPae->a[iShw2].n.u1Present)
684	{
685	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
686	pgmPoolFree(pVM,
687	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
688	pPage->idx,
689	iShw2);
690	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
691	}
692	}
693	break;
694	}
695
696	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
697	{
698	/*
699	* Hopefully this doesn't happen very often:
700	* - messing with the bits of pd pointers without changing the physical address
701	*/
702	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
703	{
704	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
705	const unsigned iShw = off / sizeof(X86PDPE);
706	if (uShw.pPDPT->a[iShw].n.u1Present)
707	{
708	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
709	pgmPoolFree(pVM, uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK, pPage->idx, iShw);
710	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
711	}
712	/* paranoia / a bit assumptive. */
713	if ( pCpu
714	&& (off & 7)
715	&& (off & 7) + cbWrite > sizeof(X86PDPE))
716	{
717	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDPE);
718	if (uShw.pPDPT->a[iShw2].n.u1Present)
719	{
720	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
721	pgmPoolFree(pVM, uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK, pPage->idx, iShw2);
722	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
723	}
724	}
725	}
726	break;
727	}
728
729	case PGMPOOLKIND_64BIT_PML4:
730	{
731	/*
732	* Hopefully this doesn't happen very often:
733	* - messing with the bits of pd pointers without changing the physical address
734	*/
735	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
736	{
737	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
738	const unsigned iShw = off / sizeof(X86PDPE);
739	if (uShw.pPML4->a[iShw].n.u1Present)
740	{
741	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPML4->a[iShw].u));
742	pgmPoolFree(pVM, uShw.pPML4->a[iShw].u & X86_PML4E_PG_MASK, pPage->idx, iShw);
743	ASMAtomicWriteSize(&uShw.pPML4->a[iShw].u, 0);
744	}
745	/* paranoia / a bit assumptive. */
746	if ( pCpu
747	&& (off & 7)
748	&& (off & 7) + cbWrite > sizeof(X86PDPE))
749	{
750	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PML4E);
751	if (uShw.pPML4->a[iShw2].n.u1Present)
752	{
753	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPML4->a[iShw2].u));
754	pgmPoolFree(pVM, uShw.pPML4->a[iShw2].u & X86_PML4E_PG_MASK, pPage->idx, iShw2);
755	ASMAtomicWriteSize(&uShw.pPML4->a[iShw2].u, 0);
756	}
757	}
758	}
759	break;
760	}
761	#endif /* IN_RING0 */
762
763	default:
764	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
765	}
766	PGMPOOL_UNLOCK_PTR(pVM, uShw.pv);
767
768	/* next */
769	if (pPage->iMonitoredNext == NIL_PGMPOOL_IDX)
770	return;
771	pPage = &pPool->aPages[pPage->iMonitoredNext];
772	}
773	}
774
775	# ifndef IN_RING3
776	/**
777	* Checks if a access could be a fork operation in progress.
778	*
779	* Meaning, that the guest is setuping up the parent process for Copy-On-Write.
780	*
781	* @returns true if it's likly that we're forking, otherwise false.
782	* @param pPool The pool.
783	* @param pCpu The disassembled instruction.
784	* @param offFault The access offset.
785	*/
786	DECLINLINE(bool) pgmPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE pCpu, unsigned offFault)
787	{
788	/*
789	* i386 linux is using btr to clear X86_PTE_RW.
790	* The functions involved are (2.6.16 source inspection):
791	* clear_bit
792	* ptep_set_wrprotect
793	* copy_one_pte
794	* copy_pte_range
795	* copy_pmd_range
796	* copy_pud_range
797	* copy_page_range
798	* dup_mmap
799	* dup_mm
800	* copy_mm
801	* copy_process
802	* do_fork
803	*/
804	if ( pCpu->pCurInstr->opcode == OP_BTR
805	&& !(offFault & 4)
806	/** @todo Validate that the bit index is X86_PTE_RW. */
807	)
808	{
809	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,Fork));
810	return true;
811	}
812	return false;
813	}
814
815
816	/**
817	* Determine whether the page is likely to have been reused.
818	*
819	* @returns true if we consider the page as being reused for a different purpose.
820	* @returns false if we consider it to still be a paging page.
821	* @param pVM VM Handle.
822	* @param pRegFrame Trap register frame.
823	* @param pCpu The disassembly info for the faulting instruction.
824	* @param pvFault The fault address.
825	*
826	* @remark The REP prefix check is left to the caller because of STOSD/W.
827	*/
828	DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR pvFault)
829	{
830	#ifndef IN_RC
831	/** @todo could make this general, faulting close to rsp should be safe reuse heuristic. */
832	if ( HWACCMHasPendingIrq(pVM)
833	&& (pRegFrame->rsp - pvFault) < 32)
834	{
835	/* Fault caused by stack writes while trying to inject an interrupt event. */
836	Log(("pgmPoolMonitorIsReused: reused %RGv for interrupt stack (rsp=%RGv).\n", pvFault, pRegFrame->rsp));
837	return true;
838	}
839	#else
840	NOREF(pVM); NOREF(pvFault);
841	#endif
842
843	switch (pCpu->pCurInstr->opcode)
844	{
845	/* call implies the actual push of the return address faulted */
846	case OP_CALL:
847	Log4(("pgmPoolMonitorIsReused: CALL\n"));
848	return true;
849	case OP_PUSH:
850	Log4(("pgmPoolMonitorIsReused: PUSH\n"));
851	return true;
852	case OP_PUSHF:
853	Log4(("pgmPoolMonitorIsReused: PUSHF\n"));
854	return true;
855	case OP_PUSHA:
856	Log4(("pgmPoolMonitorIsReused: PUSHA\n"));
857	return true;
858	case OP_FXSAVE:
859	Log4(("pgmPoolMonitorIsReused: FXSAVE\n"));
860	return true;
861	case OP_MOVNTI: /* solaris - block_zero_no_xmm */
862	Log4(("pgmPoolMonitorIsReused: MOVNTI\n"));
863	return true;
864	case OP_MOVNTDQ: /* solaris - hwblkclr & hwblkpagecopy */
865	Log4(("pgmPoolMonitorIsReused: MOVNTDQ\n"));
866	return true;
867	case OP_MOVSWD:
868	case OP_STOSWD:
869	if ( pCpu->prefix == (PREFIX_REP\|PREFIX_REX)
870	&& pRegFrame->rcx >= 0x40
871	)
872	{
873	Assert(pCpu->mode == CPUMODE_64BIT);
874
875	Log(("pgmPoolMonitorIsReused: OP_STOSQ\n"));
876	return true;
877	}
878	return false;
879	}
880	if ( (pCpu->param1.flags & USE_REG_GEN32)
881	&& (pCpu->param1.base.reg_gen == USE_REG_ESP))
882	{
883	Log4(("pgmPoolMonitorIsReused: ESP\n"));
884	return true;
885	}
886
887	return false;
888	}
889
890
891	/**
892	* Flushes the page being accessed.
893	*
894	* @returns VBox status code suitable for scheduling.
895	* @param pVM The VM handle.
896	* @param pVCpu The VMCPU handle.
897	* @param pPool The pool.
898	* @param pPage The pool page (head).
899	* @param pCpu The disassembly of the write instruction.
900	* @param pRegFrame The trap register frame.
901	* @param GCPhysFault The fault address as guest physical address.
902	* @param pvFault The fault address.
903	*/
904	static int pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
905	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
906	{
907	/*
908	* First, do the flushing.
909	*/
910	int rc = pgmPoolMonitorChainFlush(pPool, pPage);
911
912	/*
913	* Emulate the instruction (xp/w2k problem, requires pc/cr2/sp detection).
914	*/
915	uint32_t cbWritten;
916	int rc2 = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, pvFault, &cbWritten);
917	if (RT_SUCCESS(rc2))
918	pRegFrame->rip += pCpu->opsize;
919	else if (rc2 == VERR_EM_INTERPRETER)
920	{
921	#ifdef IN_RC
922	if (PATMIsPatchGCAddr(pVM, (RTRCPTR)pRegFrame->eip))
923	{
924	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for patch code %04x:%RGv, ignoring.\n",
925	pRegFrame->cs, (RTGCPTR)pRegFrame->eip));
926	rc = VINF_SUCCESS;
927	STAM_COUNTER_INC(&pPool->StatMonitorRZIntrFailPatch2);
928	}
929	else
930	#endif
931	{
932	rc = VINF_EM_RAW_EMULATE_INSTR;
933	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
934	}
935	}
936	else
937	rc = rc2;
938
939	/* See use in pgmPoolAccessHandlerSimple(). */
940	PGM_INVL_VCPU_TLBS(pVCpu);
941
942	LogFlow(("pgmPoolAccessHandlerPT: returns %Rrc (flushed)\n", rc));
943	return rc;
944
945	}
946
947
948	/**
949	* Handles the STOSD write accesses.
950	*
951	* @returns VBox status code suitable for scheduling.
952	* @param pVM The VM handle.
953	* @param pPool The pool.
954	* @param pPage The pool page (head).
955	* @param pCpu The disassembly of the write instruction.
956	* @param pRegFrame The trap register frame.
957	* @param GCPhysFault The fault address as guest physical address.
958	* @param pvFault The fault address.
959	*/
960	DECLINLINE(int) pgmPoolAccessHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
961	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
962	{
963	Assert(pCpu->mode == CPUMODE_32BIT);
964
965	Log3(("pgmPoolAccessHandlerSTOSD\n"));
966
967	/*
968	* Increment the modification counter and insert it into the list
969	* of modified pages the first time.
970	*/
971	if (!pPage->cModifications++)
972	pgmPoolMonitorModifiedInsert(pPool, pPage);
973
974	/*
975	* Execute REP STOSD.
976	*
977	* This ASSUMES that we're not invoked by Trap0e on in a out-of-sync
978	* write situation, meaning that it's safe to write here.
979	*/
980	PVMCPU pVCpu = VMMGetCpu(pPool->CTX_SUFF(pVM));
981	RTGCUINTPTR pu32 = (RTGCUINTPTR)pvFault;
982	while (pRegFrame->ecx)
983	{
984	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
985	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
986	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
987	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
988	#else
989	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
990	#endif
991	#ifdef IN_RC
992	(uint32_t )pu32 = pRegFrame->eax;
993	#else
994	PGMPhysSimpleWriteGCPhys(pVM, GCPhysFault, &pRegFrame->eax, 4);
995	#endif
996	pu32 += 4;
997	GCPhysFault += 4;
998	pRegFrame->edi += 4;
999	pRegFrame->ecx--;
1000	}
1001	pRegFrame->rip += pCpu->opsize;
1002
1003	#ifdef IN_RC
1004	/* See use in pgmPoolAccessHandlerSimple(). */
1005	PGM_INVL_VCPU_TLBS(pVCpu);
1006	#endif
1007
1008	LogFlow(("pgmPoolAccessHandlerSTOSD: returns\n"));
1009	return VINF_SUCCESS;
1010	}
1011
1012
1013	/**
1014	* Handles the simple write accesses.
1015	*
1016	* @returns VBox status code suitable for scheduling.
1017	* @param pVM The VM handle.
1018	* @param pVCpu The VMCPU handle.
1019	* @param pPool The pool.
1020	* @param pPage The pool page (head).
1021	* @param pCpu The disassembly of the write instruction.
1022	* @param pRegFrame The trap register frame.
1023	* @param GCPhysFault The fault address as guest physical address.
1024	* @param pvFault The fault address.
1025	*/
1026	DECLINLINE(int) pgmPoolAccessHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
1027	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
1028	{
1029	Log3(("pgmPoolAccessHandlerSimple\n"));
1030	/*
1031	* Increment the modification counter and insert it into the list
1032	* of modified pages the first time.
1033	*/
1034	if (!pPage->cModifications++)
1035	pgmPoolMonitorModifiedInsert(pPool, pPage);
1036
1037	/*
1038	* Clear all the pages. ASSUMES that pvFault is readable.
1039	*/
1040	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1041	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
1042	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pCpu);
1043	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
1044	#else
1045	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pCpu);
1046	#endif
1047
1048	/*
1049	* Interpret the instruction.
1050	*/
1051	uint32_t cb;
1052	int rc = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, pvFault, &cb);
1053	if (RT_SUCCESS(rc))
1054	pRegFrame->rip += pCpu->opsize;
1055	else if (rc == VERR_EM_INTERPRETER)
1056	{
1057	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n",
1058	pRegFrame->cs, (RTGCPTR)pRegFrame->rip, pCpu->pCurInstr->opcode));
1059	rc = VINF_EM_RAW_EMULATE_INSTR;
1060	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
1061	}
1062
1063	#ifdef IN_RC
1064	/*
1065	* Quick hack, with logging enabled we're getting stale
1066	* code TLBs but no data TLB for EIP and crash in EMInterpretDisasOne.
1067	* Flushing here is BAD and expensive, I think EMInterpretDisasOne will
1068	* have to be fixed to support this. But that'll have to wait till next week.
1069	*
1070	* An alternative is to keep track of the changed PTEs together with the
1071	* GCPhys from the guest PT. This may proove expensive though.
1072	*
1073	* At the moment, it's VITAL that it's done AFTER the instruction interpreting
1074	* because we need the stale TLBs in some cases (XP boot). This MUST be fixed properly!
1075	*/
1076	PGM_INVL_VCPU_TLBS(pVCpu);
1077	#endif
1078
1079	LogFlow(("pgmPoolAccessHandlerSimple: returns %Rrc cb=%d\n", rc, cb));
1080	return rc;
1081	}
1082
1083	/**
1084	* \#PF Handler callback for PT write accesses.
1085	*
1086	* @returns VBox status code (appropriate for GC return).
1087	* @param pVM VM Handle.
1088	* @param uErrorCode CPU Error code.
1089	* @param pRegFrame Trap register frame.
1090	* NULL on DMA and other non CPU access.
1091	* @param pvFault The fault address (cr2).
1092	* @param GCPhysFault The GC physical address corresponding to pvFault.
1093	* @param pvUser User argument.
1094	*/
1095	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1096	{
1097	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1098	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1099	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)pvUser;
1100	PVMCPU pVCpu = VMMGetCpu(pVM);
1101
1102	LogFlow(("pgmPoolAccessHandler: pvFault=%RGv pPage=%p:{.idx=%d} GCPhysFault=%RGp\n", pvFault, pPage, pPage->idx, GCPhysFault));
1103
1104	/*
1105	* We should ALWAYS have the list head as user parameter. This
1106	* is because we use that page to record the changes.
1107	*/
1108	Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1109
1110	/*
1111	* Disassemble the faulting instruction.
1112	*/
1113	DISCPUSTATE Cpu;
1114	int rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, &Cpu, NULL);
1115	AssertRCReturn(rc, rc);
1116
1117	pgmLock(pVM);
1118	if (PHYS_PAGE_ADDRESS(GCPhysFault) != PHYS_PAGE_ADDRESS(pPage->GCPhys))
1119	{
1120	/* Pool page changed while we were waiting for the lock; ignore. */
1121	Log(("CPU%d: pgmPoolAccessHandler pgm pool page for %RGp changed (to %RGp) while waiting!\n", pVCpu->idCpu, PHYS_PAGE_ADDRESS(GCPhysFault), PHYS_PAGE_ADDRESS(pPage->GCPhys)));
1122	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1123	pgmUnlock(pVM);
1124	return VINF_SUCCESS;
1125	}
1126
1127	/*
1128	* Check if it's worth dealing with.
1129	*/
1130	bool fReused = false;
1131	if ( ( pPage->cModifications < 48 /** @todo #define / /* @todo need to check that it's not mapping EIP. / /* @todo adjust this! */
1132	\|\| pgmPoolIsPageLocked(&pVM->pgm.s, pPage)
1133	)
1134	&& !(fReused = pgmPoolMonitorIsReused(pVM, pRegFrame, &Cpu, pvFault))
1135	&& !pgmPoolMonitorIsForking(pPool, &Cpu, GCPhysFault & PAGE_OFFSET_MASK))
1136	{
1137	/*
1138	* Simple instructions, no REP prefix.
1139	*/
1140	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1141	{
1142	rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1143	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1144	pgmUnlock(pVM);
1145	return rc;
1146	}
1147
1148	/*
1149	* Windows is frequently doing small memset() operations (netio test 4k+).
1150	* We have to deal with these or we'll kill the cache and performance.
1151	*/
1152	if ( Cpu.pCurInstr->opcode == OP_STOSWD
1153	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0
1154	&& pRegFrame->ecx <= 0x20
1155	&& pRegFrame->ecx * 4 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1156	&& !((uintptr_t)pvFault & 3)
1157	&& (pRegFrame->eax == 0 \|\| pRegFrame->eax == 0x80) /* the two values observed. */
1158	&& Cpu.mode == CPUMODE_32BIT
1159	&& Cpu.opmode == CPUMODE_32BIT
1160	&& Cpu.addrmode == CPUMODE_32BIT
1161	&& Cpu.prefix == PREFIX_REP
1162	&& !pRegFrame->eflags.Bits.u1DF
1163	)
1164	{
1165	rc = pgmPoolAccessHandlerSTOSD(pVM, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1166	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,RepStosd), a);
1167	pgmUnlock(pVM);
1168	return rc;
1169	}
1170
1171	/* REP prefix, don't bother. */
1172	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,RepPrefix));
1173	Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n",
1174	pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, Cpu.pCurInstr->opcode, Cpu.prefix));
1175	}
1176
1177	/*
1178	* Not worth it, so flush it.
1179	*
1180	* If we considered it to be reused, don't go back to ring-3
1181	* to emulate failed instructions since we usually cannot
1182	* interpret then. This may be a bit risky, in which case
1183	* the reuse detection must be fixed.
1184	*/
1185	rc = pgmPoolAccessHandlerFlush(pVM, pVCpu, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1186	if (rc == VINF_EM_RAW_EMULATE_INSTR && fReused)
1187	rc = VINF_SUCCESS;
1188	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,FlushPage), a);
1189	pgmUnlock(pVM);
1190	return rc;
1191	}
1192
1193	# endif /* !IN_RING3 */
1194	#endif /* PGMPOOL_WITH_MONITORING */
1195
1196	#ifdef PGMPOOL_WITH_CACHE
1197
1198	/**
1199	* Inserts a page into the GCPhys hash table.
1200	*
1201	* @param pPool The pool.
1202	* @param pPage The page.
1203	*/
1204	DECLINLINE(void) pgmPoolHashInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1205	{
1206	Log3(("pgmPoolHashInsert: %RGp\n", pPage->GCPhys));
1207	Assert(pPage->GCPhys != NIL_RTGCPHYS); Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1208	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1209	pPage->iNext = pPool->aiHash[iHash];
1210	pPool->aiHash[iHash] = pPage->idx;
1211	}
1212
1213
1214	/**
1215	* Removes a page from the GCPhys hash table.
1216	*
1217	* @param pPool The pool.
1218	* @param pPage The page.
1219	*/
1220	DECLINLINE(void) pgmPoolHashRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1221	{
1222	Log3(("pgmPoolHashRemove: %RGp\n", pPage->GCPhys));
1223	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1224	if (pPool->aiHash[iHash] == pPage->idx)
1225	pPool->aiHash[iHash] = pPage->iNext;
1226	else
1227	{
1228	uint16_t iPrev = pPool->aiHash[iHash];
1229	for (;;)
1230	{
1231	const int16_t i = pPool->aPages[iPrev].iNext;
1232	if (i == pPage->idx)
1233	{
1234	pPool->aPages[iPrev].iNext = pPage->iNext;
1235	break;
1236	}
1237	if (i == NIL_PGMPOOL_IDX)
1238	{
1239	AssertReleaseMsgFailed(("GCPhys=%RGp idx=%#x\n", pPage->GCPhys, pPage->idx));
1240	break;
1241	}
1242	iPrev = i;
1243	}
1244	}
1245	pPage->iNext = NIL_PGMPOOL_IDX;
1246	}
1247
1248
1249	/**
1250	* Frees up one cache page.
1251	*
1252	* @returns VBox status code.
1253	* @retval VINF_SUCCESS on success.
1254	* @param pPool The pool.
1255	* @param iUser The user index.
1256	*/
1257	static int pgmPoolCacheFreeOne(PPGMPOOL pPool, uint16_t iUser)
1258	{
1259	#ifndef IN_RC
1260	const PVM pVM = pPool->CTX_SUFF(pVM);
1261	#endif
1262	Assert(pPool->iAgeHead != pPool->iAgeTail); /* We shouldn't be here if there < 2 cached entries! */
1263	STAM_COUNTER_INC(&pPool->StatCacheFreeUpOne);
1264
1265	/*
1266	* Select one page from the tail of the age list.
1267	*/
1268	PPGMPOOLPAGE pPage;
1269	for (unsigned iLoop = 0; ; iLoop++)
1270	{
1271	uint16_t iToFree = pPool->iAgeTail;
1272	if (iToFree == iUser)
1273	iToFree = pPool->aPages[iToFree].iAgePrev;
1274	/* This is the alternative to the SyncCR3 pgmPoolCacheUsed calls.
1275	if (pPool->aPages[iToFree].iUserHead != NIL_PGMPOOL_USER_INDEX)
1276	{
1277	uint16_t i = pPool->aPages[iToFree].iAgePrev;
1278	for (unsigned j = 0; j < 10 && i != NIL_PGMPOOL_USER_INDEX; j++, i = pPool->aPages[i].iAgePrev)
1279	{
1280	if (pPool->aPages[iToFree].iUserHead == NIL_PGMPOOL_USER_INDEX)
1281	continue;
1282	iToFree = i;
1283	break;
1284	}
1285	}
1286	*/
1287	Assert(iToFree != iUser);
1288	AssertRelease(iToFree != NIL_PGMPOOL_IDX);
1289	pPage = &pPool->aPages[iToFree];
1290
1291	/*
1292	* Reject any attempts at flushing the currently active shadow CR3 mapping.
1293	* Call pgmPoolCacheUsed to move the page to the head of the age list.
1294	*/
1295	if (!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage))
1296	break;
1297	LogFlow(("pgmPoolCacheFreeOne: refuse CR3 mapping\n"));
1298	pgmPoolCacheUsed(pPool, pPage);
1299	AssertLogRelReturn(iLoop < 8192, VERR_INTERNAL_ERROR);
1300	}
1301
1302	/*
1303	* Found a usable page, flush it and return.
1304	*/
1305	int rc = pgmPoolFlushPage(pPool, pPage);
1306	/* This flush was initiated by us and not the guest, so explicitly flush the TLB. */
1307	if (rc == VINF_SUCCESS)
1308	PGM_INVL_ALL_VCPU_TLBS(pVM);
1309	return rc;
1310	}
1311
1312
1313	/**
1314	* Checks if a kind mismatch is really a page being reused
1315	* or if it's just normal remappings.
1316	*
1317	* @returns true if reused and the cached page (enmKind1) should be flushed
1318	* @returns false if not reused.
1319	* @param enmKind1 The kind of the cached page.
1320	* @param enmKind2 The kind of the requested page.
1321	*/
1322	static bool pgmPoolCacheReusedByKind(PGMPOOLKIND enmKind1, PGMPOOLKIND enmKind2)
1323	{
1324	switch (enmKind1)
1325	{
1326	/*
1327	* Never reuse them. There is no remapping in non-paging mode.
1328	*/
1329	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1330	case PGMPOOLKIND_32BIT_PD_PHYS:
1331	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1332	case PGMPOOLKIND_PAE_PD_PHYS:
1333	case PGMPOOLKIND_PAE_PDPT_PHYS:
1334	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1335	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1336	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1337	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1338	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1339	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT: /* never reuse them for other types */
1340	return false;
1341
1342	/*
1343	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1344	*/
1345	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1346	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1347	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1348	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1349	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1350	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1351	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1352	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1353	case PGMPOOLKIND_32BIT_PD:
1354	case PGMPOOLKIND_PAE_PDPT:
1355	switch (enmKind2)
1356	{
1357	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1358	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1359	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1360	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1361	case PGMPOOLKIND_64BIT_PML4:
1362	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1363	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1364	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1365	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1366	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1367	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1368	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1369	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1370	return true;
1371	default:
1372	return false;
1373	}
1374
1375	/*
1376	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1377	*/
1378	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1379	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1380	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1381	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1382	case PGMPOOLKIND_64BIT_PML4:
1383	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1384	switch (enmKind2)
1385	{
1386	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1387	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1388	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1389	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1390	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1391	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1392	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1393	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1394	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1395	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1396	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1397	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1398	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1399	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1400	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1401	return true;
1402	default:
1403	return false;
1404	}
1405
1406	/*
1407	* These cannot be flushed, and it's common to reuse the PDs as PTs.
1408	*/
1409	case PGMPOOLKIND_ROOT_NESTED:
1410	return false;
1411
1412	default:
1413	AssertFatalMsgFailed(("enmKind1=%d\n", enmKind1));
1414	}
1415	}
1416
1417
1418	/**
1419	* Attempts to satisfy a pgmPoolAlloc request from the cache.
1420	*
1421	* @returns VBox status code.
1422	* @retval VINF_PGM_CACHED_PAGE on success.
1423	* @retval VERR_FILE_NOT_FOUND if not found.
1424	* @param pPool The pool.
1425	* @param GCPhys The GC physical address of the page we're gonna shadow.
1426	* @param enmKind The kind of mapping.
1427	* @param enmAccess Access type for the mapping (only relevant for big pages)
1428	* @param iUser The shadow page pool index of the user table.
1429	* @param iUserTable The index into the user table (shadowed).
1430	* @param ppPage Where to store the pointer to the page.
1431	*/
1432	static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
1433	{
1434	#ifndef IN_RC
1435	const PVM pVM = pPool->CTX_SUFF(pVM);
1436	#endif
1437	/*
1438	* Look up the GCPhys in the hash.
1439	*/
1440	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
1441	Log3(("pgmPoolCacheAlloc: %RGp kind %s iUser=%x iUserTable=%x SLOT=%d\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable, i));
1442	if (i != NIL_PGMPOOL_IDX)
1443	{
1444	do
1445	{
1446	PPGMPOOLPAGE pPage = &pPool->aPages[i];
1447	Log4(("pgmPoolCacheAlloc: slot %d found page %RGp\n", i, pPage->GCPhys));
1448	if (pPage->GCPhys == GCPhys)
1449	{
1450	if ( (PGMPOOLKIND)pPage->enmKind == enmKind
1451	&& (PGMPOOLACCESS)pPage->enmAccess == enmAccess)
1452	{
1453	/* Put it at the start of the use list to make sure pgmPoolTrackAddUser
1454	* doesn't flush it in case there are no more free use records.
1455	*/
1456	pgmPoolCacheUsed(pPool, pPage);
1457
1458	int rc = pgmPoolTrackAddUser(pPool, pPage, iUser, iUserTable);
1459	if (RT_SUCCESS(rc))
1460	{
1461	Assert((PGMPOOLKIND)pPage->enmKind == enmKind);
1462	*ppPage = pPage;
1463	STAM_COUNTER_INC(&pPool->StatCacheHits);
1464	return VINF_PGM_CACHED_PAGE;
1465	}
1466	return rc;
1467	}
1468
1469	if ((PGMPOOLKIND)pPage->enmKind != enmKind)
1470	{
1471	/*
1472	* The kind is different. In some cases we should now flush the page
1473	* as it has been reused, but in most cases this is normal remapping
1474	* of PDs as PT or big pages using the GCPhys field in a slightly
1475	* different way than the other kinds.
1476	*/
1477	if (pgmPoolCacheReusedByKind((PGMPOOLKIND)pPage->enmKind, enmKind))
1478	{
1479	STAM_COUNTER_INC(&pPool->StatCacheKindMismatches);
1480	pgmPoolFlushPage(pPool, pPage);
1481	PGM_INVL_VCPU_TLBS(VMMGetCpu(pVM)); /* see PT handler. */
1482	break;
1483	}
1484	}
1485	}
1486
1487	/* next */
1488	i = pPage->iNext;
1489	} while (i != NIL_PGMPOOL_IDX);
1490	}
1491
1492	Log3(("pgmPoolCacheAlloc: Missed GCPhys=%RGp enmKind=%s\n", GCPhys, pgmPoolPoolKindToStr(enmKind)));
1493	STAM_COUNTER_INC(&pPool->StatCacheMisses);
1494	return VERR_FILE_NOT_FOUND;
1495	}
1496
1497
1498	/**
1499	* Inserts a page into the cache.
1500	*
1501	* @param pPool The pool.
1502	* @param pPage The cached page.
1503	* @param fCanBeCached Set if the page is fit for caching from the caller's point of view.
1504	*/
1505	static void pgmPoolCacheInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fCanBeCached)
1506	{
1507	/*
1508	* Insert into the GCPhys hash if the page is fit for that.
1509	*/
1510	Assert(!pPage->fCached);
1511	if (fCanBeCached)
1512	{
1513	pPage->fCached = true;
1514	pgmPoolHashInsert(pPool, pPage);
1515	Log3(("pgmPoolCacheInsert: Caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
1516	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
1517	STAM_COUNTER_INC(&pPool->StatCacheCacheable);
1518	}
1519	else
1520	{
1521	Log3(("pgmPoolCacheInsert: Not caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
1522	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
1523	STAM_COUNTER_INC(&pPool->StatCacheUncacheable);
1524	}
1525
1526	/*
1527	* Insert at the head of the age list.
1528	*/
1529	pPage->iAgePrev = NIL_PGMPOOL_IDX;
1530	pPage->iAgeNext = pPool->iAgeHead;
1531	if (pPool->iAgeHead != NIL_PGMPOOL_IDX)
1532	pPool->aPages[pPool->iAgeHead].iAgePrev = pPage->idx;
1533	else
1534	pPool->iAgeTail = pPage->idx;
1535	pPool->iAgeHead = pPage->idx;
1536	}
1537
1538
1539	/**
1540	* Flushes a cached page.
1541	*
1542	* @param pPool The pool.
1543	* @param pPage The cached page.
1544	*/
1545	static void pgmPoolCacheFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1546	{
1547	Log3(("pgmPoolCacheFlushPage: %RGp\n", pPage->GCPhys));
1548
1549	/*
1550	* Remove the page from the hash.
1551	*/
1552	if (pPage->fCached)
1553	{
1554	pPage->fCached = false;
1555	pgmPoolHashRemove(pPool, pPage);
1556	}
1557	else
1558	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1559
1560	/*
1561	* Remove it from the age list.
1562	*/
1563	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
1564	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
1565	else
1566	pPool->iAgeTail = pPage->iAgePrev;
1567	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
1568	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
1569	else
1570	pPool->iAgeHead = pPage->iAgeNext;
1571	pPage->iAgeNext = NIL_PGMPOOL_IDX;
1572	pPage->iAgePrev = NIL_PGMPOOL_IDX;
1573	}
1574
1575	#endif /* PGMPOOL_WITH_CACHE */
1576	#ifdef PGMPOOL_WITH_MONITORING
1577
1578	/**
1579	* Looks for pages sharing the monitor.
1580	*
1581	* @returns Pointer to the head page.
1582	* @returns NULL if not found.
1583	* @param pPool The Pool
1584	* @param pNewPage The page which is going to be monitored.
1585	*/
1586	static PPGMPOOLPAGE pgmPoolMonitorGetPageByGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pNewPage)
1587	{
1588	#ifdef PGMPOOL_WITH_CACHE
1589	/*
1590	* Look up the GCPhys in the hash.
1591	*/
1592	RTGCPHYS GCPhys = pNewPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1593	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
1594	if (i == NIL_PGMPOOL_IDX)
1595	return NULL;
1596	do
1597	{
1598	PPGMPOOLPAGE pPage = &pPool->aPages[i];
1599	if ( pPage->GCPhys - GCPhys < PAGE_SIZE
1600	&& pPage != pNewPage)
1601	{
1602	switch (pPage->enmKind)
1603	{
1604	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1605	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1606	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1607	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1608	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1609	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1610	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1611	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1612	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1613	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1614	case PGMPOOLKIND_64BIT_PML4:
1615	case PGMPOOLKIND_32BIT_PD:
1616	case PGMPOOLKIND_PAE_PDPT:
1617	{
1618	/* find the head */
1619	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1620	{
1621	Assert(pPage->iMonitoredPrev != pPage->idx);
1622	pPage = &pPool->aPages[pPage->iMonitoredPrev];
1623	}
1624	return pPage;
1625	}
1626
1627	/* ignore, no monitoring. */
1628	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1629	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1630	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1631	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1632	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1633	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1634	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1635	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1636	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1637	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1638	case PGMPOOLKIND_ROOT_NESTED:
1639	case PGMPOOLKIND_PAE_PD_PHYS:
1640	case PGMPOOLKIND_PAE_PDPT_PHYS:
1641	case PGMPOOLKIND_32BIT_PD_PHYS:
1642	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
1643	break;
1644	default:
1645	AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
1646	}
1647	}
1648
1649	/* next */
1650	i = pPage->iNext;
1651	} while (i != NIL_PGMPOOL_IDX);
1652	#endif
1653	return NULL;
1654	}
1655
1656
1657	/**
1658	* Enabled write monitoring of a guest page.
1659	*
1660	* @returns VBox status code.
1661	* @retval VINF_SUCCESS on success.
1662	* @param pPool The pool.
1663	* @param pPage The cached page.
1664	*/
1665	static int pgmPoolMonitorInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1666	{
1667	LogFlow(("pgmPoolMonitorInsert %RGp\n", pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1)));
1668
1669	/*
1670	* Filter out the relevant kinds.
1671	*/
1672	switch (pPage->enmKind)
1673	{
1674	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1675	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1676	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1677	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1678	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1679	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1680	case PGMPOOLKIND_64BIT_PML4:
1681	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1682	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1683	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1684	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1685	case PGMPOOLKIND_32BIT_PD:
1686	case PGMPOOLKIND_PAE_PDPT:
1687	break;
1688
1689	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1690	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1691	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1692	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1693	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1694	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1695	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1696	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1697	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1698	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1699	case PGMPOOLKIND_ROOT_NESTED:
1700	/* Nothing to monitor here. */
1701	return VINF_SUCCESS;
1702
1703	case PGMPOOLKIND_32BIT_PD_PHYS:
1704	case PGMPOOLKIND_PAE_PDPT_PHYS:
1705	case PGMPOOLKIND_PAE_PD_PHYS:
1706	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
1707	/* Nothing to monitor here. */
1708	return VINF_SUCCESS;
1709	#ifdef PGMPOOL_WITH_MIXED_PT_CR3
1710	break;
1711	#else
1712	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1713	#endif
1714	default:
1715	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
1716	}
1717
1718	/*
1719	* Install handler.
1720	*/
1721	int rc;
1722	PPGMPOOLPAGE pPageHead = pgmPoolMonitorGetPageByGCPhys(pPool, pPage);
1723	if (pPageHead)
1724	{
1725	Assert(pPageHead != pPage); Assert(pPageHead->iMonitoredNext != pPage->idx);
1726	Assert(pPageHead->iMonitoredPrev != pPage->idx);
1727	pPage->iMonitoredPrev = pPageHead->idx;
1728	pPage->iMonitoredNext = pPageHead->iMonitoredNext;
1729	if (pPageHead->iMonitoredNext != NIL_PGMPOOL_IDX)
1730	pPool->aPages[pPageHead->iMonitoredNext].iMonitoredPrev = pPage->idx;
1731	pPageHead->iMonitoredNext = pPage->idx;
1732	rc = VINF_SUCCESS;
1733	}
1734	else
1735	{
1736	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX); Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1737	PVM pVM = pPool->CTX_SUFF(pVM);
1738	const RTGCPHYS GCPhysPage = pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1739	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
1740	GCPhysPage, GCPhysPage + (PAGE_SIZE - 1),
1741	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
1742	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
1743	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
1744	pPool->pszAccessHandler);
1745	/** @todo we should probably deal with out-of-memory conditions here, but for now increasing
1746	* the heap size should suffice. */
1747	AssertFatalMsgRC(rc, ("PGMHandlerPhysicalRegisterEx %RGp failed with %Rrc\n", GCPhysPage, rc));
1748	Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_ISSET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3));
1749	}
1750	pPage->fMonitored = true;
1751	return rc;
1752	}
1753
1754
1755	/**
1756	* Disables write monitoring of a guest page.
1757	*
1758	* @returns VBox status code.
1759	* @retval VINF_SUCCESS on success.
1760	* @param pPool The pool.
1761	* @param pPage The cached page.
1762	*/
1763	static int pgmPoolMonitorFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1764	{
1765	/*
1766	* Filter out the relevant kinds.
1767	*/
1768	switch (pPage->enmKind)
1769	{
1770	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1771	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1772	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1773	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1774	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1775	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1776	case PGMPOOLKIND_64BIT_PML4:
1777	case PGMPOOLKIND_32BIT_PD:
1778	case PGMPOOLKIND_PAE_PDPT:
1779	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1780	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1781	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1782	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1783	break;
1784
1785	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1786	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1787	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1788	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1789	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1790	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1791	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1792	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1793	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1794	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1795	case PGMPOOLKIND_ROOT_NESTED:
1796	case PGMPOOLKIND_PAE_PD_PHYS:
1797	case PGMPOOLKIND_PAE_PDPT_PHYS:
1798	case PGMPOOLKIND_32BIT_PD_PHYS:
1799	/* Nothing to monitor here. */
1800	return VINF_SUCCESS;
1801
1802	#ifdef PGMPOOL_WITH_MIXED_PT_CR3
1803	break;
1804	#endif
1805	default:
1806	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
1807	}
1808
1809	/*
1810	* Remove the page from the monitored list or uninstall it if last.
1811	*/
1812	const PVM pVM = pPool->CTX_SUFF(pVM);
1813	int rc;
1814	if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
1815	\|\| pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1816	{
1817	if (pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
1818	{
1819	PPGMPOOLPAGE pNewHead = &pPool->aPages[pPage->iMonitoredNext];
1820	pNewHead->iMonitoredPrev = NIL_PGMPOOL_IDX;
1821	rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
1822	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pNewHead),
1823	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pNewHead),
1824	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pNewHead),
1825	pPool->pszAccessHandler);
1826	AssertFatalRCSuccess(rc);
1827	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
1828	}
1829	else
1830	{
1831	pPool->aPages[pPage->iMonitoredPrev].iMonitoredNext = pPage->iMonitoredNext;
1832	if (pPage->iMonitoredNext != NIL_PGMPOOL_IDX)
1833	{
1834	pPool->aPages[pPage->iMonitoredNext].iMonitoredPrev = pPage->iMonitoredPrev;
1835	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
1836	}
1837	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
1838	rc = VINF_SUCCESS;
1839	}
1840	}
1841	else
1842	{
1843	rc = PGMHandlerPhysicalDeregister(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1));
1844	AssertFatalRC(rc);
1845	AssertMsg(!(pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_ISSET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3),
1846	("%#x %#x\n", pVM->pgm.s.fGlobalSyncFlags, pVM->fGlobalForcedActions));
1847	}
1848	pPage->fMonitored = false;
1849
1850	/*
1851	* Remove it from the list of modified pages (if in it).
1852	*/
1853	pgmPoolMonitorModifiedRemove(pPool, pPage);
1854
1855	return rc;
1856	}
1857
1858
1859	/**
1860	* Inserts the page into the list of modified pages.
1861	*
1862	* @param pPool The pool.
1863	* @param pPage The page.
1864	*/
1865	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1866	{
1867	Log3(("pgmPoolMonitorModifiedInsert: idx=%d\n", pPage->idx));
1868	AssertMsg( pPage->iModifiedNext == NIL_PGMPOOL_IDX
1869	&& pPage->iModifiedPrev == NIL_PGMPOOL_IDX
1870	&& pPool->iModifiedHead != pPage->idx,
1871	("Next=%d Prev=%d idx=%d cModifications=%d Head=%d cModifiedPages=%d\n",
1872	pPage->iModifiedNext, pPage->iModifiedPrev, pPage->idx, pPage->cModifications,
1873	pPool->iModifiedHead, pPool->cModifiedPages));
1874
1875	pPage->iModifiedNext = pPool->iModifiedHead;
1876	if (pPool->iModifiedHead != NIL_PGMPOOL_IDX)
1877	pPool->aPages[pPool->iModifiedHead].iModifiedPrev = pPage->idx;
1878	pPool->iModifiedHead = pPage->idx;
1879	pPool->cModifiedPages++;
1880	#ifdef VBOX_WITH_STATISTICS
1881	if (pPool->cModifiedPages > pPool->cModifiedPagesHigh)
1882	pPool->cModifiedPagesHigh = pPool->cModifiedPages;
1883	#endif
1884	}
1885
1886
1887	/**
1888	* Removes the page from the list of modified pages and resets the
1889	* moficiation counter.
1890	*
1891	* @param pPool The pool.
1892	* @param pPage The page which is believed to be in the list of modified pages.
1893	*/
1894	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1895	{
1896	Log3(("pgmPoolMonitorModifiedRemove: idx=%d cModifications=%d\n", pPage->idx, pPage->cModifications));
1897	if (pPool->iModifiedHead == pPage->idx)
1898	{
1899	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
1900	pPool->iModifiedHead = pPage->iModifiedNext;
1901	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
1902	{
1903	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = NIL_PGMPOOL_IDX;
1904	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1905	}
1906	pPool->cModifiedPages--;
1907	}
1908	else if (pPage->iModifiedPrev != NIL_PGMPOOL_IDX)
1909	{
1910	pPool->aPages[pPage->iModifiedPrev].iModifiedNext = pPage->iModifiedNext;
1911	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
1912	{
1913	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = pPage->iModifiedPrev;
1914	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1915	}
1916	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
1917	pPool->cModifiedPages--;
1918	}
1919	else
1920	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
1921	pPage->cModifications = 0;
1922	}
1923
1924
1925	/**
1926	* Zaps the list of modified pages, resetting their modification counters in the process.
1927	*
1928	* @param pVM The VM handle.
1929	*/
1930	void pgmPoolMonitorModifiedClearAll(PVM pVM)
1931	{
1932	pgmLock(pVM);
1933	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1934	LogFlow(("pgmPoolMonitorModifiedClearAll: cModifiedPages=%d\n", pPool->cModifiedPages));
1935
1936	unsigned cPages = 0; NOREF(cPages);
1937	uint16_t idx = pPool->iModifiedHead;
1938	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
1939	while (idx != NIL_PGMPOOL_IDX)
1940	{
1941	PPGMPOOLPAGE pPage = &pPool->aPages[idx];
1942	idx = pPage->iModifiedNext;
1943	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1944	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
1945	pPage->cModifications = 0;
1946	Assert(++cPages);
1947	}
1948	AssertMsg(cPages == pPool->cModifiedPages, ("%d != %d\n", cPages, pPool->cModifiedPages));
1949	pPool->cModifiedPages = 0;
1950	pgmUnlock(pVM);
1951	}
1952
1953
1954	#ifdef IN_RING3
1955	/**
1956	* Callback to clear all shadow pages and clear all modification counters.
1957	*
1958	* @returns VBox status code.
1959	* @param pVM The VM handle.
1960	* @param pvUser Unused parameter
1961	* @remark Should only be used when monitoring is available, thus placed in
1962	* the PGMPOOL_WITH_MONITORING #ifdef.
1963	*/
1964	DECLCALLBACK(int) pgmPoolClearAll(PVM pVM, void *pvUser)
1965	{
1966	NOREF(pvUser);
1967	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1968	STAM_PROFILE_START(&pPool->StatClearAll, c);
1969	LogFlow(("pgmPoolClearAll: cUsedPages=%d\n", pPool->cUsedPages));
1970
1971	pgmLock(pVM);
1972
1973	/*
1974	* Iterate all the pages until we've encountered all that in use.
1975	* This is simple but not quite optimal solution.
1976	*/
1977	unsigned cModifiedPages = 0; NOREF(cModifiedPages);
1978	unsigned cLeft = pPool->cUsedPages;
1979	unsigned iPage = pPool->cCurPages;
1980	while (--iPage >= PGMPOOL_IDX_FIRST)
1981	{
1982	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
1983	if (pPage->GCPhys != NIL_RTGCPHYS)
1984	{
1985	switch (pPage->enmKind)
1986	{
1987	/*
1988	* We only care about shadow page tables.
1989	*/
1990	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1991	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1992	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1993	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1994	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1995	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1996	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1997	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1998	{
1999	#ifdef PGMPOOL_WITH_USER_TRACKING
2000	if (pPage->cPresent)
2001	#endif
2002	{
2003	void *pvShw = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
2004	STAM_PROFILE_START(&pPool->StatZeroPage, z);
2005	ASMMemZeroPage(pvShw);
2006	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
2007	#ifdef PGMPOOL_WITH_USER_TRACKING
2008	pPage->cPresent = 0;
2009	pPage->iFirstPresent = ~0;
2010	#endif
2011	}
2012	}
2013	/* fall thru */
2014
2015	default:
2016	Assert(!pPage->cModifications \|\| ++cModifiedPages);
2017	Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2018	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2019	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2020	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2021	pPage->cModifications = 0;
2022	break;
2023
2024	}
2025	if (!--cLeft)
2026	break;
2027	}
2028	}
2029
2030	/* swipe the special pages too. */
2031	for (iPage = PGMPOOL_IDX_FIRST_SPECIAL; iPage < PGMPOOL_IDX_FIRST; iPage++)
2032	{
2033	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
2034	if (pPage->GCPhys != NIL_RTGCPHYS)
2035	{
2036	Assert(!pPage->cModifications \|\| ++cModifiedPages);
2037	Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2038	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2039	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2040	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2041	pPage->cModifications = 0;
2042	}
2043	}
2044
2045	#ifndef DEBUG_michael
2046	AssertMsg(cModifiedPages == pPool->cModifiedPages, ("%d != %d\n", cModifiedPages, pPool->cModifiedPages));
2047	#endif
2048	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
2049	pPool->cModifiedPages = 0;
2050
2051	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2052	/*
2053	* Clear all the GCPhys links and rebuild the phys ext free list.
2054	*/
2055	for (PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
2056	pRam;
2057	pRam = pRam->CTX_SUFF(pNext))
2058	{
2059	unsigned iPage = pRam->cb >> PAGE_SHIFT;
2060	while (iPage-- > 0)
2061	PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
2062	}
2063
2064	pPool->iPhysExtFreeHead = 0;
2065	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
2066	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
2067	for (unsigned i = 0; i < cMaxPhysExts; i++)
2068	{
2069	paPhysExts[i].iNext = i + 1;
2070	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
2071	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
2072	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
2073	}
2074	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
2075	#endif
2076
2077	pPool->cPresent = 0;
2078	pgmUnlock(pVM);
2079	PGM_INVL_ALL_VCPU_TLBS(pVM);
2080	STAM_PROFILE_STOP(&pPool->StatClearAll, c);
2081	return VINF_SUCCESS;
2082	}
2083	#endif /* IN_RING3 */
2084
2085
2086	/**
2087	* Handle SyncCR3 pool tasks
2088	*
2089	* @returns VBox status code.
2090	* @retval VINF_SUCCESS if successfully added.
2091	* @retval VINF_PGM_SYNC_CR3 is it needs to be deferred to ring 3 (GC only)
2092	* @param pVM The VM handle.
2093	* @remark Should only be used when monitoring is available, thus placed in
2094	* the PGMPOOL_WITH_MONITORING #ifdef.
2095	*/
2096	int pgmPoolSyncCR3(PVM pVM)
2097	{
2098	LogFlow(("pgmPoolSyncCR3\n"));
2099	/*
2100	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2101	* Occasionally we will have to clear all the shadow page tables because we wanted
2102	* to monitor a page which was mapped by too many shadowed page tables. This operation
2103	* sometimes refered to as a 'lightweight flush'.
2104	*/
2105	# ifdef IN_RING3 /* Don't flush in ring-0 or raw mode, it's taking too long. */
2106	if (ASMBitTestAndClear(&pVM->pgm.s.fGlobalSyncFlags, PGM_GLOBAL_SYNC_CLEAR_PGM_POOL_BIT))
2107	{
2108	VMMR3AtomicExecuteHandler(pVM, pgmPoolClearAll, NULL);
2109	# else /* !IN_RING3 */
2110	if (pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL)
2111	{
2112	LogFlow(("SyncCR3: PGM_GLOBAL_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2113	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
2114	return VINF_PGM_SYNC_CR3;
2115	# endif /* !IN_RING3 */
2116	}
2117	else
2118	pgmPoolMonitorModifiedClearAll(pVM);
2119
2120	return VINF_SUCCESS;
2121	}
2122
2123	#endif /* PGMPOOL_WITH_MONITORING */
2124	#ifdef PGMPOOL_WITH_USER_TRACKING
2125
2126	/**
2127	* Frees up at least one user entry.
2128	*
2129	* @returns VBox status code.
2130	* @retval VINF_SUCCESS if successfully added.
2131	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2132	* @param pPool The pool.
2133	* @param iUser The user index.
2134	*/
2135	static int pgmPoolTrackFreeOneUser(PPGMPOOL pPool, uint16_t iUser)
2136	{
2137	STAM_COUNTER_INC(&pPool->StatTrackFreeUpOneUser);
2138	#ifdef PGMPOOL_WITH_CACHE
2139	/*
2140	* Just free cached pages in a braindead fashion.
2141	*/
2142	/** @todo walk the age list backwards and free the first with usage. */
2143	int rc = VINF_SUCCESS;
2144	do
2145	{
2146	int rc2 = pgmPoolCacheFreeOne(pPool, iUser);
2147	if (RT_FAILURE(rc2) && rc == VINF_SUCCESS)
2148	rc = rc2;
2149	} while (pPool->iUserFreeHead == NIL_PGMPOOL_USER_INDEX);
2150	return rc;
2151	#else
2152	/*
2153	* Lazy approach.
2154	*/
2155	/* @todo This path no longer works (CR3 root pages will be flushed)!! */
2156	AssertCompileFailed();
2157	Assert(!CPUMIsGuestInLongMode(pVM));
2158	pgmPoolFlushAllInt(pPool);
2159	return VERR_PGM_POOL_FLUSHED;
2160	#endif
2161	}
2162
2163
2164	/**
2165	* Inserts a page into the cache.
2166	*
2167	* This will create user node for the page, insert it into the GCPhys
2168	* hash, and insert it into the age list.
2169	*
2170	* @returns VBox status code.
2171	* @retval VINF_SUCCESS if successfully added.
2172	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2173	* @param pPool The pool.
2174	* @param pPage The cached page.
2175	* @param GCPhys The GC physical address of the page we're gonna shadow.
2176	* @param iUser The user index.
2177	* @param iUserTable The user table index.
2178	*/
2179	DECLINLINE(int) pgmPoolTrackInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhys, uint16_t iUser, uint32_t iUserTable)
2180	{
2181	int rc = VINF_SUCCESS;
2182	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2183
2184	LogFlow(("pgmPoolTrackInsert GCPhys=%RGp iUser %x iUserTable %x\n", GCPhys, iUser, iUserTable));
2185
2186	#ifdef VBOX_STRICT
2187	/*
2188	* Check that the entry doesn't already exists.
2189	*/
2190	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2191	{
2192	uint16_t i = pPage->iUserHead;
2193	do
2194	{
2195	Assert(i < pPool->cMaxUsers);
2196	AssertMsg(paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2197	i = paUsers[i].iNext;
2198	} while (i != NIL_PGMPOOL_USER_INDEX);
2199	}
2200	#endif
2201
2202	/*
2203	* Find free a user node.
2204	*/
2205	uint16_t i = pPool->iUserFreeHead;
2206	if (i == NIL_PGMPOOL_USER_INDEX)
2207	{
2208	int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2209	if (RT_FAILURE(rc))
2210	return rc;
2211	i = pPool->iUserFreeHead;
2212	}
2213
2214	/*
2215	* Unlink the user node from the free list,
2216	* initialize and insert it into the user list.
2217	*/
2218	pPool->iUserFreeHead = paUsers[i].iNext;
2219	paUsers[i].iNext = NIL_PGMPOOL_USER_INDEX;
2220	paUsers[i].iUser = iUser;
2221	paUsers[i].iUserTable = iUserTable;
2222	pPage->iUserHead = i;
2223
2224	/*
2225	* Insert into cache and enable monitoring of the guest page if enabled.
2226	*
2227	* Until we implement caching of all levels, including the CR3 one, we'll
2228	* have to make sure we don't try monitor & cache any recursive reuse of
2229	* a monitored CR3 page. Because all windows versions are doing this we'll
2230	* have to be able to do combined access monitoring, CR3 + PT and
2231	* PD + PT (guest PAE).
2232	*
2233	* Update:
2234	* We're now cooperating with the CR3 monitor if an uncachable page is found.
2235	*/
2236	#if defined(PGMPOOL_WITH_MONITORING) \|\| defined(PGMPOOL_WITH_CACHE)
2237	# ifdef PGMPOOL_WITH_MIXED_PT_CR3
2238	const bool fCanBeMonitored = true;
2239	# else
2240	bool fCanBeMonitored = pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored == NIL_RTGCPHYS
2241	\|\| (GCPhys & X86_PTE_PAE_PG_MASK) != (pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored & X86_PTE_PAE_PG_MASK)
2242	\|\| pgmPoolIsBigPage((PGMPOOLKIND)pPage->enmKind);
2243	# endif
2244	# ifdef PGMPOOL_WITH_CACHE
2245	pgmPoolCacheInsert(pPool, pPage, fCanBeMonitored); /* This can be expanded. */
2246	# endif
2247	if (fCanBeMonitored)
2248	{
2249	# ifdef PGMPOOL_WITH_MONITORING
2250	rc = pgmPoolMonitorInsert(pPool, pPage);
2251	AssertRC(rc);
2252	}
2253	# endif
2254	#endif /* PGMPOOL_WITH_MONITORING */
2255	return rc;
2256	}
2257
2258
2259	# ifdef PGMPOOL_WITH_CACHE /* (only used when the cache is enabled.) */
2260	/**
2261	* Adds a user reference to a page.
2262	*
2263	* This will move the page to the head of the
2264	*
2265	* @returns VBox status code.
2266	* @retval VINF_SUCCESS if successfully added.
2267	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2268	* @param pPool The pool.
2269	* @param pPage The cached page.
2270	* @param iUser The user index.
2271	* @param iUserTable The user table.
2272	*/
2273	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2274	{
2275	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2276
2277	Log3(("pgmPoolTrackAddUser GCPhys = %RGp iUser %x iUserTable %x\n", pPage->GCPhys, iUser, iUserTable));
2278
2279	# ifdef VBOX_STRICT
2280	/*
2281	* Check that the entry doesn't already exists. We only allow multiple users of top-level paging structures (SHW_POOL_ROOT_IDX).
2282	*/
2283	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2284	{
2285	uint16_t i = pPage->iUserHead;
2286	do
2287	{
2288	Assert(i < pPool->cMaxUsers);
2289	AssertMsg(iUser != PGMPOOL_IDX_PD \|\| iUser != PGMPOOL_IDX_PDPT \|\| iUser != PGMPOOL_IDX_NESTED_ROOT \|\| iUser != PGMPOOL_IDX_AMD64_CR3 \|\|
2290	paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2291	i = paUsers[i].iNext;
2292	} while (i != NIL_PGMPOOL_USER_INDEX);
2293	}
2294	# endif
2295
2296	/*
2297	* Allocate a user node.
2298	*/
2299	uint16_t i = pPool->iUserFreeHead;
2300	if (i == NIL_PGMPOOL_USER_INDEX)
2301	{
2302	int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2303	if (RT_FAILURE(rc))
2304	return rc;
2305	i = pPool->iUserFreeHead;
2306	}
2307	pPool->iUserFreeHead = paUsers[i].iNext;
2308
2309	/*
2310	* Initialize the user node and insert it.
2311	*/
2312	paUsers[i].iNext = pPage->iUserHead;
2313	paUsers[i].iUser = iUser;
2314	paUsers[i].iUserTable = iUserTable;
2315	pPage->iUserHead = i;
2316
2317	# ifdef PGMPOOL_WITH_CACHE
2318	/*
2319	* Tell the cache to update its replacement stats for this page.
2320	*/
2321	pgmPoolCacheUsed(pPool, pPage);
2322	# endif
2323	return VINF_SUCCESS;
2324	}
2325	# endif /* PGMPOOL_WITH_CACHE */
2326
2327
2328	/**
2329	* Frees a user record associated with a page.
2330	*
2331	* This does not clear the entry in the user table, it simply replaces the
2332	* user record to the chain of free records.
2333	*
2334	* @param pPool The pool.
2335	* @param HCPhys The HC physical address of the shadow page.
2336	* @param iUser The shadow page pool index of the user table.
2337	* @param iUserTable The index into the user table (shadowed).
2338	*/
2339	static void pgmPoolTrackFreeUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2340	{
2341	/*
2342	* Unlink and free the specified user entry.
2343	*/
2344	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2345
2346	Log3(("pgmPoolTrackFreeUser %RGp %x %x\n", pPage->GCPhys, iUser, iUserTable));
2347	/* Special: For PAE and 32-bit paging, there is usually no more than one user. */
2348	uint16_t i = pPage->iUserHead;
2349	if ( i != NIL_PGMPOOL_USER_INDEX
2350	&& paUsers[i].iUser == iUser
2351	&& paUsers[i].iUserTable == iUserTable)
2352	{
2353	pPage->iUserHead = paUsers[i].iNext;
2354
2355	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2356	paUsers[i].iNext = pPool->iUserFreeHead;
2357	pPool->iUserFreeHead = i;
2358	return;
2359	}
2360
2361	/* General: Linear search. */
2362	uint16_t iPrev = NIL_PGMPOOL_USER_INDEX;
2363	while (i != NIL_PGMPOOL_USER_INDEX)
2364	{
2365	if ( paUsers[i].iUser == iUser
2366	&& paUsers[i].iUserTable == iUserTable)
2367	{
2368	if (iPrev != NIL_PGMPOOL_USER_INDEX)
2369	paUsers[iPrev].iNext = paUsers[i].iNext;
2370	else
2371	pPage->iUserHead = paUsers[i].iNext;
2372
2373	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2374	paUsers[i].iNext = pPool->iUserFreeHead;
2375	pPool->iUserFreeHead = i;
2376	return;
2377	}
2378	iPrev = i;
2379	i = paUsers[i].iNext;
2380	}
2381
2382	/* Fatal: didn't find it */
2383	AssertFatalMsgFailed(("Didn't find the user entry! iUser=%#x iUserTable=%#x GCPhys=%RGp\n",
2384	iUser, iUserTable, pPage->GCPhys));
2385	}
2386
2387
2388	/**
2389	* Gets the entry size of a shadow table.
2390	*
2391	* @param enmKind The kind of page.
2392	*
2393	* @returns The size of the entry in bytes. That is, 4 or 8.
2394	* @returns If the kind is not for a table, an assertion is raised and 0 is
2395	* returned.
2396	*/
2397	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind)
2398	{
2399	switch (enmKind)
2400	{
2401	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2402	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2403	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2404	case PGMPOOLKIND_32BIT_PD:
2405	case PGMPOOLKIND_32BIT_PD_PHYS:
2406	return 4;
2407
2408	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2409	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2410	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2411	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2412	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2413	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2414	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2415	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2416	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2417	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2418	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2419	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2420	case PGMPOOLKIND_64BIT_PML4:
2421	case PGMPOOLKIND_PAE_PDPT:
2422	case PGMPOOLKIND_ROOT_NESTED:
2423	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2424	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2425	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2426	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2427	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2428	case PGMPOOLKIND_PAE_PD_PHYS:
2429	case PGMPOOLKIND_PAE_PDPT_PHYS:
2430	return 8;
2431
2432	default:
2433	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2434	}
2435	}
2436
2437
2438	/**
2439	* Gets the entry size of a guest table.
2440	*
2441	* @param enmKind The kind of page.
2442	*
2443	* @returns The size of the entry in bytes. That is, 0, 4 or 8.
2444	* @returns If the kind is not for a table, an assertion is raised and 0 is
2445	* returned.
2446	*/
2447	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind)
2448	{
2449	switch (enmKind)
2450	{
2451	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2452	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2453	case PGMPOOLKIND_32BIT_PD:
2454	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2455	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2456	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2457	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2458	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2459	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2460	return 4;
2461
2462	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2463	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2464	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2465	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2466	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2467	case PGMPOOLKIND_64BIT_PML4:
2468	case PGMPOOLKIND_PAE_PDPT:
2469	return 8;
2470
2471	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2472	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2473	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2474	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2475	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2476	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2477	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2478	case PGMPOOLKIND_ROOT_NESTED:
2479	case PGMPOOLKIND_PAE_PD_PHYS:
2480	case PGMPOOLKIND_PAE_PDPT_PHYS:
2481	case PGMPOOLKIND_32BIT_PD_PHYS:
2482	/** @todo can we return 0? (nobody is calling this...) */
2483	AssertFailed();
2484	return 0;
2485
2486	default:
2487	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2488	}
2489	}
2490
2491	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2492
2493	/**
2494	* Scans one shadow page table for mappings of a physical page.
2495	*
2496	* @param pVM The VM handle.
2497	* @param pPhysPage The guest page in question.
2498	* @param iShw The shadow page table.
2499	* @param cRefs The number of references made in that PT.
2500	*/
2501	static void pgmPoolTrackFlushGCPhysPTInt(PVM pVM, PCPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs)
2502	{
2503	LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%R[pgmpage] iShw=%d cRefs=%d\n", pPhysPage, iShw, cRefs));
2504	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2505
2506	/*
2507	* Assert sanity.
2508	*/
2509	Assert(cRefs == 1);
2510	AssertFatalMsg(iShw < pPool->cCurPages && iShw != NIL_PGMPOOL_IDX, ("iShw=%d\n", iShw));
2511	PPGMPOOLPAGE pPage = &pPool->aPages[iShw];
2512
2513	/*
2514	* Then, clear the actual mappings to the page in the shadow PT.
2515	*/
2516	switch (pPage->enmKind)
2517	{
2518	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2519	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2520	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2521	{
2522	const uint32_t u32 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2523	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2524	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2525	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2526	{
2527	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX32 cRefs=%#x\n", i, pPT->a[i], cRefs));
2528	pPT->a[i].u = 0;
2529	cRefs--;
2530	if (!cRefs)
2531	return;
2532	}
2533	#ifdef LOG_ENABLED
2534	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2535	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2536	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2537	{
2538	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2539	pPT->a[i].u = 0;
2540	}
2541	#endif
2542	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
2543	break;
2544	}
2545
2546	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2547	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2548	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2549	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2550	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2551	{
2552	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2553	PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2554	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2555	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2556	{
2557	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
2558	pPT->a[i].u = 0;
2559	cRefs--;
2560	if (!cRefs)
2561	return;
2562	}
2563	#ifdef LOG_ENABLED
2564	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2565	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2566	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2567	{
2568	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2569	pPT->a[i].u = 0;
2570	}
2571	#endif
2572	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d u64=%RX64\n", cRefs, pPage->iFirstPresent, pPage->cPresent, u64));
2573	break;
2574	}
2575
2576	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2577	{
2578	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2579	PEPTPT pPT = (PEPTPT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2580	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2581	if ((pPT->a[i].u & (EPT_PTE_PG_MASK \| X86_PTE_P)) == u64)
2582	{
2583	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
2584	pPT->a[i].u = 0;
2585	cRefs--;
2586	if (!cRefs)
2587	return;
2588	}
2589	#ifdef LOG_ENABLED
2590	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2591	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2592	if ((pPT->a[i].u & (EPT_PTE_PG_MASK \| X86_PTE_P)) == u64)
2593	{
2594	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2595	pPT->a[i].u = 0;
2596	}
2597	#endif
2598	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
2599	break;
2600	}
2601
2602	default:
2603	AssertFatalMsgFailed(("enmKind=%d iShw=%d\n", pPage->enmKind, iShw));
2604	}
2605	}
2606
2607
2608	/**
2609	* Scans one shadow page table for mappings of a physical page.
2610	*
2611	* @param pVM The VM handle.
2612	* @param pPhysPage The guest page in question.
2613	* @param iShw The shadow page table.
2614	* @param cRefs The number of references made in that PT.
2615	*/
2616	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs)
2617	{
2618	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2619	LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%R[pgmpage] iShw=%d cRefs=%d\n", pPhysPage, iShw, cRefs));
2620	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPT, f);
2621	pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, iShw, cRefs);
2622	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2623	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPT, f);
2624	}
2625
2626
2627	/**
2628	* Flushes a list of shadow page tables mapping the same physical page.
2629	*
2630	* @param pVM The VM handle.
2631	* @param pPhysPage The guest page in question.
2632	* @param iPhysExt The physical cross reference extent list to flush.
2633	*/
2634	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt)
2635	{
2636	Assert(PGMIsLockOwner(pVM));
2637	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2638	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTs, f);
2639	LogFlow(("pgmPoolTrackFlushGCPhysPTs: pPhysPage=%R[pgmpage] iPhysExt\n", pPhysPage, iPhysExt));
2640
2641	const uint16_t iPhysExtStart = iPhysExt;
2642	PPGMPOOLPHYSEXT pPhysExt;
2643	do
2644	{
2645	Assert(iPhysExt < pPool->cMaxPhysExts);
2646	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
2647	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
2648	if (pPhysExt->aidx[i] != NIL_PGMPOOL_IDX)
2649	{
2650	pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, pPhysExt->aidx[i], 1);
2651	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
2652	}
2653
2654	/* next */
2655	iPhysExt = pPhysExt->iNext;
2656	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
2657
2658	/* insert the list into the free list and clear the ram range entry. */
2659	pPhysExt->iNext = pPool->iPhysExtFreeHead;
2660	pPool->iPhysExtFreeHead = iPhysExtStart;
2661	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2662
2663	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTs, f);
2664	}
2665
2666	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
2667
2668	/**
2669	* Flushes all shadow page table mappings of the given guest page.
2670	*
2671	* This is typically called when the host page backing the guest one has been
2672	* replaced or when the page protection was changed due to an access handler.
2673	*
2674	* @returns VBox status code.
2675	* @retval VINF_SUCCESS if all references has been successfully cleared.
2676	* @retval VINF_PGM_SYNC_CR3 if we're better off with a CR3 sync and a page
2677	* pool cleaning. FF and sync flags are set.
2678	*
2679	* @param pVM The VM handle.
2680	* @param pPhysPage The guest page in question.
2681	* @param pfFlushTLBs This is set to @a true if the shadow TLBs should be
2682	* flushed, it is NOT touched if this isn't necessary.
2683	* The caller MUST initialized this to @a false.
2684	*/
2685	int pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
2686	{
2687	pgmLock(pVM);
2688	int rc = VINF_SUCCESS;
2689	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2690	const uint16_t u16 = PGM_PAGE_GET_TRACKING(pPhysPage);
2691	if (u16)
2692	{
2693	/*
2694	* The zero page is currently screwing up the tracking and we'll
2695	* have to flush the whole shebang. Unless VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2696	* is defined, zero pages won't normally be mapped. Some kind of solution
2697	* will be needed for this problem of course, but it will have to wait...
2698	*/
2699	if (PGM_PAGE_IS_ZERO(pPhysPage))
2700	rc = VINF_PGM_GCPHYS_ALIASED;
2701	else
2702	{
2703	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2704	/* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow and
2705	pgmPoolTrackFlushGCPhysPTs will/may kill the pool otherwise. */
2706	PVMCPU pVCpu = VMMGetCpu(pVM);
2707	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
2708	# endif
2709
2710	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
2711	pgmPoolTrackFlushGCPhysPT(pVM,
2712	pPhysPage,
2713	PGMPOOL_TD_GET_IDX(u16),
2714	PGMPOOL_TD_GET_CREFS(u16));
2715	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
2716	pgmPoolTrackFlushGCPhysPTs(pVM, pPhysPage, PGMPOOL_TD_GET_IDX(u16));
2717	else
2718	rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
2719	*pfFlushTLBs = true;
2720
2721	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2722	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
2723	# endif
2724	}
2725	}
2726
2727	#elif defined(PGMPOOL_WITH_CACHE)
2728	if (PGM_PAGE_IS_ZERO(pPhysPage))
2729	rc = VINF_PGM_GCPHYS_ALIASED;
2730	else
2731	{
2732	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2733	/* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow kill the pool otherwise. */
2734	PVMCPU pVCpu = VMMGetCpu(pVM);
2735	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
2736	# endif
2737	rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
2738	if (rc == VINF_SUCCESS)
2739	*pfFlushTLBs = true;
2740	}
2741
2742	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2743	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
2744	# endif
2745
2746	#else
2747	rc = VINF_PGM_GCPHYS_ALIASED;
2748	#endif
2749
2750	if (rc == VINF_PGM_GCPHYS_ALIASED)
2751	{
2752	pVM->pgm.s.fGlobalSyncFlags \|= PGM_GLOBAL_SYNC_CLEAR_PGM_POOL;
2753	for (unsigned i=0;i<pVM->cCPUs;i++)
2754	{
2755	PVMCPU pVCpu = &pVM->aCpus[i];
2756	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2757	}
2758	rc = VINF_PGM_SYNC_CR3;
2759	}
2760	pgmUnlock(pVM);
2761	return rc;
2762	}
2763
2764
2765	/**
2766	* Scans all shadow page tables for mappings of a physical page.
2767	*
2768	* This may be slow, but it's most likely more efficient than cleaning
2769	* out the entire page pool / cache.
2770	*
2771	* @returns VBox status code.
2772	* @retval VINF_SUCCESS if all references has been successfully cleared.
2773	* @retval VINF_PGM_GCPHYS_ALIASED if we're better off with a CR3 sync and
2774	* a page pool cleaning.
2775	*
2776	* @param pVM The VM handle.
2777	* @param pPhysPage The guest page in question.
2778	*/
2779	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage)
2780	{
2781	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2782	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2783	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: cUsedPages=%d cPresent=%d pPhysPage=%R[pgmpage]\n",
2784	pPool->cUsedPages, pPool->cPresent, pPhysPage));
2785
2786	#if 1
2787	/*
2788	* There is a limit to what makes sense.
2789	*/
2790	if (pPool->cPresent > 1024)
2791	{
2792	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
2793	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2794	return VINF_PGM_GCPHYS_ALIASED;
2795	}
2796	#endif
2797
2798	/*
2799	* Iterate all the pages until we've encountered all that in use.
2800	* This is simple but not quite optimal solution.
2801	*/
2802	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2803	const uint32_t u32 = u64;
2804	unsigned cLeft = pPool->cUsedPages;
2805	unsigned iPage = pPool->cCurPages;
2806	while (--iPage >= PGMPOOL_IDX_FIRST)
2807	{
2808	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
2809	if (pPage->GCPhys != NIL_RTGCPHYS)
2810	{
2811	switch (pPage->enmKind)
2812	{
2813	/*
2814	* We only care about shadow page tables.
2815	*/
2816	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2817	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2818	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2819	{
2820	unsigned cPresent = pPage->cPresent;
2821	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2822	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2823	if (pPT->a[i].n.u1Present)
2824	{
2825	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2826	{
2827	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX32\n", iPage, i, pPT->a[i]));
2828	pPT->a[i].u = 0;
2829	}
2830	if (!--cPresent)
2831	break;
2832	}
2833	break;
2834	}
2835
2836	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2837	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2838	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2839	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2840	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2841	{
2842	unsigned cPresent = pPage->cPresent;
2843	PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2844	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2845	if (pPT->a[i].n.u1Present)
2846	{
2847	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2848	{
2849	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
2850	pPT->a[i].u = 0;
2851	}
2852	if (!--cPresent)
2853	break;
2854	}
2855	break;
2856	}
2857	}
2858	if (!--cLeft)
2859	break;
2860	}
2861	}
2862
2863	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2864	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2865	return VINF_SUCCESS;
2866	}
2867
2868
2869	/**
2870	* Clears the user entry in a user table.
2871	*
2872	* This is used to remove all references to a page when flushing it.
2873	*/
2874	static void pgmPoolTrackClearPageUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PCPGMPOOLUSER pUser)
2875	{
2876	Assert(pUser->iUser != NIL_PGMPOOL_IDX);
2877	Assert(pUser->iUser < pPool->cCurPages);
2878	uint32_t iUserTable = pUser->iUserTable;
2879
2880	/*
2881	* Map the user page.
2882	*/
2883	PPGMPOOLPAGE pUserPage = &pPool->aPages[pUser->iUser];
2884	union
2885	{
2886	uint64_t *pau64;
2887	uint32_t *pau32;
2888	} u;
2889	u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pUserPage);
2890
2891	LogFlow(("pgmPoolTrackClearPageUser: clear %x in %s (%RGp) (flushing %s)\n", iUserTable, pgmPoolPoolKindToStr(pUserPage->enmKind), pUserPage->Core.Key, pgmPoolPoolKindToStr(pPage->enmKind)));
2892
2893	/* Safety precaution in case we change the paging for other modes too in the future. */
2894	Assert(!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage));
2895
2896	#ifdef VBOX_STRICT
2897	/*
2898	* Some sanity checks.
2899	*/
2900	switch (pUserPage->enmKind)
2901	{
2902	case PGMPOOLKIND_32BIT_PD:
2903	case PGMPOOLKIND_32BIT_PD_PHYS:
2904	Assert(iUserTable < X86_PG_ENTRIES);
2905	break;
2906	case PGMPOOLKIND_PAE_PDPT:
2907	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2908	case PGMPOOLKIND_PAE_PDPT_PHYS:
2909	Assert(iUserTable < 4);
2910	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2911	break;
2912	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2913	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2914	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2915	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2916	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2917	case PGMPOOLKIND_PAE_PD_PHYS:
2918	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2919	break;
2920	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2921	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2922	Assert(!(u.pau64[iUserTable] & PGM_PDFLAGS_MAPPING));
2923	break;
2924	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2925	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2926	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2927	break;
2928	case PGMPOOLKIND_64BIT_PML4:
2929	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2930	/* GCPhys >> PAGE_SHIFT is the index here */
2931	break;
2932	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2933	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2934	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2935	break;
2936
2937	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2938	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2939	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2940	break;
2941
2942	case PGMPOOLKIND_ROOT_NESTED:
2943	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2944	break;
2945
2946	default:
2947	AssertMsgFailed(("enmKind=%d\n", pUserPage->enmKind));
2948	break;
2949	}
2950	#endif /* VBOX_STRICT */
2951
2952	/*
2953	* Clear the entry in the user page.
2954	*/
2955	switch (pUserPage->enmKind)
2956	{
2957	/* 32-bit entries */
2958	case PGMPOOLKIND_32BIT_PD:
2959	case PGMPOOLKIND_32BIT_PD_PHYS:
2960	u.pau32[iUserTable] = 0;
2961	break;
2962
2963	/* 64-bit entries */
2964	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2965	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2966	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2967	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2968	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2969	#if defined(IN_RC)
2970	/* In 32 bits PAE mode we must invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
2971	* non-present PDPT will continue to cause page faults.
2972	*/
2973	ASMReloadCR3();
2974	#endif
2975	/* no break */
2976	case PGMPOOLKIND_PAE_PD_PHYS:
2977	case PGMPOOLKIND_PAE_PDPT_PHYS:
2978	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2979	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2980	case PGMPOOLKIND_64BIT_PML4:
2981	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2982	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2983	case PGMPOOLKIND_PAE_PDPT:
2984	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2985	case PGMPOOLKIND_ROOT_NESTED:
2986	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2987	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2988	u.pau64[iUserTable] = 0;
2989	break;
2990
2991	default:
2992	AssertFatalMsgFailed(("enmKind=%d iUser=%#x iUserTable=%#x\n", pUserPage->enmKind, pUser->iUser, pUser->iUserTable));
2993	}
2994	}
2995
2996
2997	/**
2998	* Clears all users of a page.
2999	*/
3000	static void pgmPoolTrackClearPageUsers(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3001	{
3002	/*
3003	* Free all the user records.
3004	*/
3005	LogFlow(("pgmPoolTrackClearPageUsers %RGp\n", pPage->GCPhys));
3006
3007	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
3008	uint16_t i = pPage->iUserHead;
3009	while (i != NIL_PGMPOOL_USER_INDEX)
3010	{
3011	/* Clear enter in user table. */
3012	pgmPoolTrackClearPageUser(pPool, pPage, &paUsers[i]);
3013
3014	/* Free it. */
3015	const uint16_t iNext = paUsers[i].iNext;
3016	paUsers[i].iUser = NIL_PGMPOOL_IDX;
3017	paUsers[i].iNext = pPool->iUserFreeHead;
3018	pPool->iUserFreeHead = i;
3019
3020	/* Next. */
3021	i = iNext;
3022	}
3023	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3024	}
3025
3026	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3027
3028	/**
3029	* Allocates a new physical cross reference extent.
3030	*
3031	* @returns Pointer to the allocated extent on success. NULL if we're out of them.
3032	* @param pVM The VM handle.
3033	* @param piPhysExt Where to store the phys ext index.
3034	*/
3035	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt)
3036	{
3037	Assert(PGMIsLockOwner(pVM));
3038	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3039	uint16_t iPhysExt = pPool->iPhysExtFreeHead;
3040	if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
3041	{
3042	STAM_COUNTER_INC(&pPool->StamTrackPhysExtAllocFailures);
3043	return NULL;
3044	}
3045	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3046	pPool->iPhysExtFreeHead = pPhysExt->iNext;
3047	pPhysExt->iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3048	*piPhysExt = iPhysExt;
3049	return pPhysExt;
3050	}
3051
3052
3053	/**
3054	* Frees a physical cross reference extent.
3055	*
3056	* @param pVM The VM handle.
3057	* @param iPhysExt The extent to free.
3058	*/
3059	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt)
3060	{
3061	Assert(PGMIsLockOwner(pVM));
3062	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3063	Assert(iPhysExt < pPool->cMaxPhysExts);
3064	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3065	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3066	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3067	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3068	pPool->iPhysExtFreeHead = iPhysExt;
3069	}
3070
3071
3072	/**
3073	* Frees a physical cross reference extent.
3074	*
3075	* @param pVM The VM handle.
3076	* @param iPhysExt The extent to free.
3077	*/
3078	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt)
3079	{
3080	Assert(PGMIsLockOwner(pVM));
3081	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3082
3083	const uint16_t iPhysExtStart = iPhysExt;
3084	PPGMPOOLPHYSEXT pPhysExt;
3085	do
3086	{
3087	Assert(iPhysExt < pPool->cMaxPhysExts);
3088	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3089	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3090	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3091
3092	/* next */
3093	iPhysExt = pPhysExt->iNext;
3094	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3095
3096	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3097	pPool->iPhysExtFreeHead = iPhysExtStart;
3098	}
3099
3100
3101	/**
3102	* Insert a reference into a list of physical cross reference extents.
3103	*
3104	* @returns The new tracking data for PGMPAGE.
3105	*
3106	* @param pVM The VM handle.
3107	* @param iPhysExt The physical extent index of the list head.
3108	* @param iShwPT The shadow page table index.
3109	*
3110	*/
3111	static uint16_t pgmPoolTrackPhysExtInsert(PVM pVM, uint16_t iPhysExt, uint16_t iShwPT)
3112	{
3113	Assert(PGMIsLockOwner(pVM));
3114	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3115	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3116
3117	/* special common case. */
3118	if (paPhysExts[iPhysExt].aidx[2] == NIL_PGMPOOL_IDX)
3119	{
3120	paPhysExts[iPhysExt].aidx[2] = iShwPT;
3121	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3122	LogFlow(("pgmPoolTrackPhysExtAddref: %d:{,,%d}\n", iPhysExt, iShwPT));
3123	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3124	}
3125
3126	/* general treatment. */
3127	const uint16_t iPhysExtStart = iPhysExt;
3128	unsigned cMax = 15;
3129	for (;;)
3130	{
3131	Assert(iPhysExt < pPool->cMaxPhysExts);
3132	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3133	if (paPhysExts[iPhysExt].aidx[i] == NIL_PGMPOOL_IDX)
3134	{
3135	paPhysExts[iPhysExt].aidx[i] = iShwPT;
3136	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3137	LogFlow(("pgmPoolTrackPhysExtAddref: %d:{%d} i=%d cMax=%d\n", iPhysExt, iShwPT, i, cMax));
3138	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtStart);
3139	}
3140	if (!--cMax)
3141	{
3142	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3143	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3144	LogFlow(("pgmPoolTrackPhysExtAddref: overflow (1) iShwPT=%d\n", iShwPT));
3145	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3146	}
3147	}
3148
3149	/* add another extent to the list. */
3150	PPGMPOOLPHYSEXT pNew = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3151	if (!pNew)
3152	{
3153	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3154	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3155	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3156	}
3157	pNew->iNext = iPhysExtStart;
3158	pNew->aidx[0] = iShwPT;
3159	LogFlow(("pgmPoolTrackPhysExtAddref: added new extent %d:{%d}->%d\n", iPhysExt, iShwPT, iPhysExtStart));
3160	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3161	}
3162
3163
3164	/**
3165	* Add a reference to guest physical page where extents are in use.
3166	*
3167	* @returns The new tracking data for PGMPAGE.
3168	*
3169	* @param pVM The VM handle.
3170	* @param u16 The ram range flags (top 16-bits).
3171	* @param iShwPT The shadow page table index.
3172	*/
3173	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT)
3174	{
3175	pgmLock(pVM);
3176	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3177	{
3178	/*
3179	* Convert to extent list.
3180	*/
3181	Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
3182	uint16_t iPhysExt;
3183	PPGMPOOLPHYSEXT pPhysExt = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3184	if (pPhysExt)
3185	{
3186	LogFlow(("pgmPoolTrackPhysExtAddref: new extent: %d:{%d, %d}\n", iPhysExt, PGMPOOL_TD_GET_IDX(u16), iShwPT));
3187	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliased);
3188	pPhysExt->aidx[0] = PGMPOOL_TD_GET_IDX(u16);
3189	pPhysExt->aidx[1] = iShwPT;
3190	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3191	}
3192	else
3193	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3194	}
3195	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3196	{
3197	/*
3198	* Insert into the extent list.
3199	*/
3200	u16 = pgmPoolTrackPhysExtInsert(pVM, PGMPOOL_TD_GET_IDX(u16), iShwPT);
3201	}
3202	else
3203	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedLots);
3204	pgmUnlock(pVM);
3205	return u16;
3206	}
3207
3208
3209	/**
3210	* Clear references to guest physical memory.
3211	*
3212	* @param pPool The pool.
3213	* @param pPage The page.
3214	* @param pPhysPage Pointer to the aPages entry in the ram range.
3215	*/
3216	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMPAGE pPhysPage)
3217	{
3218	const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
3219	AssertFatalMsg(cRefs == PGMPOOL_TD_CREFS_PHYSEXT, ("cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3220
3221	uint16_t iPhysExt = PGM_PAGE_GET_TD_IDX(pPhysPage);
3222	if (iPhysExt != PGMPOOL_TD_IDX_OVERFLOWED)
3223	{
3224	PVM pVM = pPool->CTX_SUFF(pVM);
3225	pgmLock(pVM);
3226
3227	uint16_t iPhysExtPrev = NIL_PGMPOOL_PHYSEXT_INDEX;
3228	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3229	do
3230	{
3231	Assert(iPhysExt < pPool->cMaxPhysExts);
3232
3233	/*
3234	* Look for the shadow page and check if it's all freed.
3235	*/
3236	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3237	{
3238	if (paPhysExts[iPhysExt].aidx[i] == pPage->idx)
3239	{
3240	paPhysExts[iPhysExt].aidx[i] = NIL_PGMPOOL_IDX;
3241
3242	for (i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3243	if (paPhysExts[iPhysExt].aidx[i] != NIL_PGMPOOL_IDX)
3244	{
3245	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3246	pgmUnlock(pVM);
3247	return;
3248	}
3249
3250	/* we can free the node. */
3251	const uint16_t iPhysExtNext = paPhysExts[iPhysExt].iNext;
3252	if ( iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX
3253	&& iPhysExtNext == NIL_PGMPOOL_PHYSEXT_INDEX)
3254	{
3255	/* lonely node */
3256	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3257	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d lonely\n", pPhysPage, pPage->idx));
3258	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3259	}
3260	else if (iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX)
3261	{
3262	/* head */
3263	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d head\n", pPhysPage, pPage->idx));
3264	PGM_PAGE_SET_TRACKING(pPhysPage, PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtNext));
3265	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3266	}
3267	else
3268	{
3269	/* in list */
3270	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3271	paPhysExts[iPhysExtPrev].iNext = iPhysExtNext;
3272	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3273	}
3274	iPhysExt = iPhysExtNext;
3275	pgmUnlock(pVM);
3276	return;
3277	}
3278	}
3279
3280	/* next */
3281	iPhysExtPrev = iPhysExt;
3282	iPhysExt = paPhysExts[iPhysExt].iNext;
3283	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3284
3285	pgmUnlock(pVM);
3286	AssertFatalMsgFailed(("not-found! cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3287	}
3288	else /* nothing to do */
3289	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage]\n", pPhysPage));
3290	}
3291
3292
3293	/**
3294	* Clear references to guest physical memory.
3295	*
3296	* This is the same as pgmPoolTracDerefGCPhys except that the guest physical address
3297	* is assumed to be correct, so the linear search can be skipped and we can assert
3298	* at an earlier point.
3299	*
3300	* @param pPool The pool.
3301	* @param pPage The page.
3302	* @param HCPhys The host physical address corresponding to the guest page.
3303	* @param GCPhys The guest physical address corresponding to HCPhys.
3304	*/
3305	static void pgmPoolTracDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhys)
3306	{
3307	/*
3308	* Walk range list.
3309	*/
3310	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3311	while (pRam)
3312	{
3313	RTGCPHYS off = GCPhys - pRam->GCPhys;
3314	if (off < pRam->cb)
3315	{
3316	/* does it match? */
3317	const unsigned iPage = off >> PAGE_SHIFT;
3318	Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3319	#ifdef LOG_ENABLED
3320	RTHCPHYS HCPhysPage = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]);
3321	Log2(("pgmPoolTracDerefGCPhys %RHp vs %RHp\n", HCPhysPage, HCPhys));
3322	#endif
3323	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3324	{
3325	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3326	return;
3327	}
3328	break;
3329	}
3330	pRam = pRam->CTX_SUFF(pNext);
3331	}
3332	AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp\n", HCPhys, GCPhys));
3333	}
3334
3335
3336	/**
3337	* Clear references to guest physical memory.
3338	*
3339	* @param pPool The pool.
3340	* @param pPage The page.
3341	* @param HCPhys The host physical address corresponding to the guest page.
3342	* @param GCPhysHint The guest physical address which may corresponding to HCPhys.
3343	*/
3344	static void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint)
3345	{
3346	Log4(("pgmPoolTracDerefGCPhysHint %RHp %RGp\n", HCPhys, GCPhysHint));
3347
3348	/*
3349	* Walk range list.
3350	*/
3351	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3352	while (pRam)
3353	{
3354	RTGCPHYS off = GCPhysHint - pRam->GCPhys;
3355	if (off < pRam->cb)
3356	{
3357	/* does it match? */
3358	const unsigned iPage = off >> PAGE_SHIFT;
3359	Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3360	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3361	{
3362	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3363	return;
3364	}
3365	break;
3366	}
3367	pRam = pRam->CTX_SUFF(pNext);
3368	}
3369
3370	/*
3371	* Damn, the hint didn't work. We'll have to do an expensive linear search.
3372	*/
3373	STAM_COUNTER_INC(&pPool->StatTrackLinearRamSearches);
3374	pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3375	while (pRam)
3376	{
3377	unsigned iPage = pRam->cb >> PAGE_SHIFT;
3378	while (iPage-- > 0)
3379	{
3380	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3381	{
3382	Log4(("pgmPoolTracDerefGCPhysHint: Linear HCPhys=%RHp GCPhysHint=%RGp GCPhysReal=%RGp\n",
3383	HCPhys, GCPhysHint, pRam->GCPhys + (iPage << PAGE_SHIFT)));
3384	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3385	return;
3386	}
3387	}
3388	pRam = pRam->CTX_SUFF(pNext);
3389	}
3390
3391	AssertFatalMsgFailed(("HCPhys=%RHp GCPhysHint=%RGp\n", HCPhys, GCPhysHint));
3392	}
3393
3394
3395	/**
3396	* Clear references to guest physical memory in a 32-bit / 32-bit page table.
3397	*
3398	* @param pPool The pool.
3399	* @param pPage The page.
3400	* @param pShwPT The shadow page table (mapping of the page).
3401	* @param pGstPT The guest page table.
3402	*/
3403	DECLINLINE(void) pgmPoolTrackDerefPT32Bit32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT, PCX86PT pGstPT)
3404	{
3405	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
3406	if (pShwPT->a[i].n.u1Present)
3407	{
3408	Log4(("pgmPoolTrackDerefPT32Bit32Bit: i=%d pte=%RX32 hint=%RX32\n",
3409	i, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
3410	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
3411	if (!--pPage->cPresent)
3412	break;
3413	}
3414	}
3415
3416
3417	/**
3418	* Clear references to guest physical memory in a PAE / 32-bit page table.
3419	*
3420	* @param pPool The pool.
3421	* @param pPage The page.
3422	* @param pShwPT The shadow page table (mapping of the page).
3423	* @param pGstPT The guest page table (just a half one).
3424	*/
3425	DECLINLINE(void) pgmPoolTrackDerefPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PT pGstPT)
3426	{
3427	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++)
3428	if (pShwPT->a[i].n.u1Present)
3429	{
3430	Log4(("pgmPoolTrackDerefPTPae32Bit: i=%d pte=%RX64 hint=%RX32\n",
3431	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
3432	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
3433	}
3434	}
3435
3436
3437	/**
3438	* Clear references to guest physical memory in a PAE / PAE page table.
3439	*
3440	* @param pPool The pool.
3441	* @param pPage The page.
3442	* @param pShwPT The shadow page table (mapping of the page).
3443	* @param pGstPT The guest page table.
3444	*/
3445	DECLINLINE(void) pgmPoolTrackDerefPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
3446	{
3447	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++)
3448	if (pShwPT->a[i].n.u1Present)
3449	{
3450	Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n",
3451	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
3452	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK);
3453	}
3454	}
3455
3456
3457	/**
3458	* Clear references to guest physical memory in a 32-bit / 4MB page table.
3459	*
3460	* @param pPool The pool.
3461	* @param pPage The page.
3462	* @param pShwPT The shadow page table (mapping of the page).
3463	*/
3464	DECLINLINE(void) pgmPoolTrackDerefPT32Bit4MB(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT)
3465	{
3466	RTGCPHYS GCPhys = pPage->GCPhys;
3467	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3468	if (pShwPT->a[i].n.u1Present)
3469	{
3470	Log4(("pgmPoolTrackDerefPT32Bit4MB: i=%d pte=%RX32 GCPhys=%RGp\n",
3471	i, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys));
3472	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys);
3473	}
3474	}
3475
3476
3477	/**
3478	* Clear references to guest physical memory in a PAE / 2/4MB page table.
3479	*
3480	* @param pPool The pool.
3481	* @param pPage The page.
3482	* @param pShwPT The shadow page table (mapping of the page).
3483	*/
3484	DECLINLINE(void) pgmPoolTrackDerefPTPaeBig(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT)
3485	{
3486	RTGCPHYS GCPhys = pPage->GCPhys;
3487	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3488	if (pShwPT->a[i].n.u1Present)
3489	{
3490	Log4(("pgmPoolTrackDerefPTPaeBig: i=%d pte=%RX64 hint=%RGp\n",
3491	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys));
3492	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys);
3493	}
3494	}
3495
3496	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
3497
3498
3499	/**
3500	* Clear references to shadowed pages in a 32 bits page directory.
3501	*
3502	* @param pPool The pool.
3503	* @param pPage The page.
3504	* @param pShwPD The shadow page directory (mapping of the page).
3505	*/
3506	DECLINLINE(void) pgmPoolTrackDerefPD(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PD pShwPD)
3507	{
3508	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3509	{
3510	if ( pShwPD->a[i].n.u1Present
3511	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
3512	)
3513	{
3514	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PG_MASK);
3515	if (pSubPage)
3516	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3517	else
3518	AssertFatalMsgFailed(("%x\n", pShwPD->a[i].u & X86_PDE_PG_MASK));
3519	}
3520	}
3521	}
3522
3523	/**
3524	* Clear references to shadowed pages in a PAE (legacy or 64 bits) page directory.
3525	*
3526	* @param pPool The pool.
3527	* @param pPage The page.
3528	* @param pShwPD The shadow page directory (mapping of the page).
3529	*/
3530	DECLINLINE(void) pgmPoolTrackDerefPDPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPAE pShwPD)
3531	{
3532	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3533	{
3534	if ( pShwPD->a[i].n.u1Present
3535	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
3536	)
3537	{
3538	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PAE_PG_MASK);
3539	if (pSubPage)
3540	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3541	else
3542	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & X86_PDE_PAE_PG_MASK));
3543	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3544	}
3545	}
3546	}
3547
3548	/**
3549	* Clear references to shadowed pages in a PAE page directory pointer table.
3550	*
3551	* @param pPool The pool.
3552	* @param pPage The page.
3553	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3554	*/
3555	DECLINLINE(void) pgmPoolTrackDerefPDPTPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
3556	{
3557	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
3558	{
3559	if ( pShwPDPT->a[i].n.u1Present
3560	&& !(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING)
3561	)
3562	{
3563	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
3564	if (pSubPage)
3565	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3566	else
3567	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
3568	}
3569	}
3570	}
3571
3572
3573	/**
3574	* Clear references to shadowed pages in a 64-bit page directory pointer table.
3575	*
3576	* @param pPool The pool.
3577	* @param pPage The page.
3578	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3579	*/
3580	DECLINLINE(void) pgmPoolTrackDerefPDPT64Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
3581	{
3582	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
3583	{
3584	Assert(!(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING));
3585	if (pShwPDPT->a[i].n.u1Present)
3586	{
3587	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
3588	if (pSubPage)
3589	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3590	else
3591	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
3592	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3593	}
3594	}
3595	}
3596
3597
3598	/**
3599	* Clear references to shadowed pages in a 64-bit level 4 page table.
3600	*
3601	* @param pPool The pool.
3602	* @param pPage The page.
3603	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
3604	*/
3605	DECLINLINE(void) pgmPoolTrackDerefPML464Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PML4 pShwPML4)
3606	{
3607	for (unsigned i = 0; i < RT_ELEMENTS(pShwPML4->a); i++)
3608	{
3609	if (pShwPML4->a[i].n.u1Present)
3610	{
3611	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPML4->a[i].u & X86_PDPE_PG_MASK);
3612	if (pSubPage)
3613	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3614	else
3615	AssertFatalMsgFailed(("%RX64\n", pShwPML4->a[i].u & X86_PML4E_PG_MASK));
3616	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3617	}
3618	}
3619	}
3620
3621
3622	/**
3623	* Clear references to shadowed pages in an EPT page table.
3624	*
3625	* @param pPool The pool.
3626	* @param pPage The page.
3627	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
3628	*/
3629	DECLINLINE(void) pgmPoolTrackDerefPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPT pShwPT)
3630	{
3631	RTGCPHYS GCPhys = pPage->GCPhys;
3632	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3633	if (pShwPT->a[i].n.u1Present)
3634	{
3635	Log4(("pgmPoolTrackDerefPTEPT: i=%d pte=%RX64 GCPhys=%RX64\n",
3636	i, pShwPT->a[i].u & EPT_PTE_PG_MASK, pPage->GCPhys));
3637	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & EPT_PTE_PG_MASK, GCPhys);
3638	}
3639	}
3640
3641
3642	/**
3643	* Clear references to shadowed pages in an EPT page directory.
3644	*
3645	* @param pPool The pool.
3646	* @param pPage The page.
3647	* @param pShwPD The shadow page directory (mapping of the page).
3648	*/
3649	DECLINLINE(void) pgmPoolTrackDerefPDEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPD pShwPD)
3650	{
3651	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3652	{
3653	if (pShwPD->a[i].n.u1Present)
3654	{
3655	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & EPT_PDE_PG_MASK);
3656	if (pSubPage)
3657	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3658	else
3659	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & EPT_PDE_PG_MASK));
3660	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3661	}
3662	}
3663	}
3664
3665
3666	/**
3667	* Clear references to shadowed pages in an EPT page directory pointer table.
3668	*
3669	* @param pPool The pool.
3670	* @param pPage The page.
3671	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3672	*/
3673	DECLINLINE(void) pgmPoolTrackDerefPDPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPDPT pShwPDPT)
3674	{
3675	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
3676	{
3677	if (pShwPDPT->a[i].n.u1Present)
3678	{
3679	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK);
3680	if (pSubPage)
3681	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3682	else
3683	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK));
3684	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3685	}
3686	}
3687	}
3688
3689
3690	/**
3691	* Clears all references made by this page.
3692	*
3693	* This includes other shadow pages and GC physical addresses.
3694	*
3695	* @param pPool The pool.
3696	* @param pPage The page.
3697	*/
3698	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3699	{
3700	/*
3701	* Map the shadow page and take action according to the page kind.
3702	*/
3703	void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
3704	switch (pPage->enmKind)
3705	{
3706	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3707	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3708	{
3709	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3710	void *pvGst;
3711	int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3712	pgmPoolTrackDerefPT32Bit32Bit(pPool, pPage, (PX86PT)pvShw, (PCX86PT)pvGst);
3713	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3714	break;
3715	}
3716
3717	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3718	{
3719	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3720	void *pvGst;
3721	int rc = PGM_GCPHYS_2_PTR_EX(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3722	pgmPoolTrackDerefPTPae32Bit(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PT)pvGst);
3723	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3724	break;
3725	}
3726
3727	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3728	{
3729	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3730	void *pvGst;
3731	int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3732	pgmPoolTrackDerefPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
3733	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3734	break;
3735	}
3736
3737	case PGMPOOLKIND_32BIT_PT_FOR_PHYS: /* treat it like a 4 MB page */
3738	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3739	{
3740	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3741	pgmPoolTrackDerefPT32Bit4MB(pPool, pPage, (PX86PT)pvShw);
3742	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3743	break;
3744	}
3745
3746	case PGMPOOLKIND_PAE_PT_FOR_PHYS: /* treat it like a 2 MB page */
3747	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3748	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3749	{
3750	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3751	pgmPoolTrackDerefPTPaeBig(pPool, pPage, (PX86PTPAE)pvShw);
3752	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3753	break;
3754	}
3755
3756	#else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
3757	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3758	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3759	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3760	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3761	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3762	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3763	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3764	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3765	break;
3766	#endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
3767
3768	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3769	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3770	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3771	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3772	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3773	case PGMPOOLKIND_PAE_PD_PHYS:
3774	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3775	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3776	pgmPoolTrackDerefPDPae(pPool, pPage, (PX86PDPAE)pvShw);
3777	break;
3778
3779	case PGMPOOLKIND_32BIT_PD_PHYS:
3780	case PGMPOOLKIND_32BIT_PD:
3781	pgmPoolTrackDerefPD(pPool, pPage, (PX86PD)pvShw);
3782	break;
3783
3784	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3785	case PGMPOOLKIND_PAE_PDPT:
3786	case PGMPOOLKIND_PAE_PDPT_PHYS:
3787	pgmPoolTrackDerefPDPTPae(pPool, pPage, (PX86PDPT)pvShw);
3788	break;
3789
3790	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3791	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3792	pgmPoolTrackDerefPDPT64Bit(pPool, pPage, (PX86PDPT)pvShw);
3793	break;
3794
3795	case PGMPOOLKIND_64BIT_PML4:
3796	pgmPoolTrackDerefPML464Bit(pPool, pPage, (PX86PML4)pvShw);
3797	break;
3798
3799	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3800	pgmPoolTrackDerefPTEPT(pPool, pPage, (PEPTPT)pvShw);
3801	break;
3802
3803	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3804	pgmPoolTrackDerefPDEPT(pPool, pPage, (PEPTPD)pvShw);
3805	break;
3806
3807	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3808	pgmPoolTrackDerefPDPTEPT(pPool, pPage, (PEPTPDPT)pvShw);
3809	break;
3810
3811	default:
3812	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
3813	}
3814
3815	/* paranoia, clear the shadow page. Remove this laser (i.e. let Alloc and ClearAll do it). */
3816	STAM_PROFILE_START(&pPool->StatZeroPage, z);
3817	ASMMemZeroPage(pvShw);
3818	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
3819	pPage->fZeroed = true;
3820	PGMPOOL_UNLOCK_PTR(pPool->CTX_SUFF(pVM), pvShw);
3821	}
3822	#endif /* PGMPOOL_WITH_USER_TRACKING */
3823
3824	/**
3825	* Flushes a pool page.
3826	*
3827	* This moves the page to the free list after removing all user references to it.
3828	*
3829	* @returns VBox status code.
3830	* @retval VINF_SUCCESS on success.
3831	* @param pPool The pool.
3832	* @param HCPhys The HC physical address of the shadow page.
3833	*/
3834	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3835	{
3836	PVM pVM = pPool->CTX_SUFF(pVM);
3837
3838	int rc = VINF_SUCCESS;
3839	STAM_PROFILE_START(&pPool->StatFlushPage, f);
3840	LogFlow(("pgmPoolFlushPage: pPage=%p:{.Key=%RHp, .idx=%d, .enmKind=%s, .GCPhys=%RGp}\n",
3841	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
3842
3843	/*
3844	* Quietly reject any attempts at flushing any of the special root pages.
3845	*/
3846	if (pPage->idx < PGMPOOL_IDX_FIRST)
3847	{
3848	AssertFailed(); /* can no longer happen */
3849	Log(("pgmPoolFlushPage: special root page, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
3850	return VINF_SUCCESS;
3851	}
3852
3853	pgmLock(pVM);
3854
3855	/*
3856	* Quietly reject any attempts at flushing the currently active shadow CR3 mapping
3857	*/
3858	if (pgmPoolIsPageLocked(&pVM->pgm.s, pPage))
3859	{
3860	AssertMsg( pPage->enmKind == PGMPOOLKIND_64BIT_PML4
3861	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT
3862	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT_FOR_32BIT
3863	\|\| pPage->enmKind == PGMPOOLKIND_32BIT_PD
3864	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD
3865	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD
3866	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD
3867	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD
3868	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
3869	("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(VMMGetCpu(pVM)), pPage->Core.Key, pPage->enmKind));
3870	Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
3871	pgmUnlock(pVM);
3872	return VINF_SUCCESS;
3873	}
3874
3875	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3876	/* Start a subset so we won't run out of mapping space. */
3877	PVMCPU pVCpu = VMMGetCpu(pVM);
3878	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
3879	#endif
3880
3881	/*
3882	* Mark the page as being in need of a ASMMemZeroPage().
3883	*/
3884	pPage->fZeroed = false;
3885
3886	#ifdef PGMPOOL_WITH_USER_TRACKING
3887	/*
3888	* Clear the page.
3889	*/
3890	pgmPoolTrackClearPageUsers(pPool, pPage);
3891	STAM_PROFILE_START(&pPool->StatTrackDeref,a);
3892	pgmPoolTrackDeref(pPool, pPage);
3893	STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
3894	#endif
3895
3896	#ifdef PGMPOOL_WITH_CACHE
3897	/*
3898	* Flush it from the cache.
3899	*/
3900	pgmPoolCacheFlushPage(pPool, pPage);
3901	#endif /* PGMPOOL_WITH_CACHE */
3902
3903	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3904	/* Heavy stuff done. */
3905	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
3906	#endif
3907
3908	#ifdef PGMPOOL_WITH_MONITORING
3909	/*
3910	* Deregistering the monitoring.
3911	*/
3912	if (pPage->fMonitored)
3913	rc = pgmPoolMonitorFlush(pPool, pPage);
3914	#endif
3915
3916	/*
3917	* Free the page.
3918	*/
3919	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
3920	pPage->iNext = pPool->iFreeHead;
3921	pPool->iFreeHead = pPage->idx;
3922	pPage->enmKind = PGMPOOLKIND_FREE;
3923	pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
3924	pPage->GCPhys = NIL_RTGCPHYS;
3925	pPage->fReusedFlushPending = false;
3926
3927	pPool->cUsedPages--;
3928	pgmUnlock(pVM);
3929	STAM_PROFILE_STOP(&pPool->StatFlushPage, f);
3930	return rc;
3931	}
3932
3933
3934	/**
3935	* Frees a usage of a pool page.
3936	*
3937	* The caller is responsible to updating the user table so that it no longer
3938	* references the shadow page.
3939	*
3940	* @param pPool The pool.
3941	* @param HCPhys The HC physical address of the shadow page.
3942	* @param iUser The shadow page pool index of the user table.
3943	* @param iUserTable The index into the user table (shadowed).
3944	*/
3945	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
3946	{
3947	PVM pVM = pPool->CTX_SUFF(pVM);
3948
3949	STAM_PROFILE_START(&pPool->StatFree, a);
3950	LogFlow(("pgmPoolFreeByPage: pPage=%p:{.Key=%RHp, .idx=%d, enmKind=%s} iUser=%#x iUserTable=%#x\n",
3951	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), iUser, iUserTable));
3952	Assert(pPage->idx >= PGMPOOL_IDX_FIRST);
3953	pgmLock(pVM);
3954	#ifdef PGMPOOL_WITH_USER_TRACKING
3955	pgmPoolTrackFreeUser(pPool, pPage, iUser, iUserTable);
3956	#endif
3957	#ifdef PGMPOOL_WITH_CACHE
3958	if (!pPage->fCached)
3959	#endif
3960	pgmPoolFlushPage(pPool, pPage);
3961	pgmUnlock(pVM);
3962	STAM_PROFILE_STOP(&pPool->StatFree, a);
3963	}
3964
3965
3966	/**
3967	* Makes one or more free page free.
3968	*
3969	* @returns VBox status code.
3970	* @retval VINF_SUCCESS on success.
3971	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
3972	*
3973	* @param pPool The pool.
3974	* @param enmKind Page table kind
3975	* @param iUser The user of the page.
3976	*/
3977	static int pgmPoolMakeMoreFreePages(PPGMPOOL pPool, PGMPOOLKIND enmKind, uint16_t iUser)
3978	{
3979	PVM pVM = pPool->CTX_SUFF(pVM);
3980
3981	LogFlow(("pgmPoolMakeMoreFreePages: iUser=%#x\n", iUser));
3982
3983	/*
3984	* If the pool isn't full grown yet, expand it.
3985	*/
3986	if ( pPool->cCurPages < pPool->cMaxPages
3987	#if defined(IN_RC)
3988	/* Hack alert: we can't deal with jumps to ring 3 when called from MapCR3 and allocating pages for PAE PDs. */
3989	&& enmKind != PGMPOOLKIND_PAE_PD_FOR_PAE_PD
3990	&& (enmKind < PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD \|\| enmKind > PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD)
3991	#endif
3992	)
3993	{
3994	STAM_PROFILE_ADV_SUSPEND(&pPool->StatAlloc, a);
3995	#ifdef IN_RING3
3996	int rc = PGMR3PoolGrow(pVM);
3997	#else
3998	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_POOL_GROW, 0);
3999	#endif
4000	if (RT_FAILURE(rc))
4001	return rc;
4002	STAM_PROFILE_ADV_RESUME(&pPool->StatAlloc, a);
4003	if (pPool->iFreeHead != NIL_PGMPOOL_IDX)
4004	return VINF_SUCCESS;
4005	}
4006
4007	#ifdef PGMPOOL_WITH_CACHE
4008	/*
4009	* Free one cached page.
4010	*/
4011	return pgmPoolCacheFreeOne(pPool, iUser);
4012	#else
4013	/*
4014	* Flush the pool.
4015	*
4016	* If we have tracking enabled, it should be possible to come up with
4017	* a cheap replacement strategy...
4018	*/
4019	/* @todo This path no longer works (CR3 root pages will be flushed)!! */
4020	AssertCompileFailed();
4021	Assert(!CPUMIsGuestInLongMode(pVM));
4022	pgmPoolFlushAllInt(pPool);
4023	return VERR_PGM_POOL_FLUSHED;
4024	#endif
4025	}
4026
4027	/**
4028	* Allocates a page from the pool.
4029	*
4030	* This page may actually be a cached page and not in need of any processing
4031	* on the callers part.
4032	*
4033	* @returns VBox status code.
4034	* @retval VINF_SUCCESS if a NEW page was allocated.
4035	* @retval VINF_PGM_CACHED_PAGE if a CACHED page was returned.
4036	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4037	* @param pVM The VM handle.
4038	* @param GCPhys The GC physical address of the page we're gonna shadow.
4039	* For 4MB and 2MB PD entries, it's the first address the
4040	* shadow PT is covering.
4041	* @param enmKind The kind of mapping.
4042	* @param enmAccess Access type for the mapping (only relevant for big pages)
4043	* @param iUser The shadow page pool index of the user table.
4044	* @param iUserTable The index into the user table (shadowed).
4045	* @param ppPage Where to store the pointer to the page. NULL is stored here on failure.
4046	*/
4047	int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
4048	{
4049	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4050	STAM_PROFILE_ADV_START(&pPool->StatAlloc, a);
4051	LogFlow(("pgmPoolAlloc: GCPhys=%RGp enmKind=%s iUser=%#x iUserTable=%#x\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable));
4052	*ppPage = NULL;
4053	/** @todo CSAM/PGMPrefetchPage messes up here during CSAMR3CheckGates
4054	* (TRPMR3SyncIDT) because of FF priority. Try fix that?
4055	* Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL)); */
4056
4057	pgmLock(pVM);
4058
4059	#ifdef PGMPOOL_WITH_CACHE
4060	if (pPool->fCacheEnabled)
4061	{
4062	int rc2 = pgmPoolCacheAlloc(pPool, GCPhys, enmKind, enmAccess, iUser, iUserTable, ppPage);
4063	if (RT_SUCCESS(rc2))
4064	{
4065	pgmUnlock(pVM);
4066	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4067	LogFlow(("pgmPoolAlloc: cached returns %Rrc ppPage=%p:{.Key=%RHp, .idx=%d}\n", rc2, ppPage, (ppPage)->Core.Key, (ppPage)->idx));
4068	return rc2;
4069	}
4070	}
4071	#endif
4072
4073	/*
4074	* Allocate a new one.
4075	*/
4076	int rc = VINF_SUCCESS;
4077	uint16_t iNew = pPool->iFreeHead;
4078	if (iNew == NIL_PGMPOOL_IDX)
4079	{
4080	rc = pgmPoolMakeMoreFreePages(pPool, enmKind, iUser);
4081	if (RT_FAILURE(rc))
4082	{
4083	pgmUnlock(pVM);
4084	Log(("pgmPoolAlloc: returns %Rrc (Free)\n", rc));
4085	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4086	return rc;
4087	}
4088	iNew = pPool->iFreeHead;
4089	AssertReleaseReturn(iNew != NIL_PGMPOOL_IDX, VERR_INTERNAL_ERROR);
4090	}
4091
4092	/* unlink the free head */
4093	PPGMPOOLPAGE pPage = &pPool->aPages[iNew];
4094	pPool->iFreeHead = pPage->iNext;
4095	pPage->iNext = NIL_PGMPOOL_IDX;
4096
4097	/*
4098	* Initialize it.
4099	*/
4100	pPool->cUsedPages++; /* physical handler registration / pgmPoolTrackFlushGCPhysPTsSlow requirement. */
4101	pPage->enmKind = enmKind;
4102	pPage->enmAccess = enmAccess;
4103	pPage->GCPhys = GCPhys;
4104	pPage->fSeenNonGlobal = false; /* Set this to 'true' to disable this feature. */
4105	pPage->fMonitored = false;
4106	pPage->fCached = false;
4107	pPage->fReusedFlushPending = false;
4108	#ifdef PGMPOOL_WITH_MONITORING
4109	pPage->cModifications = 0;
4110	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4111	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4112	#else
4113	pPage->fCR3Mix = false;
4114	#endif
4115	#ifdef PGMPOOL_WITH_USER_TRACKING
4116	pPage->cPresent = 0;
4117	pPage->iFirstPresent = ~0;
4118
4119	/*
4120	* Insert into the tracking and cache. If this fails, free the page.
4121	*/
4122	int rc3 = pgmPoolTrackInsert(pPool, pPage, GCPhys, iUser, iUserTable);
4123	if (RT_FAILURE(rc3))
4124	{
4125	pPool->cUsedPages--;
4126	pPage->enmKind = PGMPOOLKIND_FREE;
4127	pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4128	pPage->GCPhys = NIL_RTGCPHYS;
4129	pPage->iNext = pPool->iFreeHead;
4130	pPool->iFreeHead = pPage->idx;
4131	pgmUnlock(pVM);
4132	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4133	Log(("pgmPoolAlloc: returns %Rrc (Insert)\n", rc3));
4134	return rc3;
4135	}
4136	#endif /* PGMPOOL_WITH_USER_TRACKING */
4137
4138	/*
4139	* Commit the allocation, clear the page and return.
4140	*/
4141	#ifdef VBOX_WITH_STATISTICS
4142	if (pPool->cUsedPages > pPool->cUsedPagesHigh)
4143	pPool->cUsedPagesHigh = pPool->cUsedPages;
4144	#endif
4145
4146	if (!pPage->fZeroed)
4147	{
4148	STAM_PROFILE_START(&pPool->StatZeroPage, z);
4149	void *pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
4150	ASMMemZeroPage(pv);
4151	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4152	}
4153
4154	*ppPage = pPage;
4155	pgmUnlock(pVM);
4156	LogFlow(("pgmPoolAlloc: returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d, .fCached=%RTbool, .fMonitored=%RTbool}\n",
4157	rc, pPage, pPage->Core.Key, pPage->idx, pPage->fCached, pPage->fMonitored));
4158	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4159	return rc;
4160	}
4161
4162
4163	/**
4164	* Frees a usage of a pool page.
4165	*
4166	* @param pVM The VM handle.
4167	* @param HCPhys The HC physical address of the shadow page.
4168	* @param iUser The shadow page pool index of the user table.
4169	* @param iUserTable The index into the user table (shadowed).
4170	*/
4171	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable)
4172	{
4173	LogFlow(("pgmPoolFree: HCPhys=%RHp iUser=%#x iUserTable=%#x\n", HCPhys, iUser, iUserTable));
4174	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4175	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, HCPhys), iUser, iUserTable);
4176	}
4177
4178	/**
4179	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
4180	*
4181	* @returns Pointer to the shadow page structure.
4182	* @param pPool The pool.
4183	* @param HCPhys The HC physical address of the shadow page.
4184	*/
4185	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4186	{
4187	PVM pVM = pPool->CTX_SUFF(pVM);
4188
4189	/*
4190	* Look up the page.
4191	*/
4192	pgmLock(pVM);
4193	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4194	pgmUnlock(pVM);
4195
4196	AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4197	return pPage;
4198	}
4199
4200
4201	#ifdef IN_RING3
4202	/**
4203	* Flushes the entire cache.
4204	*
4205	* It will assert a global CR3 flush (FF) and assumes the caller is aware of this
4206	* and execute this CR3 flush.
4207	*
4208	* @param pPool The pool.
4209	*/
4210	void pgmR3PoolReset(PVM pVM)
4211	{
4212	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4213
4214	Assert(PGMIsLockOwner(pVM));
4215	STAM_PROFILE_START(&pPool->StatFlushAllInt, a);
4216	LogFlow(("pgmPoolFlushAllInt:\n"));
4217
4218	/*
4219	* If there are no pages in the pool, there is nothing to do.
4220	*/
4221	if (pPool->cCurPages <= PGMPOOL_IDX_FIRST)
4222	{
4223	STAM_PROFILE_STOP(&pPool->StatFlushAllInt, a);
4224	return;
4225	}
4226
4227	/*
4228	* Exit the shadow mode since we're going to clear everything,
4229	* including the root page.
4230	*/
4231	for (unsigned i=0;i<pVM->cCPUs;i++)
4232	{
4233	PVMCPU pVCpu = &pVM->aCpus[i];
4234	pgmR3ExitShadowModeBeforePoolFlush(pVM, pVCpu);
4235	}
4236
4237	/*
4238	* Nuke the free list and reinsert all pages into it.
4239	*/
4240	for (unsigned i = pPool->cCurPages - 1; i >= PGMPOOL_IDX_FIRST; i--)
4241	{
4242	PPGMPOOLPAGE pPage = &pPool->aPages[i];
4243
4244	Assert(pPage->Core.Key == MMPage2Phys(pVM, pPage->pvPageR3));
4245	#ifdef PGMPOOL_WITH_MONITORING
4246	if (pPage->fMonitored)
4247	pgmPoolMonitorFlush(pPool, pPage);
4248	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4249	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4250	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
4251	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
4252	pPage->cModifications = 0;
4253	#endif
4254	pPage->GCPhys = NIL_RTGCPHYS;
4255	pPage->enmKind = PGMPOOLKIND_FREE;
4256	pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4257	Assert(pPage->idx == i);
4258	pPage->iNext = i + 1;
4259	pPage->fZeroed = false; /* This could probably be optimized, but better safe than sorry. */
4260	pPage->fSeenNonGlobal = false;
4261	pPage->fMonitored = false;
4262	pPage->fCached = false;
4263	pPage->fReusedFlushPending = false;
4264	#ifdef PGMPOOL_WITH_USER_TRACKING
4265	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
4266	#else
4267	pPage->fCR3Mix = false;
4268	#endif
4269	#ifdef PGMPOOL_WITH_CACHE
4270	pPage->iAgeNext = NIL_PGMPOOL_IDX;
4271	pPage->iAgePrev = NIL_PGMPOOL_IDX;
4272	#endif
4273	pPage->cLocked = 0;
4274	}
4275	pPool->aPages[pPool->cCurPages - 1].iNext = NIL_PGMPOOL_IDX;
4276	pPool->iFreeHead = PGMPOOL_IDX_FIRST;
4277	pPool->cUsedPages = 0;
4278
4279	#ifdef PGMPOOL_WITH_USER_TRACKING
4280	/*
4281	* Zap and reinitialize the user records.
4282	*/
4283	pPool->cPresent = 0;
4284	pPool->iUserFreeHead = 0;
4285	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
4286	const unsigned cMaxUsers = pPool->cMaxUsers;
4287	for (unsigned i = 0; i < cMaxUsers; i++)
4288	{
4289	paUsers[i].iNext = i + 1;
4290	paUsers[i].iUser = NIL_PGMPOOL_IDX;
4291	paUsers[i].iUserTable = 0xfffffffe;
4292	}
4293	paUsers[cMaxUsers - 1].iNext = NIL_PGMPOOL_USER_INDEX;
4294	#endif
4295
4296	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4297	/*
4298	* Clear all the GCPhys links and rebuild the phys ext free list.
4299	*/
4300	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
4301	pRam;
4302	pRam = pRam->CTX_SUFF(pNext))
4303	{
4304	unsigned iPage = pRam->cb >> PAGE_SHIFT;
4305	while (iPage-- > 0)
4306	PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
4307	}
4308
4309	pPool->iPhysExtFreeHead = 0;
4310	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
4311	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
4312	for (unsigned i = 0; i < cMaxPhysExts; i++)
4313	{
4314	paPhysExts[i].iNext = i + 1;
4315	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
4316	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
4317	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
4318	}
4319	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
4320	#endif
4321
4322	#ifdef PGMPOOL_WITH_MONITORING
4323	/*
4324	* Just zap the modified list.
4325	*/
4326	pPool->cModifiedPages = 0;
4327	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
4328	#endif
4329
4330	#ifdef PGMPOOL_WITH_CACHE
4331	/*
4332	* Clear the GCPhys hash and the age list.
4333	*/
4334	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aiHash); i++)
4335	pPool->aiHash[i] = NIL_PGMPOOL_IDX;
4336	pPool->iAgeHead = NIL_PGMPOOL_IDX;
4337	pPool->iAgeTail = NIL_PGMPOOL_IDX;
4338	#endif
4339
4340	/*
4341	* Reinsert active pages into the hash and ensure monitoring chains are correct.
4342	*/
4343	for (unsigned i = PGMPOOL_IDX_FIRST_SPECIAL; i < PGMPOOL_IDX_FIRST; i++)
4344	{
4345	PPGMPOOLPAGE pPage = &pPool->aPages[i];
4346	pPage->iNext = NIL_PGMPOOL_IDX;
4347	#ifdef PGMPOOL_WITH_MONITORING
4348	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4349	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4350	pPage->cModifications = 0;
4351	/* ASSUMES that we're not sharing with any of the other special pages (safe for now). */
4352	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
4353	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
4354	if (pPage->fMonitored)
4355	{
4356	int rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
4357	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
4358	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
4359	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
4360	pPool->pszAccessHandler);
4361	AssertFatalRCSuccess(rc);
4362	# ifdef PGMPOOL_WITH_CACHE
4363	pgmPoolHashInsert(pPool, pPage);
4364	# endif
4365	}
4366	#endif
4367	#ifdef PGMPOOL_WITH_USER_TRACKING
4368	Assert(pPage->iUserHead == NIL_PGMPOOL_USER_INDEX); /* for now */
4369	#endif
4370	#ifdef PGMPOOL_WITH_CACHE
4371	Assert(pPage->iAgeNext == NIL_PGMPOOL_IDX);
4372	Assert(pPage->iAgePrev == NIL_PGMPOOL_IDX);
4373	#endif
4374	}
4375
4376	for (unsigned i=0;i<pVM->cCPUs;i++)
4377	{
4378	PVMCPU pVCpu = &pVM->aCpus[i];
4379	/*
4380	* Re-enter the shadowing mode and assert Sync CR3 FF.
4381	*/
4382	pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
4383	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4384	}
4385
4386	STAM_PROFILE_STOP(&pPool->StatFlushAllInt, a);
4387	}
4388	#endif /* IN_RING3 */
4389
4390	#ifdef LOG_ENABLED
4391	static const char *pgmPoolPoolKindToStr(uint8_t enmKind)
4392	{
4393	switch(enmKind)
4394	{
4395	case PGMPOOLKIND_INVALID:
4396	return "PGMPOOLKIND_INVALID";
4397	case PGMPOOLKIND_FREE:
4398	return "PGMPOOLKIND_FREE";
4399	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
4400	return "PGMPOOLKIND_32BIT_PT_FOR_PHYS";
4401	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4402	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT";
4403	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4404	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB";
4405	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
4406	return "PGMPOOLKIND_PAE_PT_FOR_PHYS";
4407	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4408	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_PT";
4409	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4410	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB";
4411	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4412	return "PGMPOOLKIND_PAE_PT_FOR_PAE_PT";
4413	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4414	return "PGMPOOLKIND_PAE_PT_FOR_PAE_2MB";
4415	case PGMPOOLKIND_32BIT_PD:
4416	return "PGMPOOLKIND_32BIT_PD";
4417	case PGMPOOLKIND_32BIT_PD_PHYS:
4418	return "PGMPOOLKIND_32BIT_PD_PHYS";
4419	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4420	return "PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD";
4421	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4422	return "PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD";
4423	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4424	return "PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD";
4425	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4426	return "PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD";
4427	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4428	return "PGMPOOLKIND_PAE_PD_FOR_PAE_PD";
4429	case PGMPOOLKIND_PAE_PD_PHYS:
4430	return "PGMPOOLKIND_PAE_PD_PHYS";
4431	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4432	return "PGMPOOLKIND_PAE_PDPT_FOR_32BIT";
4433	case PGMPOOLKIND_PAE_PDPT:
4434	return "PGMPOOLKIND_PAE_PDPT";
4435	case PGMPOOLKIND_PAE_PDPT_PHYS:
4436	return "PGMPOOLKIND_PAE_PDPT_PHYS";
4437	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4438	return "PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT";
4439	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4440	return "PGMPOOLKIND_64BIT_PDPT_FOR_PHYS";
4441	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4442	return "PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD";
4443	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4444	return "PGMPOOLKIND_64BIT_PD_FOR_PHYS";
4445	case PGMPOOLKIND_64BIT_PML4:
4446	return "PGMPOOLKIND_64BIT_PML4";
4447	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4448	return "PGMPOOLKIND_EPT_PDPT_FOR_PHYS";
4449	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4450	return "PGMPOOLKIND_EPT_PD_FOR_PHYS";
4451	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4452	return "PGMPOOLKIND_EPT_PT_FOR_PHYS";
4453	case PGMPOOLKIND_ROOT_NESTED:
4454	return "PGMPOOLKIND_ROOT_NESTED";
4455	}
4456	return "Unknown kind!";
4457	}
4458	#endif /* LOG_ENABLED*/

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp@ 20136

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