PGMAllPool.cpp@ 20135

Last change on this file since 20135 was 20135, checked in by vboxsync, 16 years ago
Prevent reuse of cached larged pages with different access attributes.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 161.9 KB

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1	/* $Id: PGMAllPool.cpp 20135 2009-05-29 07:44:12Z vboxsync $ */
2	/** @file
3	* PGM Shadow Page Pool.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.215389.xyz. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM_POOL
27	#include <VBox/pgm.h>
28	#include <VBox/mm.h>
29	#include <VBox/em.h>
30	#include <VBox/cpum.h>
31	#ifdef IN_RC
32	# include <VBox/patm.h>
33	#endif
34	#include "PGMInternal.h"
35	#include <VBox/vm.h>
36	#include <VBox/disopcode.h>
37	#include <VBox/hwacc_vmx.h>
38
39	#include <VBox/log.h>
40	#include <VBox/err.h>
41	#include <iprt/asm.h>
42	#include <iprt/string.h>
43
44
45	/*******************************************************************************
46	* Internal Functions *
47	*******************************************************************************/
48	__BEGIN_DECLS
49	static void pgmPoolFlushAllInt(PPGMPOOL pPool);
50	#ifdef PGMPOOL_WITH_USER_TRACKING
51	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind);
52	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind);
53	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
54	#endif
55	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
56	static void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint);
57	#endif
58	#ifdef PGMPOOL_WITH_CACHE
59	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
60	#endif
61	#ifdef PGMPOOL_WITH_MONITORING
62	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
63	#endif
64	#ifndef IN_RING3
65	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
66	#endif
67	#ifdef LOG_ENABLED
68	static const char *pgmPoolPoolKindToStr(uint8_t enmKind);
69	#endif
70
71	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
72	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
73	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
74	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
75	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
76	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
77
78	__END_DECLS
79
80
81	/**
82	* Checks if the specified page pool kind is for a 4MB or 2MB guest page.
83	*
84	* @returns true if it's the shadow of a 4MB or 2MB guest page, otherwise false.
85	* @param enmKind The page kind.
86	*/
87	DECLINLINE(bool) pgmPoolIsBigPage(PGMPOOLKIND enmKind)
88	{
89	switch (enmKind)
90	{
91	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
92	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
93	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
94	return true;
95	default:
96	return false;
97	}
98	}
99
100	/** @def PGMPOOL_PAGE_2_LOCKED_PTR
101	* Maps a pool page pool into the current context and lock it (RC only).
102	*
103	* @returns VBox status code.
104	* @param pVM The VM handle.
105	* @param pPage The pool page.
106	*
107	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
108	* small page window employeed by that function. Be careful.
109	* @remark There is no need to assert on the result.
110	*/
111	#if defined(IN_RC)
112	DECLINLINE(void *) PGMPOOL_PAGE_2_LOCKED_PTR(PVM pVM, PPGMPOOLPAGE pPage)
113	{
114	void *pv = pgmPoolMapPageInlined(&pVM->pgm.s, pPage);
115
116	/* Make sure the dynamic mapping will not be reused. */
117	if (pv)
118	PGMDynLockHCPage(pVM, (uint8_t *)pv);
119
120	return pv;
121	}
122	#else
123	# define PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage) PGMPOOL_PAGE_2_PTR(pVM, pPage)
124	#endif
125
126	/** @def PGMPOOL_UNLOCK_PTR
127	* Unlock a previously locked dynamic caching (RC only).
128	*
129	* @returns VBox status code.
130	* @param pVM The VM handle.
131	* @param pPage The pool page.
132	*
133	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
134	* small page window employeed by that function. Be careful.
135	* @remark There is no need to assert on the result.
136	*/
137	#if defined(IN_RC)
138	DECLINLINE(void) PGMPOOL_UNLOCK_PTR(PVM pVM, void *pvPage)
139	{
140	if (pvPage)
141	PGMDynUnlockHCPage(pVM, (uint8_t *)pvPage);
142	}
143	#else
144	# define PGMPOOL_UNLOCK_PTR(pVM, pPage) do {} while (0)
145	#endif
146
147
148	#ifdef PGMPOOL_WITH_MONITORING
149	/**
150	* Determin the size of a write instruction.
151	* @returns number of bytes written.
152	* @param pDis The disassembler state.
153	*/
154	static unsigned pgmPoolDisasWriteSize(PDISCPUSTATE pDis)
155	{
156	/*
157	* This is very crude and possibly wrong for some opcodes,
158	* but since it's not really supposed to be called we can
159	* probably live with that.
160	*/
161	return DISGetParamSize(pDis, &pDis->param1);
162	}
163
164
165	/**
166	* Flushes a chain of pages sharing the same access monitor.
167	*
168	* @returns VBox status code suitable for scheduling.
169	* @param pPool The pool.
170	* @param pPage A page in the chain.
171	*/
172	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
173	{
174	LogFlow(("pgmPoolMonitorChainFlush: Flush page %RGp type=%d\n", pPage->GCPhys, pPage->enmKind));
175
176	/*
177	* Find the list head.
178	*/
179	uint16_t idx = pPage->idx;
180	if (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
181	{
182	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
183	{
184	idx = pPage->iMonitoredPrev;
185	Assert(idx != pPage->idx);
186	pPage = &pPool->aPages[idx];
187	}
188	}
189
190	/*
191	* Iterate the list flushing each shadow page.
192	*/
193	int rc = VINF_SUCCESS;
194	for (;;)
195	{
196	idx = pPage->iMonitoredNext;
197	Assert(idx != pPage->idx);
198	if (pPage->idx >= PGMPOOL_IDX_FIRST)
199	{
200	int rc2 = pgmPoolFlushPage(pPool, pPage);
201	AssertRC(rc2);
202	}
203	/* next */
204	if (idx == NIL_PGMPOOL_IDX)
205	break;
206	pPage = &pPool->aPages[idx];
207	}
208	return rc;
209	}
210
211
212	/**
213	* Wrapper for getting the current context pointer to the entry being modified.
214	*
215	* @returns VBox status code suitable for scheduling.
216	* @param pVM VM Handle.
217	* @param pvDst Destination address
218	* @param pvSrc Source guest virtual address.
219	* @param GCPhysSrc The source guest physical address.
220	* @param cb Size of data to read
221	*/
222	DECLINLINE(int) pgmPoolPhysSimpleReadGCPhys(PVM pVM, void *pvDst, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvSrc, RTGCPHYS GCPhysSrc, size_t cb)
223	{
224	#if defined(IN_RING3)
225	memcpy(pvDst, (RTHCPTR)((uintptr_t)pvSrc & ~(RTHCUINTPTR)(cb - 1)), cb);
226	return VINF_SUCCESS;
227	#else
228	/* @todo in RC we could attempt to use the virtual address, although this can cause many faults (PAE Windows XP guest). */
229	return PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysSrc & ~(RTGCPHYS)(cb - 1), cb);
230	#endif
231	}
232
233	/**
234	* Process shadow entries before they are changed by the guest.
235	*
236	* For PT entries we will clear them. For PD entries, we'll simply check
237	* for mapping conflicts and set the SyncCR3 FF if found.
238	*
239	* @param pVCpu VMCPU handle
240	* @param pPool The pool.
241	* @param pPage The head page.
242	* @param GCPhysFault The guest physical fault address.
243	* @param uAddress In R0 and GC this is the guest context fault address (flat).
244	* In R3 this is the host context 'fault' address.
245	* @param pCpu The disassembler state for figuring out the write size.
246	* This need not be specified if the caller knows we won't do cross entry accesses.
247	*/
248	void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu)
249	{
250	Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
251	const unsigned off = GCPhysFault & PAGE_OFFSET_MASK;
252	const unsigned cbWrite = (pCpu) ? pgmPoolDisasWriteSize(pCpu) : 0;
253	PVM pVM = pPool->CTX_SUFF(pVM);
254
255	LogFlow(("pgmPoolMonitorChainChanging: %RGv phys=%RGp kind=%s cbWrite=%d\n", (RTGCPTR)pvAddress, GCPhysFault, pgmPoolPoolKindToStr(pPage->enmKind), cbWrite));
256	for (;;)
257	{
258	union
259	{
260	void *pv;
261	PX86PT pPT;
262	PX86PTPAE pPTPae;
263	PX86PD pPD;
264	PX86PDPAE pPDPae;
265	PX86PDPT pPDPT;
266	PX86PML4 pPML4;
267	} uShw;
268
269	uShw.pv = NULL;
270	switch (pPage->enmKind)
271	{
272	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
273	{
274	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
275	const unsigned iShw = off / sizeof(X86PTE);
276	LogFlow(("PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT iShw=%x\n", iShw));
277	if (uShw.pPT->a[iShw].n.u1Present)
278	{
279	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
280	X86PTE GstPte;
281
282	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
283	AssertRC(rc);
284	Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
285	pgmPoolTracDerefGCPhysHint(pPool, pPage,
286	uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK,
287	GstPte.u & X86_PTE_PG_MASK);
288	# endif
289	ASMAtomicWriteSize(&uShw.pPT->a[iShw], 0);
290	}
291	break;
292	}
293
294	/* page/2 sized */
295	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
296	{
297	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
298	if (!((off ^ pPage->GCPhys) & (PAGE_SIZE / 2)))
299	{
300	const unsigned iShw = (off / sizeof(X86PTE)) & (X86_PG_PAE_ENTRIES - 1);
301	LogFlow(("PGMPOOLKIND_PAE_PT_FOR_32BIT_PT iShw=%x\n", iShw));
302	if (uShw.pPTPae->a[iShw].n.u1Present)
303	{
304	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
305	X86PTE GstPte;
306	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
307	AssertRC(rc);
308
309	Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
310	pgmPoolTracDerefGCPhysHint(pPool, pPage,
311	uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
312	GstPte.u & X86_PTE_PG_MASK);
313	# endif
314	ASMAtomicWriteSize(&uShw.pPTPae->a[iShw], 0);
315	}
316	}
317	break;
318	}
319
320	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
321	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
322	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
323	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
324	{
325	unsigned iGst = off / sizeof(X86PDE);
326	unsigned iShwPdpt = iGst / 256;
327	unsigned iShw = (iGst % 256) * 2;
328	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
329
330	LogFlow(("pgmPoolMonitorChainChanging PAE for 32 bits: iGst=%x iShw=%x idx = %d page idx=%d\n", iGst, iShw, iShwPdpt, pPage->enmKind - PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD));
331	if (iShwPdpt == pPage->enmKind - (unsigned)PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD)
332	{
333	for (unsigned i = 0; i < 2; i++)
334	{
335	# ifndef IN_RING0
336	if ((uShw.pPDPae->a[iShw + i].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
337	{
338	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
339	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
340	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw=%#x!\n", iShwPdpt, iShw+i));
341	break;
342	}
343	else
344	# endif /* !IN_RING0 */
345	if (uShw.pPDPae->a[iShw+i].n.u1Present)
346	{
347	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw+i, uShw.pPDPae->a[iShw+i].u));
348	pgmPoolFree(pVM,
349	uShw.pPDPae->a[iShw+i].u & X86_PDE_PAE_PG_MASK,
350	pPage->idx,
351	iShw + i);
352	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw+i], 0);
353	}
354
355	/* paranoia / a bit assumptive. */
356	if ( pCpu
357	&& (off & 3)
358	&& (off & 3) + cbWrite > 4)
359	{
360	const unsigned iShw2 = iShw + 2 + i;
361	if (iShw2 < RT_ELEMENTS(uShw.pPDPae->a))
362	{
363	# ifndef IN_RING0
364	if ((uShw.pPDPae->a[iShw2].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
365	{
366	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
367	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
368	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw2=%#x!\n", iShwPdpt, iShw2));
369	break;
370	}
371	else
372	# endif /* !IN_RING0 */
373	if (uShw.pPDPae->a[iShw2].n.u1Present)
374	{
375	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
376	pgmPoolFree(pVM,
377	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
378	pPage->idx,
379	iShw2);
380	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
381	}
382	}
383	}
384	}
385	}
386	break;
387	}
388
389	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
390	{
391	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
392	const unsigned iShw = off / sizeof(X86PTEPAE);
393	if (uShw.pPTPae->a[iShw].n.u1Present)
394	{
395	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
396	X86PTEPAE GstPte;
397	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
398	AssertRC(rc);
399
400	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
401	pgmPoolTracDerefGCPhysHint(pPool, pPage,
402	uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
403	GstPte.u & X86_PTE_PAE_PG_MASK);
404	# endif
405	ASMAtomicWriteSize(&uShw.pPTPae->a[iShw].u, 0);
406	}
407
408	/* paranoia / a bit assumptive. */
409	if ( pCpu
410	&& (off & 7)
411	&& (off & 7) + cbWrite > sizeof(X86PTEPAE))
412	{
413	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTEPAE);
414	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPTPae->a));
415
416	if (uShw.pPTPae->a[iShw2].n.u1Present)
417	{
418	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
419	X86PTEPAE GstPte;
420	# ifdef IN_RING3
421	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, (RTHCPTR)((RTHCUINTPTR)pvAddress + sizeof(GstPte)), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
422	# else
423	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress + sizeof(GstPte), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
424	# endif
425	AssertRC(rc);
426	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
427	pgmPoolTracDerefGCPhysHint(pPool, pPage,
428	uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK,
429	GstPte.u & X86_PTE_PAE_PG_MASK);
430	# endif
431	ASMAtomicWriteSize(&uShw.pPTPae->a[iShw2].u ,0);
432	}
433	}
434	break;
435	}
436
437	case PGMPOOLKIND_32BIT_PD:
438	{
439	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
440	const unsigned iShw = off / sizeof(X86PTE); // ASSUMING 32-bit guest paging!
441
442	LogFlow(("pgmPoolMonitorChainChanging: PGMPOOLKIND_32BIT_PD %x\n", iShw));
443	# ifndef IN_RING0
444	if (uShw.pPD->a[iShw].u & PGM_PDFLAGS_MAPPING)
445	{
446	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
447	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
448	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
449	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
450	break;
451	}
452	# endif /* !IN_RING0 */
453	# ifndef IN_RING0
454	else
455	# endif /* !IN_RING0 */
456	{
457	if (uShw.pPD->a[iShw].n.u1Present)
458	{
459	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
460	pgmPoolFree(pVM,
461	uShw.pPD->a[iShw].u & X86_PDE_PAE_PG_MASK,
462	pPage->idx,
463	iShw);
464	ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
465	}
466	}
467	/* paranoia / a bit assumptive. */
468	if ( pCpu
469	&& (off & 3)
470	&& (off & 3) + cbWrite > sizeof(X86PTE))
471	{
472	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTE);
473	if ( iShw2 != iShw
474	&& iShw2 < RT_ELEMENTS(uShw.pPD->a))
475	{
476	# ifndef IN_RING0
477	if (uShw.pPD->a[iShw2].u & PGM_PDFLAGS_MAPPING)
478	{
479	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
480	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
481	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
482	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
483	break;
484	}
485	# endif /* !IN_RING0 */
486	# ifndef IN_RING0
487	else
488	# endif /* !IN_RING0 */
489	{
490	if (uShw.pPD->a[iShw2].n.u1Present)
491	{
492	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPD->a[iShw2].u));
493	pgmPoolFree(pVM,
494	uShw.pPD->a[iShw2].u & X86_PDE_PAE_PG_MASK,
495	pPage->idx,
496	iShw2);
497	ASMAtomicWriteSize(&uShw.pPD->a[iShw2].u, 0);
498	}
499	}
500	}
501	}
502	#if 0 /* useful when running PGMAssertCR3(), a bit too troublesome for general use (TLBs). */
503	if ( uShw.pPD->a[iShw].n.u1Present
504	&& !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
505	{
506	LogFlow(("pgmPoolMonitorChainChanging: iShw=%#x: %RX32 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
507	# ifdef IN_RC /* TLB load - we're pushing things a bit... */
508	ASMProbeReadByte(pvAddress);
509	# endif
510	pgmPoolFree(pVM, uShw.pPD->a[iShw].u & X86_PDE_PG_MASK, pPage->idx, iShw);
511	ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
512	}
513	#endif
514	break;
515	}
516
517	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
518	{
519	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
520	const unsigned iShw = off / sizeof(X86PDEPAE);
521	#ifndef IN_RING0
522	if (uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING)
523	{
524	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
525	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
526	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
527	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
528	break;
529	}
530	#endif /* !IN_RING0 */
531	/*
532	* Causes trouble when the guest uses a PDE to refer to the whole page table level
533	* structure. (Invalidate here; faults later on when it tries to change the page
534	* table entries -> recheck; probably only applies to the RC case.)
535	*/
536	# ifndef IN_RING0
537	else
538	# endif /* !IN_RING0 */
539	{
540	if (uShw.pPDPae->a[iShw].n.u1Present)
541	{
542	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
543	pgmPoolFree(pVM,
544	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
545	pPage->idx,
546	iShw);
547	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
548	}
549	}
550	/* paranoia / a bit assumptive. */
551	if ( pCpu
552	&& (off & 7)
553	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
554	{
555	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
556	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
557
558	#ifndef IN_RING0
559	if ( iShw2 != iShw
560	&& uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING)
561	{
562	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
563	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
564	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
565	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
566	break;
567	}
568	#endif /* !IN_RING0 */
569	# ifndef IN_RING0
570	else
571	# endif /* !IN_RING0 */
572	if (uShw.pPDPae->a[iShw2].n.u1Present)
573	{
574	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
575	pgmPoolFree(pVM,
576	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
577	pPage->idx,
578	iShw2);
579	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
580	}
581	}
582	break;
583	}
584
585	case PGMPOOLKIND_PAE_PDPT:
586	{
587	/*
588	* Hopefully this doesn't happen very often:
589	* - touching unused parts of the page
590	* - messing with the bits of pd pointers without changing the physical address
591	*/
592	/* PDPT roots are not page aligned; 32 byte only! */
593	const unsigned offPdpt = GCPhysFault - pPage->GCPhys;
594
595	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
596	const unsigned iShw = offPdpt / sizeof(X86PDPE);
597	if (iShw < X86_PG_PAE_PDPE_ENTRIES) /* don't use RT_ELEMENTS(uShw.pPDPT->a), because that's for long mode only */
598	{
599	# ifndef IN_RING0
600	if (uShw.pPDPT->a[iShw].u & PGM_PLXFLAGS_MAPPING)
601	{
602	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
603	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
604	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
605	LogFlow(("pgmPoolMonitorChainChanging: Detected pdpt conflict at iShw=%#x!\n", iShw));
606	break;
607	}
608	# endif /* !IN_RING0 */
609	# ifndef IN_RING0
610	else
611	# endif /* !IN_RING0 */
612	if (uShw.pPDPT->a[iShw].n.u1Present)
613	{
614	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
615	pgmPoolFree(pVM,
616	uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK,
617	pPage->idx,
618	iShw);
619	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
620	}
621
622	/* paranoia / a bit assumptive. */
623	if ( pCpu
624	&& (offPdpt & 7)
625	&& (offPdpt & 7) + cbWrite > sizeof(X86PDPE))
626	{
627	const unsigned iShw2 = (offPdpt + cbWrite - 1) / sizeof(X86PDPE);
628	if ( iShw2 != iShw
629	&& iShw2 < X86_PG_PAE_PDPE_ENTRIES)
630	{
631	# ifndef IN_RING0
632	if (uShw.pPDPT->a[iShw2].u & PGM_PLXFLAGS_MAPPING)
633	{
634	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
635	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
636	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
637	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
638	break;
639	}
640	# endif /* !IN_RING0 */
641	# ifndef IN_RING0
642	else
643	# endif /* !IN_RING0 */
644	if (uShw.pPDPT->a[iShw2].n.u1Present)
645	{
646	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
647	pgmPoolFree(pVM,
648	uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK,
649	pPage->idx,
650	iShw2);
651	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
652	}
653	}
654	}
655	}
656	break;
657	}
658
659	#ifndef IN_RC
660	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
661	{
662	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
663	const unsigned iShw = off / sizeof(X86PDEPAE);
664	Assert(!(uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING));
665	if (uShw.pPDPae->a[iShw].n.u1Present)
666	{
667	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
668	pgmPoolFree(pVM,
669	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
670	pPage->idx,
671	iShw);
672	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
673	}
674	/* paranoia / a bit assumptive. */
675	if ( pCpu
676	&& (off & 7)
677	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
678	{
679	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
680	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
681
682	Assert(!(uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING));
683	if (uShw.pPDPae->a[iShw2].n.u1Present)
684	{
685	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
686	pgmPoolFree(pVM,
687	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
688	pPage->idx,
689	iShw2);
690	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
691	}
692	}
693	break;
694	}
695
696	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
697	{
698	/*
699	* Hopefully this doesn't happen very often:
700	* - messing with the bits of pd pointers without changing the physical address
701	*/
702	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
703	{
704	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
705	const unsigned iShw = off / sizeof(X86PDPE);
706	if (uShw.pPDPT->a[iShw].n.u1Present)
707	{
708	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
709	pgmPoolFree(pVM, uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK, pPage->idx, iShw);
710	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
711	}
712	/* paranoia / a bit assumptive. */
713	if ( pCpu
714	&& (off & 7)
715	&& (off & 7) + cbWrite > sizeof(X86PDPE))
716	{
717	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDPE);
718	if (uShw.pPDPT->a[iShw2].n.u1Present)
719	{
720	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
721	pgmPoolFree(pVM, uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK, pPage->idx, iShw2);
722	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
723	}
724	}
725	}
726	break;
727	}
728
729	case PGMPOOLKIND_64BIT_PML4:
730	{
731	/*
732	* Hopefully this doesn't happen very often:
733	* - messing with the bits of pd pointers without changing the physical address
734	*/
735	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
736	{
737	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
738	const unsigned iShw = off / sizeof(X86PDPE);
739	if (uShw.pPML4->a[iShw].n.u1Present)
740	{
741	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPML4->a[iShw].u));
742	pgmPoolFree(pVM, uShw.pPML4->a[iShw].u & X86_PML4E_PG_MASK, pPage->idx, iShw);
743	ASMAtomicWriteSize(&uShw.pPML4->a[iShw].u, 0);
744	}
745	/* paranoia / a bit assumptive. */
746	if ( pCpu
747	&& (off & 7)
748	&& (off & 7) + cbWrite > sizeof(X86PDPE))
749	{
750	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PML4E);
751	if (uShw.pPML4->a[iShw2].n.u1Present)
752	{
753	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPML4->a[iShw2].u));
754	pgmPoolFree(pVM, uShw.pPML4->a[iShw2].u & X86_PML4E_PG_MASK, pPage->idx, iShw2);
755	ASMAtomicWriteSize(&uShw.pPML4->a[iShw2].u, 0);
756	}
757	}
758	}
759	break;
760	}
761	#endif /* IN_RING0 */
762
763	default:
764	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
765	}
766	PGMPOOL_UNLOCK_PTR(pVM, uShw.pv);
767
768	/* next */
769	if (pPage->iMonitoredNext == NIL_PGMPOOL_IDX)
770	return;
771	pPage = &pPool->aPages[pPage->iMonitoredNext];
772	}
773	}
774
775	# ifndef IN_RING3
776	/**
777	* Checks if a access could be a fork operation in progress.
778	*
779	* Meaning, that the guest is setuping up the parent process for Copy-On-Write.
780	*
781	* @returns true if it's likly that we're forking, otherwise false.
782	* @param pPool The pool.
783	* @param pCpu The disassembled instruction.
784	* @param offFault The access offset.
785	*/
786	DECLINLINE(bool) pgmPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE pCpu, unsigned offFault)
787	{
788	/*
789	* i386 linux is using btr to clear X86_PTE_RW.
790	* The functions involved are (2.6.16 source inspection):
791	* clear_bit
792	* ptep_set_wrprotect
793	* copy_one_pte
794	* copy_pte_range
795	* copy_pmd_range
796	* copy_pud_range
797	* copy_page_range
798	* dup_mmap
799	* dup_mm
800	* copy_mm
801	* copy_process
802	* do_fork
803	*/
804	if ( pCpu->pCurInstr->opcode == OP_BTR
805	&& !(offFault & 4)
806	/** @todo Validate that the bit index is X86_PTE_RW. */
807	)
808	{
809	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,Fork));
810	return true;
811	}
812	return false;
813	}
814
815
816	/**
817	* Determine whether the page is likely to have been reused.
818	*
819	* @returns true if we consider the page as being reused for a different purpose.
820	* @returns false if we consider it to still be a paging page.
821	* @param pVM VM Handle.
822	* @param pRegFrame Trap register frame.
823	* @param pCpu The disassembly info for the faulting instruction.
824	* @param pvFault The fault address.
825	*
826	* @remark The REP prefix check is left to the caller because of STOSD/W.
827	*/
828	DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR pvFault)
829	{
830	#ifndef IN_RC
831	/** @todo could make this general, faulting close to rsp should be safe reuse heuristic. */
832	if ( HWACCMHasPendingIrq(pVM)
833	&& (pRegFrame->rsp - pvFault) < 32)
834	{
835	/* Fault caused by stack writes while trying to inject an interrupt event. */
836	Log(("pgmPoolMonitorIsReused: reused %RGv for interrupt stack (rsp=%RGv).\n", pvFault, pRegFrame->rsp));
837	return true;
838	}
839	#else
840	NOREF(pVM); NOREF(pvFault);
841	#endif
842
843	switch (pCpu->pCurInstr->opcode)
844	{
845	/* call implies the actual push of the return address faulted */
846	case OP_CALL:
847	Log4(("pgmPoolMonitorIsReused: CALL\n"));
848	return true;
849	case OP_PUSH:
850	Log4(("pgmPoolMonitorIsReused: PUSH\n"));
851	return true;
852	case OP_PUSHF:
853	Log4(("pgmPoolMonitorIsReused: PUSHF\n"));
854	return true;
855	case OP_PUSHA:
856	Log4(("pgmPoolMonitorIsReused: PUSHA\n"));
857	return true;
858	case OP_FXSAVE:
859	Log4(("pgmPoolMonitorIsReused: FXSAVE\n"));
860	return true;
861	case OP_MOVNTI: /* solaris - block_zero_no_xmm */
862	Log4(("pgmPoolMonitorIsReused: MOVNTI\n"));
863	return true;
864	case OP_MOVNTDQ: /* solaris - hwblkclr & hwblkpagecopy */
865	Log4(("pgmPoolMonitorIsReused: MOVNTDQ\n"));
866	return true;
867	case OP_MOVSWD:
868	case OP_STOSWD:
869	if ( pCpu->prefix == (PREFIX_REP\|PREFIX_REX)
870	&& pRegFrame->rcx >= 0x40
871	)
872	{
873	Assert(pCpu->mode == CPUMODE_64BIT);
874
875	Log(("pgmPoolMonitorIsReused: OP_STOSQ\n"));
876	return true;
877	}
878	return false;
879	}
880	if ( (pCpu->param1.flags & USE_REG_GEN32)
881	&& (pCpu->param1.base.reg_gen == USE_REG_ESP))
882	{
883	Log4(("pgmPoolMonitorIsReused: ESP\n"));
884	return true;
885	}
886
887	return false;
888	}
889
890
891	/**
892	* Flushes the page being accessed.
893	*
894	* @returns VBox status code suitable for scheduling.
895	* @param pVM The VM handle.
896	* @param pVCpu The VMCPU handle.
897	* @param pPool The pool.
898	* @param pPage The pool page (head).
899	* @param pCpu The disassembly of the write instruction.
900	* @param pRegFrame The trap register frame.
901	* @param GCPhysFault The fault address as guest physical address.
902	* @param pvFault The fault address.
903	*/
904	static int pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
905	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
906	{
907	/*
908	* First, do the flushing.
909	*/
910	int rc = pgmPoolMonitorChainFlush(pPool, pPage);
911
912	/*
913	* Emulate the instruction (xp/w2k problem, requires pc/cr2/sp detection).
914	*/
915	uint32_t cbWritten;
916	int rc2 = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, pvFault, &cbWritten);
917	if (RT_SUCCESS(rc2))
918	pRegFrame->rip += pCpu->opsize;
919	else if (rc2 == VERR_EM_INTERPRETER)
920	{
921	#ifdef IN_RC
922	if (PATMIsPatchGCAddr(pVM, (RTRCPTR)pRegFrame->eip))
923	{
924	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for patch code %04x:%RGv, ignoring.\n",
925	pRegFrame->cs, (RTGCPTR)pRegFrame->eip));
926	rc = VINF_SUCCESS;
927	STAM_COUNTER_INC(&pPool->StatMonitorRZIntrFailPatch2);
928	}
929	else
930	#endif
931	{
932	rc = VINF_EM_RAW_EMULATE_INSTR;
933	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
934	}
935	}
936	else
937	rc = rc2;
938
939	/* See use in pgmPoolAccessHandlerSimple(). */
940	PGM_INVL_VCPU_TLBS(pVCpu);
941
942	LogFlow(("pgmPoolAccessHandlerPT: returns %Rrc (flushed)\n", rc));
943	return rc;
944
945	}
946
947
948	/**
949	* Handles the STOSD write accesses.
950	*
951	* @returns VBox status code suitable for scheduling.
952	* @param pVM The VM handle.
953	* @param pPool The pool.
954	* @param pPage The pool page (head).
955	* @param pCpu The disassembly of the write instruction.
956	* @param pRegFrame The trap register frame.
957	* @param GCPhysFault The fault address as guest physical address.
958	* @param pvFault The fault address.
959	*/
960	DECLINLINE(int) pgmPoolAccessHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
961	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
962	{
963	Assert(pCpu->mode == CPUMODE_32BIT);
964
965	Log3(("pgmPoolAccessHandlerSTOSD\n"));
966
967	/*
968	* Increment the modification counter and insert it into the list
969	* of modified pages the first time.
970	*/
971	if (!pPage->cModifications++)
972	pgmPoolMonitorModifiedInsert(pPool, pPage);
973
974	/*
975	* Execute REP STOSD.
976	*
977	* This ASSUMES that we're not invoked by Trap0e on in a out-of-sync
978	* write situation, meaning that it's safe to write here.
979	*/
980	PVMCPU pVCpu = VMMGetCpu(pPool->CTX_SUFF(pVM));
981	RTGCUINTPTR pu32 = (RTGCUINTPTR)pvFault;
982	while (pRegFrame->ecx)
983	{
984	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
985	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
986	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
987	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
988	#else
989	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
990	#endif
991	#ifdef IN_RC
992	(uint32_t )pu32 = pRegFrame->eax;
993	#else
994	PGMPhysSimpleWriteGCPhys(pVM, GCPhysFault, &pRegFrame->eax, 4);
995	#endif
996	pu32 += 4;
997	GCPhysFault += 4;
998	pRegFrame->edi += 4;
999	pRegFrame->ecx--;
1000	}
1001	pRegFrame->rip += pCpu->opsize;
1002
1003	#ifdef IN_RC
1004	/* See use in pgmPoolAccessHandlerSimple(). */
1005	PGM_INVL_VCPU_TLBS(pVCpu);
1006	#endif
1007
1008	LogFlow(("pgmPoolAccessHandlerSTOSD: returns\n"));
1009	return VINF_SUCCESS;
1010	}
1011
1012
1013	/**
1014	* Handles the simple write accesses.
1015	*
1016	* @returns VBox status code suitable for scheduling.
1017	* @param pVM The VM handle.
1018	* @param pVCpu The VMCPU handle.
1019	* @param pPool The pool.
1020	* @param pPage The pool page (head).
1021	* @param pCpu The disassembly of the write instruction.
1022	* @param pRegFrame The trap register frame.
1023	* @param GCPhysFault The fault address as guest physical address.
1024	* @param pvFault The fault address.
1025	*/
1026	DECLINLINE(int) pgmPoolAccessHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
1027	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
1028	{
1029	Log3(("pgmPoolAccessHandlerSimple\n"));
1030	/*
1031	* Increment the modification counter and insert it into the list
1032	* of modified pages the first time.
1033	*/
1034	if (!pPage->cModifications++)
1035	pgmPoolMonitorModifiedInsert(pPool, pPage);
1036
1037	/*
1038	* Clear all the pages. ASSUMES that pvFault is readable.
1039	*/
1040	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1041	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
1042	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pCpu);
1043	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
1044	#else
1045	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pCpu);
1046	#endif
1047
1048	/*
1049	* Interpret the instruction.
1050	*/
1051	uint32_t cb;
1052	int rc = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, pvFault, &cb);
1053	if (RT_SUCCESS(rc))
1054	pRegFrame->rip += pCpu->opsize;
1055	else if (rc == VERR_EM_INTERPRETER)
1056	{
1057	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n",
1058	pRegFrame->cs, (RTGCPTR)pRegFrame->rip, pCpu->pCurInstr->opcode));
1059	rc = VINF_EM_RAW_EMULATE_INSTR;
1060	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
1061	}
1062
1063	#ifdef IN_RC
1064	/*
1065	* Quick hack, with logging enabled we're getting stale
1066	* code TLBs but no data TLB for EIP and crash in EMInterpretDisasOne.
1067	* Flushing here is BAD and expensive, I think EMInterpretDisasOne will
1068	* have to be fixed to support this. But that'll have to wait till next week.
1069	*
1070	* An alternative is to keep track of the changed PTEs together with the
1071	* GCPhys from the guest PT. This may proove expensive though.
1072	*
1073	* At the moment, it's VITAL that it's done AFTER the instruction interpreting
1074	* because we need the stale TLBs in some cases (XP boot). This MUST be fixed properly!
1075	*/
1076	PGM_INVL_VCPU_TLBS(pVCpu);
1077	#endif
1078
1079	LogFlow(("pgmPoolAccessHandlerSimple: returns %Rrc cb=%d\n", rc, cb));
1080	return rc;
1081	}
1082
1083	/**
1084	* \#PF Handler callback for PT write accesses.
1085	*
1086	* @returns VBox status code (appropriate for GC return).
1087	* @param pVM VM Handle.
1088	* @param uErrorCode CPU Error code.
1089	* @param pRegFrame Trap register frame.
1090	* NULL on DMA and other non CPU access.
1091	* @param pvFault The fault address (cr2).
1092	* @param GCPhysFault The GC physical address corresponding to pvFault.
1093	* @param pvUser User argument.
1094	*/
1095	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1096	{
1097	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1098	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1099	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)pvUser;
1100	PVMCPU pVCpu = VMMGetCpu(pVM);
1101
1102	LogFlow(("pgmPoolAccessHandler: pvFault=%RGv pPage=%p:{.idx=%d} GCPhysFault=%RGp\n", pvFault, pPage, pPage->idx, GCPhysFault));
1103
1104	/*
1105	* We should ALWAYS have the list head as user parameter. This
1106	* is because we use that page to record the changes.
1107	*/
1108	Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1109
1110	/*
1111	* Disassemble the faulting instruction.
1112	*/
1113	DISCPUSTATE Cpu;
1114	int rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, &Cpu, NULL);
1115	AssertRCReturn(rc, rc);
1116
1117	pgmLock(pVM);
1118	if (PHYS_PAGE_ADDRESS(GCPhysFault) != PHYS_PAGE_ADDRESS(pPage->GCPhys))
1119	{
1120	/* Pool page changed while we were waiting for the lock; ignore. */
1121	Log(("CPU%d: pgmPoolAccessHandler pgm pool page for %RGp changed (to %RGp) while waiting!\n", pVCpu->idCpu, PHYS_PAGE_ADDRESS(GCPhysFault), PHYS_PAGE_ADDRESS(pPage->GCPhys)));
1122	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1123	pgmUnlock(pVM);
1124	return VINF_SUCCESS;
1125	}
1126
1127	/*
1128	* Check if it's worth dealing with.
1129	*/
1130	bool fReused = false;
1131	if ( ( pPage->cModifications < 48 /** @todo #define / /* @todo need to check that it's not mapping EIP. / /* @todo adjust this! */
1132	\|\| pgmPoolIsPageLocked(&pVM->pgm.s, pPage)
1133	)
1134	&& !(fReused = pgmPoolMonitorIsReused(pVM, pRegFrame, &Cpu, pvFault))
1135	&& !pgmPoolMonitorIsForking(pPool, &Cpu, GCPhysFault & PAGE_OFFSET_MASK))
1136	{
1137	/*
1138	* Simple instructions, no REP prefix.
1139	*/
1140	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1141	{
1142	rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1143	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1144	pgmUnlock(pVM);
1145	return rc;
1146	}
1147
1148	/*
1149	* Windows is frequently doing small memset() operations (netio test 4k+).
1150	* We have to deal with these or we'll kill the cache and performance.
1151	*/
1152	if ( Cpu.pCurInstr->opcode == OP_STOSWD
1153	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0
1154	&& pRegFrame->ecx <= 0x20
1155	&& pRegFrame->ecx * 4 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1156	&& !((uintptr_t)pvFault & 3)
1157	&& (pRegFrame->eax == 0 \|\| pRegFrame->eax == 0x80) /* the two values observed. */
1158	&& Cpu.mode == CPUMODE_32BIT
1159	&& Cpu.opmode == CPUMODE_32BIT
1160	&& Cpu.addrmode == CPUMODE_32BIT
1161	&& Cpu.prefix == PREFIX_REP
1162	&& !pRegFrame->eflags.Bits.u1DF
1163	)
1164	{
1165	rc = pgmPoolAccessHandlerSTOSD(pVM, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1166	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,RepStosd), a);
1167	pgmUnlock(pVM);
1168	return rc;
1169	}
1170
1171	/* REP prefix, don't bother. */
1172	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,RepPrefix));
1173	Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n",
1174	pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, Cpu.pCurInstr->opcode, Cpu.prefix));
1175	}
1176
1177	/*
1178	* Not worth it, so flush it.
1179	*
1180	* If we considered it to be reused, don't go back to ring-3
1181	* to emulate failed instructions since we usually cannot
1182	* interpret then. This may be a bit risky, in which case
1183	* the reuse detection must be fixed.
1184	*/
1185	rc = pgmPoolAccessHandlerFlush(pVM, pVCpu, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1186	if (rc == VINF_EM_RAW_EMULATE_INSTR && fReused)
1187	rc = VINF_SUCCESS;
1188	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,FlushPage), a);
1189	pgmUnlock(pVM);
1190	return rc;
1191	}
1192
1193	# endif /* !IN_RING3 */
1194	#endif /* PGMPOOL_WITH_MONITORING */
1195
1196	#ifdef PGMPOOL_WITH_CACHE
1197
1198	/**
1199	* Inserts a page into the GCPhys hash table.
1200	*
1201	* @param pPool The pool.
1202	* @param pPage The page.
1203	*/
1204	DECLINLINE(void) pgmPoolHashInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1205	{
1206	Log3(("pgmPoolHashInsert: %RGp\n", pPage->GCPhys));
1207	Assert(pPage->GCPhys != NIL_RTGCPHYS); Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1208	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1209	pPage->iNext = pPool->aiHash[iHash];
1210	pPool->aiHash[iHash] = pPage->idx;
1211	}
1212
1213
1214	/**
1215	* Removes a page from the GCPhys hash table.
1216	*
1217	* @param pPool The pool.
1218	* @param pPage The page.
1219	*/
1220	DECLINLINE(void) pgmPoolHashRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1221	{
1222	Log3(("pgmPoolHashRemove: %RGp\n", pPage->GCPhys));
1223	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1224	if (pPool->aiHash[iHash] == pPage->idx)
1225	pPool->aiHash[iHash] = pPage->iNext;
1226	else
1227	{
1228	uint16_t iPrev = pPool->aiHash[iHash];
1229	for (;;)
1230	{
1231	const int16_t i = pPool->aPages[iPrev].iNext;
1232	if (i == pPage->idx)
1233	{
1234	pPool->aPages[iPrev].iNext = pPage->iNext;
1235	break;
1236	}
1237	if (i == NIL_PGMPOOL_IDX)
1238	{
1239	AssertReleaseMsgFailed(("GCPhys=%RGp idx=%#x\n", pPage->GCPhys, pPage->idx));
1240	break;
1241	}
1242	iPrev = i;
1243	}
1244	}
1245	pPage->iNext = NIL_PGMPOOL_IDX;
1246	}
1247
1248
1249	/**
1250	* Frees up one cache page.
1251	*
1252	* @returns VBox status code.
1253	* @retval VINF_SUCCESS on success.
1254	* @param pPool The pool.
1255	* @param iUser The user index.
1256	*/
1257	static int pgmPoolCacheFreeOne(PPGMPOOL pPool, uint16_t iUser)
1258	{
1259	#ifndef IN_RC
1260	const PVM pVM = pPool->CTX_SUFF(pVM);
1261	#endif
1262	Assert(pPool->iAgeHead != pPool->iAgeTail); /* We shouldn't be here if there < 2 cached entries! */
1263	STAM_COUNTER_INC(&pPool->StatCacheFreeUpOne);
1264
1265	/*
1266	* Select one page from the tail of the age list.
1267	*/
1268	PPGMPOOLPAGE pPage;
1269	for (unsigned iLoop = 0; ; iLoop++)
1270	{
1271	uint16_t iToFree = pPool->iAgeTail;
1272	if (iToFree == iUser)
1273	iToFree = pPool->aPages[iToFree].iAgePrev;
1274	/* This is the alternative to the SyncCR3 pgmPoolCacheUsed calls.
1275	if (pPool->aPages[iToFree].iUserHead != NIL_PGMPOOL_USER_INDEX)
1276	{
1277	uint16_t i = pPool->aPages[iToFree].iAgePrev;
1278	for (unsigned j = 0; j < 10 && i != NIL_PGMPOOL_USER_INDEX; j++, i = pPool->aPages[i].iAgePrev)
1279	{
1280	if (pPool->aPages[iToFree].iUserHead == NIL_PGMPOOL_USER_INDEX)
1281	continue;
1282	iToFree = i;
1283	break;
1284	}
1285	}
1286	*/
1287	Assert(iToFree != iUser);
1288	AssertRelease(iToFree != NIL_PGMPOOL_IDX);
1289	pPage = &pPool->aPages[iToFree];
1290
1291	/*
1292	* Reject any attempts at flushing the currently active shadow CR3 mapping.
1293	* Call pgmPoolCacheUsed to move the page to the head of the age list.
1294	*/
1295	if (!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage))
1296	break;
1297	LogFlow(("pgmPoolCacheFreeOne: refuse CR3 mapping\n"));
1298	pgmPoolCacheUsed(pPool, pPage);
1299	AssertLogRelReturn(iLoop < 8192, VERR_INTERNAL_ERROR);
1300	}
1301
1302	/*
1303	* Found a usable page, flush it and return.
1304	*/
1305	int rc = pgmPoolFlushPage(pPool, pPage);
1306	/* This flush was initiated by us and not the guest, so explicitly flush the TLB. */
1307	if (rc == VINF_SUCCESS)
1308	PGM_INVL_ALL_VCPU_TLBS(pVM);
1309	return rc;
1310	}
1311
1312
1313	/**
1314	* Checks if a kind mismatch is really a page being reused
1315	* or if it's just normal remappings.
1316	*
1317	* @returns true if reused and the cached page (enmKind1) should be flushed
1318	* @returns false if not reused.
1319	* @param enmKind1 The kind of the cached page.
1320	* @param enmKind2 The kind of the requested page.
1321	*/
1322	static bool pgmPoolCacheReusedByKind(PGMPOOLKIND enmKind1, PGMPOOLKIND enmKind2)
1323	{
1324	switch (enmKind1)
1325	{
1326	/*
1327	* Never reuse them. There is no remapping in non-paging mode.
1328	*/
1329	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1330	case PGMPOOLKIND_32BIT_PD_PHYS:
1331	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1332	case PGMPOOLKIND_PAE_PD_PHYS:
1333	case PGMPOOLKIND_PAE_PDPT_PHYS:
1334	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1335	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1336	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1337	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1338	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1339	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT: /* never reuse them for other types */
1340	return false;
1341
1342	/*
1343	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1344	*/
1345	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1346	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1347	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1348	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1349	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1350	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1351	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1352	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1353	case PGMPOOLKIND_32BIT_PD:
1354	case PGMPOOLKIND_PAE_PDPT:
1355	switch (enmKind2)
1356	{
1357	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1358	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1359	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1360	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1361	case PGMPOOLKIND_64BIT_PML4:
1362	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1363	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1364	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1365	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1366	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1367	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1368	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1369	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1370	return true;
1371	default:
1372	return false;
1373	}
1374
1375	/*
1376	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1377	*/
1378	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1379	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1380	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1381	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1382	case PGMPOOLKIND_64BIT_PML4:
1383	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1384	switch (enmKind2)
1385	{
1386	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1387	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1388	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1389	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1390	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1391	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1392	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1393	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1394	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1395	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1396	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1397	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1398	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1399	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1400	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1401	return true;
1402	default:
1403	return false;
1404	}
1405
1406	/*
1407	* These cannot be flushed, and it's common to reuse the PDs as PTs.
1408	*/
1409	case PGMPOOLKIND_ROOT_NESTED:
1410	return false;
1411
1412	default:
1413	AssertFatalMsgFailed(("enmKind1=%d\n", enmKind1));
1414	}
1415	}
1416
1417
1418	/**
1419	* Attempts to satisfy a pgmPoolAlloc request from the cache.
1420	*
1421	* @returns VBox status code.
1422	* @retval VINF_PGM_CACHED_PAGE on success.
1423	* @retval VERR_FILE_NOT_FOUND if not found.
1424	* @param pPool The pool.
1425	* @param GCPhys The GC physical address of the page we're gonna shadow.
1426	* @param enmKind The kind of mapping.
1427	* @param iUser The shadow page pool index of the user table.
1428	* @param iUserTable The index into the user table (shadowed).
1429	* @param ppPage Where to store the pointer to the page.
1430	*/
1431	static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
1432	{
1433	#ifndef IN_RC
1434	const PVM pVM = pPool->CTX_SUFF(pVM);
1435	#endif
1436	/*
1437	* Look up the GCPhys in the hash.
1438	*/
1439	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
1440	Log3(("pgmPoolCacheAlloc: %RGp kind %s iUser=%x iUserTable=%x SLOT=%d\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable, i));
1441	if (i != NIL_PGMPOOL_IDX)
1442	{
1443	do
1444	{
1445	PPGMPOOLPAGE pPage = &pPool->aPages[i];
1446	Log4(("pgmPoolCacheAlloc: slot %d found page %RGp\n", i, pPage->GCPhys));
1447	if (pPage->GCPhys == GCPhys)
1448	{
1449	if ( (PGMPOOLKIND)pPage->enmKind == enmKind
1450	&& (PGMPOOLACCESS)pPage->enmAccess == enmAccess)
1451	{
1452	/* Put it at the start of the use list to make sure pgmPoolTrackAddUser
1453	* doesn't flush it in case there are no more free use records.
1454	*/
1455	pgmPoolCacheUsed(pPool, pPage);
1456
1457	int rc = pgmPoolTrackAddUser(pPool, pPage, iUser, iUserTable);
1458	if (RT_SUCCESS(rc))
1459	{
1460	Assert((PGMPOOLKIND)pPage->enmKind == enmKind);
1461	*ppPage = pPage;
1462	STAM_COUNTER_INC(&pPool->StatCacheHits);
1463	return VINF_PGM_CACHED_PAGE;
1464	}
1465	return rc;
1466	}
1467
1468	if ((PGMPOOLKIND)pPage->enmKind != enmKind)
1469	{
1470	/*
1471	* The kind is different. In some cases we should now flush the page
1472	* as it has been reused, but in most cases this is normal remapping
1473	* of PDs as PT or big pages using the GCPhys field in a slightly
1474	* different way than the other kinds.
1475	*/
1476	if (pgmPoolCacheReusedByKind((PGMPOOLKIND)pPage->enmKind, enmKind))
1477	{
1478	STAM_COUNTER_INC(&pPool->StatCacheKindMismatches);
1479	pgmPoolFlushPage(pPool, pPage);
1480	PGM_INVL_VCPU_TLBS(VMMGetCpu(pVM)); /* see PT handler. */
1481	break;
1482	}
1483	}
1484	}
1485
1486	/* next */
1487	i = pPage->iNext;
1488	} while (i != NIL_PGMPOOL_IDX);
1489	}
1490
1491	Log3(("pgmPoolCacheAlloc: Missed GCPhys=%RGp enmKind=%s\n", GCPhys, pgmPoolPoolKindToStr(enmKind)));
1492	STAM_COUNTER_INC(&pPool->StatCacheMisses);
1493	return VERR_FILE_NOT_FOUND;
1494	}
1495
1496
1497	/**
1498	* Inserts a page into the cache.
1499	*
1500	* @param pPool The pool.
1501	* @param pPage The cached page.
1502	* @param fCanBeCached Set if the page is fit for caching from the caller's point of view.
1503	*/
1504	static void pgmPoolCacheInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fCanBeCached)
1505	{
1506	/*
1507	* Insert into the GCPhys hash if the page is fit for that.
1508	*/
1509	Assert(!pPage->fCached);
1510	if (fCanBeCached)
1511	{
1512	pPage->fCached = true;
1513	pgmPoolHashInsert(pPool, pPage);
1514	Log3(("pgmPoolCacheInsert: Caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
1515	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
1516	STAM_COUNTER_INC(&pPool->StatCacheCacheable);
1517	}
1518	else
1519	{
1520	Log3(("pgmPoolCacheInsert: Not caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
1521	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
1522	STAM_COUNTER_INC(&pPool->StatCacheUncacheable);
1523	}
1524
1525	/*
1526	* Insert at the head of the age list.
1527	*/
1528	pPage->iAgePrev = NIL_PGMPOOL_IDX;
1529	pPage->iAgeNext = pPool->iAgeHead;
1530	if (pPool->iAgeHead != NIL_PGMPOOL_IDX)
1531	pPool->aPages[pPool->iAgeHead].iAgePrev = pPage->idx;
1532	else
1533	pPool->iAgeTail = pPage->idx;
1534	pPool->iAgeHead = pPage->idx;
1535	}
1536
1537
1538	/**
1539	* Flushes a cached page.
1540	*
1541	* @param pPool The pool.
1542	* @param pPage The cached page.
1543	*/
1544	static void pgmPoolCacheFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1545	{
1546	Log3(("pgmPoolCacheFlushPage: %RGp\n", pPage->GCPhys));
1547
1548	/*
1549	* Remove the page from the hash.
1550	*/
1551	if (pPage->fCached)
1552	{
1553	pPage->fCached = false;
1554	pgmPoolHashRemove(pPool, pPage);
1555	}
1556	else
1557	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1558
1559	/*
1560	* Remove it from the age list.
1561	*/
1562	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
1563	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
1564	else
1565	pPool->iAgeTail = pPage->iAgePrev;
1566	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
1567	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
1568	else
1569	pPool->iAgeHead = pPage->iAgeNext;
1570	pPage->iAgeNext = NIL_PGMPOOL_IDX;
1571	pPage->iAgePrev = NIL_PGMPOOL_IDX;
1572	}
1573
1574	#endif /* PGMPOOL_WITH_CACHE */
1575	#ifdef PGMPOOL_WITH_MONITORING
1576
1577	/**
1578	* Looks for pages sharing the monitor.
1579	*
1580	* @returns Pointer to the head page.
1581	* @returns NULL if not found.
1582	* @param pPool The Pool
1583	* @param pNewPage The page which is going to be monitored.
1584	*/
1585	static PPGMPOOLPAGE pgmPoolMonitorGetPageByGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pNewPage)
1586	{
1587	#ifdef PGMPOOL_WITH_CACHE
1588	/*
1589	* Look up the GCPhys in the hash.
1590	*/
1591	RTGCPHYS GCPhys = pNewPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1592	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
1593	if (i == NIL_PGMPOOL_IDX)
1594	return NULL;
1595	do
1596	{
1597	PPGMPOOLPAGE pPage = &pPool->aPages[i];
1598	if ( pPage->GCPhys - GCPhys < PAGE_SIZE
1599	&& pPage != pNewPage)
1600	{
1601	switch (pPage->enmKind)
1602	{
1603	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1604	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1605	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1606	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1607	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1608	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1609	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1610	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1611	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1612	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1613	case PGMPOOLKIND_64BIT_PML4:
1614	case PGMPOOLKIND_32BIT_PD:
1615	case PGMPOOLKIND_PAE_PDPT:
1616	{
1617	/* find the head */
1618	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1619	{
1620	Assert(pPage->iMonitoredPrev != pPage->idx);
1621	pPage = &pPool->aPages[pPage->iMonitoredPrev];
1622	}
1623	return pPage;
1624	}
1625
1626	/* ignore, no monitoring. */
1627	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1628	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1629	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1630	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1631	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1632	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1633	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1634	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1635	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1636	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1637	case PGMPOOLKIND_ROOT_NESTED:
1638	case PGMPOOLKIND_PAE_PD_PHYS:
1639	case PGMPOOLKIND_PAE_PDPT_PHYS:
1640	case PGMPOOLKIND_32BIT_PD_PHYS:
1641	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
1642	break;
1643	default:
1644	AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
1645	}
1646	}
1647
1648	/* next */
1649	i = pPage->iNext;
1650	} while (i != NIL_PGMPOOL_IDX);
1651	#endif
1652	return NULL;
1653	}
1654
1655
1656	/**
1657	* Enabled write monitoring of a guest page.
1658	*
1659	* @returns VBox status code.
1660	* @retval VINF_SUCCESS on success.
1661	* @param pPool The pool.
1662	* @param pPage The cached page.
1663	*/
1664	static int pgmPoolMonitorInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1665	{
1666	LogFlow(("pgmPoolMonitorInsert %RGp\n", pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1)));
1667
1668	/*
1669	* Filter out the relevant kinds.
1670	*/
1671	switch (pPage->enmKind)
1672	{
1673	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1674	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1675	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1676	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1677	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1678	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1679	case PGMPOOLKIND_64BIT_PML4:
1680	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1681	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1682	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1683	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1684	case PGMPOOLKIND_32BIT_PD:
1685	case PGMPOOLKIND_PAE_PDPT:
1686	break;
1687
1688	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1689	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1690	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1691	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1692	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1693	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1694	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1695	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1696	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1697	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1698	case PGMPOOLKIND_ROOT_NESTED:
1699	/* Nothing to monitor here. */
1700	return VINF_SUCCESS;
1701
1702	case PGMPOOLKIND_32BIT_PD_PHYS:
1703	case PGMPOOLKIND_PAE_PDPT_PHYS:
1704	case PGMPOOLKIND_PAE_PD_PHYS:
1705	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
1706	/* Nothing to monitor here. */
1707	return VINF_SUCCESS;
1708	#ifdef PGMPOOL_WITH_MIXED_PT_CR3
1709	break;
1710	#else
1711	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1712	#endif
1713	default:
1714	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
1715	}
1716
1717	/*
1718	* Install handler.
1719	*/
1720	int rc;
1721	PPGMPOOLPAGE pPageHead = pgmPoolMonitorGetPageByGCPhys(pPool, pPage);
1722	if (pPageHead)
1723	{
1724	Assert(pPageHead != pPage); Assert(pPageHead->iMonitoredNext != pPage->idx);
1725	Assert(pPageHead->iMonitoredPrev != pPage->idx);
1726	pPage->iMonitoredPrev = pPageHead->idx;
1727	pPage->iMonitoredNext = pPageHead->iMonitoredNext;
1728	if (pPageHead->iMonitoredNext != NIL_PGMPOOL_IDX)
1729	pPool->aPages[pPageHead->iMonitoredNext].iMonitoredPrev = pPage->idx;
1730	pPageHead->iMonitoredNext = pPage->idx;
1731	rc = VINF_SUCCESS;
1732	}
1733	else
1734	{
1735	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX); Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1736	PVM pVM = pPool->CTX_SUFF(pVM);
1737	const RTGCPHYS GCPhysPage = pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1738	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
1739	GCPhysPage, GCPhysPage + (PAGE_SIZE - 1),
1740	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
1741	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
1742	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
1743	pPool->pszAccessHandler);
1744	/** @todo we should probably deal with out-of-memory conditions here, but for now increasing
1745	* the heap size should suffice. */
1746	AssertFatalMsgRC(rc, ("PGMHandlerPhysicalRegisterEx %RGp failed with %Rrc\n", GCPhysPage, rc));
1747	Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_ISSET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3));
1748	}
1749	pPage->fMonitored = true;
1750	return rc;
1751	}
1752
1753
1754	/**
1755	* Disables write monitoring of a guest page.
1756	*
1757	* @returns VBox status code.
1758	* @retval VINF_SUCCESS on success.
1759	* @param pPool The pool.
1760	* @param pPage The cached page.
1761	*/
1762	static int pgmPoolMonitorFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1763	{
1764	/*
1765	* Filter out the relevant kinds.
1766	*/
1767	switch (pPage->enmKind)
1768	{
1769	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1770	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1771	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1772	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1773	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1774	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1775	case PGMPOOLKIND_64BIT_PML4:
1776	case PGMPOOLKIND_32BIT_PD:
1777	case PGMPOOLKIND_PAE_PDPT:
1778	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1779	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1780	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1781	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1782	break;
1783
1784	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1785	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1786	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1787	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1788	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1789	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1790	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1791	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1792	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1793	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1794	case PGMPOOLKIND_ROOT_NESTED:
1795	case PGMPOOLKIND_PAE_PD_PHYS:
1796	case PGMPOOLKIND_PAE_PDPT_PHYS:
1797	case PGMPOOLKIND_32BIT_PD_PHYS:
1798	/* Nothing to monitor here. */
1799	return VINF_SUCCESS;
1800
1801	#ifdef PGMPOOL_WITH_MIXED_PT_CR3
1802	break;
1803	#endif
1804	default:
1805	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
1806	}
1807
1808	/*
1809	* Remove the page from the monitored list or uninstall it if last.
1810	*/
1811	const PVM pVM = pPool->CTX_SUFF(pVM);
1812	int rc;
1813	if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
1814	\|\| pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1815	{
1816	if (pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
1817	{
1818	PPGMPOOLPAGE pNewHead = &pPool->aPages[pPage->iMonitoredNext];
1819	pNewHead->iMonitoredPrev = NIL_PGMPOOL_IDX;
1820	rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
1821	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pNewHead),
1822	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pNewHead),
1823	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pNewHead),
1824	pPool->pszAccessHandler);
1825	AssertFatalRCSuccess(rc);
1826	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
1827	}
1828	else
1829	{
1830	pPool->aPages[pPage->iMonitoredPrev].iMonitoredNext = pPage->iMonitoredNext;
1831	if (pPage->iMonitoredNext != NIL_PGMPOOL_IDX)
1832	{
1833	pPool->aPages[pPage->iMonitoredNext].iMonitoredPrev = pPage->iMonitoredPrev;
1834	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
1835	}
1836	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
1837	rc = VINF_SUCCESS;
1838	}
1839	}
1840	else
1841	{
1842	rc = PGMHandlerPhysicalDeregister(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1));
1843	AssertFatalRC(rc);
1844	AssertMsg(!(pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_ISSET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3),
1845	("%#x %#x\n", pVM->pgm.s.fGlobalSyncFlags, pVM->fGlobalForcedActions));
1846	}
1847	pPage->fMonitored = false;
1848
1849	/*
1850	* Remove it from the list of modified pages (if in it).
1851	*/
1852	pgmPoolMonitorModifiedRemove(pPool, pPage);
1853
1854	return rc;
1855	}
1856
1857
1858	/**
1859	* Inserts the page into the list of modified pages.
1860	*
1861	* @param pPool The pool.
1862	* @param pPage The page.
1863	*/
1864	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1865	{
1866	Log3(("pgmPoolMonitorModifiedInsert: idx=%d\n", pPage->idx));
1867	AssertMsg( pPage->iModifiedNext == NIL_PGMPOOL_IDX
1868	&& pPage->iModifiedPrev == NIL_PGMPOOL_IDX
1869	&& pPool->iModifiedHead != pPage->idx,
1870	("Next=%d Prev=%d idx=%d cModifications=%d Head=%d cModifiedPages=%d\n",
1871	pPage->iModifiedNext, pPage->iModifiedPrev, pPage->idx, pPage->cModifications,
1872	pPool->iModifiedHead, pPool->cModifiedPages));
1873
1874	pPage->iModifiedNext = pPool->iModifiedHead;
1875	if (pPool->iModifiedHead != NIL_PGMPOOL_IDX)
1876	pPool->aPages[pPool->iModifiedHead].iModifiedPrev = pPage->idx;
1877	pPool->iModifiedHead = pPage->idx;
1878	pPool->cModifiedPages++;
1879	#ifdef VBOX_WITH_STATISTICS
1880	if (pPool->cModifiedPages > pPool->cModifiedPagesHigh)
1881	pPool->cModifiedPagesHigh = pPool->cModifiedPages;
1882	#endif
1883	}
1884
1885
1886	/**
1887	* Removes the page from the list of modified pages and resets the
1888	* moficiation counter.
1889	*
1890	* @param pPool The pool.
1891	* @param pPage The page which is believed to be in the list of modified pages.
1892	*/
1893	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1894	{
1895	Log3(("pgmPoolMonitorModifiedRemove: idx=%d cModifications=%d\n", pPage->idx, pPage->cModifications));
1896	if (pPool->iModifiedHead == pPage->idx)
1897	{
1898	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
1899	pPool->iModifiedHead = pPage->iModifiedNext;
1900	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
1901	{
1902	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = NIL_PGMPOOL_IDX;
1903	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1904	}
1905	pPool->cModifiedPages--;
1906	}
1907	else if (pPage->iModifiedPrev != NIL_PGMPOOL_IDX)
1908	{
1909	pPool->aPages[pPage->iModifiedPrev].iModifiedNext = pPage->iModifiedNext;
1910	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
1911	{
1912	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = pPage->iModifiedPrev;
1913	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1914	}
1915	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
1916	pPool->cModifiedPages--;
1917	}
1918	else
1919	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
1920	pPage->cModifications = 0;
1921	}
1922
1923
1924	/**
1925	* Zaps the list of modified pages, resetting their modification counters in the process.
1926	*
1927	* @param pVM The VM handle.
1928	*/
1929	void pgmPoolMonitorModifiedClearAll(PVM pVM)
1930	{
1931	pgmLock(pVM);
1932	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1933	LogFlow(("pgmPoolMonitorModifiedClearAll: cModifiedPages=%d\n", pPool->cModifiedPages));
1934
1935	unsigned cPages = 0; NOREF(cPages);
1936	uint16_t idx = pPool->iModifiedHead;
1937	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
1938	while (idx != NIL_PGMPOOL_IDX)
1939	{
1940	PPGMPOOLPAGE pPage = &pPool->aPages[idx];
1941	idx = pPage->iModifiedNext;
1942	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1943	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
1944	pPage->cModifications = 0;
1945	Assert(++cPages);
1946	}
1947	AssertMsg(cPages == pPool->cModifiedPages, ("%d != %d\n", cPages, pPool->cModifiedPages));
1948	pPool->cModifiedPages = 0;
1949	pgmUnlock(pVM);
1950	}
1951
1952
1953	#ifdef IN_RING3
1954	/**
1955	* Callback to clear all shadow pages and clear all modification counters.
1956	*
1957	* @returns VBox status code.
1958	* @param pVM The VM handle.
1959	* @param pvUser Unused parameter
1960	* @remark Should only be used when monitoring is available, thus placed in
1961	* the PGMPOOL_WITH_MONITORING #ifdef.
1962	*/
1963	DECLCALLBACK(int) pgmPoolClearAll(PVM pVM, void *pvUser)
1964	{
1965	NOREF(pvUser);
1966	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1967	STAM_PROFILE_START(&pPool->StatClearAll, c);
1968	LogFlow(("pgmPoolClearAll: cUsedPages=%d\n", pPool->cUsedPages));
1969
1970	pgmLock(pVM);
1971
1972	/*
1973	* Iterate all the pages until we've encountered all that in use.
1974	* This is simple but not quite optimal solution.
1975	*/
1976	unsigned cModifiedPages = 0; NOREF(cModifiedPages);
1977	unsigned cLeft = pPool->cUsedPages;
1978	unsigned iPage = pPool->cCurPages;
1979	while (--iPage >= PGMPOOL_IDX_FIRST)
1980	{
1981	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
1982	if (pPage->GCPhys != NIL_RTGCPHYS)
1983	{
1984	switch (pPage->enmKind)
1985	{
1986	/*
1987	* We only care about shadow page tables.
1988	*/
1989	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1990	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1991	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1992	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1993	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1994	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1995	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1996	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1997	{
1998	#ifdef PGMPOOL_WITH_USER_TRACKING
1999	if (pPage->cPresent)
2000	#endif
2001	{
2002	void *pvShw = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
2003	STAM_PROFILE_START(&pPool->StatZeroPage, z);
2004	ASMMemZeroPage(pvShw);
2005	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
2006	#ifdef PGMPOOL_WITH_USER_TRACKING
2007	pPage->cPresent = 0;
2008	pPage->iFirstPresent = ~0;
2009	#endif
2010	}
2011	}
2012	/* fall thru */
2013
2014	default:
2015	Assert(!pPage->cModifications \|\| ++cModifiedPages);
2016	Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2017	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2018	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2019	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2020	pPage->cModifications = 0;
2021	break;
2022
2023	}
2024	if (!--cLeft)
2025	break;
2026	}
2027	}
2028
2029	/* swipe the special pages too. */
2030	for (iPage = PGMPOOL_IDX_FIRST_SPECIAL; iPage < PGMPOOL_IDX_FIRST; iPage++)
2031	{
2032	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
2033	if (pPage->GCPhys != NIL_RTGCPHYS)
2034	{
2035	Assert(!pPage->cModifications \|\| ++cModifiedPages);
2036	Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2037	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2038	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2039	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2040	pPage->cModifications = 0;
2041	}
2042	}
2043
2044	#ifndef DEBUG_michael
2045	AssertMsg(cModifiedPages == pPool->cModifiedPages, ("%d != %d\n", cModifiedPages, pPool->cModifiedPages));
2046	#endif
2047	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
2048	pPool->cModifiedPages = 0;
2049
2050	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2051	/*
2052	* Clear all the GCPhys links and rebuild the phys ext free list.
2053	*/
2054	for (PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
2055	pRam;
2056	pRam = pRam->CTX_SUFF(pNext))
2057	{
2058	unsigned iPage = pRam->cb >> PAGE_SHIFT;
2059	while (iPage-- > 0)
2060	PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
2061	}
2062
2063	pPool->iPhysExtFreeHead = 0;
2064	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
2065	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
2066	for (unsigned i = 0; i < cMaxPhysExts; i++)
2067	{
2068	paPhysExts[i].iNext = i + 1;
2069	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
2070	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
2071	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
2072	}
2073	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
2074	#endif
2075
2076	pPool->cPresent = 0;
2077	pgmUnlock(pVM);
2078	PGM_INVL_ALL_VCPU_TLBS(pVM);
2079	STAM_PROFILE_STOP(&pPool->StatClearAll, c);
2080	return VINF_SUCCESS;
2081	}
2082	#endif /* IN_RING3 */
2083
2084
2085	/**
2086	* Handle SyncCR3 pool tasks
2087	*
2088	* @returns VBox status code.
2089	* @retval VINF_SUCCESS if successfully added.
2090	* @retval VINF_PGM_SYNC_CR3 is it needs to be deferred to ring 3 (GC only)
2091	* @param pVM The VM handle.
2092	* @remark Should only be used when monitoring is available, thus placed in
2093	* the PGMPOOL_WITH_MONITORING #ifdef.
2094	*/
2095	int pgmPoolSyncCR3(PVM pVM)
2096	{
2097	LogFlow(("pgmPoolSyncCR3\n"));
2098	/*
2099	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2100	* Occasionally we will have to clear all the shadow page tables because we wanted
2101	* to monitor a page which was mapped by too many shadowed page tables. This operation
2102	* sometimes refered to as a 'lightweight flush'.
2103	*/
2104	# ifdef IN_RING3 /* Don't flush in ring-0 or raw mode, it's taking too long. */
2105	if (ASMBitTestAndClear(&pVM->pgm.s.fGlobalSyncFlags, PGM_GLOBAL_SYNC_CLEAR_PGM_POOL_BIT))
2106	{
2107	VMMR3AtomicExecuteHandler(pVM, pgmPoolClearAll, NULL);
2108	# else /* !IN_RING3 */
2109	if (pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL)
2110	{
2111	LogFlow(("SyncCR3: PGM_GLOBAL_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2112	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
2113	return VINF_PGM_SYNC_CR3;
2114	# endif /* !IN_RING3 */
2115	}
2116	else
2117	pgmPoolMonitorModifiedClearAll(pVM);
2118
2119	return VINF_SUCCESS;
2120	}
2121
2122	#endif /* PGMPOOL_WITH_MONITORING */
2123	#ifdef PGMPOOL_WITH_USER_TRACKING
2124
2125	/**
2126	* Frees up at least one user entry.
2127	*
2128	* @returns VBox status code.
2129	* @retval VINF_SUCCESS if successfully added.
2130	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2131	* @param pPool The pool.
2132	* @param iUser The user index.
2133	*/
2134	static int pgmPoolTrackFreeOneUser(PPGMPOOL pPool, uint16_t iUser)
2135	{
2136	STAM_COUNTER_INC(&pPool->StatTrackFreeUpOneUser);
2137	#ifdef PGMPOOL_WITH_CACHE
2138	/*
2139	* Just free cached pages in a braindead fashion.
2140	*/
2141	/** @todo walk the age list backwards and free the first with usage. */
2142	int rc = VINF_SUCCESS;
2143	do
2144	{
2145	int rc2 = pgmPoolCacheFreeOne(pPool, iUser);
2146	if (RT_FAILURE(rc2) && rc == VINF_SUCCESS)
2147	rc = rc2;
2148	} while (pPool->iUserFreeHead == NIL_PGMPOOL_USER_INDEX);
2149	return rc;
2150	#else
2151	/*
2152	* Lazy approach.
2153	*/
2154	/* @todo This path no longer works (CR3 root pages will be flushed)!! */
2155	AssertCompileFailed();
2156	Assert(!CPUMIsGuestInLongMode(pVM));
2157	pgmPoolFlushAllInt(pPool);
2158	return VERR_PGM_POOL_FLUSHED;
2159	#endif
2160	}
2161
2162
2163	/**
2164	* Inserts a page into the cache.
2165	*
2166	* This will create user node for the page, insert it into the GCPhys
2167	* hash, and insert it into the age list.
2168	*
2169	* @returns VBox status code.
2170	* @retval VINF_SUCCESS if successfully added.
2171	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2172	* @param pPool The pool.
2173	* @param pPage The cached page.
2174	* @param GCPhys The GC physical address of the page we're gonna shadow.
2175	* @param iUser The user index.
2176	* @param iUserTable The user table index.
2177	*/
2178	DECLINLINE(int) pgmPoolTrackInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhys, uint16_t iUser, uint32_t iUserTable)
2179	{
2180	int rc = VINF_SUCCESS;
2181	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2182
2183	LogFlow(("pgmPoolTrackInsert GCPhys=%RGp iUser %x iUserTable %x\n", GCPhys, iUser, iUserTable));
2184
2185	#ifdef VBOX_STRICT
2186	/*
2187	* Check that the entry doesn't already exists.
2188	*/
2189	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2190	{
2191	uint16_t i = pPage->iUserHead;
2192	do
2193	{
2194	Assert(i < pPool->cMaxUsers);
2195	AssertMsg(paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2196	i = paUsers[i].iNext;
2197	} while (i != NIL_PGMPOOL_USER_INDEX);
2198	}
2199	#endif
2200
2201	/*
2202	* Find free a user node.
2203	*/
2204	uint16_t i = pPool->iUserFreeHead;
2205	if (i == NIL_PGMPOOL_USER_INDEX)
2206	{
2207	int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2208	if (RT_FAILURE(rc))
2209	return rc;
2210	i = pPool->iUserFreeHead;
2211	}
2212
2213	/*
2214	* Unlink the user node from the free list,
2215	* initialize and insert it into the user list.
2216	*/
2217	pPool->iUserFreeHead = paUsers[i].iNext;
2218	paUsers[i].iNext = NIL_PGMPOOL_USER_INDEX;
2219	paUsers[i].iUser = iUser;
2220	paUsers[i].iUserTable = iUserTable;
2221	pPage->iUserHead = i;
2222
2223	/*
2224	* Insert into cache and enable monitoring of the guest page if enabled.
2225	*
2226	* Until we implement caching of all levels, including the CR3 one, we'll
2227	* have to make sure we don't try monitor & cache any recursive reuse of
2228	* a monitored CR3 page. Because all windows versions are doing this we'll
2229	* have to be able to do combined access monitoring, CR3 + PT and
2230	* PD + PT (guest PAE).
2231	*
2232	* Update:
2233	* We're now cooperating with the CR3 monitor if an uncachable page is found.
2234	*/
2235	#if defined(PGMPOOL_WITH_MONITORING) \|\| defined(PGMPOOL_WITH_CACHE)
2236	# ifdef PGMPOOL_WITH_MIXED_PT_CR3
2237	const bool fCanBeMonitored = true;
2238	# else
2239	bool fCanBeMonitored = pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored == NIL_RTGCPHYS
2240	\|\| (GCPhys & X86_PTE_PAE_PG_MASK) != (pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored & X86_PTE_PAE_PG_MASK)
2241	\|\| pgmPoolIsBigPage((PGMPOOLKIND)pPage->enmKind);
2242	# endif
2243	# ifdef PGMPOOL_WITH_CACHE
2244	pgmPoolCacheInsert(pPool, pPage, fCanBeMonitored); /* This can be expanded. */
2245	# endif
2246	if (fCanBeMonitored)
2247	{
2248	# ifdef PGMPOOL_WITH_MONITORING
2249	rc = pgmPoolMonitorInsert(pPool, pPage);
2250	AssertRC(rc);
2251	}
2252	# endif
2253	#endif /* PGMPOOL_WITH_MONITORING */
2254	return rc;
2255	}
2256
2257
2258	# ifdef PGMPOOL_WITH_CACHE /* (only used when the cache is enabled.) */
2259	/**
2260	* Adds a user reference to a page.
2261	*
2262	* This will move the page to the head of the
2263	*
2264	* @returns VBox status code.
2265	* @retval VINF_SUCCESS if successfully added.
2266	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2267	* @param pPool The pool.
2268	* @param pPage The cached page.
2269	* @param iUser The user index.
2270	* @param iUserTable The user table.
2271	*/
2272	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2273	{
2274	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2275
2276	Log3(("pgmPoolTrackAddUser GCPhys = %RGp iUser %x iUserTable %x\n", pPage->GCPhys, iUser, iUserTable));
2277
2278	# ifdef VBOX_STRICT
2279	/*
2280	* Check that the entry doesn't already exists. We only allow multiple users of top-level paging structures (SHW_POOL_ROOT_IDX).
2281	*/
2282	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2283	{
2284	uint16_t i = pPage->iUserHead;
2285	do
2286	{
2287	Assert(i < pPool->cMaxUsers);
2288	AssertMsg(iUser != PGMPOOL_IDX_PD \|\| iUser != PGMPOOL_IDX_PDPT \|\| iUser != PGMPOOL_IDX_NESTED_ROOT \|\| iUser != PGMPOOL_IDX_AMD64_CR3 \|\|
2289	paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2290	i = paUsers[i].iNext;
2291	} while (i != NIL_PGMPOOL_USER_INDEX);
2292	}
2293	# endif
2294
2295	/*
2296	* Allocate a user node.
2297	*/
2298	uint16_t i = pPool->iUserFreeHead;
2299	if (i == NIL_PGMPOOL_USER_INDEX)
2300	{
2301	int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2302	if (RT_FAILURE(rc))
2303	return rc;
2304	i = pPool->iUserFreeHead;
2305	}
2306	pPool->iUserFreeHead = paUsers[i].iNext;
2307
2308	/*
2309	* Initialize the user node and insert it.
2310	*/
2311	paUsers[i].iNext = pPage->iUserHead;
2312	paUsers[i].iUser = iUser;
2313	paUsers[i].iUserTable = iUserTable;
2314	pPage->iUserHead = i;
2315
2316	# ifdef PGMPOOL_WITH_CACHE
2317	/*
2318	* Tell the cache to update its replacement stats for this page.
2319	*/
2320	pgmPoolCacheUsed(pPool, pPage);
2321	# endif
2322	return VINF_SUCCESS;
2323	}
2324	# endif /* PGMPOOL_WITH_CACHE */
2325
2326
2327	/**
2328	* Frees a user record associated with a page.
2329	*
2330	* This does not clear the entry in the user table, it simply replaces the
2331	* user record to the chain of free records.
2332	*
2333	* @param pPool The pool.
2334	* @param HCPhys The HC physical address of the shadow page.
2335	* @param iUser The shadow page pool index of the user table.
2336	* @param iUserTable The index into the user table (shadowed).
2337	*/
2338	static void pgmPoolTrackFreeUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2339	{
2340	/*
2341	* Unlink and free the specified user entry.
2342	*/
2343	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2344
2345	Log3(("pgmPoolTrackFreeUser %RGp %x %x\n", pPage->GCPhys, iUser, iUserTable));
2346	/* Special: For PAE and 32-bit paging, there is usually no more than one user. */
2347	uint16_t i = pPage->iUserHead;
2348	if ( i != NIL_PGMPOOL_USER_INDEX
2349	&& paUsers[i].iUser == iUser
2350	&& paUsers[i].iUserTable == iUserTable)
2351	{
2352	pPage->iUserHead = paUsers[i].iNext;
2353
2354	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2355	paUsers[i].iNext = pPool->iUserFreeHead;
2356	pPool->iUserFreeHead = i;
2357	return;
2358	}
2359
2360	/* General: Linear search. */
2361	uint16_t iPrev = NIL_PGMPOOL_USER_INDEX;
2362	while (i != NIL_PGMPOOL_USER_INDEX)
2363	{
2364	if ( paUsers[i].iUser == iUser
2365	&& paUsers[i].iUserTable == iUserTable)
2366	{
2367	if (iPrev != NIL_PGMPOOL_USER_INDEX)
2368	paUsers[iPrev].iNext = paUsers[i].iNext;
2369	else
2370	pPage->iUserHead = paUsers[i].iNext;
2371
2372	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2373	paUsers[i].iNext = pPool->iUserFreeHead;
2374	pPool->iUserFreeHead = i;
2375	return;
2376	}
2377	iPrev = i;
2378	i = paUsers[i].iNext;
2379	}
2380
2381	/* Fatal: didn't find it */
2382	AssertFatalMsgFailed(("Didn't find the user entry! iUser=%#x iUserTable=%#x GCPhys=%RGp\n",
2383	iUser, iUserTable, pPage->GCPhys));
2384	}
2385
2386
2387	/**
2388	* Gets the entry size of a shadow table.
2389	*
2390	* @param enmKind The kind of page.
2391	*
2392	* @returns The size of the entry in bytes. That is, 4 or 8.
2393	* @returns If the kind is not for a table, an assertion is raised and 0 is
2394	* returned.
2395	*/
2396	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind)
2397	{
2398	switch (enmKind)
2399	{
2400	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2401	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2402	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2403	case PGMPOOLKIND_32BIT_PD:
2404	case PGMPOOLKIND_32BIT_PD_PHYS:
2405	return 4;
2406
2407	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2408	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2409	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2410	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2411	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2412	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2413	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2414	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2415	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2416	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2417	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2418	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2419	case PGMPOOLKIND_64BIT_PML4:
2420	case PGMPOOLKIND_PAE_PDPT:
2421	case PGMPOOLKIND_ROOT_NESTED:
2422	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2423	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2424	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2425	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2426	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2427	case PGMPOOLKIND_PAE_PD_PHYS:
2428	case PGMPOOLKIND_PAE_PDPT_PHYS:
2429	return 8;
2430
2431	default:
2432	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2433	}
2434	}
2435
2436
2437	/**
2438	* Gets the entry size of a guest table.
2439	*
2440	* @param enmKind The kind of page.
2441	*
2442	* @returns The size of the entry in bytes. That is, 0, 4 or 8.
2443	* @returns If the kind is not for a table, an assertion is raised and 0 is
2444	* returned.
2445	*/
2446	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind)
2447	{
2448	switch (enmKind)
2449	{
2450	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2451	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2452	case PGMPOOLKIND_32BIT_PD:
2453	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2454	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2455	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2456	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2457	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2458	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2459	return 4;
2460
2461	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2462	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2463	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2464	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2465	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2466	case PGMPOOLKIND_64BIT_PML4:
2467	case PGMPOOLKIND_PAE_PDPT:
2468	return 8;
2469
2470	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2471	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2472	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2473	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2474	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2475	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2476	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2477	case PGMPOOLKIND_ROOT_NESTED:
2478	case PGMPOOLKIND_PAE_PD_PHYS:
2479	case PGMPOOLKIND_PAE_PDPT_PHYS:
2480	case PGMPOOLKIND_32BIT_PD_PHYS:
2481	/** @todo can we return 0? (nobody is calling this...) */
2482	AssertFailed();
2483	return 0;
2484
2485	default:
2486	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2487	}
2488	}
2489
2490	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2491
2492	/**
2493	* Scans one shadow page table for mappings of a physical page.
2494	*
2495	* @param pVM The VM handle.
2496	* @param pPhysPage The guest page in question.
2497	* @param iShw The shadow page table.
2498	* @param cRefs The number of references made in that PT.
2499	*/
2500	static void pgmPoolTrackFlushGCPhysPTInt(PVM pVM, PCPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs)
2501	{
2502	LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%R[pgmpage] iShw=%d cRefs=%d\n", pPhysPage, iShw, cRefs));
2503	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2504
2505	/*
2506	* Assert sanity.
2507	*/
2508	Assert(cRefs == 1);
2509	AssertFatalMsg(iShw < pPool->cCurPages && iShw != NIL_PGMPOOL_IDX, ("iShw=%d\n", iShw));
2510	PPGMPOOLPAGE pPage = &pPool->aPages[iShw];
2511
2512	/*
2513	* Then, clear the actual mappings to the page in the shadow PT.
2514	*/
2515	switch (pPage->enmKind)
2516	{
2517	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2518	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2519	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2520	{
2521	const uint32_t u32 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2522	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2523	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2524	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2525	{
2526	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX32 cRefs=%#x\n", i, pPT->a[i], cRefs));
2527	pPT->a[i].u = 0;
2528	cRefs--;
2529	if (!cRefs)
2530	return;
2531	}
2532	#ifdef LOG_ENABLED
2533	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2534	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2535	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2536	{
2537	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2538	pPT->a[i].u = 0;
2539	}
2540	#endif
2541	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
2542	break;
2543	}
2544
2545	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2546	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2547	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2548	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2549	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2550	{
2551	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2552	PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2553	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2554	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2555	{
2556	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
2557	pPT->a[i].u = 0;
2558	cRefs--;
2559	if (!cRefs)
2560	return;
2561	}
2562	#ifdef LOG_ENABLED
2563	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2564	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2565	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2566	{
2567	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2568	pPT->a[i].u = 0;
2569	}
2570	#endif
2571	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d u64=%RX64\n", cRefs, pPage->iFirstPresent, pPage->cPresent, u64));
2572	break;
2573	}
2574
2575	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2576	{
2577	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2578	PEPTPT pPT = (PEPTPT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2579	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2580	if ((pPT->a[i].u & (EPT_PTE_PG_MASK \| X86_PTE_P)) == u64)
2581	{
2582	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
2583	pPT->a[i].u = 0;
2584	cRefs--;
2585	if (!cRefs)
2586	return;
2587	}
2588	#ifdef LOG_ENABLED
2589	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2590	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2591	if ((pPT->a[i].u & (EPT_PTE_PG_MASK \| X86_PTE_P)) == u64)
2592	{
2593	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2594	pPT->a[i].u = 0;
2595	}
2596	#endif
2597	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
2598	break;
2599	}
2600
2601	default:
2602	AssertFatalMsgFailed(("enmKind=%d iShw=%d\n", pPage->enmKind, iShw));
2603	}
2604	}
2605
2606
2607	/**
2608	* Scans one shadow page table for mappings of a physical page.
2609	*
2610	* @param pVM The VM handle.
2611	* @param pPhysPage The guest page in question.
2612	* @param iShw The shadow page table.
2613	* @param cRefs The number of references made in that PT.
2614	*/
2615	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs)
2616	{
2617	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2618	LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%R[pgmpage] iShw=%d cRefs=%d\n", pPhysPage, iShw, cRefs));
2619	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPT, f);
2620	pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, iShw, cRefs);
2621	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2622	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPT, f);
2623	}
2624
2625
2626	/**
2627	* Flushes a list of shadow page tables mapping the same physical page.
2628	*
2629	* @param pVM The VM handle.
2630	* @param pPhysPage The guest page in question.
2631	* @param iPhysExt The physical cross reference extent list to flush.
2632	*/
2633	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt)
2634	{
2635	Assert(PGMIsLockOwner(pVM));
2636	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2637	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTs, f);
2638	LogFlow(("pgmPoolTrackFlushGCPhysPTs: pPhysPage=%R[pgmpage] iPhysExt\n", pPhysPage, iPhysExt));
2639
2640	const uint16_t iPhysExtStart = iPhysExt;
2641	PPGMPOOLPHYSEXT pPhysExt;
2642	do
2643	{
2644	Assert(iPhysExt < pPool->cMaxPhysExts);
2645	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
2646	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
2647	if (pPhysExt->aidx[i] != NIL_PGMPOOL_IDX)
2648	{
2649	pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, pPhysExt->aidx[i], 1);
2650	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
2651	}
2652
2653	/* next */
2654	iPhysExt = pPhysExt->iNext;
2655	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
2656
2657	/* insert the list into the free list and clear the ram range entry. */
2658	pPhysExt->iNext = pPool->iPhysExtFreeHead;
2659	pPool->iPhysExtFreeHead = iPhysExtStart;
2660	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2661
2662	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTs, f);
2663	}
2664
2665	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
2666
2667	/**
2668	* Flushes all shadow page table mappings of the given guest page.
2669	*
2670	* This is typically called when the host page backing the guest one has been
2671	* replaced or when the page protection was changed due to an access handler.
2672	*
2673	* @returns VBox status code.
2674	* @retval VINF_SUCCESS if all references has been successfully cleared.
2675	* @retval VINF_PGM_SYNC_CR3 if we're better off with a CR3 sync and a page
2676	* pool cleaning. FF and sync flags are set.
2677	*
2678	* @param pVM The VM handle.
2679	* @param pPhysPage The guest page in question.
2680	* @param pfFlushTLBs This is set to @a true if the shadow TLBs should be
2681	* flushed, it is NOT touched if this isn't necessary.
2682	* The caller MUST initialized this to @a false.
2683	*/
2684	int pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
2685	{
2686	pgmLock(pVM);
2687	int rc = VINF_SUCCESS;
2688	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2689	const uint16_t u16 = PGM_PAGE_GET_TRACKING(pPhysPage);
2690	if (u16)
2691	{
2692	/*
2693	* The zero page is currently screwing up the tracking and we'll
2694	* have to flush the whole shebang. Unless VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2695	* is defined, zero pages won't normally be mapped. Some kind of solution
2696	* will be needed for this problem of course, but it will have to wait...
2697	*/
2698	if (PGM_PAGE_IS_ZERO(pPhysPage))
2699	rc = VINF_PGM_GCPHYS_ALIASED;
2700	else
2701	{
2702	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2703	/* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow and
2704	pgmPoolTrackFlushGCPhysPTs will/may kill the pool otherwise. */
2705	PVMCPU pVCpu = VMMGetCpu(pVM);
2706	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
2707	# endif
2708
2709	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
2710	pgmPoolTrackFlushGCPhysPT(pVM,
2711	pPhysPage,
2712	PGMPOOL_TD_GET_IDX(u16),
2713	PGMPOOL_TD_GET_CREFS(u16));
2714	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
2715	pgmPoolTrackFlushGCPhysPTs(pVM, pPhysPage, PGMPOOL_TD_GET_IDX(u16));
2716	else
2717	rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
2718	*pfFlushTLBs = true;
2719
2720	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2721	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
2722	# endif
2723	}
2724	}
2725
2726	#elif defined(PGMPOOL_WITH_CACHE)
2727	if (PGM_PAGE_IS_ZERO(pPhysPage))
2728	rc = VINF_PGM_GCPHYS_ALIASED;
2729	else
2730	{
2731	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2732	/* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow kill the pool otherwise. */
2733	PVMCPU pVCpu = VMMGetCpu(pVM);
2734	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
2735	# endif
2736	rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
2737	if (rc == VINF_SUCCESS)
2738	*pfFlushTLBs = true;
2739	}
2740
2741	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2742	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
2743	# endif
2744
2745	#else
2746	rc = VINF_PGM_GCPHYS_ALIASED;
2747	#endif
2748
2749	if (rc == VINF_PGM_GCPHYS_ALIASED)
2750	{
2751	pVM->pgm.s.fGlobalSyncFlags \|= PGM_GLOBAL_SYNC_CLEAR_PGM_POOL;
2752	for (unsigned i=0;i<pVM->cCPUs;i++)
2753	{
2754	PVMCPU pVCpu = &pVM->aCpus[i];
2755	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2756	}
2757	rc = VINF_PGM_SYNC_CR3;
2758	}
2759	pgmUnlock(pVM);
2760	return rc;
2761	}
2762
2763
2764	/**
2765	* Scans all shadow page tables for mappings of a physical page.
2766	*
2767	* This may be slow, but it's most likely more efficient than cleaning
2768	* out the entire page pool / cache.
2769	*
2770	* @returns VBox status code.
2771	* @retval VINF_SUCCESS if all references has been successfully cleared.
2772	* @retval VINF_PGM_GCPHYS_ALIASED if we're better off with a CR3 sync and
2773	* a page pool cleaning.
2774	*
2775	* @param pVM The VM handle.
2776	* @param pPhysPage The guest page in question.
2777	*/
2778	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage)
2779	{
2780	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2781	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2782	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: cUsedPages=%d cPresent=%d pPhysPage=%R[pgmpage]\n",
2783	pPool->cUsedPages, pPool->cPresent, pPhysPage));
2784
2785	#if 1
2786	/*
2787	* There is a limit to what makes sense.
2788	*/
2789	if (pPool->cPresent > 1024)
2790	{
2791	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
2792	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2793	return VINF_PGM_GCPHYS_ALIASED;
2794	}
2795	#endif
2796
2797	/*
2798	* Iterate all the pages until we've encountered all that in use.
2799	* This is simple but not quite optimal solution.
2800	*/
2801	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2802	const uint32_t u32 = u64;
2803	unsigned cLeft = pPool->cUsedPages;
2804	unsigned iPage = pPool->cCurPages;
2805	while (--iPage >= PGMPOOL_IDX_FIRST)
2806	{
2807	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
2808	if (pPage->GCPhys != NIL_RTGCPHYS)
2809	{
2810	switch (pPage->enmKind)
2811	{
2812	/*
2813	* We only care about shadow page tables.
2814	*/
2815	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2816	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2817	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2818	{
2819	unsigned cPresent = pPage->cPresent;
2820	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2821	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2822	if (pPT->a[i].n.u1Present)
2823	{
2824	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2825	{
2826	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX32\n", iPage, i, pPT->a[i]));
2827	pPT->a[i].u = 0;
2828	}
2829	if (!--cPresent)
2830	break;
2831	}
2832	break;
2833	}
2834
2835	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2836	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2837	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2838	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2839	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2840	{
2841	unsigned cPresent = pPage->cPresent;
2842	PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2843	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2844	if (pPT->a[i].n.u1Present)
2845	{
2846	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2847	{
2848	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
2849	pPT->a[i].u = 0;
2850	}
2851	if (!--cPresent)
2852	break;
2853	}
2854	break;
2855	}
2856	}
2857	if (!--cLeft)
2858	break;
2859	}
2860	}
2861
2862	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2863	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2864	return VINF_SUCCESS;
2865	}
2866
2867
2868	/**
2869	* Clears the user entry in a user table.
2870	*
2871	* This is used to remove all references to a page when flushing it.
2872	*/
2873	static void pgmPoolTrackClearPageUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PCPGMPOOLUSER pUser)
2874	{
2875	Assert(pUser->iUser != NIL_PGMPOOL_IDX);
2876	Assert(pUser->iUser < pPool->cCurPages);
2877	uint32_t iUserTable = pUser->iUserTable;
2878
2879	/*
2880	* Map the user page.
2881	*/
2882	PPGMPOOLPAGE pUserPage = &pPool->aPages[pUser->iUser];
2883	union
2884	{
2885	uint64_t *pau64;
2886	uint32_t *pau32;
2887	} u;
2888	u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pUserPage);
2889
2890	LogFlow(("pgmPoolTrackClearPageUser: clear %x in %s (%RGp) (flushing %s)\n", iUserTable, pgmPoolPoolKindToStr(pUserPage->enmKind), pUserPage->Core.Key, pgmPoolPoolKindToStr(pPage->enmKind)));
2891
2892	/* Safety precaution in case we change the paging for other modes too in the future. */
2893	Assert(!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage));
2894
2895	#ifdef VBOX_STRICT
2896	/*
2897	* Some sanity checks.
2898	*/
2899	switch (pUserPage->enmKind)
2900	{
2901	case PGMPOOLKIND_32BIT_PD:
2902	case PGMPOOLKIND_32BIT_PD_PHYS:
2903	Assert(iUserTable < X86_PG_ENTRIES);
2904	break;
2905	case PGMPOOLKIND_PAE_PDPT:
2906	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2907	case PGMPOOLKIND_PAE_PDPT_PHYS:
2908	Assert(iUserTable < 4);
2909	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2910	break;
2911	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2912	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2913	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2914	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2915	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2916	case PGMPOOLKIND_PAE_PD_PHYS:
2917	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2918	break;
2919	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2920	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2921	Assert(!(u.pau64[iUserTable] & PGM_PDFLAGS_MAPPING));
2922	break;
2923	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2924	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2925	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2926	break;
2927	case PGMPOOLKIND_64BIT_PML4:
2928	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2929	/* GCPhys >> PAGE_SHIFT is the index here */
2930	break;
2931	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2932	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2933	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2934	break;
2935
2936	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2937	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2938	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2939	break;
2940
2941	case PGMPOOLKIND_ROOT_NESTED:
2942	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2943	break;
2944
2945	default:
2946	AssertMsgFailed(("enmKind=%d\n", pUserPage->enmKind));
2947	break;
2948	}
2949	#endif /* VBOX_STRICT */
2950
2951	/*
2952	* Clear the entry in the user page.
2953	*/
2954	switch (pUserPage->enmKind)
2955	{
2956	/* 32-bit entries */
2957	case PGMPOOLKIND_32BIT_PD:
2958	case PGMPOOLKIND_32BIT_PD_PHYS:
2959	u.pau32[iUserTable] = 0;
2960	break;
2961
2962	/* 64-bit entries */
2963	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2964	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2965	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2966	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2967	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2968	#if defined(IN_RC)
2969	/* In 32 bits PAE mode we must invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
2970	* non-present PDPT will continue to cause page faults.
2971	*/
2972	ASMReloadCR3();
2973	#endif
2974	/* no break */
2975	case PGMPOOLKIND_PAE_PD_PHYS:
2976	case PGMPOOLKIND_PAE_PDPT_PHYS:
2977	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2978	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2979	case PGMPOOLKIND_64BIT_PML4:
2980	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2981	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2982	case PGMPOOLKIND_PAE_PDPT:
2983	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2984	case PGMPOOLKIND_ROOT_NESTED:
2985	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2986	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2987	u.pau64[iUserTable] = 0;
2988	break;
2989
2990	default:
2991	AssertFatalMsgFailed(("enmKind=%d iUser=%#x iUserTable=%#x\n", pUserPage->enmKind, pUser->iUser, pUser->iUserTable));
2992	}
2993	}
2994
2995
2996	/**
2997	* Clears all users of a page.
2998	*/
2999	static void pgmPoolTrackClearPageUsers(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3000	{
3001	/*
3002	* Free all the user records.
3003	*/
3004	LogFlow(("pgmPoolTrackClearPageUsers %RGp\n", pPage->GCPhys));
3005
3006	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
3007	uint16_t i = pPage->iUserHead;
3008	while (i != NIL_PGMPOOL_USER_INDEX)
3009	{
3010	/* Clear enter in user table. */
3011	pgmPoolTrackClearPageUser(pPool, pPage, &paUsers[i]);
3012
3013	/* Free it. */
3014	const uint16_t iNext = paUsers[i].iNext;
3015	paUsers[i].iUser = NIL_PGMPOOL_IDX;
3016	paUsers[i].iNext = pPool->iUserFreeHead;
3017	pPool->iUserFreeHead = i;
3018
3019	/* Next. */
3020	i = iNext;
3021	}
3022	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3023	}
3024
3025	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3026
3027	/**
3028	* Allocates a new physical cross reference extent.
3029	*
3030	* @returns Pointer to the allocated extent on success. NULL if we're out of them.
3031	* @param pVM The VM handle.
3032	* @param piPhysExt Where to store the phys ext index.
3033	*/
3034	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt)
3035	{
3036	Assert(PGMIsLockOwner(pVM));
3037	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3038	uint16_t iPhysExt = pPool->iPhysExtFreeHead;
3039	if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
3040	{
3041	STAM_COUNTER_INC(&pPool->StamTrackPhysExtAllocFailures);
3042	return NULL;
3043	}
3044	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3045	pPool->iPhysExtFreeHead = pPhysExt->iNext;
3046	pPhysExt->iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3047	*piPhysExt = iPhysExt;
3048	return pPhysExt;
3049	}
3050
3051
3052	/**
3053	* Frees a physical cross reference extent.
3054	*
3055	* @param pVM The VM handle.
3056	* @param iPhysExt The extent to free.
3057	*/
3058	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt)
3059	{
3060	Assert(PGMIsLockOwner(pVM));
3061	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3062	Assert(iPhysExt < pPool->cMaxPhysExts);
3063	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3064	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3065	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3066	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3067	pPool->iPhysExtFreeHead = iPhysExt;
3068	}
3069
3070
3071	/**
3072	* Frees a physical cross reference extent.
3073	*
3074	* @param pVM The VM handle.
3075	* @param iPhysExt The extent to free.
3076	*/
3077	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt)
3078	{
3079	Assert(PGMIsLockOwner(pVM));
3080	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3081
3082	const uint16_t iPhysExtStart = iPhysExt;
3083	PPGMPOOLPHYSEXT pPhysExt;
3084	do
3085	{
3086	Assert(iPhysExt < pPool->cMaxPhysExts);
3087	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3088	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3089	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3090
3091	/* next */
3092	iPhysExt = pPhysExt->iNext;
3093	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3094
3095	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3096	pPool->iPhysExtFreeHead = iPhysExtStart;
3097	}
3098
3099
3100	/**
3101	* Insert a reference into a list of physical cross reference extents.
3102	*
3103	* @returns The new tracking data for PGMPAGE.
3104	*
3105	* @param pVM The VM handle.
3106	* @param iPhysExt The physical extent index of the list head.
3107	* @param iShwPT The shadow page table index.
3108	*
3109	*/
3110	static uint16_t pgmPoolTrackPhysExtInsert(PVM pVM, uint16_t iPhysExt, uint16_t iShwPT)
3111	{
3112	Assert(PGMIsLockOwner(pVM));
3113	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3114	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3115
3116	/* special common case. */
3117	if (paPhysExts[iPhysExt].aidx[2] == NIL_PGMPOOL_IDX)
3118	{
3119	paPhysExts[iPhysExt].aidx[2] = iShwPT;
3120	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3121	LogFlow(("pgmPoolTrackPhysExtAddref: %d:{,,%d}\n", iPhysExt, iShwPT));
3122	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3123	}
3124
3125	/* general treatment. */
3126	const uint16_t iPhysExtStart = iPhysExt;
3127	unsigned cMax = 15;
3128	for (;;)
3129	{
3130	Assert(iPhysExt < pPool->cMaxPhysExts);
3131	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3132	if (paPhysExts[iPhysExt].aidx[i] == NIL_PGMPOOL_IDX)
3133	{
3134	paPhysExts[iPhysExt].aidx[i] = iShwPT;
3135	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3136	LogFlow(("pgmPoolTrackPhysExtAddref: %d:{%d} i=%d cMax=%d\n", iPhysExt, iShwPT, i, cMax));
3137	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtStart);
3138	}
3139	if (!--cMax)
3140	{
3141	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3142	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3143	LogFlow(("pgmPoolTrackPhysExtAddref: overflow (1) iShwPT=%d\n", iShwPT));
3144	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3145	}
3146	}
3147
3148	/* add another extent to the list. */
3149	PPGMPOOLPHYSEXT pNew = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3150	if (!pNew)
3151	{
3152	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3153	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3154	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3155	}
3156	pNew->iNext = iPhysExtStart;
3157	pNew->aidx[0] = iShwPT;
3158	LogFlow(("pgmPoolTrackPhysExtAddref: added new extent %d:{%d}->%d\n", iPhysExt, iShwPT, iPhysExtStart));
3159	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3160	}
3161
3162
3163	/**
3164	* Add a reference to guest physical page where extents are in use.
3165	*
3166	* @returns The new tracking data for PGMPAGE.
3167	*
3168	* @param pVM The VM handle.
3169	* @param u16 The ram range flags (top 16-bits).
3170	* @param iShwPT The shadow page table index.
3171	*/
3172	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT)
3173	{
3174	pgmLock(pVM);
3175	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3176	{
3177	/*
3178	* Convert to extent list.
3179	*/
3180	Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
3181	uint16_t iPhysExt;
3182	PPGMPOOLPHYSEXT pPhysExt = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3183	if (pPhysExt)
3184	{
3185	LogFlow(("pgmPoolTrackPhysExtAddref: new extent: %d:{%d, %d}\n", iPhysExt, PGMPOOL_TD_GET_IDX(u16), iShwPT));
3186	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliased);
3187	pPhysExt->aidx[0] = PGMPOOL_TD_GET_IDX(u16);
3188	pPhysExt->aidx[1] = iShwPT;
3189	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3190	}
3191	else
3192	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3193	}
3194	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3195	{
3196	/*
3197	* Insert into the extent list.
3198	*/
3199	u16 = pgmPoolTrackPhysExtInsert(pVM, PGMPOOL_TD_GET_IDX(u16), iShwPT);
3200	}
3201	else
3202	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedLots);
3203	pgmUnlock(pVM);
3204	return u16;
3205	}
3206
3207
3208	/**
3209	* Clear references to guest physical memory.
3210	*
3211	* @param pPool The pool.
3212	* @param pPage The page.
3213	* @param pPhysPage Pointer to the aPages entry in the ram range.
3214	*/
3215	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMPAGE pPhysPage)
3216	{
3217	const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
3218	AssertFatalMsg(cRefs == PGMPOOL_TD_CREFS_PHYSEXT, ("cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3219
3220	uint16_t iPhysExt = PGM_PAGE_GET_TD_IDX(pPhysPage);
3221	if (iPhysExt != PGMPOOL_TD_IDX_OVERFLOWED)
3222	{
3223	PVM pVM = pPool->CTX_SUFF(pVM);
3224	pgmLock(pVM);
3225
3226	uint16_t iPhysExtPrev = NIL_PGMPOOL_PHYSEXT_INDEX;
3227	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3228	do
3229	{
3230	Assert(iPhysExt < pPool->cMaxPhysExts);
3231
3232	/*
3233	* Look for the shadow page and check if it's all freed.
3234	*/
3235	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3236	{
3237	if (paPhysExts[iPhysExt].aidx[i] == pPage->idx)
3238	{
3239	paPhysExts[iPhysExt].aidx[i] = NIL_PGMPOOL_IDX;
3240
3241	for (i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3242	if (paPhysExts[iPhysExt].aidx[i] != NIL_PGMPOOL_IDX)
3243	{
3244	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3245	pgmUnlock(pVM);
3246	return;
3247	}
3248
3249	/* we can free the node. */
3250	const uint16_t iPhysExtNext = paPhysExts[iPhysExt].iNext;
3251	if ( iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX
3252	&& iPhysExtNext == NIL_PGMPOOL_PHYSEXT_INDEX)
3253	{
3254	/* lonely node */
3255	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3256	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d lonely\n", pPhysPage, pPage->idx));
3257	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3258	}
3259	else if (iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX)
3260	{
3261	/* head */
3262	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d head\n", pPhysPage, pPage->idx));
3263	PGM_PAGE_SET_TRACKING(pPhysPage, PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtNext));
3264	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3265	}
3266	else
3267	{
3268	/* in list */
3269	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3270	paPhysExts[iPhysExtPrev].iNext = iPhysExtNext;
3271	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3272	}
3273	iPhysExt = iPhysExtNext;
3274	pgmUnlock(pVM);
3275	return;
3276	}
3277	}
3278
3279	/* next */
3280	iPhysExtPrev = iPhysExt;
3281	iPhysExt = paPhysExts[iPhysExt].iNext;
3282	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3283
3284	pgmUnlock(pVM);
3285	AssertFatalMsgFailed(("not-found! cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3286	}
3287	else /* nothing to do */
3288	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage]\n", pPhysPage));
3289	}
3290
3291
3292	/**
3293	* Clear references to guest physical memory.
3294	*
3295	* This is the same as pgmPoolTracDerefGCPhys except that the guest physical address
3296	* is assumed to be correct, so the linear search can be skipped and we can assert
3297	* at an earlier point.
3298	*
3299	* @param pPool The pool.
3300	* @param pPage The page.
3301	* @param HCPhys The host physical address corresponding to the guest page.
3302	* @param GCPhys The guest physical address corresponding to HCPhys.
3303	*/
3304	static void pgmPoolTracDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhys)
3305	{
3306	/*
3307	* Walk range list.
3308	*/
3309	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3310	while (pRam)
3311	{
3312	RTGCPHYS off = GCPhys - pRam->GCPhys;
3313	if (off < pRam->cb)
3314	{
3315	/* does it match? */
3316	const unsigned iPage = off >> PAGE_SHIFT;
3317	Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3318	#ifdef LOG_ENABLED
3319	RTHCPHYS HCPhysPage = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]);
3320	Log2(("pgmPoolTracDerefGCPhys %RHp vs %RHp\n", HCPhysPage, HCPhys));
3321	#endif
3322	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3323	{
3324	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3325	return;
3326	}
3327	break;
3328	}
3329	pRam = pRam->CTX_SUFF(pNext);
3330	}
3331	AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp\n", HCPhys, GCPhys));
3332	}
3333
3334
3335	/**
3336	* Clear references to guest physical memory.
3337	*
3338	* @param pPool The pool.
3339	* @param pPage The page.
3340	* @param HCPhys The host physical address corresponding to the guest page.
3341	* @param GCPhysHint The guest physical address which may corresponding to HCPhys.
3342	*/
3343	static void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint)
3344	{
3345	Log4(("pgmPoolTracDerefGCPhysHint %RHp %RGp\n", HCPhys, GCPhysHint));
3346
3347	/*
3348	* Walk range list.
3349	*/
3350	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3351	while (pRam)
3352	{
3353	RTGCPHYS off = GCPhysHint - pRam->GCPhys;
3354	if (off < pRam->cb)
3355	{
3356	/* does it match? */
3357	const unsigned iPage = off >> PAGE_SHIFT;
3358	Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3359	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3360	{
3361	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3362	return;
3363	}
3364	break;
3365	}
3366	pRam = pRam->CTX_SUFF(pNext);
3367	}
3368
3369	/*
3370	* Damn, the hint didn't work. We'll have to do an expensive linear search.
3371	*/
3372	STAM_COUNTER_INC(&pPool->StatTrackLinearRamSearches);
3373	pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3374	while (pRam)
3375	{
3376	unsigned iPage = pRam->cb >> PAGE_SHIFT;
3377	while (iPage-- > 0)
3378	{
3379	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3380	{
3381	Log4(("pgmPoolTracDerefGCPhysHint: Linear HCPhys=%RHp GCPhysHint=%RGp GCPhysReal=%RGp\n",
3382	HCPhys, GCPhysHint, pRam->GCPhys + (iPage << PAGE_SHIFT)));
3383	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3384	return;
3385	}
3386	}
3387	pRam = pRam->CTX_SUFF(pNext);
3388	}
3389
3390	AssertFatalMsgFailed(("HCPhys=%RHp GCPhysHint=%RGp\n", HCPhys, GCPhysHint));
3391	}
3392
3393
3394	/**
3395	* Clear references to guest physical memory in a 32-bit / 32-bit page table.
3396	*
3397	* @param pPool The pool.
3398	* @param pPage The page.
3399	* @param pShwPT The shadow page table (mapping of the page).
3400	* @param pGstPT The guest page table.
3401	*/
3402	DECLINLINE(void) pgmPoolTrackDerefPT32Bit32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT, PCX86PT pGstPT)
3403	{
3404	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
3405	if (pShwPT->a[i].n.u1Present)
3406	{
3407	Log4(("pgmPoolTrackDerefPT32Bit32Bit: i=%d pte=%RX32 hint=%RX32\n",
3408	i, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
3409	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
3410	if (!--pPage->cPresent)
3411	break;
3412	}
3413	}
3414
3415
3416	/**
3417	* Clear references to guest physical memory in a PAE / 32-bit page table.
3418	*
3419	* @param pPool The pool.
3420	* @param pPage The page.
3421	* @param pShwPT The shadow page table (mapping of the page).
3422	* @param pGstPT The guest page table (just a half one).
3423	*/
3424	DECLINLINE(void) pgmPoolTrackDerefPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PT pGstPT)
3425	{
3426	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++)
3427	if (pShwPT->a[i].n.u1Present)
3428	{
3429	Log4(("pgmPoolTrackDerefPTPae32Bit: i=%d pte=%RX64 hint=%RX32\n",
3430	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
3431	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
3432	}
3433	}
3434
3435
3436	/**
3437	* Clear references to guest physical memory in a PAE / PAE page table.
3438	*
3439	* @param pPool The pool.
3440	* @param pPage The page.
3441	* @param pShwPT The shadow page table (mapping of the page).
3442	* @param pGstPT The guest page table.
3443	*/
3444	DECLINLINE(void) pgmPoolTrackDerefPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
3445	{
3446	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++)
3447	if (pShwPT->a[i].n.u1Present)
3448	{
3449	Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n",
3450	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
3451	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK);
3452	}
3453	}
3454
3455
3456	/**
3457	* Clear references to guest physical memory in a 32-bit / 4MB page table.
3458	*
3459	* @param pPool The pool.
3460	* @param pPage The page.
3461	* @param pShwPT The shadow page table (mapping of the page).
3462	*/
3463	DECLINLINE(void) pgmPoolTrackDerefPT32Bit4MB(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT)
3464	{
3465	RTGCPHYS GCPhys = pPage->GCPhys;
3466	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3467	if (pShwPT->a[i].n.u1Present)
3468	{
3469	Log4(("pgmPoolTrackDerefPT32Bit4MB: i=%d pte=%RX32 GCPhys=%RGp\n",
3470	i, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys));
3471	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys);
3472	}
3473	}
3474
3475
3476	/**
3477	* Clear references to guest physical memory in a PAE / 2/4MB page table.
3478	*
3479	* @param pPool The pool.
3480	* @param pPage The page.
3481	* @param pShwPT The shadow page table (mapping of the page).
3482	*/
3483	DECLINLINE(void) pgmPoolTrackDerefPTPaeBig(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT)
3484	{
3485	RTGCPHYS GCPhys = pPage->GCPhys;
3486	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3487	if (pShwPT->a[i].n.u1Present)
3488	{
3489	Log4(("pgmPoolTrackDerefPTPaeBig: i=%d pte=%RX64 hint=%RGp\n",
3490	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys));
3491	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys);
3492	}
3493	}
3494
3495	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
3496
3497
3498	/**
3499	* Clear references to shadowed pages in a 32 bits page directory.
3500	*
3501	* @param pPool The pool.
3502	* @param pPage The page.
3503	* @param pShwPD The shadow page directory (mapping of the page).
3504	*/
3505	DECLINLINE(void) pgmPoolTrackDerefPD(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PD pShwPD)
3506	{
3507	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3508	{
3509	if ( pShwPD->a[i].n.u1Present
3510	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
3511	)
3512	{
3513	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PG_MASK);
3514	if (pSubPage)
3515	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3516	else
3517	AssertFatalMsgFailed(("%x\n", pShwPD->a[i].u & X86_PDE_PG_MASK));
3518	}
3519	}
3520	}
3521
3522	/**
3523	* Clear references to shadowed pages in a PAE (legacy or 64 bits) page directory.
3524	*
3525	* @param pPool The pool.
3526	* @param pPage The page.
3527	* @param pShwPD The shadow page directory (mapping of the page).
3528	*/
3529	DECLINLINE(void) pgmPoolTrackDerefPDPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPAE pShwPD)
3530	{
3531	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3532	{
3533	if ( pShwPD->a[i].n.u1Present
3534	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
3535	)
3536	{
3537	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PAE_PG_MASK);
3538	if (pSubPage)
3539	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3540	else
3541	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & X86_PDE_PAE_PG_MASK));
3542	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3543	}
3544	}
3545	}
3546
3547	/**
3548	* Clear references to shadowed pages in a PAE page directory pointer table.
3549	*
3550	* @param pPool The pool.
3551	* @param pPage The page.
3552	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3553	*/
3554	DECLINLINE(void) pgmPoolTrackDerefPDPTPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
3555	{
3556	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
3557	{
3558	if ( pShwPDPT->a[i].n.u1Present
3559	&& !(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING)
3560	)
3561	{
3562	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
3563	if (pSubPage)
3564	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3565	else
3566	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
3567	}
3568	}
3569	}
3570
3571
3572	/**
3573	* Clear references to shadowed pages in a 64-bit page directory pointer table.
3574	*
3575	* @param pPool The pool.
3576	* @param pPage The page.
3577	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3578	*/
3579	DECLINLINE(void) pgmPoolTrackDerefPDPT64Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
3580	{
3581	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
3582	{
3583	Assert(!(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING));
3584	if (pShwPDPT->a[i].n.u1Present)
3585	{
3586	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
3587	if (pSubPage)
3588	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3589	else
3590	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
3591	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3592	}
3593	}
3594	}
3595
3596
3597	/**
3598	* Clear references to shadowed pages in a 64-bit level 4 page table.
3599	*
3600	* @param pPool The pool.
3601	* @param pPage The page.
3602	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
3603	*/
3604	DECLINLINE(void) pgmPoolTrackDerefPML464Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PML4 pShwPML4)
3605	{
3606	for (unsigned i = 0; i < RT_ELEMENTS(pShwPML4->a); i++)
3607	{
3608	if (pShwPML4->a[i].n.u1Present)
3609	{
3610	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPML4->a[i].u & X86_PDPE_PG_MASK);
3611	if (pSubPage)
3612	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3613	else
3614	AssertFatalMsgFailed(("%RX64\n", pShwPML4->a[i].u & X86_PML4E_PG_MASK));
3615	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3616	}
3617	}
3618	}
3619
3620
3621	/**
3622	* Clear references to shadowed pages in an EPT page table.
3623	*
3624	* @param pPool The pool.
3625	* @param pPage The page.
3626	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
3627	*/
3628	DECLINLINE(void) pgmPoolTrackDerefPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPT pShwPT)
3629	{
3630	RTGCPHYS GCPhys = pPage->GCPhys;
3631	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3632	if (pShwPT->a[i].n.u1Present)
3633	{
3634	Log4(("pgmPoolTrackDerefPTEPT: i=%d pte=%RX64 GCPhys=%RX64\n",
3635	i, pShwPT->a[i].u & EPT_PTE_PG_MASK, pPage->GCPhys));
3636	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & EPT_PTE_PG_MASK, GCPhys);
3637	}
3638	}
3639
3640
3641	/**
3642	* Clear references to shadowed pages in an EPT page directory.
3643	*
3644	* @param pPool The pool.
3645	* @param pPage The page.
3646	* @param pShwPD The shadow page directory (mapping of the page).
3647	*/
3648	DECLINLINE(void) pgmPoolTrackDerefPDEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPD pShwPD)
3649	{
3650	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3651	{
3652	if (pShwPD->a[i].n.u1Present)
3653	{
3654	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & EPT_PDE_PG_MASK);
3655	if (pSubPage)
3656	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3657	else
3658	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & EPT_PDE_PG_MASK));
3659	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3660	}
3661	}
3662	}
3663
3664
3665	/**
3666	* Clear references to shadowed pages in an EPT page directory pointer table.
3667	*
3668	* @param pPool The pool.
3669	* @param pPage The page.
3670	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3671	*/
3672	DECLINLINE(void) pgmPoolTrackDerefPDPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPDPT pShwPDPT)
3673	{
3674	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
3675	{
3676	if (pShwPDPT->a[i].n.u1Present)
3677	{
3678	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK);
3679	if (pSubPage)
3680	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3681	else
3682	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK));
3683	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3684	}
3685	}
3686	}
3687
3688
3689	/**
3690	* Clears all references made by this page.
3691	*
3692	* This includes other shadow pages and GC physical addresses.
3693	*
3694	* @param pPool The pool.
3695	* @param pPage The page.
3696	*/
3697	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3698	{
3699	/*
3700	* Map the shadow page and take action according to the page kind.
3701	*/
3702	void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
3703	switch (pPage->enmKind)
3704	{
3705	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3706	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3707	{
3708	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3709	void *pvGst;
3710	int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3711	pgmPoolTrackDerefPT32Bit32Bit(pPool, pPage, (PX86PT)pvShw, (PCX86PT)pvGst);
3712	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3713	break;
3714	}
3715
3716	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3717	{
3718	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3719	void *pvGst;
3720	int rc = PGM_GCPHYS_2_PTR_EX(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3721	pgmPoolTrackDerefPTPae32Bit(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PT)pvGst);
3722	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3723	break;
3724	}
3725
3726	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3727	{
3728	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3729	void *pvGst;
3730	int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3731	pgmPoolTrackDerefPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
3732	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3733	break;
3734	}
3735
3736	case PGMPOOLKIND_32BIT_PT_FOR_PHYS: /* treat it like a 4 MB page */
3737	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3738	{
3739	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3740	pgmPoolTrackDerefPT32Bit4MB(pPool, pPage, (PX86PT)pvShw);
3741	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3742	break;
3743	}
3744
3745	case PGMPOOLKIND_PAE_PT_FOR_PHYS: /* treat it like a 2 MB page */
3746	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3747	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3748	{
3749	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3750	pgmPoolTrackDerefPTPaeBig(pPool, pPage, (PX86PTPAE)pvShw);
3751	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3752	break;
3753	}
3754
3755	#else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
3756	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3757	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3758	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3759	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3760	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3761	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3762	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3763	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3764	break;
3765	#endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
3766
3767	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3768	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3769	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3770	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3771	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3772	case PGMPOOLKIND_PAE_PD_PHYS:
3773	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3774	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3775	pgmPoolTrackDerefPDPae(pPool, pPage, (PX86PDPAE)pvShw);
3776	break;
3777
3778	case PGMPOOLKIND_32BIT_PD_PHYS:
3779	case PGMPOOLKIND_32BIT_PD:
3780	pgmPoolTrackDerefPD(pPool, pPage, (PX86PD)pvShw);
3781	break;
3782
3783	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3784	case PGMPOOLKIND_PAE_PDPT:
3785	case PGMPOOLKIND_PAE_PDPT_PHYS:
3786	pgmPoolTrackDerefPDPTPae(pPool, pPage, (PX86PDPT)pvShw);
3787	break;
3788
3789	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3790	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3791	pgmPoolTrackDerefPDPT64Bit(pPool, pPage, (PX86PDPT)pvShw);
3792	break;
3793
3794	case PGMPOOLKIND_64BIT_PML4:
3795	pgmPoolTrackDerefPML464Bit(pPool, pPage, (PX86PML4)pvShw);
3796	break;
3797
3798	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3799	pgmPoolTrackDerefPTEPT(pPool, pPage, (PEPTPT)pvShw);
3800	break;
3801
3802	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3803	pgmPoolTrackDerefPDEPT(pPool, pPage, (PEPTPD)pvShw);
3804	break;
3805
3806	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3807	pgmPoolTrackDerefPDPTEPT(pPool, pPage, (PEPTPDPT)pvShw);
3808	break;
3809
3810	default:
3811	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
3812	}
3813
3814	/* paranoia, clear the shadow page. Remove this laser (i.e. let Alloc and ClearAll do it). */
3815	STAM_PROFILE_START(&pPool->StatZeroPage, z);
3816	ASMMemZeroPage(pvShw);
3817	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
3818	pPage->fZeroed = true;
3819	PGMPOOL_UNLOCK_PTR(pPool->CTX_SUFF(pVM), pvShw);
3820	}
3821	#endif /* PGMPOOL_WITH_USER_TRACKING */
3822
3823	/**
3824	* Flushes a pool page.
3825	*
3826	* This moves the page to the free list after removing all user references to it.
3827	*
3828	* @returns VBox status code.
3829	* @retval VINF_SUCCESS on success.
3830	* @param pPool The pool.
3831	* @param HCPhys The HC physical address of the shadow page.
3832	*/
3833	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3834	{
3835	PVM pVM = pPool->CTX_SUFF(pVM);
3836
3837	int rc = VINF_SUCCESS;
3838	STAM_PROFILE_START(&pPool->StatFlushPage, f);
3839	LogFlow(("pgmPoolFlushPage: pPage=%p:{.Key=%RHp, .idx=%d, .enmKind=%s, .GCPhys=%RGp}\n",
3840	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
3841
3842	/*
3843	* Quietly reject any attempts at flushing any of the special root pages.
3844	*/
3845	if (pPage->idx < PGMPOOL_IDX_FIRST)
3846	{
3847	AssertFailed(); /* can no longer happen */
3848	Log(("pgmPoolFlushPage: special root page, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
3849	return VINF_SUCCESS;
3850	}
3851
3852	pgmLock(pVM);
3853
3854	/*
3855	* Quietly reject any attempts at flushing the currently active shadow CR3 mapping
3856	*/
3857	if (pgmPoolIsPageLocked(&pVM->pgm.s, pPage))
3858	{
3859	AssertMsg( pPage->enmKind == PGMPOOLKIND_64BIT_PML4
3860	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT
3861	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT_FOR_32BIT
3862	\|\| pPage->enmKind == PGMPOOLKIND_32BIT_PD
3863	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD
3864	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD
3865	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD
3866	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD
3867	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
3868	("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(VMMGetCpu(pVM)), pPage->Core.Key, pPage->enmKind));
3869	Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
3870	pgmUnlock(pVM);
3871	return VINF_SUCCESS;
3872	}
3873
3874	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3875	/* Start a subset so we won't run out of mapping space. */
3876	PVMCPU pVCpu = VMMGetCpu(pVM);
3877	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
3878	#endif
3879
3880	/*
3881	* Mark the page as being in need of a ASMMemZeroPage().
3882	*/
3883	pPage->fZeroed = false;
3884
3885	#ifdef PGMPOOL_WITH_USER_TRACKING
3886	/*
3887	* Clear the page.
3888	*/
3889	pgmPoolTrackClearPageUsers(pPool, pPage);
3890	STAM_PROFILE_START(&pPool->StatTrackDeref,a);
3891	pgmPoolTrackDeref(pPool, pPage);
3892	STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
3893	#endif
3894
3895	#ifdef PGMPOOL_WITH_CACHE
3896	/*
3897	* Flush it from the cache.
3898	*/
3899	pgmPoolCacheFlushPage(pPool, pPage);
3900	#endif /* PGMPOOL_WITH_CACHE */
3901
3902	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3903	/* Heavy stuff done. */
3904	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
3905	#endif
3906
3907	#ifdef PGMPOOL_WITH_MONITORING
3908	/*
3909	* Deregistering the monitoring.
3910	*/
3911	if (pPage->fMonitored)
3912	rc = pgmPoolMonitorFlush(pPool, pPage);
3913	#endif
3914
3915	/*
3916	* Free the page.
3917	*/
3918	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
3919	pPage->iNext = pPool->iFreeHead;
3920	pPool->iFreeHead = pPage->idx;
3921	pPage->enmKind = PGMPOOLKIND_FREE;
3922	pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
3923	pPage->GCPhys = NIL_RTGCPHYS;
3924	pPage->fReusedFlushPending = false;
3925
3926	pPool->cUsedPages--;
3927	pgmUnlock(pVM);
3928	STAM_PROFILE_STOP(&pPool->StatFlushPage, f);
3929	return rc;
3930	}
3931
3932
3933	/**
3934	* Frees a usage of a pool page.
3935	*
3936	* The caller is responsible to updating the user table so that it no longer
3937	* references the shadow page.
3938	*
3939	* @param pPool The pool.
3940	* @param HCPhys The HC physical address of the shadow page.
3941	* @param iUser The shadow page pool index of the user table.
3942	* @param iUserTable The index into the user table (shadowed).
3943	*/
3944	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
3945	{
3946	PVM pVM = pPool->CTX_SUFF(pVM);
3947
3948	STAM_PROFILE_START(&pPool->StatFree, a);
3949	LogFlow(("pgmPoolFreeByPage: pPage=%p:{.Key=%RHp, .idx=%d, enmKind=%s} iUser=%#x iUserTable=%#x\n",
3950	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), iUser, iUserTable));
3951	Assert(pPage->idx >= PGMPOOL_IDX_FIRST);
3952	pgmLock(pVM);
3953	#ifdef PGMPOOL_WITH_USER_TRACKING
3954	pgmPoolTrackFreeUser(pPool, pPage, iUser, iUserTable);
3955	#endif
3956	#ifdef PGMPOOL_WITH_CACHE
3957	if (!pPage->fCached)
3958	#endif
3959	pgmPoolFlushPage(pPool, pPage);
3960	pgmUnlock(pVM);
3961	STAM_PROFILE_STOP(&pPool->StatFree, a);
3962	}
3963
3964
3965	/**
3966	* Makes one or more free page free.
3967	*
3968	* @returns VBox status code.
3969	* @retval VINF_SUCCESS on success.
3970	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
3971	*
3972	* @param pPool The pool.
3973	* @param enmKind Page table kind
3974	* @param iUser The user of the page.
3975	*/
3976	static int pgmPoolMakeMoreFreePages(PPGMPOOL pPool, PGMPOOLKIND enmKind, uint16_t iUser)
3977	{
3978	PVM pVM = pPool->CTX_SUFF(pVM);
3979
3980	LogFlow(("pgmPoolMakeMoreFreePages: iUser=%#x\n", iUser));
3981
3982	/*
3983	* If the pool isn't full grown yet, expand it.
3984	*/
3985	if ( pPool->cCurPages < pPool->cMaxPages
3986	#if defined(IN_RC)
3987	/* Hack alert: we can't deal with jumps to ring 3 when called from MapCR3 and allocating pages for PAE PDs. */
3988	&& enmKind != PGMPOOLKIND_PAE_PD_FOR_PAE_PD
3989	&& (enmKind < PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD \|\| enmKind > PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD)
3990	#endif
3991	)
3992	{
3993	STAM_PROFILE_ADV_SUSPEND(&pPool->StatAlloc, a);
3994	#ifdef IN_RING3
3995	int rc = PGMR3PoolGrow(pVM);
3996	#else
3997	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_POOL_GROW, 0);
3998	#endif
3999	if (RT_FAILURE(rc))
4000	return rc;
4001	STAM_PROFILE_ADV_RESUME(&pPool->StatAlloc, a);
4002	if (pPool->iFreeHead != NIL_PGMPOOL_IDX)
4003	return VINF_SUCCESS;
4004	}
4005
4006	#ifdef PGMPOOL_WITH_CACHE
4007	/*
4008	* Free one cached page.
4009	*/
4010	return pgmPoolCacheFreeOne(pPool, iUser);
4011	#else
4012	/*
4013	* Flush the pool.
4014	*
4015	* If we have tracking enabled, it should be possible to come up with
4016	* a cheap replacement strategy...
4017	*/
4018	/* @todo This path no longer works (CR3 root pages will be flushed)!! */
4019	AssertCompileFailed();
4020	Assert(!CPUMIsGuestInLongMode(pVM));
4021	pgmPoolFlushAllInt(pPool);
4022	return VERR_PGM_POOL_FLUSHED;
4023	#endif
4024	}
4025
4026	/**
4027	* Allocates a page from the pool.
4028	*
4029	* This page may actually be a cached page and not in need of any processing
4030	* on the callers part.
4031	*
4032	* @returns VBox status code.
4033	* @retval VINF_SUCCESS if a NEW page was allocated.
4034	* @retval VINF_PGM_CACHED_PAGE if a CACHED page was returned.
4035	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4036	* @param pVM The VM handle.
4037	* @param GCPhys The GC physical address of the page we're gonna shadow.
4038	* For 4MB and 2MB PD entries, it's the first address the
4039	* shadow PT is covering.
4040	* @param enmKind The kind of mapping.
4041	* @param enmAccess Access type for the mapping (only relevant for big pages)
4042	* @param iUser The shadow page pool index of the user table.
4043	* @param iUserTable The index into the user table (shadowed).
4044	* @param ppPage Where to store the pointer to the page. NULL is stored here on failure.
4045	*/
4046	int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
4047	{
4048	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4049	STAM_PROFILE_ADV_START(&pPool->StatAlloc, a);
4050	LogFlow(("pgmPoolAlloc: GCPhys=%RGp enmKind=%s iUser=%#x iUserTable=%#x\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable));
4051	*ppPage = NULL;
4052	/** @todo CSAM/PGMPrefetchPage messes up here during CSAMR3CheckGates
4053	* (TRPMR3SyncIDT) because of FF priority. Try fix that?
4054	* Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL)); */
4055
4056	pgmLock(pVM);
4057
4058	#ifdef PGMPOOL_WITH_CACHE
4059	if (pPool->fCacheEnabled)
4060	{
4061	int rc2 = pgmPoolCacheAlloc(pPool, GCPhys, enmKind, enmAccess, iUser, iUserTable, ppPage);
4062	if (RT_SUCCESS(rc2))
4063	{
4064	pgmUnlock(pVM);
4065	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4066	LogFlow(("pgmPoolAlloc: cached returns %Rrc ppPage=%p:{.Key=%RHp, .idx=%d}\n", rc2, ppPage, (ppPage)->Core.Key, (ppPage)->idx));
4067	return rc2;
4068	}
4069	}
4070	#endif
4071
4072	/*
4073	* Allocate a new one.
4074	*/
4075	int rc = VINF_SUCCESS;
4076	uint16_t iNew = pPool->iFreeHead;
4077	if (iNew == NIL_PGMPOOL_IDX)
4078	{
4079	rc = pgmPoolMakeMoreFreePages(pPool, enmKind, iUser);
4080	if (RT_FAILURE(rc))
4081	{
4082	pgmUnlock(pVM);
4083	Log(("pgmPoolAlloc: returns %Rrc (Free)\n", rc));
4084	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4085	return rc;
4086	}
4087	iNew = pPool->iFreeHead;
4088	AssertReleaseReturn(iNew != NIL_PGMPOOL_IDX, VERR_INTERNAL_ERROR);
4089	}
4090
4091	/* unlink the free head */
4092	PPGMPOOLPAGE pPage = &pPool->aPages[iNew];
4093	pPool->iFreeHead = pPage->iNext;
4094	pPage->iNext = NIL_PGMPOOL_IDX;
4095
4096	/*
4097	* Initialize it.
4098	*/
4099	pPool->cUsedPages++; /* physical handler registration / pgmPoolTrackFlushGCPhysPTsSlow requirement. */
4100	pPage->enmKind = enmKind;
4101	pPage->enmAccess = enmAccess;
4102	pPage->GCPhys = GCPhys;
4103	pPage->fSeenNonGlobal = false; /* Set this to 'true' to disable this feature. */
4104	pPage->fMonitored = false;
4105	pPage->fCached = false;
4106	pPage->fReusedFlushPending = false;
4107	#ifdef PGMPOOL_WITH_MONITORING
4108	pPage->cModifications = 0;
4109	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4110	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4111	#else
4112	pPage->fCR3Mix = false;
4113	#endif
4114	#ifdef PGMPOOL_WITH_USER_TRACKING
4115	pPage->cPresent = 0;
4116	pPage->iFirstPresent = ~0;
4117
4118	/*
4119	* Insert into the tracking and cache. If this fails, free the page.
4120	*/
4121	int rc3 = pgmPoolTrackInsert(pPool, pPage, GCPhys, iUser, iUserTable);
4122	if (RT_FAILURE(rc3))
4123	{
4124	pPool->cUsedPages--;
4125	pPage->enmKind = PGMPOOLKIND_FREE;
4126	pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4127	pPage->GCPhys = NIL_RTGCPHYS;
4128	pPage->iNext = pPool->iFreeHead;
4129	pPool->iFreeHead = pPage->idx;
4130	pgmUnlock(pVM);
4131	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4132	Log(("pgmPoolAlloc: returns %Rrc (Insert)\n", rc3));
4133	return rc3;
4134	}
4135	#endif /* PGMPOOL_WITH_USER_TRACKING */
4136
4137	/*
4138	* Commit the allocation, clear the page and return.
4139	*/
4140	#ifdef VBOX_WITH_STATISTICS
4141	if (pPool->cUsedPages > pPool->cUsedPagesHigh)
4142	pPool->cUsedPagesHigh = pPool->cUsedPages;
4143	#endif
4144
4145	if (!pPage->fZeroed)
4146	{
4147	STAM_PROFILE_START(&pPool->StatZeroPage, z);
4148	void *pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
4149	ASMMemZeroPage(pv);
4150	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4151	}
4152
4153	*ppPage = pPage;
4154	pgmUnlock(pVM);
4155	LogFlow(("pgmPoolAlloc: returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d, .fCached=%RTbool, .fMonitored=%RTbool}\n",
4156	rc, pPage, pPage->Core.Key, pPage->idx, pPage->fCached, pPage->fMonitored));
4157	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4158	return rc;
4159	}
4160
4161
4162	/**
4163	* Frees a usage of a pool page.
4164	*
4165	* @param pVM The VM handle.
4166	* @param HCPhys The HC physical address of the shadow page.
4167	* @param iUser The shadow page pool index of the user table.
4168	* @param iUserTable The index into the user table (shadowed).
4169	*/
4170	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable)
4171	{
4172	LogFlow(("pgmPoolFree: HCPhys=%RHp iUser=%#x iUserTable=%#x\n", HCPhys, iUser, iUserTable));
4173	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4174	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, HCPhys), iUser, iUserTable);
4175	}
4176
4177	/**
4178	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
4179	*
4180	* @returns Pointer to the shadow page structure.
4181	* @param pPool The pool.
4182	* @param HCPhys The HC physical address of the shadow page.
4183	*/
4184	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4185	{
4186	PVM pVM = pPool->CTX_SUFF(pVM);
4187
4188	/*
4189	* Look up the page.
4190	*/
4191	pgmLock(pVM);
4192	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4193	pgmUnlock(pVM);
4194
4195	AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4196	return pPage;
4197	}
4198
4199
4200	#ifdef IN_RING3
4201	/**
4202	* Flushes the entire cache.
4203	*
4204	* It will assert a global CR3 flush (FF) and assumes the caller is aware of this
4205	* and execute this CR3 flush.
4206	*
4207	* @param pPool The pool.
4208	*/
4209	void pgmR3PoolReset(PVM pVM)
4210	{
4211	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4212
4213	Assert(PGMIsLockOwner(pVM));
4214	STAM_PROFILE_START(&pPool->StatFlushAllInt, a);
4215	LogFlow(("pgmPoolFlushAllInt:\n"));
4216
4217	/*
4218	* If there are no pages in the pool, there is nothing to do.
4219	*/
4220	if (pPool->cCurPages <= PGMPOOL_IDX_FIRST)
4221	{
4222	STAM_PROFILE_STOP(&pPool->StatFlushAllInt, a);
4223	return;
4224	}
4225
4226	/*
4227	* Exit the shadow mode since we're going to clear everything,
4228	* including the root page.
4229	*/
4230	for (unsigned i=0;i<pVM->cCPUs;i++)
4231	{
4232	PVMCPU pVCpu = &pVM->aCpus[i];
4233	pgmR3ExitShadowModeBeforePoolFlush(pVM, pVCpu);
4234	}
4235
4236	/*
4237	* Nuke the free list and reinsert all pages into it.
4238	*/
4239	for (unsigned i = pPool->cCurPages - 1; i >= PGMPOOL_IDX_FIRST; i--)
4240	{
4241	PPGMPOOLPAGE pPage = &pPool->aPages[i];
4242
4243	Assert(pPage->Core.Key == MMPage2Phys(pVM, pPage->pvPageR3));
4244	#ifdef PGMPOOL_WITH_MONITORING
4245	if (pPage->fMonitored)
4246	pgmPoolMonitorFlush(pPool, pPage);
4247	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4248	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4249	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
4250	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
4251	pPage->cModifications = 0;
4252	#endif
4253	pPage->GCPhys = NIL_RTGCPHYS;
4254	pPage->enmKind = PGMPOOLKIND_FREE;
4255	pPage->enmAccess = PGMPOOLACCESS_DONTCARE;
4256	Assert(pPage->idx == i);
4257	pPage->iNext = i + 1;
4258	pPage->fZeroed = false; /* This could probably be optimized, but better safe than sorry. */
4259	pPage->fSeenNonGlobal = false;
4260	pPage->fMonitored = false;
4261	pPage->fCached = false;
4262	pPage->fReusedFlushPending = false;
4263	#ifdef PGMPOOL_WITH_USER_TRACKING
4264	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
4265	#else
4266	pPage->fCR3Mix = false;
4267	#endif
4268	#ifdef PGMPOOL_WITH_CACHE
4269	pPage->iAgeNext = NIL_PGMPOOL_IDX;
4270	pPage->iAgePrev = NIL_PGMPOOL_IDX;
4271	#endif
4272	pPage->cLocked = 0;
4273	}
4274	pPool->aPages[pPool->cCurPages - 1].iNext = NIL_PGMPOOL_IDX;
4275	pPool->iFreeHead = PGMPOOL_IDX_FIRST;
4276	pPool->cUsedPages = 0;
4277
4278	#ifdef PGMPOOL_WITH_USER_TRACKING
4279	/*
4280	* Zap and reinitialize the user records.
4281	*/
4282	pPool->cPresent = 0;
4283	pPool->iUserFreeHead = 0;
4284	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
4285	const unsigned cMaxUsers = pPool->cMaxUsers;
4286	for (unsigned i = 0; i < cMaxUsers; i++)
4287	{
4288	paUsers[i].iNext = i + 1;
4289	paUsers[i].iUser = NIL_PGMPOOL_IDX;
4290	paUsers[i].iUserTable = 0xfffffffe;
4291	}
4292	paUsers[cMaxUsers - 1].iNext = NIL_PGMPOOL_USER_INDEX;
4293	#endif
4294
4295	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4296	/*
4297	* Clear all the GCPhys links and rebuild the phys ext free list.
4298	*/
4299	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
4300	pRam;
4301	pRam = pRam->CTX_SUFF(pNext))
4302	{
4303	unsigned iPage = pRam->cb >> PAGE_SHIFT;
4304	while (iPage-- > 0)
4305	PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
4306	}
4307
4308	pPool->iPhysExtFreeHead = 0;
4309	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
4310	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
4311	for (unsigned i = 0; i < cMaxPhysExts; i++)
4312	{
4313	paPhysExts[i].iNext = i + 1;
4314	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
4315	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
4316	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
4317	}
4318	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
4319	#endif
4320
4321	#ifdef PGMPOOL_WITH_MONITORING
4322	/*
4323	* Just zap the modified list.
4324	*/
4325	pPool->cModifiedPages = 0;
4326	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
4327	#endif
4328
4329	#ifdef PGMPOOL_WITH_CACHE
4330	/*
4331	* Clear the GCPhys hash and the age list.
4332	*/
4333	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aiHash); i++)
4334	pPool->aiHash[i] = NIL_PGMPOOL_IDX;
4335	pPool->iAgeHead = NIL_PGMPOOL_IDX;
4336	pPool->iAgeTail = NIL_PGMPOOL_IDX;
4337	#endif
4338
4339	/*
4340	* Reinsert active pages into the hash and ensure monitoring chains are correct.
4341	*/
4342	for (unsigned i = PGMPOOL_IDX_FIRST_SPECIAL; i < PGMPOOL_IDX_FIRST; i++)
4343	{
4344	PPGMPOOLPAGE pPage = &pPool->aPages[i];
4345	pPage->iNext = NIL_PGMPOOL_IDX;
4346	#ifdef PGMPOOL_WITH_MONITORING
4347	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4348	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4349	pPage->cModifications = 0;
4350	/* ASSUMES that we're not sharing with any of the other special pages (safe for now). */
4351	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
4352	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
4353	if (pPage->fMonitored)
4354	{
4355	int rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
4356	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
4357	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
4358	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
4359	pPool->pszAccessHandler);
4360	AssertFatalRCSuccess(rc);
4361	# ifdef PGMPOOL_WITH_CACHE
4362	pgmPoolHashInsert(pPool, pPage);
4363	# endif
4364	}
4365	#endif
4366	#ifdef PGMPOOL_WITH_USER_TRACKING
4367	Assert(pPage->iUserHead == NIL_PGMPOOL_USER_INDEX); /* for now */
4368	#endif
4369	#ifdef PGMPOOL_WITH_CACHE
4370	Assert(pPage->iAgeNext == NIL_PGMPOOL_IDX);
4371	Assert(pPage->iAgePrev == NIL_PGMPOOL_IDX);
4372	#endif
4373	}
4374
4375	for (unsigned i=0;i<pVM->cCPUs;i++)
4376	{
4377	PVMCPU pVCpu = &pVM->aCpus[i];
4378	/*
4379	* Re-enter the shadowing mode and assert Sync CR3 FF.
4380	*/
4381	pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
4382	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4383	}
4384
4385	STAM_PROFILE_STOP(&pPool->StatFlushAllInt, a);
4386	}
4387	#endif /* IN_RING3 */
4388
4389	#ifdef LOG_ENABLED
4390	static const char *pgmPoolPoolKindToStr(uint8_t enmKind)
4391	{
4392	switch(enmKind)
4393	{
4394	case PGMPOOLKIND_INVALID:
4395	return "PGMPOOLKIND_INVALID";
4396	case PGMPOOLKIND_FREE:
4397	return "PGMPOOLKIND_FREE";
4398	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
4399	return "PGMPOOLKIND_32BIT_PT_FOR_PHYS";
4400	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4401	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT";
4402	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4403	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB";
4404	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
4405	return "PGMPOOLKIND_PAE_PT_FOR_PHYS";
4406	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4407	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_PT";
4408	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4409	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB";
4410	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4411	return "PGMPOOLKIND_PAE_PT_FOR_PAE_PT";
4412	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4413	return "PGMPOOLKIND_PAE_PT_FOR_PAE_2MB";
4414	case PGMPOOLKIND_32BIT_PD:
4415	return "PGMPOOLKIND_32BIT_PD";
4416	case PGMPOOLKIND_32BIT_PD_PHYS:
4417	return "PGMPOOLKIND_32BIT_PD_PHYS";
4418	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4419	return "PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD";
4420	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4421	return "PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD";
4422	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4423	return "PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD";
4424	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4425	return "PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD";
4426	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4427	return "PGMPOOLKIND_PAE_PD_FOR_PAE_PD";
4428	case PGMPOOLKIND_PAE_PD_PHYS:
4429	return "PGMPOOLKIND_PAE_PD_PHYS";
4430	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4431	return "PGMPOOLKIND_PAE_PDPT_FOR_32BIT";
4432	case PGMPOOLKIND_PAE_PDPT:
4433	return "PGMPOOLKIND_PAE_PDPT";
4434	case PGMPOOLKIND_PAE_PDPT_PHYS:
4435	return "PGMPOOLKIND_PAE_PDPT_PHYS";
4436	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4437	return "PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT";
4438	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4439	return "PGMPOOLKIND_64BIT_PDPT_FOR_PHYS";
4440	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4441	return "PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD";
4442	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4443	return "PGMPOOLKIND_64BIT_PD_FOR_PHYS";
4444	case PGMPOOLKIND_64BIT_PML4:
4445	return "PGMPOOLKIND_64BIT_PML4";
4446	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4447	return "PGMPOOLKIND_EPT_PDPT_FOR_PHYS";
4448	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4449	return "PGMPOOLKIND_EPT_PD_FOR_PHYS";
4450	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4451	return "PGMPOOLKIND_EPT_PT_FOR_PHYS";
4452	case PGMPOOLKIND_ROOT_NESTED:
4453	return "PGMPOOLKIND_ROOT_NESTED";
4454	}
4455	return "Unknown kind!";
4456	}
4457	#endif /* LOG_ENABLED*/

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp@ 20135

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