PGMAllPool.cpp@ 19872

Last change on this file since 19872 was 19872, checked in by vboxsync, 16 years ago
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1	/* $Id: PGMAllPool.cpp 19872 2009-05-20 15:05:53Z vboxsync $ */
2	/** @file
3	* PGM Shadow Page Pool.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.215389.xyz. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PGM_POOL
27	#include <VBox/pgm.h>
28	#include <VBox/mm.h>
29	#include <VBox/em.h>
30	#include <VBox/cpum.h>
31	#ifdef IN_RC
32	# include <VBox/patm.h>
33	#endif
34	#include "PGMInternal.h"
35	#include <VBox/vm.h>
36	#include <VBox/disopcode.h>
37	#include <VBox/hwacc_vmx.h>
38
39	#include <VBox/log.h>
40	#include <VBox/err.h>
41	#include <iprt/asm.h>
42	#include <iprt/string.h>
43
44
45	/*******************************************************************************
46	* Internal Functions *
47	*******************************************************************************/
48	__BEGIN_DECLS
49	static void pgmPoolFlushAllInt(PPGMPOOL pPool);
50	#ifdef PGMPOOL_WITH_USER_TRACKING
51	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind);
52	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind);
53	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
54	#endif
55	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
56	static void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint);
57	#endif
58	#ifdef PGMPOOL_WITH_CACHE
59	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
60	#endif
61	#ifdef PGMPOOL_WITH_MONITORING
62	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
63	#endif
64	#ifndef IN_RING3
65	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
66	#endif
67	#ifdef LOG_ENABLED
68	static const char *pgmPoolPoolKindToStr(uint8_t enmKind);
69	#endif
70
71	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs);
72	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt);
73	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage);
74	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt);
75	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt);
76	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt);
77
78	__END_DECLS
79
80
81	/**
82	* Checks if the specified page pool kind is for a 4MB or 2MB guest page.
83	*
84	* @returns true if it's the shadow of a 4MB or 2MB guest page, otherwise false.
85	* @param enmKind The page kind.
86	*/
87	DECLINLINE(bool) pgmPoolIsBigPage(PGMPOOLKIND enmKind)
88	{
89	switch (enmKind)
90	{
91	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
92	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
93	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
94	return true;
95	default:
96	return false;
97	}
98	}
99
100	/** @def PGMPOOL_PAGE_2_LOCKED_PTR
101	* Maps a pool page pool into the current context and lock it (RC only).
102	*
103	* @returns VBox status code.
104	* @param pVM The VM handle.
105	* @param pPage The pool page.
106	*
107	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
108	* small page window employeed by that function. Be careful.
109	* @remark There is no need to assert on the result.
110	*/
111	#if defined(IN_RC)
112	DECLINLINE(void *) PGMPOOL_PAGE_2_LOCKED_PTR(PVM pVM, PPGMPOOLPAGE pPage)
113	{
114	void *pv = pgmPoolMapPageInlined(&pVM->pgm.s, pPage);
115
116	/* Make sure the dynamic mapping will not be reused. */
117	if (pv)
118	PGMDynLockHCPage(pVM, (uint8_t *)pv);
119
120	return pv;
121	}
122	#else
123	# define PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage) PGMPOOL_PAGE_2_PTR(pVM, pPage)
124	#endif
125
126	/** @def PGMPOOL_UNLOCK_PTR
127	* Unlock a previously locked dynamic caching (RC only).
128	*
129	* @returns VBox status code.
130	* @param pVM The VM handle.
131	* @param pPage The pool page.
132	*
133	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
134	* small page window employeed by that function. Be careful.
135	* @remark There is no need to assert on the result.
136	*/
137	#if defined(IN_RC)
138	DECLINLINE(void) PGMPOOL_UNLOCK_PTR(PVM pVM, void *pvPage)
139	{
140	if (pvPage)
141	PGMDynUnlockHCPage(pVM, (uint8_t *)pvPage);
142	}
143	#else
144	# define PGMPOOL_UNLOCK_PTR(pVM, pPage) do {} while (0)
145	#endif
146
147
148	#ifdef PGMPOOL_WITH_MONITORING
149	/**
150	* Determin the size of a write instruction.
151	* @returns number of bytes written.
152	* @param pDis The disassembler state.
153	*/
154	static unsigned pgmPoolDisasWriteSize(PDISCPUSTATE pDis)
155	{
156	/*
157	* This is very crude and possibly wrong for some opcodes,
158	* but since it's not really supposed to be called we can
159	* probably live with that.
160	*/
161	return DISGetParamSize(pDis, &pDis->param1);
162	}
163
164
165	/**
166	* Flushes a chain of pages sharing the same access monitor.
167	*
168	* @returns VBox status code suitable for scheduling.
169	* @param pPool The pool.
170	* @param pPage A page in the chain.
171	*/
172	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
173	{
174	LogFlow(("pgmPoolMonitorChainFlush: Flush page %RGp type=%d\n", pPage->GCPhys, pPage->enmKind));
175
176	/*
177	* Find the list head.
178	*/
179	uint16_t idx = pPage->idx;
180	if (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
181	{
182	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
183	{
184	idx = pPage->iMonitoredPrev;
185	Assert(idx != pPage->idx);
186	pPage = &pPool->aPages[idx];
187	}
188	}
189
190	/*
191	* Iterate the list flushing each shadow page.
192	*/
193	int rc = VINF_SUCCESS;
194	for (;;)
195	{
196	idx = pPage->iMonitoredNext;
197	Assert(idx != pPage->idx);
198	if (pPage->idx >= PGMPOOL_IDX_FIRST)
199	{
200	int rc2 = pgmPoolFlushPage(pPool, pPage);
201	AssertRC(rc2);
202	}
203	/* next */
204	if (idx == NIL_PGMPOOL_IDX)
205	break;
206	pPage = &pPool->aPages[idx];
207	}
208	return rc;
209	}
210
211
212	/**
213	* Wrapper for getting the current context pointer to the entry being modified.
214	*
215	* @returns VBox status code suitable for scheduling.
216	* @param pVM VM Handle.
217	* @param pvDst Destination address
218	* @param pvSrc Source guest virtual address.
219	* @param GCPhysSrc The source guest physical address.
220	* @param cb Size of data to read
221	*/
222	DECLINLINE(int) pgmPoolPhysSimpleReadGCPhys(PVM pVM, void *pvDst, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvSrc, RTGCPHYS GCPhysSrc, size_t cb)
223	{
224	#if defined(IN_RING3)
225	memcpy(pvDst, (RTHCPTR)((uintptr_t)pvSrc & ~(RTHCUINTPTR)(cb - 1)), cb);
226	return VINF_SUCCESS;
227	#else
228	/* @todo in RC we could attempt to use the virtual address, although this can cause many faults (PAE Windows XP guest). */
229	return PGMPhysSimpleReadGCPhys(pVM, pvDst, GCPhysSrc & ~(RTGCPHYS)(cb - 1), cb);
230	#endif
231	}
232
233	/**
234	* Process shadow entries before they are changed by the guest.
235	*
236	* For PT entries we will clear them. For PD entries, we'll simply check
237	* for mapping conflicts and set the SyncCR3 FF if found.
238	*
239	* @param pVCpu VMCPU handle
240	* @param pPool The pool.
241	* @param pPage The head page.
242	* @param GCPhysFault The guest physical fault address.
243	* @param uAddress In R0 and GC this is the guest context fault address (flat).
244	* In R3 this is the host context 'fault' address.
245	* @param pCpu The disassembler state for figuring out the write size.
246	* This need not be specified if the caller knows we won't do cross entry accesses.
247	*/
248	void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, PDISCPUSTATE pCpu)
249	{
250	Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
251	const unsigned off = GCPhysFault & PAGE_OFFSET_MASK;
252	const unsigned cbWrite = (pCpu) ? pgmPoolDisasWriteSize(pCpu) : 0;
253	PVM pVM = pPool->CTX_SUFF(pVM);
254
255	LogFlow(("pgmPoolMonitorChainChanging: %RGv phys=%RGp kind=%s cbWrite=%d\n", (RTGCPTR)pvAddress, GCPhysFault, pgmPoolPoolKindToStr(pPage->enmKind), cbWrite));
256	for (;;)
257	{
258	union
259	{
260	void *pv;
261	PX86PT pPT;
262	PX86PTPAE pPTPae;
263	PX86PD pPD;
264	PX86PDPAE pPDPae;
265	PX86PDPT pPDPT;
266	PX86PML4 pPML4;
267	} uShw;
268
269	uShw.pv = NULL;
270	switch (pPage->enmKind)
271	{
272	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
273	{
274	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
275	const unsigned iShw = off / sizeof(X86PTE);
276	LogFlow(("PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT iShw=%x\n", iShw));
277	if (uShw.pPT->a[iShw].n.u1Present)
278	{
279	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
280	X86PTE GstPte;
281
282	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
283	AssertRC(rc);
284	Log4(("pgmPoolMonitorChainChanging 32_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
285	pgmPoolTracDerefGCPhysHint(pPool, pPage,
286	uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK,
287	GstPte.u & X86_PTE_PG_MASK);
288	# endif
289	ASMAtomicWriteSize(&uShw.pPT->a[iShw], 0);
290	}
291	break;
292	}
293
294	/* page/2 sized */
295	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
296	{
297	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
298	if (!((off ^ pPage->GCPhys) & (PAGE_SIZE / 2)))
299	{
300	const unsigned iShw = (off / sizeof(X86PTE)) & (X86_PG_PAE_ENTRIES - 1);
301	LogFlow(("PGMPOOLKIND_PAE_PT_FOR_32BIT_PT iShw=%x\n", iShw));
302	if (uShw.pPTPae->a[iShw].n.u1Present)
303	{
304	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
305	X86PTE GstPte;
306	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
307	AssertRC(rc);
308
309	Log4(("pgmPoolMonitorChainChanging pae_32: deref %016RX64 GCPhys %08RX32\n", uShw.pPT->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PG_MASK));
310	pgmPoolTracDerefGCPhysHint(pPool, pPage,
311	uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
312	GstPte.u & X86_PTE_PG_MASK);
313	# endif
314	ASMAtomicWriteSize(&uShw.pPTPae->a[iShw], 0);
315	}
316	}
317	break;
318	}
319
320	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
321	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
322	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
323	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
324	{
325	unsigned iGst = off / sizeof(X86PDE);
326	unsigned iShwPdpt = iGst / 256;
327	unsigned iShw = (iGst % 256) * 2;
328	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
329
330	LogFlow(("pgmPoolMonitorChainChanging PAE for 32 bits: iGst=%x iShw=%x idx = %d page idx=%d\n", iGst, iShw, iShwPdpt, pPage->enmKind - PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD));
331	if (iShwPdpt == pPage->enmKind - (unsigned)PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD)
332	{
333	for (unsigned i = 0; i < 2; i++)
334	{
335	# ifndef IN_RING0
336	if ((uShw.pPDPae->a[iShw + i].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
337	{
338	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
339	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
340	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw=%#x!\n", iShwPdpt, iShw+i));
341	break;
342	}
343	else
344	# endif /* !IN_RING0 */
345	if (uShw.pPDPae->a[iShw+i].n.u1Present)
346	{
347	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw+i, uShw.pPDPae->a[iShw+i].u));
348	pgmPoolFree(pVM,
349	uShw.pPDPae->a[iShw+i].u & X86_PDE_PAE_PG_MASK,
350	pPage->idx,
351	iShw + i);
352	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw+i], 0);
353	}
354
355	/* paranoia / a bit assumptive. */
356	if ( pCpu
357	&& (off & 3)
358	&& (off & 3) + cbWrite > 4)
359	{
360	const unsigned iShw2 = iShw + 2 + i;
361	if (iShw2 < RT_ELEMENTS(uShw.pPDPae->a))
362	{
363	# ifndef IN_RING0
364	if ((uShw.pPDPae->a[iShw2].u & (PGM_PDFLAGS_MAPPING \| X86_PDE_P)) == (PGM_PDFLAGS_MAPPING \| X86_PDE_P))
365	{
366	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
367	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
368	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShwPdpt=%#x iShw2=%#x!\n", iShwPdpt, iShw2));
369	break;
370	}
371	else
372	# endif /* !IN_RING0 */
373	if (uShw.pPDPae->a[iShw2].n.u1Present)
374	{
375	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
376	pgmPoolFree(pVM,
377	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
378	pPage->idx,
379	iShw2);
380	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
381	}
382	}
383	}
384	}
385	}
386	break;
387	}
388
389	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
390	{
391	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
392	const unsigned iShw = off / sizeof(X86PTEPAE);
393	if (uShw.pPTPae->a[iShw].n.u1Present)
394	{
395	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
396	X86PTEPAE GstPte;
397	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress, GCPhysFault, sizeof(GstPte));
398	AssertRC(rc);
399
400	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
401	pgmPoolTracDerefGCPhysHint(pPool, pPage,
402	uShw.pPTPae->a[iShw].u & X86_PTE_PAE_PG_MASK,
403	GstPte.u & X86_PTE_PAE_PG_MASK);
404	# endif
405	ASMAtomicWriteSize(&uShw.pPTPae->a[iShw].u, 0);
406	}
407
408	/* paranoia / a bit assumptive. */
409	if ( pCpu
410	&& (off & 7)
411	&& (off & 7) + cbWrite > sizeof(X86PTEPAE))
412	{
413	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTEPAE);
414	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPTPae->a));
415
416	if (uShw.pPTPae->a[iShw2].n.u1Present)
417	{
418	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
419	X86PTEPAE GstPte;
420	# ifdef IN_RING3
421	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, (RTHCPTR)((RTHCUINTPTR)pvAddress + sizeof(GstPte)), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
422	# else
423	int rc = pgmPoolPhysSimpleReadGCPhys(pVM, &GstPte, pvAddress + sizeof(GstPte), GCPhysFault + sizeof(GstPte), sizeof(GstPte));
424	# endif
425	AssertRC(rc);
426	Log4(("pgmPoolMonitorChainChanging pae: deref %016RX64 GCPhys %016RX64\n", uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK, GstPte.u & X86_PTE_PAE_PG_MASK));
427	pgmPoolTracDerefGCPhysHint(pPool, pPage,
428	uShw.pPTPae->a[iShw2].u & X86_PTE_PAE_PG_MASK,
429	GstPte.u & X86_PTE_PAE_PG_MASK);
430	# endif
431	ASMAtomicWriteSize(&uShw.pPTPae->a[iShw2].u ,0);
432	}
433	}
434	break;
435	}
436
437	case PGMPOOLKIND_32BIT_PD:
438	{
439	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
440	const unsigned iShw = off / sizeof(X86PTE); // ASSUMING 32-bit guest paging!
441
442	LogFlow(("pgmPoolMonitorChainChanging: PGMPOOLKIND_32BIT_PD %x\n", iShw));
443	# ifndef IN_RING0
444	if (uShw.pPD->a[iShw].u & PGM_PDFLAGS_MAPPING)
445	{
446	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
447	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
448	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
449	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
450	break;
451	}
452	# endif /* !IN_RING0 */
453	# ifndef IN_RING0
454	else
455	# endif /* !IN_RING0 */
456	{
457	if (uShw.pPD->a[iShw].n.u1Present)
458	{
459	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
460	pgmPoolFree(pVM,
461	uShw.pPD->a[iShw].u & X86_PDE_PAE_PG_MASK,
462	pPage->idx,
463	iShw);
464	ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
465	}
466	}
467	/* paranoia / a bit assumptive. */
468	if ( pCpu
469	&& (off & 3)
470	&& (off & 3) + cbWrite > sizeof(X86PTE))
471	{
472	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PTE);
473	if ( iShw2 != iShw
474	&& iShw2 < RT_ELEMENTS(uShw.pPD->a))
475	{
476	# ifndef IN_RING0
477	if (uShw.pPD->a[iShw2].u & PGM_PDFLAGS_MAPPING)
478	{
479	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
480	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
481	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
482	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
483	break;
484	}
485	# endif /* !IN_RING0 */
486	# ifndef IN_RING0
487	else
488	# endif /* !IN_RING0 */
489	{
490	if (uShw.pPD->a[iShw2].n.u1Present)
491	{
492	LogFlow(("pgmPoolMonitorChainChanging: 32 bit pd iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPD->a[iShw2].u));
493	pgmPoolFree(pVM,
494	uShw.pPD->a[iShw2].u & X86_PDE_PAE_PG_MASK,
495	pPage->idx,
496	iShw2);
497	ASMAtomicWriteSize(&uShw.pPD->a[iShw2].u, 0);
498	}
499	}
500	}
501	}
502	#if 0 /* useful when running PGMAssertCR3(), a bit too troublesome for general use (TLBs). */
503	if ( uShw.pPD->a[iShw].n.u1Present
504	&& !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
505	{
506	LogFlow(("pgmPoolMonitorChainChanging: iShw=%#x: %RX32 -> freeing it!\n", iShw, uShw.pPD->a[iShw].u));
507	# ifdef IN_RC /* TLB load - we're pushing things a bit... */
508	ASMProbeReadByte(pvAddress);
509	# endif
510	pgmPoolFree(pVM, uShw.pPD->a[iShw].u & X86_PDE_PG_MASK, pPage->idx, iShw);
511	ASMAtomicWriteSize(&uShw.pPD->a[iShw].u, 0);
512	}
513	#endif
514	break;
515	}
516
517	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
518	{
519	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
520	const unsigned iShw = off / sizeof(X86PDEPAE);
521	#ifndef IN_RING0
522	if (uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING)
523	{
524	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
525	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
526	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
527	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw=%#x!\n", iShw));
528	break;
529	}
530	#endif /* !IN_RING0 */
531	/*
532	* Causes trouble when the guest uses a PDE to refer to the whole page table level
533	* structure. (Invalidate here; faults later on when it tries to change the page
534	* table entries -> recheck; probably only applies to the RC case.)
535	*/
536	# ifndef IN_RING0
537	else
538	# endif /* !IN_RING0 */
539	{
540	if (uShw.pPDPae->a[iShw].n.u1Present)
541	{
542	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
543	pgmPoolFree(pVM,
544	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
545	pPage->idx,
546	iShw);
547	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
548	}
549	}
550	/* paranoia / a bit assumptive. */
551	if ( pCpu
552	&& (off & 7)
553	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
554	{
555	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
556	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
557
558	#ifndef IN_RING0
559	if ( iShw2 != iShw
560	&& uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING)
561	{
562	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
563	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
564	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
565	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
566	break;
567	}
568	#endif /* !IN_RING0 */
569	# ifndef IN_RING0
570	else
571	# endif /* !IN_RING0 */
572	if (uShw.pPDPae->a[iShw2].n.u1Present)
573	{
574	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
575	pgmPoolFree(pVM,
576	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
577	pPage->idx,
578	iShw2);
579	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
580	}
581	}
582	break;
583	}
584
585	case PGMPOOLKIND_PAE_PDPT:
586	{
587	/*
588	* Hopefully this doesn't happen very often:
589	* - touching unused parts of the page
590	* - messing with the bits of pd pointers without changing the physical address
591	*/
592	/* PDPT roots are not page aligned; 32 byte only! */
593	const unsigned offPdpt = GCPhysFault - pPage->GCPhys;
594
595	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
596	const unsigned iShw = offPdpt / sizeof(X86PDPE);
597	if (iShw < X86_PG_PAE_PDPE_ENTRIES) /* don't use RT_ELEMENTS(uShw.pPDPT->a), because that's for long mode only */
598	{
599	# ifndef IN_RING0
600	if (uShw.pPDPT->a[iShw].u & PGM_PLXFLAGS_MAPPING)
601	{
602	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
603	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
604	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
605	LogFlow(("pgmPoolMonitorChainChanging: Detected pdpt conflict at iShw=%#x!\n", iShw));
606	break;
607	}
608	# endif /* !IN_RING0 */
609	# ifndef IN_RING0
610	else
611	# endif /* !IN_RING0 */
612	if (uShw.pPDPT->a[iShw].n.u1Present)
613	{
614	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
615	pgmPoolFree(pVM,
616	uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK,
617	pPage->idx,
618	iShw);
619	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
620	}
621
622	/* paranoia / a bit assumptive. */
623	if ( pCpu
624	&& (offPdpt & 7)
625	&& (offPdpt & 7) + cbWrite > sizeof(X86PDPE))
626	{
627	const unsigned iShw2 = (offPdpt + cbWrite - 1) / sizeof(X86PDPE);
628	if ( iShw2 != iShw
629	&& iShw2 < X86_PG_PAE_PDPE_ENTRIES)
630	{
631	# ifndef IN_RING0
632	if (uShw.pPDPT->a[iShw2].u & PGM_PLXFLAGS_MAPPING)
633	{
634	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
635	STAM_COUNTER_INC(&(pVCpu->pgm.s.StatRZGuestCR3WriteConflict));
636	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
637	LogFlow(("pgmPoolMonitorChainChanging: Detected conflict at iShw2=%#x!\n", iShw2));
638	break;
639	}
640	# endif /* !IN_RING0 */
641	# ifndef IN_RING0
642	else
643	# endif /* !IN_RING0 */
644	if (uShw.pPDPT->a[iShw2].n.u1Present)
645	{
646	LogFlow(("pgmPoolMonitorChainChanging: pae pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
647	pgmPoolFree(pVM,
648	uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK,
649	pPage->idx,
650	iShw2);
651	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
652	}
653	}
654	}
655	}
656	break;
657	}
658
659	#ifndef IN_RC
660	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
661	{
662	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
663	const unsigned iShw = off / sizeof(X86PDEPAE);
664	Assert(!(uShw.pPDPae->a[iShw].u & PGM_PDFLAGS_MAPPING));
665	if (uShw.pPDPae->a[iShw].n.u1Present)
666	{
667	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPae->a[iShw].u));
668	pgmPoolFree(pVM,
669	uShw.pPDPae->a[iShw].u & X86_PDE_PAE_PG_MASK,
670	pPage->idx,
671	iShw);
672	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw].u, 0);
673	}
674	/* paranoia / a bit assumptive. */
675	if ( pCpu
676	&& (off & 7)
677	&& (off & 7) + cbWrite > sizeof(X86PDEPAE))
678	{
679	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDEPAE);
680	AssertBreak(iShw2 < RT_ELEMENTS(uShw.pPDPae->a));
681
682	Assert(!(uShw.pPDPae->a[iShw2].u & PGM_PDFLAGS_MAPPING));
683	if (uShw.pPDPae->a[iShw2].n.u1Present)
684	{
685	LogFlow(("pgmPoolMonitorChainChanging: pae pd iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPae->a[iShw2].u));
686	pgmPoolFree(pVM,
687	uShw.pPDPae->a[iShw2].u & X86_PDE_PAE_PG_MASK,
688	pPage->idx,
689	iShw2);
690	ASMAtomicWriteSize(&uShw.pPDPae->a[iShw2].u, 0);
691	}
692	}
693	break;
694	}
695
696	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
697	{
698	/*
699	* Hopefully this doesn't happen very often:
700	* - messing with the bits of pd pointers without changing the physical address
701	*/
702	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
703	{
704	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
705	const unsigned iShw = off / sizeof(X86PDPE);
706	if (uShw.pPDPT->a[iShw].n.u1Present)
707	{
708	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPDPT->a[iShw].u));
709	pgmPoolFree(pVM, uShw.pPDPT->a[iShw].u & X86_PDPE_PG_MASK, pPage->idx, iShw);
710	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw].u, 0);
711	}
712	/* paranoia / a bit assumptive. */
713	if ( pCpu
714	&& (off & 7)
715	&& (off & 7) + cbWrite > sizeof(X86PDPE))
716	{
717	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PDPE);
718	if (uShw.pPDPT->a[iShw2].n.u1Present)
719	{
720	LogFlow(("pgmPoolMonitorChainChanging: pdpt iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPDPT->a[iShw2].u));
721	pgmPoolFree(pVM, uShw.pPDPT->a[iShw2].u & X86_PDPE_PG_MASK, pPage->idx, iShw2);
722	ASMAtomicWriteSize(&uShw.pPDPT->a[iShw2].u, 0);
723	}
724	}
725	}
726	break;
727	}
728
729	case PGMPOOLKIND_64BIT_PML4:
730	{
731	/*
732	* Hopefully this doesn't happen very often:
733	* - messing with the bits of pd pointers without changing the physical address
734	*/
735	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
736	{
737	uShw.pv = PGMPOOL_PAGE_2_LOCKED_PTR(pVM, pPage);
738	const unsigned iShw = off / sizeof(X86PDPE);
739	if (uShw.pPML4->a[iShw].n.u1Present)
740	{
741	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPML4->a[iShw].u));
742	pgmPoolFree(pVM, uShw.pPML4->a[iShw].u & X86_PML4E_PG_MASK, pPage->idx, iShw);
743	ASMAtomicWriteSize(&uShw.pPML4->a[iShw].u, 0);
744	}
745	/* paranoia / a bit assumptive. */
746	if ( pCpu
747	&& (off & 7)
748	&& (off & 7) + cbWrite > sizeof(X86PDPE))
749	{
750	const unsigned iShw2 = (off + cbWrite - 1) / sizeof(X86PML4E);
751	if (uShw.pPML4->a[iShw2].n.u1Present)
752	{
753	LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPML4->a[iShw2].u));
754	pgmPoolFree(pVM, uShw.pPML4->a[iShw2].u & X86_PML4E_PG_MASK, pPage->idx, iShw2);
755	ASMAtomicWriteSize(&uShw.pPML4->a[iShw2].u, 0);
756	}
757	}
758	}
759	break;
760	}
761	#endif /* IN_RING0 */
762
763	default:
764	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
765	}
766	PGMPOOL_UNLOCK_PTR(pVM, uShw.pv);
767
768	/* next */
769	if (pPage->iMonitoredNext == NIL_PGMPOOL_IDX)
770	return;
771	pPage = &pPool->aPages[pPage->iMonitoredNext];
772	}
773	}
774
775	# ifndef IN_RING3
776	/**
777	* Checks if a access could be a fork operation in progress.
778	*
779	* Meaning, that the guest is setuping up the parent process for Copy-On-Write.
780	*
781	* @returns true if it's likly that we're forking, otherwise false.
782	* @param pPool The pool.
783	* @param pCpu The disassembled instruction.
784	* @param offFault The access offset.
785	*/
786	DECLINLINE(bool) pgmPoolMonitorIsForking(PPGMPOOL pPool, PDISCPUSTATE pCpu, unsigned offFault)
787	{
788	/*
789	* i386 linux is using btr to clear X86_PTE_RW.
790	* The functions involved are (2.6.16 source inspection):
791	* clear_bit
792	* ptep_set_wrprotect
793	* copy_one_pte
794	* copy_pte_range
795	* copy_pmd_range
796	* copy_pud_range
797	* copy_page_range
798	* dup_mmap
799	* dup_mm
800	* copy_mm
801	* copy_process
802	* do_fork
803	*/
804	if ( pCpu->pCurInstr->opcode == OP_BTR
805	&& !(offFault & 4)
806	/** @todo Validate that the bit index is X86_PTE_RW. */
807	)
808	{
809	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,Fork));
810	return true;
811	}
812	return false;
813	}
814
815
816	/**
817	* Determine whether the page is likely to have been reused.
818	*
819	* @returns true if we consider the page as being reused for a different purpose.
820	* @returns false if we consider it to still be a paging page.
821	* @param pVM VM Handle.
822	* @param pRegFrame Trap register frame.
823	* @param pCpu The disassembly info for the faulting instruction.
824	* @param pvFault The fault address.
825	*
826	* @remark The REP prefix check is left to the caller because of STOSD/W.
827	*/
828	DECLINLINE(bool) pgmPoolMonitorIsReused(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, RTGCPTR pvFault)
829	{
830	#ifndef IN_RC
831	/** @todo could make this general, faulting close to rsp should be safe reuse heuristic. */
832	if ( HWACCMHasPendingIrq(pVM)
833	&& (pRegFrame->rsp - pvFault) < 32)
834	{
835	/* Fault caused by stack writes while trying to inject an interrupt event. */
836	Log(("pgmPoolMonitorIsReused: reused %RGv for interrupt stack (rsp=%RGv).\n", pvFault, pRegFrame->rsp));
837	return true;
838	}
839	#else
840	NOREF(pVM); NOREF(pvFault);
841	#endif
842
843	switch (pCpu->pCurInstr->opcode)
844	{
845	/* call implies the actual push of the return address faulted */
846	case OP_CALL:
847	Log4(("pgmPoolMonitorIsReused: CALL\n"));
848	return true;
849	case OP_PUSH:
850	Log4(("pgmPoolMonitorIsReused: PUSH\n"));
851	return true;
852	case OP_PUSHF:
853	Log4(("pgmPoolMonitorIsReused: PUSHF\n"));
854	return true;
855	case OP_PUSHA:
856	Log4(("pgmPoolMonitorIsReused: PUSHA\n"));
857	return true;
858	case OP_FXSAVE:
859	Log4(("pgmPoolMonitorIsReused: FXSAVE\n"));
860	return true;
861	case OP_MOVNTI: /* solaris - block_zero_no_xmm */
862	Log4(("pgmPoolMonitorIsReused: MOVNTI\n"));
863	return true;
864	case OP_MOVNTDQ: /* solaris - hwblkclr & hwblkpagecopy */
865	Log4(("pgmPoolMonitorIsReused: MOVNTDQ\n"));
866	return true;
867	case OP_MOVSWD:
868	case OP_STOSWD:
869	if ( pCpu->prefix == (PREFIX_REP\|PREFIX_REX)
870	&& pRegFrame->rcx >= 0x40
871	)
872	{
873	Assert(pCpu->mode == CPUMODE_64BIT);
874
875	Log(("pgmPoolMonitorIsReused: OP_STOSQ\n"));
876	return true;
877	}
878	return false;
879	}
880	if ( (pCpu->param1.flags & USE_REG_GEN32)
881	&& (pCpu->param1.base.reg_gen == USE_REG_ESP))
882	{
883	Log4(("pgmPoolMonitorIsReused: ESP\n"));
884	return true;
885	}
886
887	return false;
888	}
889
890
891	/**
892	* Flushes the page being accessed.
893	*
894	* @returns VBox status code suitable for scheduling.
895	* @param pVM The VM handle.
896	* @param pVCpu The VMCPU handle.
897	* @param pPool The pool.
898	* @param pPage The pool page (head).
899	* @param pCpu The disassembly of the write instruction.
900	* @param pRegFrame The trap register frame.
901	* @param GCPhysFault The fault address as guest physical address.
902	* @param pvFault The fault address.
903	*/
904	static int pgmPoolAccessHandlerFlush(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
905	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
906	{
907	/*
908	* First, do the flushing.
909	*/
910	int rc = pgmPoolMonitorChainFlush(pPool, pPage);
911
912	/*
913	* Emulate the instruction (xp/w2k problem, requires pc/cr2/sp detection).
914	*/
915	uint32_t cbWritten;
916	int rc2 = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, pvFault, &cbWritten);
917	if (RT_SUCCESS(rc2))
918	pRegFrame->rip += pCpu->opsize;
919	else if (rc2 == VERR_EM_INTERPRETER)
920	{
921	#ifdef IN_RC
922	if (PATMIsPatchGCAddr(pVM, (RTRCPTR)pRegFrame->eip))
923	{
924	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for patch code %04x:%RGv, ignoring.\n",
925	pRegFrame->cs, (RTGCPTR)pRegFrame->eip));
926	rc = VINF_SUCCESS;
927	STAM_COUNTER_INC(&pPool->StatMonitorRZIntrFailPatch2);
928	}
929	else
930	#endif
931	{
932	rc = VINF_EM_RAW_EMULATE_INSTR;
933	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
934	}
935	}
936	else
937	rc = rc2;
938
939	/* See use in pgmPoolAccessHandlerSimple(). */
940	PGM_INVL_VCPU_TLBS(pVCpu);
941
942	LogFlow(("pgmPoolAccessHandlerPT: returns %Rrc (flushed)\n", rc));
943	return rc;
944
945	}
946
947
948	/**
949	* Handles the STOSD write accesses.
950	*
951	* @returns VBox status code suitable for scheduling.
952	* @param pVM The VM handle.
953	* @param pPool The pool.
954	* @param pPage The pool page (head).
955	* @param pCpu The disassembly of the write instruction.
956	* @param pRegFrame The trap register frame.
957	* @param GCPhysFault The fault address as guest physical address.
958	* @param pvFault The fault address.
959	*/
960	DECLINLINE(int) pgmPoolAccessHandlerSTOSD(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
961	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
962	{
963	Assert(pCpu->mode == CPUMODE_32BIT);
964
965	Log3(("pgmPoolAccessHandlerSTOSD\n"));
966
967	/*
968	* Increment the modification counter and insert it into the list
969	* of modified pages the first time.
970	*/
971	if (!pPage->cModifications++)
972	pgmPoolMonitorModifiedInsert(pPool, pPage);
973
974	/*
975	* Execute REP STOSD.
976	*
977	* This ASSUMES that we're not invoked by Trap0e on in a out-of-sync
978	* write situation, meaning that it's safe to write here.
979	*/
980	PVMCPU pVCpu = VMMGetCpu(pPool->CTX_SUFF(pVM));
981	RTGCUINTPTR pu32 = (RTGCUINTPTR)pvFault;
982	while (pRegFrame->ecx)
983	{
984	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
985	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
986	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
987	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
988	#else
989	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, (RTGCPTR)pu32, NULL);
990	#endif
991	#ifdef IN_RC
992	(uint32_t )pu32 = pRegFrame->eax;
993	#else
994	PGMPhysSimpleWriteGCPhys(pVM, GCPhysFault, &pRegFrame->eax, 4);
995	#endif
996	pu32 += 4;
997	GCPhysFault += 4;
998	pRegFrame->edi += 4;
999	pRegFrame->ecx--;
1000	}
1001	pRegFrame->rip += pCpu->opsize;
1002
1003	#ifdef IN_RC
1004	/* See use in pgmPoolAccessHandlerSimple(). */
1005	PGM_INVL_VCPU_TLBS(pVCpu);
1006	#endif
1007
1008	LogFlow(("pgmPoolAccessHandlerSTOSD: returns\n"));
1009	return VINF_SUCCESS;
1010	}
1011
1012
1013	/**
1014	* Handles the simple write accesses.
1015	*
1016	* @returns VBox status code suitable for scheduling.
1017	* @param pVM The VM handle.
1018	* @param pVCpu The VMCPU handle.
1019	* @param pPool The pool.
1020	* @param pPage The pool page (head).
1021	* @param pCpu The disassembly of the write instruction.
1022	* @param pRegFrame The trap register frame.
1023	* @param GCPhysFault The fault address as guest physical address.
1024	* @param pvFault The fault address.
1025	*/
1026	DECLINLINE(int) pgmPoolAccessHandlerSimple(PVM pVM, PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, PDISCPUSTATE pCpu,
1027	PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, RTGCPTR pvFault)
1028	{
1029	Log3(("pgmPoolAccessHandlerSimple\n"));
1030	/*
1031	* Increment the modification counter and insert it into the list
1032	* of modified pages the first time.
1033	*/
1034	if (!pPage->cModifications++)
1035	pgmPoolMonitorModifiedInsert(pPool, pPage);
1036
1037	/*
1038	* Clear all the pages. ASSUMES that pvFault is readable.
1039	*/
1040	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
1041	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
1042	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pCpu);
1043	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
1044	#else
1045	pgmPoolMonitorChainChanging(pVCpu, pPool, pPage, GCPhysFault, pvFault, pCpu);
1046	#endif
1047
1048	/*
1049	* Interpret the instruction.
1050	*/
1051	uint32_t cb;
1052	int rc = EMInterpretInstructionCPU(pVM, pVCpu, pCpu, pRegFrame, pvFault, &cb);
1053	if (RT_SUCCESS(rc))
1054	pRegFrame->rip += pCpu->opsize;
1055	else if (rc == VERR_EM_INTERPRETER)
1056	{
1057	LogFlow(("pgmPoolAccessHandlerPTWorker: Interpretation failed for %04x:%RGv - opcode=%d\n",
1058	pRegFrame->cs, (RTGCPTR)pRegFrame->rip, pCpu->pCurInstr->opcode));
1059	rc = VINF_EM_RAW_EMULATE_INSTR;
1060	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,EmulateInstr));
1061	}
1062
1063	#ifdef IN_RC
1064	/*
1065	* Quick hack, with logging enabled we're getting stale
1066	* code TLBs but no data TLB for EIP and crash in EMInterpretDisasOne.
1067	* Flushing here is BAD and expensive, I think EMInterpretDisasOne will
1068	* have to be fixed to support this. But that'll have to wait till next week.
1069	*
1070	* An alternative is to keep track of the changed PTEs together with the
1071	* GCPhys from the guest PT. This may proove expensive though.
1072	*
1073	* At the moment, it's VITAL that it's done AFTER the instruction interpreting
1074	* because we need the stale TLBs in some cases (XP boot). This MUST be fixed properly!
1075	*/
1076	PGM_INVL_VCPU_TLBS(pVCpu);
1077	#endif
1078
1079	LogFlow(("pgmPoolAccessHandlerSimple: returns %Rrc cb=%d\n", rc, cb));
1080	return rc;
1081	}
1082
1083	/**
1084	* \#PF Handler callback for PT write accesses.
1085	*
1086	* @returns VBox status code (appropriate for GC return).
1087	* @param pVM VM Handle.
1088	* @param uErrorCode CPU Error code.
1089	* @param pRegFrame Trap register frame.
1090	* NULL on DMA and other non CPU access.
1091	* @param pvFault The fault address (cr2).
1092	* @param GCPhysFault The GC physical address corresponding to pvFault.
1093	* @param pvUser User argument.
1094	*/
1095	DECLEXPORT(int) pgmPoolAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
1096	{
1097	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), a);
1098	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1099	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)pvUser;
1100	PVMCPU pVCpu = VMMGetCpu(pVM);
1101
1102	LogFlow(("pgmPoolAccessHandler: pvFault=%RGv pPage=%p:{.idx=%d} GCPhysFault=%RGp\n", pvFault, pPage, pPage->idx, GCPhysFault));
1103
1104	/*
1105	* We should ALWAYS have the list head as user parameter. This
1106	* is because we use that page to record the changes.
1107	*/
1108	Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1109
1110	/*
1111	* Disassemble the faulting instruction.
1112	*/
1113	DISCPUSTATE Cpu;
1114	int rc = EMInterpretDisasOne(pVM, pVCpu, pRegFrame, &Cpu, NULL);
1115	AssertRCReturn(rc, rc);
1116
1117	pgmLock(pVM);
1118	AssertMsg(PHYS_PAGE_ADDRESS(GCPhysFault) == PHYS_PAGE_ADDRESS(pPage->GCPhys), ("%RGp vs %RGp\n", PHYS_PAGE_ADDRESS(GCPhysFault), pPage->GCPhys));
1119
1120	/*
1121	* Check if it's worth dealing with.
1122	*/
1123	bool fReused = false;
1124	if ( ( pPage->cModifications < 48 /** @todo #define / /* @todo need to check that it's not mapping EIP. / /* @todo adjust this! */
1125	\|\| pgmPoolIsPageLocked(&pVM->pgm.s, pPage)
1126	)
1127	&& !(fReused = pgmPoolMonitorIsReused(pVM, pRegFrame, &Cpu, pvFault))
1128	&& !pgmPoolMonitorIsForking(pPool, &Cpu, GCPhysFault & PAGE_OFFSET_MASK))
1129	{
1130	/*
1131	* Simple instructions, no REP prefix.
1132	*/
1133	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1134	{
1135	rc = pgmPoolAccessHandlerSimple(pVM, pVCpu, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1136	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,Handled), a);
1137	pgmUnlock(pVM);
1138	return rc;
1139	}
1140
1141	/*
1142	* Windows is frequently doing small memset() operations (netio test 4k+).
1143	* We have to deal with these or we'll kill the cache and performance.
1144	*/
1145	if ( Cpu.pCurInstr->opcode == OP_STOSWD
1146	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0
1147	&& pRegFrame->ecx <= 0x20
1148	&& pRegFrame->ecx * 4 <= PAGE_SIZE - ((uintptr_t)pvFault & PAGE_OFFSET_MASK)
1149	&& !((uintptr_t)pvFault & 3)
1150	&& (pRegFrame->eax == 0 \|\| pRegFrame->eax == 0x80) /* the two values observed. */
1151	&& Cpu.mode == CPUMODE_32BIT
1152	&& Cpu.opmode == CPUMODE_32BIT
1153	&& Cpu.addrmode == CPUMODE_32BIT
1154	&& Cpu.prefix == PREFIX_REP
1155	&& !pRegFrame->eflags.Bits.u1DF
1156	)
1157	{
1158	rc = pgmPoolAccessHandlerSTOSD(pVM, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1159	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,RepStosd), a);
1160	pgmUnlock(pVM);
1161	return rc;
1162	}
1163
1164	/* REP prefix, don't bother. */
1165	STAM_COUNTER_INC(&pPool->CTX_MID_Z(StatMonitor,RepPrefix));
1166	Log4(("pgmPoolAccessHandler: eax=%#x ecx=%#x edi=%#x esi=%#x rip=%RGv opcode=%d prefix=%#x\n",
1167	pRegFrame->eax, pRegFrame->ecx, pRegFrame->edi, pRegFrame->esi, (RTGCPTR)pRegFrame->rip, Cpu.pCurInstr->opcode, Cpu.prefix));
1168	}
1169
1170	/*
1171	* Not worth it, so flush it.
1172	*
1173	* If we considered it to be reused, don't go back to ring-3
1174	* to emulate failed instructions since we usually cannot
1175	* interpret then. This may be a bit risky, in which case
1176	* the reuse detection must be fixed.
1177	*/
1178	rc = pgmPoolAccessHandlerFlush(pVM, pVCpu, pPool, pPage, &Cpu, pRegFrame, GCPhysFault, pvFault);
1179	if (rc == VINF_EM_RAW_EMULATE_INSTR && fReused)
1180	rc = VINF_SUCCESS;
1181	STAM_PROFILE_STOP_EX(&pVM->pgm.s.CTX_SUFF(pPool)->CTX_SUFF_Z(StatMonitor), &pPool->CTX_MID_Z(StatMonitor,FlushPage), a);
1182	pgmUnlock(pVM);
1183	return rc;
1184	}
1185
1186	# endif /* !IN_RING3 */
1187	#endif /* PGMPOOL_WITH_MONITORING */
1188
1189	#ifdef PGMPOOL_WITH_CACHE
1190
1191	/**
1192	* Inserts a page into the GCPhys hash table.
1193	*
1194	* @param pPool The pool.
1195	* @param pPage The page.
1196	*/
1197	DECLINLINE(void) pgmPoolHashInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1198	{
1199	Log3(("pgmPoolHashInsert: %RGp\n", pPage->GCPhys));
1200	Assert(pPage->GCPhys != NIL_RTGCPHYS); Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1201	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1202	pPage->iNext = pPool->aiHash[iHash];
1203	pPool->aiHash[iHash] = pPage->idx;
1204	}
1205
1206
1207	/**
1208	* Removes a page from the GCPhys hash table.
1209	*
1210	* @param pPool The pool.
1211	* @param pPage The page.
1212	*/
1213	DECLINLINE(void) pgmPoolHashRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1214	{
1215	Log3(("pgmPoolHashRemove: %RGp\n", pPage->GCPhys));
1216	uint16_t iHash = PGMPOOL_HASH(pPage->GCPhys);
1217	if (pPool->aiHash[iHash] == pPage->idx)
1218	pPool->aiHash[iHash] = pPage->iNext;
1219	else
1220	{
1221	uint16_t iPrev = pPool->aiHash[iHash];
1222	for (;;)
1223	{
1224	const int16_t i = pPool->aPages[iPrev].iNext;
1225	if (i == pPage->idx)
1226	{
1227	pPool->aPages[iPrev].iNext = pPage->iNext;
1228	break;
1229	}
1230	if (i == NIL_PGMPOOL_IDX)
1231	{
1232	AssertReleaseMsgFailed(("GCPhys=%RGp idx=%#x\n", pPage->GCPhys, pPage->idx));
1233	break;
1234	}
1235	iPrev = i;
1236	}
1237	}
1238	pPage->iNext = NIL_PGMPOOL_IDX;
1239	}
1240
1241
1242	/**
1243	* Frees up one cache page.
1244	*
1245	* @returns VBox status code.
1246	* @retval VINF_SUCCESS on success.
1247	* @param pPool The pool.
1248	* @param iUser The user index.
1249	*/
1250	static int pgmPoolCacheFreeOne(PPGMPOOL pPool, uint16_t iUser)
1251	{
1252	#ifndef IN_RC
1253	const PVM pVM = pPool->CTX_SUFF(pVM);
1254	#endif
1255	Assert(pPool->iAgeHead != pPool->iAgeTail); /* We shouldn't be here if there < 2 cached entries! */
1256	STAM_COUNTER_INC(&pPool->StatCacheFreeUpOne);
1257
1258	/*
1259	* Select one page from the tail of the age list.
1260	*/
1261	PPGMPOOLPAGE pPage;
1262	for (unsigned iLoop = 0; ; iLoop++)
1263	{
1264	uint16_t iToFree = pPool->iAgeTail;
1265	if (iToFree == iUser)
1266	iToFree = pPool->aPages[iToFree].iAgePrev;
1267	/* This is the alternative to the SyncCR3 pgmPoolCacheUsed calls.
1268	if (pPool->aPages[iToFree].iUserHead != NIL_PGMPOOL_USER_INDEX)
1269	{
1270	uint16_t i = pPool->aPages[iToFree].iAgePrev;
1271	for (unsigned j = 0; j < 10 && i != NIL_PGMPOOL_USER_INDEX; j++, i = pPool->aPages[i].iAgePrev)
1272	{
1273	if (pPool->aPages[iToFree].iUserHead == NIL_PGMPOOL_USER_INDEX)
1274	continue;
1275	iToFree = i;
1276	break;
1277	}
1278	}
1279	*/
1280	Assert(iToFree != iUser);
1281	AssertRelease(iToFree != NIL_PGMPOOL_IDX);
1282	pPage = &pPool->aPages[iToFree];
1283
1284	/*
1285	* Reject any attempts at flushing the currently active shadow CR3 mapping.
1286	* Call pgmPoolCacheUsed to move the page to the head of the age list.
1287	*/
1288	if (!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage))
1289	break;
1290	LogFlow(("pgmPoolCacheFreeOne: refuse CR3 mapping\n"));
1291	pgmPoolCacheUsed(pPool, pPage);
1292	AssertLogRelReturn(iLoop < 8192, VERR_INTERNAL_ERROR);
1293	}
1294
1295	/*
1296	* Found a usable page, flush it and return.
1297	*/
1298	int rc = pgmPoolFlushPage(pPool, pPage);
1299	if (rc == VINF_SUCCESS)
1300	PGM_INVL_VCPU_TLBS(VMMGetCpu(pVM)); /* see PT handler. */
1301	return rc;
1302	}
1303
1304
1305	/**
1306	* Checks if a kind mismatch is really a page being reused
1307	* or if it's just normal remappings.
1308	*
1309	* @returns true if reused and the cached page (enmKind1) should be flushed
1310	* @returns false if not reused.
1311	* @param enmKind1 The kind of the cached page.
1312	* @param enmKind2 The kind of the requested page.
1313	*/
1314	static bool pgmPoolCacheReusedByKind(PGMPOOLKIND enmKind1, PGMPOOLKIND enmKind2)
1315	{
1316	switch (enmKind1)
1317	{
1318	/*
1319	* Never reuse them. There is no remapping in non-paging mode.
1320	*/
1321	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1322	case PGMPOOLKIND_32BIT_PD_PHYS:
1323	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1324	case PGMPOOLKIND_PAE_PD_PHYS:
1325	case PGMPOOLKIND_PAE_PDPT_PHYS:
1326	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1327	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1328	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1329	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1330	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1331	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT: /* never reuse them for other types */
1332	return false;
1333
1334	/*
1335	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1336	*/
1337	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1338	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1339	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1340	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1341	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1342	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1343	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1344	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1345	case PGMPOOLKIND_32BIT_PD:
1346	case PGMPOOLKIND_PAE_PDPT:
1347	switch (enmKind2)
1348	{
1349	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1350	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1351	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1352	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1353	case PGMPOOLKIND_64BIT_PML4:
1354	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1355	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1356	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1357	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1358	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1359	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1360	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1361	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1362	return true;
1363	default:
1364	return false;
1365	}
1366
1367	/*
1368	* It's perfectly fine to reuse these, except for PAE and non-paging stuff.
1369	*/
1370	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1371	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1372	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1373	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1374	case PGMPOOLKIND_64BIT_PML4:
1375	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1376	switch (enmKind2)
1377	{
1378	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1379	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1380	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1381	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1382	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1383	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1384	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1385	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1386	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1387	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1388	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1389	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1390	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1391	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1392	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1393	return true;
1394	default:
1395	return false;
1396	}
1397
1398	/*
1399	* These cannot be flushed, and it's common to reuse the PDs as PTs.
1400	*/
1401	case PGMPOOLKIND_ROOT_NESTED:
1402	return false;
1403
1404	default:
1405	AssertFatalMsgFailed(("enmKind1=%d\n", enmKind1));
1406	}
1407	}
1408
1409
1410	/**
1411	* Attempts to satisfy a pgmPoolAlloc request from the cache.
1412	*
1413	* @returns VBox status code.
1414	* @retval VINF_PGM_CACHED_PAGE on success.
1415	* @retval VERR_FILE_NOT_FOUND if not found.
1416	* @param pPool The pool.
1417	* @param GCPhys The GC physical address of the page we're gonna shadow.
1418	* @param enmKind The kind of mapping.
1419	* @param iUser The shadow page pool index of the user table.
1420	* @param iUserTable The index into the user table (shadowed).
1421	* @param ppPage Where to store the pointer to the page.
1422	*/
1423	static int pgmPoolCacheAlloc(PPGMPOOL pPool, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
1424	{
1425	#ifndef IN_RC
1426	const PVM pVM = pPool->CTX_SUFF(pVM);
1427	#endif
1428	/*
1429	* Look up the GCPhys in the hash.
1430	*/
1431	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
1432	Log3(("pgmPoolCacheAlloc: %RGp kind %s iUser=%x iUserTable=%x SLOT=%d\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable, i));
1433	if (i != NIL_PGMPOOL_IDX)
1434	{
1435	do
1436	{
1437	PPGMPOOLPAGE pPage = &pPool->aPages[i];
1438	Log4(("pgmPoolCacheAlloc: slot %d found page %RGp\n", i, pPage->GCPhys));
1439	if (pPage->GCPhys == GCPhys)
1440	{
1441	if ((PGMPOOLKIND)pPage->enmKind == enmKind)
1442	{
1443	/* Put it at the start of the use list to make sure pgmPoolTrackAddUser
1444	* doesn't flush it in case there are no more free use records.
1445	*/
1446	pgmPoolCacheUsed(pPool, pPage);
1447
1448	int rc = pgmPoolTrackAddUser(pPool, pPage, iUser, iUserTable);
1449	if (RT_SUCCESS(rc))
1450	{
1451	Assert((PGMPOOLKIND)pPage->enmKind == enmKind);
1452	*ppPage = pPage;
1453	STAM_COUNTER_INC(&pPool->StatCacheHits);
1454	return VINF_PGM_CACHED_PAGE;
1455	}
1456	return rc;
1457	}
1458
1459	/*
1460	* The kind is different. In some cases we should now flush the page
1461	* as it has been reused, but in most cases this is normal remapping
1462	* of PDs as PT or big pages using the GCPhys field in a slightly
1463	* different way than the other kinds.
1464	*/
1465	if (pgmPoolCacheReusedByKind((PGMPOOLKIND)pPage->enmKind, enmKind))
1466	{
1467	STAM_COUNTER_INC(&pPool->StatCacheKindMismatches);
1468	pgmPoolFlushPage(pPool, pPage);
1469	PGM_INVL_VCPU_TLBS(VMMGetCpu(pVM)); /* see PT handler. */
1470	break;
1471	}
1472	}
1473
1474	/* next */
1475	i = pPage->iNext;
1476	} while (i != NIL_PGMPOOL_IDX);
1477	}
1478
1479	Log3(("pgmPoolCacheAlloc: Missed GCPhys=%RGp enmKind=%s\n", GCPhys, pgmPoolPoolKindToStr(enmKind)));
1480	STAM_COUNTER_INC(&pPool->StatCacheMisses);
1481	return VERR_FILE_NOT_FOUND;
1482	}
1483
1484
1485	/**
1486	* Inserts a page into the cache.
1487	*
1488	* @param pPool The pool.
1489	* @param pPage The cached page.
1490	* @param fCanBeCached Set if the page is fit for caching from the caller's point of view.
1491	*/
1492	static void pgmPoolCacheInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fCanBeCached)
1493	{
1494	/*
1495	* Insert into the GCPhys hash if the page is fit for that.
1496	*/
1497	Assert(!pPage->fCached);
1498	if (fCanBeCached)
1499	{
1500	pPage->fCached = true;
1501	pgmPoolHashInsert(pPool, pPage);
1502	Log3(("pgmPoolCacheInsert: Caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
1503	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
1504	STAM_COUNTER_INC(&pPool->StatCacheCacheable);
1505	}
1506	else
1507	{
1508	Log3(("pgmPoolCacheInsert: Not caching %p:{.Core=%RHp, .idx=%d, .enmKind=%s, GCPhys=%RGp}\n",
1509	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
1510	STAM_COUNTER_INC(&pPool->StatCacheUncacheable);
1511	}
1512
1513	/*
1514	* Insert at the head of the age list.
1515	*/
1516	pPage->iAgePrev = NIL_PGMPOOL_IDX;
1517	pPage->iAgeNext = pPool->iAgeHead;
1518	if (pPool->iAgeHead != NIL_PGMPOOL_IDX)
1519	pPool->aPages[pPool->iAgeHead].iAgePrev = pPage->idx;
1520	else
1521	pPool->iAgeTail = pPage->idx;
1522	pPool->iAgeHead = pPage->idx;
1523	}
1524
1525
1526	/**
1527	* Flushes a cached page.
1528	*
1529	* @param pPool The pool.
1530	* @param pPage The cached page.
1531	*/
1532	static void pgmPoolCacheFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1533	{
1534	Log3(("pgmPoolCacheFlushPage: %RGp\n", pPage->GCPhys));
1535
1536	/*
1537	* Remove the page from the hash.
1538	*/
1539	if (pPage->fCached)
1540	{
1541	pPage->fCached = false;
1542	pgmPoolHashRemove(pPool, pPage);
1543	}
1544	else
1545	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
1546
1547	/*
1548	* Remove it from the age list.
1549	*/
1550	if (pPage->iAgeNext != NIL_PGMPOOL_IDX)
1551	pPool->aPages[pPage->iAgeNext].iAgePrev = pPage->iAgePrev;
1552	else
1553	pPool->iAgeTail = pPage->iAgePrev;
1554	if (pPage->iAgePrev != NIL_PGMPOOL_IDX)
1555	pPool->aPages[pPage->iAgePrev].iAgeNext = pPage->iAgeNext;
1556	else
1557	pPool->iAgeHead = pPage->iAgeNext;
1558	pPage->iAgeNext = NIL_PGMPOOL_IDX;
1559	pPage->iAgePrev = NIL_PGMPOOL_IDX;
1560	}
1561
1562	#endif /* PGMPOOL_WITH_CACHE */
1563	#ifdef PGMPOOL_WITH_MONITORING
1564
1565	/**
1566	* Looks for pages sharing the monitor.
1567	*
1568	* @returns Pointer to the head page.
1569	* @returns NULL if not found.
1570	* @param pPool The Pool
1571	* @param pNewPage The page which is going to be monitored.
1572	*/
1573	static PPGMPOOLPAGE pgmPoolMonitorGetPageByGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pNewPage)
1574	{
1575	#ifdef PGMPOOL_WITH_CACHE
1576	/*
1577	* Look up the GCPhys in the hash.
1578	*/
1579	RTGCPHYS GCPhys = pNewPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1580	unsigned i = pPool->aiHash[PGMPOOL_HASH(GCPhys)];
1581	if (i == NIL_PGMPOOL_IDX)
1582	return NULL;
1583	do
1584	{
1585	PPGMPOOLPAGE pPage = &pPool->aPages[i];
1586	if ( pPage->GCPhys - GCPhys < PAGE_SIZE
1587	&& pPage != pNewPage)
1588	{
1589	switch (pPage->enmKind)
1590	{
1591	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1592	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1593	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1594	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1595	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1596	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1597	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1598	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1599	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1600	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1601	case PGMPOOLKIND_64BIT_PML4:
1602	case PGMPOOLKIND_32BIT_PD:
1603	case PGMPOOLKIND_PAE_PDPT:
1604	{
1605	/* find the head */
1606	while (pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1607	{
1608	Assert(pPage->iMonitoredPrev != pPage->idx);
1609	pPage = &pPool->aPages[pPage->iMonitoredPrev];
1610	}
1611	return pPage;
1612	}
1613
1614	/* ignore, no monitoring. */
1615	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1616	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1617	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1618	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1619	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1620	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1621	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1622	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1623	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1624	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1625	case PGMPOOLKIND_ROOT_NESTED:
1626	case PGMPOOLKIND_PAE_PD_PHYS:
1627	case PGMPOOLKIND_PAE_PDPT_PHYS:
1628	case PGMPOOLKIND_32BIT_PD_PHYS:
1629	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
1630	break;
1631	default:
1632	AssertFatalMsgFailed(("enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
1633	}
1634	}
1635
1636	/* next */
1637	i = pPage->iNext;
1638	} while (i != NIL_PGMPOOL_IDX);
1639	#endif
1640	return NULL;
1641	}
1642
1643
1644	/**
1645	* Enabled write monitoring of a guest page.
1646	*
1647	* @returns VBox status code.
1648	* @retval VINF_SUCCESS on success.
1649	* @param pPool The pool.
1650	* @param pPage The cached page.
1651	*/
1652	static int pgmPoolMonitorInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1653	{
1654	LogFlow(("pgmPoolMonitorInsert %RGp\n", pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1)));
1655
1656	/*
1657	* Filter out the relevant kinds.
1658	*/
1659	switch (pPage->enmKind)
1660	{
1661	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1662	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1663	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1664	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1665	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1666	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1667	case PGMPOOLKIND_64BIT_PML4:
1668	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1669	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1670	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1671	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1672	case PGMPOOLKIND_32BIT_PD:
1673	case PGMPOOLKIND_PAE_PDPT:
1674	break;
1675
1676	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1677	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1678	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1679	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1680	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1681	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1682	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1683	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1684	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1685	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1686	case PGMPOOLKIND_ROOT_NESTED:
1687	/* Nothing to monitor here. */
1688	return VINF_SUCCESS;
1689
1690	case PGMPOOLKIND_32BIT_PD_PHYS:
1691	case PGMPOOLKIND_PAE_PDPT_PHYS:
1692	case PGMPOOLKIND_PAE_PD_PHYS:
1693	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
1694	/* Nothing to monitor here. */
1695	return VINF_SUCCESS;
1696	#ifdef PGMPOOL_WITH_MIXED_PT_CR3
1697	break;
1698	#else
1699	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1700	#endif
1701	default:
1702	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
1703	}
1704
1705	/*
1706	* Install handler.
1707	*/
1708	int rc;
1709	PPGMPOOLPAGE pPageHead = pgmPoolMonitorGetPageByGCPhys(pPool, pPage);
1710	if (pPageHead)
1711	{
1712	Assert(pPageHead != pPage); Assert(pPageHead->iMonitoredNext != pPage->idx);
1713	Assert(pPageHead->iMonitoredPrev != pPage->idx);
1714	pPage->iMonitoredPrev = pPageHead->idx;
1715	pPage->iMonitoredNext = pPageHead->iMonitoredNext;
1716	if (pPageHead->iMonitoredNext != NIL_PGMPOOL_IDX)
1717	pPool->aPages[pPageHead->iMonitoredNext].iMonitoredPrev = pPage->idx;
1718	pPageHead->iMonitoredNext = pPage->idx;
1719	rc = VINF_SUCCESS;
1720	}
1721	else
1722	{
1723	Assert(pPage->iMonitoredNext == NIL_PGMPOOL_IDX); Assert(pPage->iMonitoredPrev == NIL_PGMPOOL_IDX);
1724	PVM pVM = pPool->CTX_SUFF(pVM);
1725	const RTGCPHYS GCPhysPage = pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1);
1726	rc = PGMHandlerPhysicalRegisterEx(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
1727	GCPhysPage, GCPhysPage + (PAGE_SIZE - 1),
1728	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
1729	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
1730	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
1731	pPool->pszAccessHandler);
1732	/** @todo we should probably deal with out-of-memory conditions here, but for now increasing
1733	* the heap size should suffice. */
1734	AssertFatalMsgRC(rc, ("PGMHandlerPhysicalRegisterEx %RGp failed with %Rrc\n", GCPhysPage, rc));
1735	Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_ISSET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3));
1736	}
1737	pPage->fMonitored = true;
1738	return rc;
1739	}
1740
1741
1742	/**
1743	* Disables write monitoring of a guest page.
1744	*
1745	* @returns VBox status code.
1746	* @retval VINF_SUCCESS on success.
1747	* @param pPool The pool.
1748	* @param pPage The cached page.
1749	*/
1750	static int pgmPoolMonitorFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1751	{
1752	/*
1753	* Filter out the relevant kinds.
1754	*/
1755	switch (pPage->enmKind)
1756	{
1757	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1758	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1759	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
1760	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1761	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
1762	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
1763	case PGMPOOLKIND_64BIT_PML4:
1764	case PGMPOOLKIND_32BIT_PD:
1765	case PGMPOOLKIND_PAE_PDPT:
1766	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
1767	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
1768	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
1769	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
1770	break;
1771
1772	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1773	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1774	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1775	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1776	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1777	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
1778	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
1779	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
1780	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
1781	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
1782	case PGMPOOLKIND_ROOT_NESTED:
1783	case PGMPOOLKIND_PAE_PD_PHYS:
1784	case PGMPOOLKIND_PAE_PDPT_PHYS:
1785	case PGMPOOLKIND_32BIT_PD_PHYS:
1786	/* Nothing to monitor here. */
1787	return VINF_SUCCESS;
1788
1789	#ifdef PGMPOOL_WITH_MIXED_PT_CR3
1790	break;
1791	#endif
1792	default:
1793	AssertFatalMsgFailed(("This can't happen! enmKind=%d\n", pPage->enmKind));
1794	}
1795
1796	/*
1797	* Remove the page from the monitored list or uninstall it if last.
1798	*/
1799	const PVM pVM = pPool->CTX_SUFF(pVM);
1800	int rc;
1801	if ( pPage->iMonitoredNext != NIL_PGMPOOL_IDX
1802	\|\| pPage->iMonitoredPrev != NIL_PGMPOOL_IDX)
1803	{
1804	if (pPage->iMonitoredPrev == NIL_PGMPOOL_IDX)
1805	{
1806	PPGMPOOLPAGE pNewHead = &pPool->aPages[pPage->iMonitoredNext];
1807	pNewHead->iMonitoredPrev = NIL_PGMPOOL_IDX;
1808	rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
1809	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pNewHead),
1810	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pNewHead),
1811	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pNewHead),
1812	pPool->pszAccessHandler);
1813	AssertFatalRCSuccess(rc);
1814	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
1815	}
1816	else
1817	{
1818	pPool->aPages[pPage->iMonitoredPrev].iMonitoredNext = pPage->iMonitoredNext;
1819	if (pPage->iMonitoredNext != NIL_PGMPOOL_IDX)
1820	{
1821	pPool->aPages[pPage->iMonitoredNext].iMonitoredPrev = pPage->iMonitoredPrev;
1822	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
1823	}
1824	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
1825	rc = VINF_SUCCESS;
1826	}
1827	}
1828	else
1829	{
1830	rc = PGMHandlerPhysicalDeregister(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1));
1831	AssertFatalRC(rc);
1832	AssertMsg(!(pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL) \|\| VMCPU_FF_ISSET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3),
1833	("%#x %#x\n", pVM->pgm.s.fGlobalSyncFlags, pVM->fGlobalForcedActions));
1834	}
1835	pPage->fMonitored = false;
1836
1837	/*
1838	* Remove it from the list of modified pages (if in it).
1839	*/
1840	pgmPoolMonitorModifiedRemove(pPool, pPage);
1841
1842	return rc;
1843	}
1844
1845
1846	/**
1847	* Inserts the page into the list of modified pages.
1848	*
1849	* @param pPool The pool.
1850	* @param pPage The page.
1851	*/
1852	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1853	{
1854	Log3(("pgmPoolMonitorModifiedInsert: idx=%d\n", pPage->idx));
1855	AssertMsg( pPage->iModifiedNext == NIL_PGMPOOL_IDX
1856	&& pPage->iModifiedPrev == NIL_PGMPOOL_IDX
1857	&& pPool->iModifiedHead != pPage->idx,
1858	("Next=%d Prev=%d idx=%d cModifications=%d Head=%d cModifiedPages=%d\n",
1859	pPage->iModifiedNext, pPage->iModifiedPrev, pPage->idx, pPage->cModifications,
1860	pPool->iModifiedHead, pPool->cModifiedPages));
1861
1862	pPage->iModifiedNext = pPool->iModifiedHead;
1863	if (pPool->iModifiedHead != NIL_PGMPOOL_IDX)
1864	pPool->aPages[pPool->iModifiedHead].iModifiedPrev = pPage->idx;
1865	pPool->iModifiedHead = pPage->idx;
1866	pPool->cModifiedPages++;
1867	#ifdef VBOX_WITH_STATISTICS
1868	if (pPool->cModifiedPages > pPool->cModifiedPagesHigh)
1869	pPool->cModifiedPagesHigh = pPool->cModifiedPages;
1870	#endif
1871	}
1872
1873
1874	/**
1875	* Removes the page from the list of modified pages and resets the
1876	* moficiation counter.
1877	*
1878	* @param pPool The pool.
1879	* @param pPage The page which is believed to be in the list of modified pages.
1880	*/
1881	static void pgmPoolMonitorModifiedRemove(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
1882	{
1883	Log3(("pgmPoolMonitorModifiedRemove: idx=%d cModifications=%d\n", pPage->idx, pPage->cModifications));
1884	if (pPool->iModifiedHead == pPage->idx)
1885	{
1886	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
1887	pPool->iModifiedHead = pPage->iModifiedNext;
1888	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
1889	{
1890	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = NIL_PGMPOOL_IDX;
1891	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1892	}
1893	pPool->cModifiedPages--;
1894	}
1895	else if (pPage->iModifiedPrev != NIL_PGMPOOL_IDX)
1896	{
1897	pPool->aPages[pPage->iModifiedPrev].iModifiedNext = pPage->iModifiedNext;
1898	if (pPage->iModifiedNext != NIL_PGMPOOL_IDX)
1899	{
1900	pPool->aPages[pPage->iModifiedNext].iModifiedPrev = pPage->iModifiedPrev;
1901	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1902	}
1903	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
1904	pPool->cModifiedPages--;
1905	}
1906	else
1907	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX);
1908	pPage->cModifications = 0;
1909	}
1910
1911
1912	/**
1913	* Zaps the list of modified pages, resetting their modification counters in the process.
1914	*
1915	* @param pVM The VM handle.
1916	*/
1917	void pgmPoolMonitorModifiedClearAll(PVM pVM)
1918	{
1919	pgmLock(pVM);
1920	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1921	LogFlow(("pgmPoolMonitorModifiedClearAll: cModifiedPages=%d\n", pPool->cModifiedPages));
1922
1923	unsigned cPages = 0; NOREF(cPages);
1924	uint16_t idx = pPool->iModifiedHead;
1925	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
1926	while (idx != NIL_PGMPOOL_IDX)
1927	{
1928	PPGMPOOLPAGE pPage = &pPool->aPages[idx];
1929	idx = pPage->iModifiedNext;
1930	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
1931	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
1932	pPage->cModifications = 0;
1933	Assert(++cPages);
1934	}
1935	AssertMsg(cPages == pPool->cModifiedPages, ("%d != %d\n", cPages, pPool->cModifiedPages));
1936	pPool->cModifiedPages = 0;
1937	pgmUnlock(pVM);
1938	}
1939
1940
1941	#ifdef IN_RING3
1942	/**
1943	* Callback to clear all shadow pages and clear all modification counters.
1944	*
1945	* @returns VBox status code.
1946	* @param pVM The VM handle.
1947	* @param pvUser Unused parameter
1948	* @remark Should only be used when monitoring is available, thus placed in
1949	* the PGMPOOL_WITH_MONITORING #ifdef.
1950	*/
1951	DECLCALLBACK(int) pgmPoolClearAll(PVM pVM, void *pvUser)
1952	{
1953	NOREF(pvUser);
1954	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1955	STAM_PROFILE_START(&pPool->StatClearAll, c);
1956	LogFlow(("pgmPoolClearAll: cUsedPages=%d\n", pPool->cUsedPages));
1957
1958	pgmLock(pVM);
1959
1960	/*
1961	* Iterate all the pages until we've encountered all that in use.
1962	* This is simple but not quite optimal solution.
1963	*/
1964	unsigned cModifiedPages = 0; NOREF(cModifiedPages);
1965	unsigned cLeft = pPool->cUsedPages;
1966	unsigned iPage = pPool->cCurPages;
1967	while (--iPage >= PGMPOOL_IDX_FIRST)
1968	{
1969	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
1970	if (pPage->GCPhys != NIL_RTGCPHYS)
1971	{
1972	switch (pPage->enmKind)
1973	{
1974	/*
1975	* We only care about shadow page tables.
1976	*/
1977	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
1978	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
1979	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
1980	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
1981	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
1982	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
1983	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
1984	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
1985	{
1986	#ifdef PGMPOOL_WITH_USER_TRACKING
1987	if (pPage->cPresent)
1988	#endif
1989	{
1990	void *pvShw = PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pPage);
1991	STAM_PROFILE_START(&pPool->StatZeroPage, z);
1992	ASMMemZeroPage(pvShw);
1993	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
1994	#ifdef PGMPOOL_WITH_USER_TRACKING
1995	pPage->cPresent = 0;
1996	pPage->iFirstPresent = ~0;
1997	#endif
1998	}
1999	}
2000	/* fall thru */
2001
2002	default:
2003	Assert(!pPage->cModifications \|\| ++cModifiedPages);
2004	Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2005	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2006	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2007	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2008	pPage->cModifications = 0;
2009	break;
2010
2011	}
2012	if (!--cLeft)
2013	break;
2014	}
2015	}
2016
2017	/* swipe the special pages too. */
2018	for (iPage = PGMPOOL_IDX_FIRST_SPECIAL; iPage < PGMPOOL_IDX_FIRST; iPage++)
2019	{
2020	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
2021	if (pPage->GCPhys != NIL_RTGCPHYS)
2022	{
2023	Assert(!pPage->cModifications \|\| ++cModifiedPages);
2024	Assert(pPage->iModifiedNext == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2025	Assert(pPage->iModifiedPrev == NIL_PGMPOOL_IDX \|\| pPage->cModifications);
2026	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
2027	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
2028	pPage->cModifications = 0;
2029	}
2030	}
2031
2032	#ifndef DEBUG_michael
2033	AssertMsg(cModifiedPages == pPool->cModifiedPages, ("%d != %d\n", cModifiedPages, pPool->cModifiedPages));
2034	#endif
2035	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
2036	pPool->cModifiedPages = 0;
2037
2038	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2039	/*
2040	* Clear all the GCPhys links and rebuild the phys ext free list.
2041	*/
2042	for (PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
2043	pRam;
2044	pRam = pRam->CTX_SUFF(pNext))
2045	{
2046	unsigned iPage = pRam->cb >> PAGE_SHIFT;
2047	while (iPage-- > 0)
2048	PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
2049	}
2050
2051	pPool->iPhysExtFreeHead = 0;
2052	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
2053	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
2054	for (unsigned i = 0; i < cMaxPhysExts; i++)
2055	{
2056	paPhysExts[i].iNext = i + 1;
2057	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
2058	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
2059	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
2060	}
2061	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
2062	#endif
2063
2064	pPool->cPresent = 0;
2065	pgmUnlock(pVM);
2066	PGM_INVL_ALL_VCPU_TLBS(pVM);
2067	STAM_PROFILE_STOP(&pPool->StatClearAll, c);
2068	return VINF_SUCCESS;
2069	}
2070	#endif /* IN_RING3 */
2071
2072
2073	/**
2074	* Handle SyncCR3 pool tasks
2075	*
2076	* @returns VBox status code.
2077	* @retval VINF_SUCCESS if successfully added.
2078	* @retval VINF_PGM_SYNC_CR3 is it needs to be deferred to ring 3 (GC only)
2079	* @param pVM The VM handle.
2080	* @remark Should only be used when monitoring is available, thus placed in
2081	* the PGMPOOL_WITH_MONITORING #ifdef.
2082	*/
2083	int pgmPoolSyncCR3(PVM pVM)
2084	{
2085	LogFlow(("pgmPoolSyncCR3\n"));
2086	/*
2087	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2088	* Occasionally we will have to clear all the shadow page tables because we wanted
2089	* to monitor a page which was mapped by too many shadowed page tables. This operation
2090	* sometimes refered to as a 'lightweight flush'.
2091	*/
2092	# ifdef IN_RING3 /* Don't flush in ring-0 or raw mode, it's taking too long. */
2093	if (ASMBitTestAndClear(&pVM->pgm.s.fGlobalSyncFlags, PGM_GLOBAL_SYNC_CLEAR_PGM_POOL_BIT))
2094	{
2095	VMMR3AtomicExecuteHandler(pVM, pgmPoolClearAll, NULL);
2096	# else /* !IN_RING3 */
2097	if (pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL)
2098	{
2099	LogFlow(("SyncCR3: PGM_GLOBAL_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2100	VMCPU_FF_SET(VMMGetCpu(pVM), VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
2101	return VINF_PGM_SYNC_CR3;
2102	# endif /* !IN_RING3 */
2103	}
2104	else
2105	pgmPoolMonitorModifiedClearAll(pVM);
2106
2107	return VINF_SUCCESS;
2108	}
2109
2110	#endif /* PGMPOOL_WITH_MONITORING */
2111	#ifdef PGMPOOL_WITH_USER_TRACKING
2112
2113	/**
2114	* Frees up at least one user entry.
2115	*
2116	* @returns VBox status code.
2117	* @retval VINF_SUCCESS if successfully added.
2118	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2119	* @param pPool The pool.
2120	* @param iUser The user index.
2121	*/
2122	static int pgmPoolTrackFreeOneUser(PPGMPOOL pPool, uint16_t iUser)
2123	{
2124	STAM_COUNTER_INC(&pPool->StatTrackFreeUpOneUser);
2125	#ifdef PGMPOOL_WITH_CACHE
2126	/*
2127	* Just free cached pages in a braindead fashion.
2128	*/
2129	/** @todo walk the age list backwards and free the first with usage. */
2130	int rc = VINF_SUCCESS;
2131	do
2132	{
2133	int rc2 = pgmPoolCacheFreeOne(pPool, iUser);
2134	if (RT_FAILURE(rc2) && rc == VINF_SUCCESS)
2135	rc = rc2;
2136	} while (pPool->iUserFreeHead == NIL_PGMPOOL_USER_INDEX);
2137	return rc;
2138	#else
2139	/*
2140	* Lazy approach.
2141	*/
2142	/* @todo This path no longer works (CR3 root pages will be flushed)!! */
2143	AssertCompileFailed();
2144	Assert(!CPUMIsGuestInLongMode(pVM));
2145	pgmPoolFlushAllInt(pPool);
2146	return VERR_PGM_POOL_FLUSHED;
2147	#endif
2148	}
2149
2150
2151	/**
2152	* Inserts a page into the cache.
2153	*
2154	* This will create user node for the page, insert it into the GCPhys
2155	* hash, and insert it into the age list.
2156	*
2157	* @returns VBox status code.
2158	* @retval VINF_SUCCESS if successfully added.
2159	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2160	* @param pPool The pool.
2161	* @param pPage The cached page.
2162	* @param GCPhys The GC physical address of the page we're gonna shadow.
2163	* @param iUser The user index.
2164	* @param iUserTable The user table index.
2165	*/
2166	DECLINLINE(int) pgmPoolTrackInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhys, uint16_t iUser, uint32_t iUserTable)
2167	{
2168	int rc = VINF_SUCCESS;
2169	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2170
2171	LogFlow(("pgmPoolTrackInsert GCPhys=%RGp iUser %x iUserTable %x\n", GCPhys, iUser, iUserTable));
2172
2173	#ifdef VBOX_STRICT
2174	/*
2175	* Check that the entry doesn't already exists.
2176	*/
2177	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2178	{
2179	uint16_t i = pPage->iUserHead;
2180	do
2181	{
2182	Assert(i < pPool->cMaxUsers);
2183	AssertMsg(paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2184	i = paUsers[i].iNext;
2185	} while (i != NIL_PGMPOOL_USER_INDEX);
2186	}
2187	#endif
2188
2189	/*
2190	* Find free a user node.
2191	*/
2192	uint16_t i = pPool->iUserFreeHead;
2193	if (i == NIL_PGMPOOL_USER_INDEX)
2194	{
2195	int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2196	if (RT_FAILURE(rc))
2197	return rc;
2198	i = pPool->iUserFreeHead;
2199	}
2200
2201	/*
2202	* Unlink the user node from the free list,
2203	* initialize and insert it into the user list.
2204	*/
2205	pPool->iUserFreeHead = paUsers[i].iNext;
2206	paUsers[i].iNext = NIL_PGMPOOL_USER_INDEX;
2207	paUsers[i].iUser = iUser;
2208	paUsers[i].iUserTable = iUserTable;
2209	pPage->iUserHead = i;
2210
2211	/*
2212	* Insert into cache and enable monitoring of the guest page if enabled.
2213	*
2214	* Until we implement caching of all levels, including the CR3 one, we'll
2215	* have to make sure we don't try monitor & cache any recursive reuse of
2216	* a monitored CR3 page. Because all windows versions are doing this we'll
2217	* have to be able to do combined access monitoring, CR3 + PT and
2218	* PD + PT (guest PAE).
2219	*
2220	* Update:
2221	* We're now cooperating with the CR3 monitor if an uncachable page is found.
2222	*/
2223	#if defined(PGMPOOL_WITH_MONITORING) \|\| defined(PGMPOOL_WITH_CACHE)
2224	# ifdef PGMPOOL_WITH_MIXED_PT_CR3
2225	const bool fCanBeMonitored = true;
2226	# else
2227	bool fCanBeMonitored = pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored == NIL_RTGCPHYS
2228	\|\| (GCPhys & X86_PTE_PAE_PG_MASK) != (pPool->CTX_SUFF(pVM)->pgm.s.GCPhysGstCR3Monitored & X86_PTE_PAE_PG_MASK)
2229	\|\| pgmPoolIsBigPage((PGMPOOLKIND)pPage->enmKind);
2230	# endif
2231	# ifdef PGMPOOL_WITH_CACHE
2232	pgmPoolCacheInsert(pPool, pPage, fCanBeMonitored); /* This can be expanded. */
2233	# endif
2234	if (fCanBeMonitored)
2235	{
2236	# ifdef PGMPOOL_WITH_MONITORING
2237	rc = pgmPoolMonitorInsert(pPool, pPage);
2238	AssertRC(rc);
2239	}
2240	# endif
2241	#endif /* PGMPOOL_WITH_MONITORING */
2242	return rc;
2243	}
2244
2245
2246	# ifdef PGMPOOL_WITH_CACHE /* (only used when the cache is enabled.) */
2247	/**
2248	* Adds a user reference to a page.
2249	*
2250	* This will move the page to the head of the
2251	*
2252	* @returns VBox status code.
2253	* @retval VINF_SUCCESS if successfully added.
2254	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
2255	* @param pPool The pool.
2256	* @param pPage The cached page.
2257	* @param iUser The user index.
2258	* @param iUserTable The user table.
2259	*/
2260	static int pgmPoolTrackAddUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2261	{
2262	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2263
2264	Log3(("pgmPoolTrackAddUser GCPhys = %RGp iUser %x iUserTable %x\n", pPage->GCPhys, iUser, iUserTable));
2265
2266	# ifdef VBOX_STRICT
2267	/*
2268	* Check that the entry doesn't already exists. We only allow multiple users of top-level paging structures (SHW_POOL_ROOT_IDX).
2269	*/
2270	if (pPage->iUserHead != NIL_PGMPOOL_USER_INDEX)
2271	{
2272	uint16_t i = pPage->iUserHead;
2273	do
2274	{
2275	Assert(i < pPool->cMaxUsers);
2276	AssertMsg(iUser != PGMPOOL_IDX_PD \|\| iUser != PGMPOOL_IDX_PDPT \|\| iUser != PGMPOOL_IDX_NESTED_ROOT \|\| iUser != PGMPOOL_IDX_AMD64_CR3 \|\|
2277	paUsers[i].iUser != iUser \|\| paUsers[i].iUserTable != iUserTable, ("%x %x vs new %x %x\n", paUsers[i].iUser, paUsers[i].iUserTable, iUser, iUserTable));
2278	i = paUsers[i].iNext;
2279	} while (i != NIL_PGMPOOL_USER_INDEX);
2280	}
2281	# endif
2282
2283	/*
2284	* Allocate a user node.
2285	*/
2286	uint16_t i = pPool->iUserFreeHead;
2287	if (i == NIL_PGMPOOL_USER_INDEX)
2288	{
2289	int rc = pgmPoolTrackFreeOneUser(pPool, iUser);
2290	if (RT_FAILURE(rc))
2291	return rc;
2292	i = pPool->iUserFreeHead;
2293	}
2294	pPool->iUserFreeHead = paUsers[i].iNext;
2295
2296	/*
2297	* Initialize the user node and insert it.
2298	*/
2299	paUsers[i].iNext = pPage->iUserHead;
2300	paUsers[i].iUser = iUser;
2301	paUsers[i].iUserTable = iUserTable;
2302	pPage->iUserHead = i;
2303
2304	# ifdef PGMPOOL_WITH_CACHE
2305	/*
2306	* Tell the cache to update its replacement stats for this page.
2307	*/
2308	pgmPoolCacheUsed(pPool, pPage);
2309	# endif
2310	return VINF_SUCCESS;
2311	}
2312	# endif /* PGMPOOL_WITH_CACHE */
2313
2314
2315	/**
2316	* Frees a user record associated with a page.
2317	*
2318	* This does not clear the entry in the user table, it simply replaces the
2319	* user record to the chain of free records.
2320	*
2321	* @param pPool The pool.
2322	* @param HCPhys The HC physical address of the shadow page.
2323	* @param iUser The shadow page pool index of the user table.
2324	* @param iUserTable The index into the user table (shadowed).
2325	*/
2326	static void pgmPoolTrackFreeUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
2327	{
2328	/*
2329	* Unlink and free the specified user entry.
2330	*/
2331	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2332
2333	Log3(("pgmPoolTrackFreeUser %RGp %x %x\n", pPage->GCPhys, iUser, iUserTable));
2334	/* Special: For PAE and 32-bit paging, there is usually no more than one user. */
2335	uint16_t i = pPage->iUserHead;
2336	if ( i != NIL_PGMPOOL_USER_INDEX
2337	&& paUsers[i].iUser == iUser
2338	&& paUsers[i].iUserTable == iUserTable)
2339	{
2340	pPage->iUserHead = paUsers[i].iNext;
2341
2342	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2343	paUsers[i].iNext = pPool->iUserFreeHead;
2344	pPool->iUserFreeHead = i;
2345	return;
2346	}
2347
2348	/* General: Linear search. */
2349	uint16_t iPrev = NIL_PGMPOOL_USER_INDEX;
2350	while (i != NIL_PGMPOOL_USER_INDEX)
2351	{
2352	if ( paUsers[i].iUser == iUser
2353	&& paUsers[i].iUserTable == iUserTable)
2354	{
2355	if (iPrev != NIL_PGMPOOL_USER_INDEX)
2356	paUsers[iPrev].iNext = paUsers[i].iNext;
2357	else
2358	pPage->iUserHead = paUsers[i].iNext;
2359
2360	paUsers[i].iUser = NIL_PGMPOOL_IDX;
2361	paUsers[i].iNext = pPool->iUserFreeHead;
2362	pPool->iUserFreeHead = i;
2363	return;
2364	}
2365	iPrev = i;
2366	i = paUsers[i].iNext;
2367	}
2368
2369	/* Fatal: didn't find it */
2370	AssertFatalMsgFailed(("Didn't find the user entry! iUser=%#x iUserTable=%#x GCPhys=%RGp\n",
2371	iUser, iUserTable, pPage->GCPhys));
2372	}
2373
2374
2375	/**
2376	* Gets the entry size of a shadow table.
2377	*
2378	* @param enmKind The kind of page.
2379	*
2380	* @returns The size of the entry in bytes. That is, 4 or 8.
2381	* @returns If the kind is not for a table, an assertion is raised and 0 is
2382	* returned.
2383	*/
2384	DECLINLINE(unsigned) pgmPoolTrackGetShadowEntrySize(PGMPOOLKIND enmKind)
2385	{
2386	switch (enmKind)
2387	{
2388	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2389	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2390	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2391	case PGMPOOLKIND_32BIT_PD:
2392	case PGMPOOLKIND_32BIT_PD_PHYS:
2393	return 4;
2394
2395	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2396	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2397	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2398	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2399	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2400	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2401	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2402	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2403	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2404	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2405	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2406	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2407	case PGMPOOLKIND_64BIT_PML4:
2408	case PGMPOOLKIND_PAE_PDPT:
2409	case PGMPOOLKIND_ROOT_NESTED:
2410	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2411	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2412	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2413	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2414	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2415	case PGMPOOLKIND_PAE_PD_PHYS:
2416	case PGMPOOLKIND_PAE_PDPT_PHYS:
2417	return 8;
2418
2419	default:
2420	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2421	}
2422	}
2423
2424
2425	/**
2426	* Gets the entry size of a guest table.
2427	*
2428	* @param enmKind The kind of page.
2429	*
2430	* @returns The size of the entry in bytes. That is, 0, 4 or 8.
2431	* @returns If the kind is not for a table, an assertion is raised and 0 is
2432	* returned.
2433	*/
2434	DECLINLINE(unsigned) pgmPoolTrackGetGuestEntrySize(PGMPOOLKIND enmKind)
2435	{
2436	switch (enmKind)
2437	{
2438	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2439	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2440	case PGMPOOLKIND_32BIT_PD:
2441	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2442	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2443	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2444	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2445	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2446	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2447	return 4;
2448
2449	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2450	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2451	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2452	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2453	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2454	case PGMPOOLKIND_64BIT_PML4:
2455	case PGMPOOLKIND_PAE_PDPT:
2456	return 8;
2457
2458	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2459	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2460	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2461	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2462	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2463	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2464	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2465	case PGMPOOLKIND_ROOT_NESTED:
2466	case PGMPOOLKIND_PAE_PD_PHYS:
2467	case PGMPOOLKIND_PAE_PDPT_PHYS:
2468	case PGMPOOLKIND_32BIT_PD_PHYS:
2469	/** @todo can we return 0? (nobody is calling this...) */
2470	AssertFailed();
2471	return 0;
2472
2473	default:
2474	AssertFatalMsgFailed(("enmKind=%d\n", enmKind));
2475	}
2476	}
2477
2478	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2479
2480	/**
2481	* Scans one shadow page table for mappings of a physical page.
2482	*
2483	* @param pVM The VM handle.
2484	* @param pPhysPage The guest page in question.
2485	* @param iShw The shadow page table.
2486	* @param cRefs The number of references made in that PT.
2487	*/
2488	static void pgmPoolTrackFlushGCPhysPTInt(PVM pVM, PCPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs)
2489	{
2490	LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%R[pgmpage] iShw=%d cRefs=%d\n", pPhysPage, iShw, cRefs));
2491	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2492
2493	/*
2494	* Assert sanity.
2495	*/
2496	Assert(cRefs == 1);
2497	AssertFatalMsg(iShw < pPool->cCurPages && iShw != NIL_PGMPOOL_IDX, ("iShw=%d\n", iShw));
2498	PPGMPOOLPAGE pPage = &pPool->aPages[iShw];
2499
2500	/*
2501	* Then, clear the actual mappings to the page in the shadow PT.
2502	*/
2503	switch (pPage->enmKind)
2504	{
2505	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2506	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2507	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2508	{
2509	const uint32_t u32 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2510	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2511	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2512	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2513	{
2514	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX32 cRefs=%#x\n", i, pPT->a[i], cRefs));
2515	pPT->a[i].u = 0;
2516	cRefs--;
2517	if (!cRefs)
2518	return;
2519	}
2520	#ifdef LOG_ENABLED
2521	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2522	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2523	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2524	{
2525	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2526	pPT->a[i].u = 0;
2527	}
2528	#endif
2529	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
2530	break;
2531	}
2532
2533	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2534	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2535	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2536	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2537	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2538	{
2539	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2540	PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2541	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2542	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2543	{
2544	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
2545	pPT->a[i].u = 0;
2546	cRefs--;
2547	if (!cRefs)
2548	return;
2549	}
2550	#ifdef LOG_ENABLED
2551	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2552	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2553	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2554	{
2555	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2556	pPT->a[i].u = 0;
2557	}
2558	#endif
2559	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d u64=%RX64\n", cRefs, pPage->iFirstPresent, pPage->cPresent, u64));
2560	break;
2561	}
2562
2563	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
2564	{
2565	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2566	PEPTPT pPT = (PEPTPT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2567	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2568	if ((pPT->a[i].u & (EPT_PTE_PG_MASK \| X86_PTE_P)) == u64)
2569	{
2570	Log4(("pgmPoolTrackFlushGCPhysPTs: i=%d pte=%RX64 cRefs=%#x\n", i, pPT->a[i], cRefs));
2571	pPT->a[i].u = 0;
2572	cRefs--;
2573	if (!cRefs)
2574	return;
2575	}
2576	#ifdef LOG_ENABLED
2577	RTLogPrintf("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent);
2578	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
2579	if ((pPT->a[i].u & (EPT_PTE_PG_MASK \| X86_PTE_P)) == u64)
2580	{
2581	RTLogPrintf("i=%d cRefs=%d\n", i, cRefs--);
2582	pPT->a[i].u = 0;
2583	}
2584	#endif
2585	AssertFatalMsgFailed(("cRefs=%d iFirstPresent=%d cPresent=%d\n", cRefs, pPage->iFirstPresent, pPage->cPresent));
2586	break;
2587	}
2588
2589	default:
2590	AssertFatalMsgFailed(("enmKind=%d iShw=%d\n", pPage->enmKind, iShw));
2591	}
2592	}
2593
2594
2595	/**
2596	* Scans one shadow page table for mappings of a physical page.
2597	*
2598	* @param pVM The VM handle.
2599	* @param pPhysPage The guest page in question.
2600	* @param iShw The shadow page table.
2601	* @param cRefs The number of references made in that PT.
2602	*/
2603	void pgmPoolTrackFlushGCPhysPT(PVM pVM, PPGMPAGE pPhysPage, uint16_t iShw, uint16_t cRefs)
2604	{
2605	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2606	LogFlow(("pgmPoolTrackFlushGCPhysPT: pPhysPage=%R[pgmpage] iShw=%d cRefs=%d\n", pPhysPage, iShw, cRefs));
2607	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPT, f);
2608	pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, iShw, cRefs);
2609	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2610	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPT, f);
2611	}
2612
2613
2614	/**
2615	* Flushes a list of shadow page tables mapping the same physical page.
2616	*
2617	* @param pVM The VM handle.
2618	* @param pPhysPage The guest page in question.
2619	* @param iPhysExt The physical cross reference extent list to flush.
2620	*/
2621	void pgmPoolTrackFlushGCPhysPTs(PVM pVM, PPGMPAGE pPhysPage, uint16_t iPhysExt)
2622	{
2623	Assert(PGMIsLockOwner(pVM));
2624	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2625	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTs, f);
2626	LogFlow(("pgmPoolTrackFlushGCPhysPTs: pPhysPage=%R[pgmpage] iPhysExt\n", pPhysPage, iPhysExt));
2627
2628	const uint16_t iPhysExtStart = iPhysExt;
2629	PPGMPOOLPHYSEXT pPhysExt;
2630	do
2631	{
2632	Assert(iPhysExt < pPool->cMaxPhysExts);
2633	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
2634	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
2635	if (pPhysExt->aidx[i] != NIL_PGMPOOL_IDX)
2636	{
2637	pgmPoolTrackFlushGCPhysPTInt(pVM, pPhysPage, pPhysExt->aidx[i], 1);
2638	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
2639	}
2640
2641	/* next */
2642	iPhysExt = pPhysExt->iNext;
2643	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
2644
2645	/* insert the list into the free list and clear the ram range entry. */
2646	pPhysExt->iNext = pPool->iPhysExtFreeHead;
2647	pPool->iPhysExtFreeHead = iPhysExtStart;
2648	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2649
2650	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTs, f);
2651	}
2652
2653	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
2654
2655	/**
2656	* Flushes all shadow page table mappings of the given guest page.
2657	*
2658	* This is typically called when the host page backing the guest one has been
2659	* replaced or when the page protection was changed due to an access handler.
2660	*
2661	* @returns VBox status code.
2662	* @retval VINF_SUCCESS if all references has been successfully cleared.
2663	* @retval VINF_PGM_SYNC_CR3 if we're better off with a CR3 sync and a page
2664	* pool cleaning. FF and sync flags are set.
2665	*
2666	* @param pVM The VM handle.
2667	* @param pPhysPage The guest page in question.
2668	* @param pfFlushTLBs This is set to @a true if the shadow TLBs should be
2669	* flushed, it is NOT touched if this isn't necessary.
2670	* The caller MUST initialized this to @a false.
2671	*/
2672	int pgmPoolTrackFlushGCPhys(PVM pVM, PPGMPAGE pPhysPage, bool *pfFlushTLBs)
2673	{
2674	pgmLock(pVM);
2675	int rc = VINF_SUCCESS;
2676	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
2677	const uint16_t u16 = PGM_PAGE_GET_TRACKING(pPhysPage);
2678	if (u16)
2679	{
2680	/*
2681	* The zero page is currently screwing up the tracking and we'll
2682	* have to flush the whole shebang. Unless VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2683	* is defined, zero pages won't normally be mapped. Some kind of solution
2684	* will be needed for this problem of course, but it will have to wait...
2685	*/
2686	if (PGM_PAGE_IS_ZERO(pPhysPage))
2687	rc = VINF_PGM_GCPHYS_ALIASED;
2688	else
2689	{
2690	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2691	/* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow and
2692	pgmPoolTrackFlushGCPhysPTs will/may kill the pool otherwise. */
2693	PVMCPU pVCpu = VMMGetCpu(pVM);
2694	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
2695	# endif
2696
2697	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
2698	pgmPoolTrackFlushGCPhysPT(pVM,
2699	pPhysPage,
2700	PGMPOOL_TD_GET_IDX(u16),
2701	PGMPOOL_TD_GET_CREFS(u16));
2702	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
2703	pgmPoolTrackFlushGCPhysPTs(pVM, pPhysPage, PGMPOOL_TD_GET_IDX(u16));
2704	else
2705	rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
2706	*pfFlushTLBs = true;
2707
2708	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2709	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
2710	# endif
2711	}
2712	}
2713
2714	#elif defined(PGMPOOL_WITH_CACHE)
2715	if (PGM_PAGE_IS_ZERO(pPhysPage))
2716	rc = VINF_PGM_GCPHYS_ALIASED;
2717	else
2718	{
2719	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2720	/* Start a subset here because pgmPoolTrackFlushGCPhysPTsSlow kill the pool otherwise. */
2721	PVMCPU pVCpu = VMMGetCpu(pVM);
2722	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
2723	# endif
2724	rc = pgmPoolTrackFlushGCPhysPTsSlow(pVM, pPhysPage);
2725	if (rc == VINF_SUCCESS)
2726	*pfFlushTLBs = true;
2727	}
2728
2729	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2730	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
2731	# endif
2732
2733	#else
2734	rc = VINF_PGM_GCPHYS_ALIASED;
2735	#endif
2736
2737	if (rc == VINF_PGM_GCPHYS_ALIASED)
2738	{
2739	pVM->pgm.s.fGlobalSyncFlags \|= PGM_GLOBAL_SYNC_CLEAR_PGM_POOL;
2740	for (unsigned i=0;i<pVM->cCPUs;i++)
2741	{
2742	PVMCPU pVCpu = &pVM->aCpus[i];
2743	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2744	}
2745	rc = VINF_PGM_SYNC_CR3;
2746	}
2747	pgmUnlock(pVM);
2748	return rc;
2749	}
2750
2751
2752	/**
2753	* Scans all shadow page tables for mappings of a physical page.
2754	*
2755	* This may be slow, but it's most likely more efficient than cleaning
2756	* out the entire page pool / cache.
2757	*
2758	* @returns VBox status code.
2759	* @retval VINF_SUCCESS if all references has been successfully cleared.
2760	* @retval VINF_PGM_GCPHYS_ALIASED if we're better off with a CR3 sync and
2761	* a page pool cleaning.
2762	*
2763	* @param pVM The VM handle.
2764	* @param pPhysPage The guest page in question.
2765	*/
2766	int pgmPoolTrackFlushGCPhysPTsSlow(PVM pVM, PPGMPAGE pPhysPage)
2767	{
2768	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2769	STAM_PROFILE_START(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2770	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: cUsedPages=%d cPresent=%d pPhysPage=%R[pgmpage]\n",
2771	pPool->cUsedPages, pPool->cPresent, pPhysPage));
2772
2773	#if 1
2774	/*
2775	* There is a limit to what makes sense.
2776	*/
2777	if (pPool->cPresent > 1024)
2778	{
2779	LogFlow(("pgmPoolTrackFlushGCPhysPTsSlow: giving up... (cPresent=%d)\n", pPool->cPresent));
2780	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2781	return VINF_PGM_GCPHYS_ALIASED;
2782	}
2783	#endif
2784
2785	/*
2786	* Iterate all the pages until we've encountered all that in use.
2787	* This is simple but not quite optimal solution.
2788	*/
2789	const uint64_t u64 = PGM_PAGE_GET_HCPHYS(pPhysPage) \| X86_PTE_P;
2790	const uint32_t u32 = u64;
2791	unsigned cLeft = pPool->cUsedPages;
2792	unsigned iPage = pPool->cCurPages;
2793	while (--iPage >= PGMPOOL_IDX_FIRST)
2794	{
2795	PPGMPOOLPAGE pPage = &pPool->aPages[iPage];
2796	if (pPage->GCPhys != NIL_RTGCPHYS)
2797	{
2798	switch (pPage->enmKind)
2799	{
2800	/*
2801	* We only care about shadow page tables.
2802	*/
2803	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
2804	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
2805	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
2806	{
2807	unsigned cPresent = pPage->cPresent;
2808	PX86PT pPT = (PX86PT)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2809	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2810	if (pPT->a[i].n.u1Present)
2811	{
2812	if ((pPT->a[i].u & (X86_PTE_PG_MASK \| X86_PTE_P)) == u32)
2813	{
2814	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX32\n", iPage, i, pPT->a[i]));
2815	pPT->a[i].u = 0;
2816	}
2817	if (!--cPresent)
2818	break;
2819	}
2820	break;
2821	}
2822
2823	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
2824	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
2825	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
2826	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
2827	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
2828	{
2829	unsigned cPresent = pPage->cPresent;
2830	PX86PTPAE pPT = (PX86PTPAE)PGMPOOL_PAGE_2_PTR(pVM, pPage);
2831	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pPT->a); i++)
2832	if (pPT->a[i].n.u1Present)
2833	{
2834	if ((pPT->a[i].u & (X86_PTE_PAE_PG_MASK \| X86_PTE_P)) == u64)
2835	{
2836	//Log4(("pgmPoolTrackFlushGCPhysPTsSlow: idx=%d i=%d pte=%RX64\n", iPage, i, pPT->a[i]));
2837	pPT->a[i].u = 0;
2838	}
2839	if (!--cPresent)
2840	break;
2841	}
2842	break;
2843	}
2844	}
2845	if (!--cLeft)
2846	break;
2847	}
2848	}
2849
2850	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
2851	STAM_PROFILE_STOP(&pPool->StatTrackFlushGCPhysPTsSlow, s);
2852	return VINF_SUCCESS;
2853	}
2854
2855
2856	/**
2857	* Clears the user entry in a user table.
2858	*
2859	* This is used to remove all references to a page when flushing it.
2860	*/
2861	static void pgmPoolTrackClearPageUser(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PCPGMPOOLUSER pUser)
2862	{
2863	Assert(pUser->iUser != NIL_PGMPOOL_IDX);
2864	Assert(pUser->iUser < pPool->cCurPages);
2865	uint32_t iUserTable = pUser->iUserTable;
2866
2867	/*
2868	* Map the user page.
2869	*/
2870	PPGMPOOLPAGE pUserPage = &pPool->aPages[pUser->iUser];
2871	union
2872	{
2873	uint64_t *pau64;
2874	uint32_t *pau32;
2875	} u;
2876	u.pau64 = (uint64_t *)PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pUserPage);
2877
2878	LogFlow(("pgmPoolTrackClearPageUser: clear %x in %s (%RGp) (flushing %s)\n", iUserTable, pgmPoolPoolKindToStr(pUserPage->enmKind), pUserPage->Core.Key, pgmPoolPoolKindToStr(pPage->enmKind)));
2879
2880	/* Safety precaution in case we change the paging for other modes too in the future. */
2881	Assert(!pgmPoolIsPageLocked(&pPool->CTX_SUFF(pVM)->pgm.s, pPage));
2882
2883	#ifdef VBOX_STRICT
2884	/*
2885	* Some sanity checks.
2886	*/
2887	switch (pUserPage->enmKind)
2888	{
2889	case PGMPOOLKIND_32BIT_PD:
2890	case PGMPOOLKIND_32BIT_PD_PHYS:
2891	Assert(iUserTable < X86_PG_ENTRIES);
2892	break;
2893	case PGMPOOLKIND_PAE_PDPT:
2894	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2895	case PGMPOOLKIND_PAE_PDPT_PHYS:
2896	Assert(iUserTable < 4);
2897	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2898	break;
2899	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2900	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2901	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2902	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2903	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2904	case PGMPOOLKIND_PAE_PD_PHYS:
2905	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2906	break;
2907	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2908	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2909	Assert(!(u.pau64[iUserTable] & PGM_PDFLAGS_MAPPING));
2910	break;
2911	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2912	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2913	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2914	break;
2915	case PGMPOOLKIND_64BIT_PML4:
2916	Assert(!(u.pau64[iUserTable] & PGM_PLXFLAGS_PERMANENT));
2917	/* GCPhys >> PAGE_SHIFT is the index here */
2918	break;
2919	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2920	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2921	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2922	break;
2923
2924	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2925	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2926	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2927	break;
2928
2929	case PGMPOOLKIND_ROOT_NESTED:
2930	Assert(iUserTable < X86_PG_PAE_ENTRIES);
2931	break;
2932
2933	default:
2934	AssertMsgFailed(("enmKind=%d\n", pUserPage->enmKind));
2935	break;
2936	}
2937	#endif /* VBOX_STRICT */
2938
2939	/*
2940	* Clear the entry in the user page.
2941	*/
2942	switch (pUserPage->enmKind)
2943	{
2944	/* 32-bit entries */
2945	case PGMPOOLKIND_32BIT_PD:
2946	case PGMPOOLKIND_32BIT_PD_PHYS:
2947	u.pau32[iUserTable] = 0;
2948	break;
2949
2950	/* 64-bit entries */
2951	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
2952	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
2953	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
2954	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
2955	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
2956	#if defined(IN_RC)
2957	/* In 32 bits PAE mode we must invalidate the TLB when changing a PDPT entry; the CPU fetches them only during cr3 load, so any
2958	* non-present PDPT will continue to cause page faults.
2959	*/
2960	ASMReloadCR3();
2961	#endif
2962	/* no break */
2963	case PGMPOOLKIND_PAE_PD_PHYS:
2964	case PGMPOOLKIND_PAE_PDPT_PHYS:
2965	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
2966	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
2967	case PGMPOOLKIND_64BIT_PML4:
2968	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
2969	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
2970	case PGMPOOLKIND_PAE_PDPT:
2971	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
2972	case PGMPOOLKIND_ROOT_NESTED:
2973	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
2974	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
2975	u.pau64[iUserTable] = 0;
2976	break;
2977
2978	default:
2979	AssertFatalMsgFailed(("enmKind=%d iUser=%#x iUserTable=%#x\n", pUserPage->enmKind, pUser->iUser, pUser->iUserTable));
2980	}
2981	}
2982
2983
2984	/**
2985	* Clears all users of a page.
2986	*/
2987	static void pgmPoolTrackClearPageUsers(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
2988	{
2989	/*
2990	* Free all the user records.
2991	*/
2992	LogFlow(("pgmPoolTrackClearPageUsers %RGp\n", pPage->GCPhys));
2993
2994	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
2995	uint16_t i = pPage->iUserHead;
2996	while (i != NIL_PGMPOOL_USER_INDEX)
2997	{
2998	/* Clear enter in user table. */
2999	pgmPoolTrackClearPageUser(pPool, pPage, &paUsers[i]);
3000
3001	/* Free it. */
3002	const uint16_t iNext = paUsers[i].iNext;
3003	paUsers[i].iUser = NIL_PGMPOOL_IDX;
3004	paUsers[i].iNext = pPool->iUserFreeHead;
3005	pPool->iUserFreeHead = i;
3006
3007	/* Next. */
3008	i = iNext;
3009	}
3010	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
3011	}
3012
3013	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3014
3015	/**
3016	* Allocates a new physical cross reference extent.
3017	*
3018	* @returns Pointer to the allocated extent on success. NULL if we're out of them.
3019	* @param pVM The VM handle.
3020	* @param piPhysExt Where to store the phys ext index.
3021	*/
3022	PPGMPOOLPHYSEXT pgmPoolTrackPhysExtAlloc(PVM pVM, uint16_t *piPhysExt)
3023	{
3024	Assert(PGMIsLockOwner(pVM));
3025	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3026	uint16_t iPhysExt = pPool->iPhysExtFreeHead;
3027	if (iPhysExt == NIL_PGMPOOL_PHYSEXT_INDEX)
3028	{
3029	STAM_COUNTER_INC(&pPool->StamTrackPhysExtAllocFailures);
3030	return NULL;
3031	}
3032	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3033	pPool->iPhysExtFreeHead = pPhysExt->iNext;
3034	pPhysExt->iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
3035	*piPhysExt = iPhysExt;
3036	return pPhysExt;
3037	}
3038
3039
3040	/**
3041	* Frees a physical cross reference extent.
3042	*
3043	* @param pVM The VM handle.
3044	* @param iPhysExt The extent to free.
3045	*/
3046	void pgmPoolTrackPhysExtFree(PVM pVM, uint16_t iPhysExt)
3047	{
3048	Assert(PGMIsLockOwner(pVM));
3049	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3050	Assert(iPhysExt < pPool->cMaxPhysExts);
3051	PPGMPOOLPHYSEXT pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3052	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3053	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3054	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3055	pPool->iPhysExtFreeHead = iPhysExt;
3056	}
3057
3058
3059	/**
3060	* Frees a physical cross reference extent.
3061	*
3062	* @param pVM The VM handle.
3063	* @param iPhysExt The extent to free.
3064	*/
3065	void pgmPoolTrackPhysExtFreeList(PVM pVM, uint16_t iPhysExt)
3066	{
3067	Assert(PGMIsLockOwner(pVM));
3068	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3069
3070	const uint16_t iPhysExtStart = iPhysExt;
3071	PPGMPOOLPHYSEXT pPhysExt;
3072	do
3073	{
3074	Assert(iPhysExt < pPool->cMaxPhysExts);
3075	pPhysExt = &pPool->CTX_SUFF(paPhysExts)[iPhysExt];
3076	for (unsigned i = 0; i < RT_ELEMENTS(pPhysExt->aidx); i++)
3077	pPhysExt->aidx[i] = NIL_PGMPOOL_IDX;
3078
3079	/* next */
3080	iPhysExt = pPhysExt->iNext;
3081	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3082
3083	pPhysExt->iNext = pPool->iPhysExtFreeHead;
3084	pPool->iPhysExtFreeHead = iPhysExtStart;
3085	}
3086
3087
3088	/**
3089	* Insert a reference into a list of physical cross reference extents.
3090	*
3091	* @returns The new tracking data for PGMPAGE.
3092	*
3093	* @param pVM The VM handle.
3094	* @param iPhysExt The physical extent index of the list head.
3095	* @param iShwPT The shadow page table index.
3096	*
3097	*/
3098	static uint16_t pgmPoolTrackPhysExtInsert(PVM pVM, uint16_t iPhysExt, uint16_t iShwPT)
3099	{
3100	Assert(PGMIsLockOwner(pVM));
3101	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3102	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3103
3104	/* special common case. */
3105	if (paPhysExts[iPhysExt].aidx[2] == NIL_PGMPOOL_IDX)
3106	{
3107	paPhysExts[iPhysExt].aidx[2] = iShwPT;
3108	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3109	LogFlow(("pgmPoolTrackPhysExtAddref: %d:{,,%d}\n", iPhysExt, iShwPT));
3110	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3111	}
3112
3113	/* general treatment. */
3114	const uint16_t iPhysExtStart = iPhysExt;
3115	unsigned cMax = 15;
3116	for (;;)
3117	{
3118	Assert(iPhysExt < pPool->cMaxPhysExts);
3119	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3120	if (paPhysExts[iPhysExt].aidx[i] == NIL_PGMPOOL_IDX)
3121	{
3122	paPhysExts[iPhysExt].aidx[i] = iShwPT;
3123	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedMany);
3124	LogFlow(("pgmPoolTrackPhysExtAddref: %d:{%d} i=%d cMax=%d\n", iPhysExt, iShwPT, i, cMax));
3125	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtStart);
3126	}
3127	if (!--cMax)
3128	{
3129	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3130	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3131	LogFlow(("pgmPoolTrackPhysExtAddref: overflow (1) iShwPT=%d\n", iShwPT));
3132	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3133	}
3134	}
3135
3136	/* add another extent to the list. */
3137	PPGMPOOLPHYSEXT pNew = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3138	if (!pNew)
3139	{
3140	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackOverflows);
3141	pgmPoolTrackPhysExtFreeList(pVM, iPhysExtStart);
3142	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3143	}
3144	pNew->iNext = iPhysExtStart;
3145	pNew->aidx[0] = iShwPT;
3146	LogFlow(("pgmPoolTrackPhysExtAddref: added new extent %d:{%d}->%d\n", iPhysExt, iShwPT, iPhysExtStart));
3147	return PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3148	}
3149
3150
3151	/**
3152	* Add a reference to guest physical page where extents are in use.
3153	*
3154	* @returns The new tracking data for PGMPAGE.
3155	*
3156	* @param pVM The VM handle.
3157	* @param u16 The ram range flags (top 16-bits).
3158	* @param iShwPT The shadow page table index.
3159	*/
3160	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, uint16_t u16, uint16_t iShwPT)
3161	{
3162	pgmLock(pVM);
3163	if (PGMPOOL_TD_GET_CREFS(u16) != PGMPOOL_TD_CREFS_PHYSEXT)
3164	{
3165	/*
3166	* Convert to extent list.
3167	*/
3168	Assert(PGMPOOL_TD_GET_CREFS(u16) == 1);
3169	uint16_t iPhysExt;
3170	PPGMPOOLPHYSEXT pPhysExt = pgmPoolTrackPhysExtAlloc(pVM, &iPhysExt);
3171	if (pPhysExt)
3172	{
3173	LogFlow(("pgmPoolTrackPhysExtAddref: new extent: %d:{%d, %d}\n", iPhysExt, PGMPOOL_TD_GET_IDX(u16), iShwPT));
3174	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliased);
3175	pPhysExt->aidx[0] = PGMPOOL_TD_GET_IDX(u16);
3176	pPhysExt->aidx[1] = iShwPT;
3177	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExt);
3178	}
3179	else
3180	u16 = PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED);
3181	}
3182	else if (u16 != PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, PGMPOOL_TD_IDX_OVERFLOWED))
3183	{
3184	/*
3185	* Insert into the extent list.
3186	*/
3187	u16 = pgmPoolTrackPhysExtInsert(pVM, PGMPOOL_TD_GET_IDX(u16), iShwPT);
3188	}
3189	else
3190	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackAliasedLots);
3191	pgmUnlock(pVM);
3192	return u16;
3193	}
3194
3195
3196	/**
3197	* Clear references to guest physical memory.
3198	*
3199	* @param pPool The pool.
3200	* @param pPage The page.
3201	* @param pPhysPage Pointer to the aPages entry in the ram range.
3202	*/
3203	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PPGMPAGE pPhysPage)
3204	{
3205	const unsigned cRefs = PGM_PAGE_GET_TD_CREFS(pPhysPage);
3206	AssertFatalMsg(cRefs == PGMPOOL_TD_CREFS_PHYSEXT, ("cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3207
3208	uint16_t iPhysExt = PGM_PAGE_GET_TD_IDX(pPhysPage);
3209	if (iPhysExt != PGMPOOL_TD_IDX_OVERFLOWED)
3210	{
3211	PVM pVM = pPool->CTX_SUFF(pVM);
3212	pgmLock(pVM);
3213
3214	uint16_t iPhysExtPrev = NIL_PGMPOOL_PHYSEXT_INDEX;
3215	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
3216	do
3217	{
3218	Assert(iPhysExt < pPool->cMaxPhysExts);
3219
3220	/*
3221	* Look for the shadow page and check if it's all freed.
3222	*/
3223	for (unsigned i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3224	{
3225	if (paPhysExts[iPhysExt].aidx[i] == pPage->idx)
3226	{
3227	paPhysExts[iPhysExt].aidx[i] = NIL_PGMPOOL_IDX;
3228
3229	for (i = 0; i < RT_ELEMENTS(paPhysExts[iPhysExt].aidx); i++)
3230	if (paPhysExts[iPhysExt].aidx[i] != NIL_PGMPOOL_IDX)
3231	{
3232	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3233	pgmUnlock(pVM);
3234	return;
3235	}
3236
3237	/* we can free the node. */
3238	const uint16_t iPhysExtNext = paPhysExts[iPhysExt].iNext;
3239	if ( iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX
3240	&& iPhysExtNext == NIL_PGMPOOL_PHYSEXT_INDEX)
3241	{
3242	/* lonely node */
3243	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3244	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d lonely\n", pPhysPage, pPage->idx));
3245	PGM_PAGE_SET_TRACKING(pPhysPage, 0);
3246	}
3247	else if (iPhysExtPrev == NIL_PGMPOOL_PHYSEXT_INDEX)
3248	{
3249	/* head */
3250	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d head\n", pPhysPage, pPage->idx));
3251	PGM_PAGE_SET_TRACKING(pPhysPage, PGMPOOL_TD_MAKE(PGMPOOL_TD_CREFS_PHYSEXT, iPhysExtNext));
3252	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3253	}
3254	else
3255	{
3256	/* in list */
3257	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage] idx=%d\n", pPhysPage, pPage->idx));
3258	paPhysExts[iPhysExtPrev].iNext = iPhysExtNext;
3259	pgmPoolTrackPhysExtFree(pVM, iPhysExt);
3260	}
3261	iPhysExt = iPhysExtNext;
3262	pgmUnlock(pVM);
3263	return;
3264	}
3265	}
3266
3267	/* next */
3268	iPhysExtPrev = iPhysExt;
3269	iPhysExt = paPhysExts[iPhysExt].iNext;
3270	} while (iPhysExt != NIL_PGMPOOL_PHYSEXT_INDEX);
3271
3272	pgmUnlock(pVM);
3273	AssertFatalMsgFailed(("not-found! cRefs=%d pPhysPage=%R[pgmpage] pPage=%p:{.idx=%d}\n", cRefs, pPhysPage, pPage, pPage->idx));
3274	}
3275	else /* nothing to do */
3276	Log2(("pgmPoolTrackPhysExtDerefGCPhys: pPhysPage=%R[pgmpage]\n", pPhysPage));
3277	}
3278
3279
3280	/**
3281	* Clear references to guest physical memory.
3282	*
3283	* This is the same as pgmPoolTracDerefGCPhys except that the guest physical address
3284	* is assumed to be correct, so the linear search can be skipped and we can assert
3285	* at an earlier point.
3286	*
3287	* @param pPool The pool.
3288	* @param pPage The page.
3289	* @param HCPhys The host physical address corresponding to the guest page.
3290	* @param GCPhys The guest physical address corresponding to HCPhys.
3291	*/
3292	static void pgmPoolTracDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhys)
3293	{
3294	/*
3295	* Walk range list.
3296	*/
3297	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3298	while (pRam)
3299	{
3300	RTGCPHYS off = GCPhys - pRam->GCPhys;
3301	if (off < pRam->cb)
3302	{
3303	/* does it match? */
3304	const unsigned iPage = off >> PAGE_SHIFT;
3305	Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3306	#ifdef LOG_ENABLED
3307	RTHCPHYS HCPhysPage = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]);
3308	Log2(("pgmPoolTracDerefGCPhys %RHp vs %RHp\n", HCPhysPage, HCPhys));
3309	#endif
3310	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3311	{
3312	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3313	return;
3314	}
3315	break;
3316	}
3317	pRam = pRam->CTX_SUFF(pNext);
3318	}
3319	AssertFatalMsgFailed(("HCPhys=%RHp GCPhys=%RGp\n", HCPhys, GCPhys));
3320	}
3321
3322
3323	/**
3324	* Clear references to guest physical memory.
3325	*
3326	* @param pPool The pool.
3327	* @param pPage The page.
3328	* @param HCPhys The host physical address corresponding to the guest page.
3329	* @param GCPhysHint The guest physical address which may corresponding to HCPhys.
3330	*/
3331	static void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint)
3332	{
3333	Log4(("pgmPoolTracDerefGCPhysHint %RHp %RGp\n", HCPhys, GCPhysHint));
3334
3335	/*
3336	* Walk range list.
3337	*/
3338	PPGMRAMRANGE pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3339	while (pRam)
3340	{
3341	RTGCPHYS off = GCPhysHint - pRam->GCPhys;
3342	if (off < pRam->cb)
3343	{
3344	/* does it match? */
3345	const unsigned iPage = off >> PAGE_SHIFT;
3346	Assert(PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]));
3347	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3348	{
3349	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3350	return;
3351	}
3352	break;
3353	}
3354	pRam = pRam->CTX_SUFF(pNext);
3355	}
3356
3357	/*
3358	* Damn, the hint didn't work. We'll have to do an expensive linear search.
3359	*/
3360	STAM_COUNTER_INC(&pPool->StatTrackLinearRamSearches);
3361	pRam = pPool->CTX_SUFF(pVM)->pgm.s.CTX_SUFF(pRamRanges);
3362	while (pRam)
3363	{
3364	unsigned iPage = pRam->cb >> PAGE_SHIFT;
3365	while (iPage-- > 0)
3366	{
3367	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
3368	{
3369	Log4(("pgmPoolTracDerefGCPhysHint: Linear HCPhys=%RHp GCPhysHint=%RGp GCPhysReal=%RGp\n",
3370	HCPhys, GCPhysHint, pRam->GCPhys + (iPage << PAGE_SHIFT)));
3371	pgmTrackDerefGCPhys(pPool, pPage, &pRam->aPages[iPage]);
3372	return;
3373	}
3374	}
3375	pRam = pRam->CTX_SUFF(pNext);
3376	}
3377
3378	AssertFatalMsgFailed(("HCPhys=%RHp GCPhysHint=%RGp\n", HCPhys, GCPhysHint));
3379	}
3380
3381
3382	/**
3383	* Clear references to guest physical memory in a 32-bit / 32-bit page table.
3384	*
3385	* @param pPool The pool.
3386	* @param pPage The page.
3387	* @param pShwPT The shadow page table (mapping of the page).
3388	* @param pGstPT The guest page table.
3389	*/
3390	DECLINLINE(void) pgmPoolTrackDerefPT32Bit32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT, PCX86PT pGstPT)
3391	{
3392	for (unsigned i = pPage->iFirstPresent; i < RT_ELEMENTS(pShwPT->a); i++)
3393	if (pShwPT->a[i].n.u1Present)
3394	{
3395	Log4(("pgmPoolTrackDerefPT32Bit32Bit: i=%d pte=%RX32 hint=%RX32\n",
3396	i, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
3397	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
3398	if (!--pPage->cPresent)
3399	break;
3400	}
3401	}
3402
3403
3404	/**
3405	* Clear references to guest physical memory in a PAE / 32-bit page table.
3406	*
3407	* @param pPool The pool.
3408	* @param pPage The page.
3409	* @param pShwPT The shadow page table (mapping of the page).
3410	* @param pGstPT The guest page table (just a half one).
3411	*/
3412	DECLINLINE(void) pgmPoolTrackDerefPTPae32Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PT pGstPT)
3413	{
3414	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++)
3415	if (pShwPT->a[i].n.u1Present)
3416	{
3417	Log4(("pgmPoolTrackDerefPTPae32Bit: i=%d pte=%RX64 hint=%RX32\n",
3418	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK));
3419	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PG_MASK);
3420	}
3421	}
3422
3423
3424	/**
3425	* Clear references to guest physical memory in a PAE / PAE page table.
3426	*
3427	* @param pPool The pool.
3428	* @param pPage The page.
3429	* @param pShwPT The shadow page table (mapping of the page).
3430	* @param pGstPT The guest page table.
3431	*/
3432	DECLINLINE(void) pgmPoolTrackDerefPTPaePae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT, PCX86PTPAE pGstPT)
3433	{
3434	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++)
3435	if (pShwPT->a[i].n.u1Present)
3436	{
3437	Log4(("pgmPoolTrackDerefPTPaePae: i=%d pte=%RX32 hint=%RX32\n",
3438	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK));
3439	pgmPoolTracDerefGCPhysHint(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, pGstPT->a[i].u & X86_PTE_PAE_PG_MASK);
3440	}
3441	}
3442
3443
3444	/**
3445	* Clear references to guest physical memory in a 32-bit / 4MB page table.
3446	*
3447	* @param pPool The pool.
3448	* @param pPage The page.
3449	* @param pShwPT The shadow page table (mapping of the page).
3450	*/
3451	DECLINLINE(void) pgmPoolTrackDerefPT32Bit4MB(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PT pShwPT)
3452	{
3453	RTGCPHYS GCPhys = pPage->GCPhys;
3454	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3455	if (pShwPT->a[i].n.u1Present)
3456	{
3457	Log4(("pgmPoolTrackDerefPT32Bit4MB: i=%d pte=%RX32 GCPhys=%RGp\n",
3458	i, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys));
3459	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PG_MASK, GCPhys);
3460	}
3461	}
3462
3463
3464	/**
3465	* Clear references to guest physical memory in a PAE / 2/4MB page table.
3466	*
3467	* @param pPool The pool.
3468	* @param pPage The page.
3469	* @param pShwPT The shadow page table (mapping of the page).
3470	*/
3471	DECLINLINE(void) pgmPoolTrackDerefPTPaeBig(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PTPAE pShwPT)
3472	{
3473	RTGCPHYS GCPhys = pPage->GCPhys;
3474	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3475	if (pShwPT->a[i].n.u1Present)
3476	{
3477	Log4(("pgmPoolTrackDerefPTPaeBig: i=%d pte=%RX64 hint=%RGp\n",
3478	i, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys));
3479	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & X86_PTE_PAE_PG_MASK, GCPhys);
3480	}
3481	}
3482
3483	#endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
3484
3485
3486	/**
3487	* Clear references to shadowed pages in a 32 bits page directory.
3488	*
3489	* @param pPool The pool.
3490	* @param pPage The page.
3491	* @param pShwPD The shadow page directory (mapping of the page).
3492	*/
3493	DECLINLINE(void) pgmPoolTrackDerefPD(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PD pShwPD)
3494	{
3495	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3496	{
3497	if ( pShwPD->a[i].n.u1Present
3498	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
3499	)
3500	{
3501	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PG_MASK);
3502	if (pSubPage)
3503	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3504	else
3505	AssertFatalMsgFailed(("%x\n", pShwPD->a[i].u & X86_PDE_PG_MASK));
3506	}
3507	}
3508	}
3509
3510	/**
3511	* Clear references to shadowed pages in a PAE (legacy or 64 bits) page directory.
3512	*
3513	* @param pPool The pool.
3514	* @param pPage The page.
3515	* @param pShwPD The shadow page directory (mapping of the page).
3516	*/
3517	DECLINLINE(void) pgmPoolTrackDerefPDPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPAE pShwPD)
3518	{
3519	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3520	{
3521	if ( pShwPD->a[i].n.u1Present
3522	&& !(pShwPD->a[i].u & PGM_PDFLAGS_MAPPING)
3523	)
3524	{
3525	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & X86_PDE_PAE_PG_MASK);
3526	if (pSubPage)
3527	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3528	else
3529	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & X86_PDE_PAE_PG_MASK));
3530	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3531	}
3532	}
3533	}
3534
3535	/**
3536	* Clear references to shadowed pages in a PAE page directory pointer table.
3537	*
3538	* @param pPool The pool.
3539	* @param pPage The page.
3540	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3541	*/
3542	DECLINLINE(void) pgmPoolTrackDerefPDPTPae(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
3543	{
3544	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
3545	{
3546	if ( pShwPDPT->a[i].n.u1Present
3547	&& !(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING)
3548	)
3549	{
3550	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
3551	if (pSubPage)
3552	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3553	else
3554	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
3555	}
3556	}
3557	}
3558
3559
3560	/**
3561	* Clear references to shadowed pages in a 64-bit page directory pointer table.
3562	*
3563	* @param pPool The pool.
3564	* @param pPage The page.
3565	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3566	*/
3567	DECLINLINE(void) pgmPoolTrackDerefPDPT64Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PDPT pShwPDPT)
3568	{
3569	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
3570	{
3571	Assert(!(pShwPDPT->a[i].u & PGM_PLXFLAGS_MAPPING));
3572	if (pShwPDPT->a[i].n.u1Present)
3573	{
3574	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & X86_PDPE_PG_MASK);
3575	if (pSubPage)
3576	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3577	else
3578	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & X86_PDPE_PG_MASK));
3579	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3580	}
3581	}
3582	}
3583
3584
3585	/**
3586	* Clear references to shadowed pages in a 64-bit level 4 page table.
3587	*
3588	* @param pPool The pool.
3589	* @param pPage The page.
3590	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
3591	*/
3592	DECLINLINE(void) pgmPoolTrackDerefPML464Bit(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PX86PML4 pShwPML4)
3593	{
3594	for (unsigned i = 0; i < RT_ELEMENTS(pShwPML4->a); i++)
3595	{
3596	if (pShwPML4->a[i].n.u1Present)
3597	{
3598	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPML4->a[i].u & X86_PDPE_PG_MASK);
3599	if (pSubPage)
3600	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3601	else
3602	AssertFatalMsgFailed(("%RX64\n", pShwPML4->a[i].u & X86_PML4E_PG_MASK));
3603	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3604	}
3605	}
3606	}
3607
3608
3609	/**
3610	* Clear references to shadowed pages in an EPT page table.
3611	*
3612	* @param pPool The pool.
3613	* @param pPage The page.
3614	* @param pShwPML4 The shadow page directory pointer table (mapping of the page).
3615	*/
3616	DECLINLINE(void) pgmPoolTrackDerefPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPT pShwPT)
3617	{
3618	RTGCPHYS GCPhys = pPage->GCPhys;
3619	for (unsigned i = 0; i < RT_ELEMENTS(pShwPT->a); i++, GCPhys += PAGE_SIZE)
3620	if (pShwPT->a[i].n.u1Present)
3621	{
3622	Log4(("pgmPoolTrackDerefPTEPT: i=%d pte=%RX64 GCPhys=%RX64\n",
3623	i, pShwPT->a[i].u & EPT_PTE_PG_MASK, pPage->GCPhys));
3624	pgmPoolTracDerefGCPhys(pPool, pPage, pShwPT->a[i].u & EPT_PTE_PG_MASK, GCPhys);
3625	}
3626	}
3627
3628
3629	/**
3630	* Clear references to shadowed pages in an EPT page directory.
3631	*
3632	* @param pPool The pool.
3633	* @param pPage The page.
3634	* @param pShwPD The shadow page directory (mapping of the page).
3635	*/
3636	DECLINLINE(void) pgmPoolTrackDerefPDEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPD pShwPD)
3637	{
3638	for (unsigned i = 0; i < RT_ELEMENTS(pShwPD->a); i++)
3639	{
3640	if (pShwPD->a[i].n.u1Present)
3641	{
3642	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPD->a[i].u & EPT_PDE_PG_MASK);
3643	if (pSubPage)
3644	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3645	else
3646	AssertFatalMsgFailed(("%RX64\n", pShwPD->a[i].u & EPT_PDE_PG_MASK));
3647	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3648	}
3649	}
3650	}
3651
3652
3653	/**
3654	* Clear references to shadowed pages in an EPT page directory pointer table.
3655	*
3656	* @param pPool The pool.
3657	* @param pPage The page.
3658	* @param pShwPDPT The shadow page directory pointer table (mapping of the page).
3659	*/
3660	DECLINLINE(void) pgmPoolTrackDerefPDPTEPT(PPGMPOOL pPool, PPGMPOOLPAGE pPage, PEPTPDPT pShwPDPT)
3661	{
3662	for (unsigned i = 0; i < RT_ELEMENTS(pShwPDPT->a); i++)
3663	{
3664	if (pShwPDPT->a[i].n.u1Present)
3665	{
3666	PPGMPOOLPAGE pSubPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK);
3667	if (pSubPage)
3668	pgmPoolTrackFreeUser(pPool, pSubPage, pPage->idx, i);
3669	else
3670	AssertFatalMsgFailed(("%RX64\n", pShwPDPT->a[i].u & EPT_PDPTE_PG_MASK));
3671	/** @todo 64-bit guests: have to ensure that we're not exhausting the dynamic mappings! */
3672	}
3673	}
3674	}
3675
3676
3677	/**
3678	* Clears all references made by this page.
3679	*
3680	* This includes other shadow pages and GC physical addresses.
3681	*
3682	* @param pPool The pool.
3683	* @param pPage The page.
3684	*/
3685	static void pgmPoolTrackDeref(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3686	{
3687	/*
3688	* Map the shadow page and take action according to the page kind.
3689	*/
3690	void *pvShw = PGMPOOL_PAGE_2_LOCKED_PTR(pPool->CTX_SUFF(pVM), pPage);
3691	switch (pPage->enmKind)
3692	{
3693	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
3694	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3695	{
3696	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3697	void *pvGst;
3698	int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3699	pgmPoolTrackDerefPT32Bit32Bit(pPool, pPage, (PX86PT)pvShw, (PCX86PT)pvGst);
3700	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3701	break;
3702	}
3703
3704	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3705	{
3706	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3707	void *pvGst;
3708	int rc = PGM_GCPHYS_2_PTR_EX(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3709	pgmPoolTrackDerefPTPae32Bit(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PT)pvGst);
3710	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3711	break;
3712	}
3713
3714	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3715	{
3716	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3717	void *pvGst;
3718	int rc = PGM_GCPHYS_2_PTR(pPool->CTX_SUFF(pVM), pPage->GCPhys, &pvGst); AssertReleaseRC(rc);
3719	pgmPoolTrackDerefPTPaePae(pPool, pPage, (PX86PTPAE)pvShw, (PCX86PTPAE)pvGst);
3720	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3721	break;
3722	}
3723
3724	case PGMPOOLKIND_32BIT_PT_FOR_PHYS: /* treat it like a 4 MB page */
3725	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3726	{
3727	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3728	pgmPoolTrackDerefPT32Bit4MB(pPool, pPage, (PX86PT)pvShw);
3729	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3730	break;
3731	}
3732
3733	case PGMPOOLKIND_PAE_PT_FOR_PHYS: /* treat it like a 2 MB page */
3734	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3735	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3736	{
3737	STAM_PROFILE_START(&pPool->StatTrackDerefGCPhys, g);
3738	pgmPoolTrackDerefPTPaeBig(pPool, pPage, (PX86PTPAE)pvShw);
3739	STAM_PROFILE_STOP(&pPool->StatTrackDerefGCPhys, g);
3740	break;
3741	}
3742
3743	#else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
3744	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
3745	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
3746	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
3747	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
3748	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
3749	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
3750	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
3751	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
3752	break;
3753	#endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
3754
3755	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
3756	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
3757	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
3758	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
3759	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
3760	case PGMPOOLKIND_PAE_PD_PHYS:
3761	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
3762	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
3763	pgmPoolTrackDerefPDPae(pPool, pPage, (PX86PDPAE)pvShw);
3764	break;
3765
3766	case PGMPOOLKIND_32BIT_PD_PHYS:
3767	case PGMPOOLKIND_32BIT_PD:
3768	pgmPoolTrackDerefPD(pPool, pPage, (PX86PD)pvShw);
3769	break;
3770
3771	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
3772	case PGMPOOLKIND_PAE_PDPT:
3773	case PGMPOOLKIND_PAE_PDPT_PHYS:
3774	pgmPoolTrackDerefPDPTPae(pPool, pPage, (PX86PDPT)pvShw);
3775	break;
3776
3777	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
3778	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
3779	pgmPoolTrackDerefPDPT64Bit(pPool, pPage, (PX86PDPT)pvShw);
3780	break;
3781
3782	case PGMPOOLKIND_64BIT_PML4:
3783	pgmPoolTrackDerefPML464Bit(pPool, pPage, (PX86PML4)pvShw);
3784	break;
3785
3786	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
3787	pgmPoolTrackDerefPTEPT(pPool, pPage, (PEPTPT)pvShw);
3788	break;
3789
3790	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
3791	pgmPoolTrackDerefPDEPT(pPool, pPage, (PEPTPD)pvShw);
3792	break;
3793
3794	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
3795	pgmPoolTrackDerefPDPTEPT(pPool, pPage, (PEPTPDPT)pvShw);
3796	break;
3797
3798	default:
3799	AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
3800	}
3801
3802	/* paranoia, clear the shadow page. Remove this laser (i.e. let Alloc and ClearAll do it). */
3803	STAM_PROFILE_START(&pPool->StatZeroPage, z);
3804	ASMMemZeroPage(pvShw);
3805	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
3806	pPage->fZeroed = true;
3807	PGMPOOL_UNLOCK_PTR(pPool->CTX_SUFF(pVM), pvShw);
3808	}
3809	#endif /* PGMPOOL_WITH_USER_TRACKING */
3810
3811	/**
3812	* Flushes a pool page.
3813	*
3814	* This moves the page to the free list after removing all user references to it.
3815	*
3816	* @returns VBox status code.
3817	* @retval VINF_SUCCESS on success.
3818	* @param pPool The pool.
3819	* @param HCPhys The HC physical address of the shadow page.
3820	*/
3821	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3822	{
3823	PVM pVM = pPool->CTX_SUFF(pVM);
3824
3825	int rc = VINF_SUCCESS;
3826	STAM_PROFILE_START(&pPool->StatFlushPage, f);
3827	LogFlow(("pgmPoolFlushPage: pPage=%p:{.Key=%RHp, .idx=%d, .enmKind=%s, .GCPhys=%RGp}\n",
3828	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), pPage->GCPhys));
3829
3830	/*
3831	* Quietly reject any attempts at flushing any of the special root pages.
3832	*/
3833	if (pPage->idx < PGMPOOL_IDX_FIRST)
3834	{
3835	AssertFailed(); /* can no longer happen */
3836	Log(("pgmPoolFlushPage: special root page, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
3837	return VINF_SUCCESS;
3838	}
3839
3840	pgmLock(pVM);
3841
3842	/*
3843	* Quietly reject any attempts at flushing the currently active shadow CR3 mapping
3844	*/
3845	if (pgmPoolIsPageLocked(&pVM->pgm.s, pPage))
3846	{
3847	AssertMsg( pPage->enmKind == PGMPOOLKIND_64BIT_PML4
3848	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT
3849	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PDPT_FOR_32BIT
3850	\|\| pPage->enmKind == PGMPOOLKIND_32BIT_PD
3851	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD_FOR_PAE_PD
3852	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD
3853	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD
3854	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD
3855	\|\| pPage->enmKind == PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
3856	("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(VMMGetCpu(pVM)), pPage->Core.Key, pPage->enmKind));
3857	Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
3858	pgmUnlock(pVM);
3859	return VINF_SUCCESS;
3860	}
3861
3862	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3863	/* Start a subset so we won't run out of mapping space. */
3864	PVMCPU pVCpu = VMMGetCpu(pVM);
3865	uint32_t iPrevSubset = PGMDynMapPushAutoSubset(pVCpu);
3866	#endif
3867
3868	/*
3869	* Mark the page as being in need of a ASMMemZeroPage().
3870	*/
3871	pPage->fZeroed = false;
3872
3873	#ifdef PGMPOOL_WITH_USER_TRACKING
3874	/*
3875	* Clear the page.
3876	*/
3877	pgmPoolTrackClearPageUsers(pPool, pPage);
3878	STAM_PROFILE_START(&pPool->StatTrackDeref,a);
3879	pgmPoolTrackDeref(pPool, pPage);
3880	STAM_PROFILE_STOP(&pPool->StatTrackDeref,a);
3881	#endif
3882
3883	#ifdef PGMPOOL_WITH_CACHE
3884	/*
3885	* Flush it from the cache.
3886	*/
3887	pgmPoolCacheFlushPage(pPool, pPage);
3888	#endif /* PGMPOOL_WITH_CACHE */
3889
3890	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
3891	/* Heavy stuff done. */
3892	PGMDynMapPopAutoSubset(pVCpu, iPrevSubset);
3893	#endif
3894
3895	#ifdef PGMPOOL_WITH_MONITORING
3896	/*
3897	* Deregistering the monitoring.
3898	*/
3899	if (pPage->fMonitored)
3900	rc = pgmPoolMonitorFlush(pPool, pPage);
3901	#endif
3902
3903	/*
3904	* Free the page.
3905	*/
3906	Assert(pPage->iNext == NIL_PGMPOOL_IDX);
3907	pPage->iNext = pPool->iFreeHead;
3908	pPool->iFreeHead = pPage->idx;
3909	pPage->enmKind = PGMPOOLKIND_FREE;
3910	pPage->GCPhys = NIL_RTGCPHYS;
3911	pPage->fReusedFlushPending = false;
3912
3913	pPool->cUsedPages--;
3914	pgmUnlock(pVM);
3915	STAM_PROFILE_STOP(&pPool->StatFlushPage, f);
3916	return rc;
3917	}
3918
3919
3920	/**
3921	* Frees a usage of a pool page.
3922	*
3923	* The caller is responsible to updating the user table so that it no longer
3924	* references the shadow page.
3925	*
3926	* @param pPool The pool.
3927	* @param HCPhys The HC physical address of the shadow page.
3928	* @param iUser The shadow page pool index of the user table.
3929	* @param iUserTable The index into the user table (shadowed).
3930	*/
3931	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable)
3932	{
3933	PVM pVM = pPool->CTX_SUFF(pVM);
3934
3935	STAM_PROFILE_START(&pPool->StatFree, a);
3936	LogFlow(("pgmPoolFreeByPage: pPage=%p:{.Key=%RHp, .idx=%d, enmKind=%s} iUser=%#x iUserTable=%#x\n",
3937	pPage, pPage->Core.Key, pPage->idx, pgmPoolPoolKindToStr(pPage->enmKind), iUser, iUserTable));
3938	Assert(pPage->idx >= PGMPOOL_IDX_FIRST);
3939	pgmLock(pVM);
3940	#ifdef PGMPOOL_WITH_USER_TRACKING
3941	pgmPoolTrackFreeUser(pPool, pPage, iUser, iUserTable);
3942	#endif
3943	#ifdef PGMPOOL_WITH_CACHE
3944	if (!pPage->fCached)
3945	#endif
3946	pgmPoolFlushPage(pPool, pPage);
3947	pgmUnlock(pVM);
3948	STAM_PROFILE_STOP(&pPool->StatFree, a);
3949	}
3950
3951
3952	/**
3953	* Makes one or more free page free.
3954	*
3955	* @returns VBox status code.
3956	* @retval VINF_SUCCESS on success.
3957	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
3958	*
3959	* @param pPool The pool.
3960	* @param enmKind Page table kind
3961	* @param iUser The user of the page.
3962	*/
3963	static int pgmPoolMakeMoreFreePages(PPGMPOOL pPool, PGMPOOLKIND enmKind, uint16_t iUser)
3964	{
3965	LogFlow(("pgmPoolMakeMoreFreePages: iUser=%#x\n", iUser));
3966
3967	/*
3968	* If the pool isn't full grown yet, expand it.
3969	*/
3970	if ( pPool->cCurPages < pPool->cMaxPages
3971	#if defined(IN_RC)
3972	/* Hack alert: we can't deal with jumps to ring 3 when called from MapCR3 and allocating pages for PAE PDs. */
3973	&& enmKind != PGMPOOLKIND_PAE_PD_FOR_PAE_PD
3974	&& (enmKind < PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD \|\| enmKind > PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD)
3975	#endif
3976	)
3977	{
3978	STAM_PROFILE_ADV_SUSPEND(&pPool->StatAlloc, a);
3979	#ifdef IN_RING3
3980	int rc = PGMR3PoolGrow(pPool->pVMR3);
3981	#else
3982	int rc = CTXALLMID(VMM, CallHost)(pPool->CTX_SUFF(pVM), VMMCALLHOST_PGM_POOL_GROW, 0);
3983	#endif
3984	if (RT_FAILURE(rc))
3985	return rc;
3986	STAM_PROFILE_ADV_RESUME(&pPool->StatAlloc, a);
3987	if (pPool->iFreeHead != NIL_PGMPOOL_IDX)
3988	return VINF_SUCCESS;
3989	}
3990
3991	#ifdef PGMPOOL_WITH_CACHE
3992	/*
3993	* Free one cached page.
3994	*/
3995	return pgmPoolCacheFreeOne(pPool, iUser);
3996	#else
3997	/*
3998	* Flush the pool.
3999	*
4000	* If we have tracking enabled, it should be possible to come up with
4001	* a cheap replacement strategy...
4002	*/
4003	/* @todo This path no longer works (CR3 root pages will be flushed)!! */
4004	AssertCompileFailed();
4005	Assert(!CPUMIsGuestInLongMode(pVM));
4006	pgmPoolFlushAllInt(pPool);
4007	return VERR_PGM_POOL_FLUSHED;
4008	#endif
4009	}
4010
4011
4012	/**
4013	* Allocates a page from the pool.
4014	*
4015	* This page may actually be a cached page and not in need of any processing
4016	* on the callers part.
4017	*
4018	* @returns VBox status code.
4019	* @retval VINF_SUCCESS if a NEW page was allocated.
4020	* @retval VINF_PGM_CACHED_PAGE if a CACHED page was returned.
4021	* @retval VERR_PGM_POOL_FLUSHED if the pool was flushed.
4022	* @param pVM The VM handle.
4023	* @param GCPhys The GC physical address of the page we're gonna shadow.
4024	* For 4MB and 2MB PD entries, it's the first address the
4025	* shadow PT is covering.
4026	* @param enmKind The kind of mapping.
4027	* @param iUser The shadow page pool index of the user table.
4028	* @param iUserTable The index into the user table (shadowed).
4029	* @param ppPage Where to store the pointer to the page. NULL is stored here on failure.
4030	*/
4031	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable, PPPGMPOOLPAGE ppPage)
4032	{
4033	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4034	STAM_PROFILE_ADV_START(&pPool->StatAlloc, a);
4035	LogFlow(("pgmPoolAlloc: GCPhys=%RGp enmKind=%s iUser=%#x iUserTable=%#x\n", GCPhys, pgmPoolPoolKindToStr(enmKind), iUser, iUserTable));
4036	*ppPage = NULL;
4037	/** @todo CSAM/PGMPrefetchPage messes up here during CSAMR3CheckGates
4038	* (TRPMR3SyncIDT) because of FF priority. Try fix that?
4039	* Assert(!(pVM->pgm.s.fGlobalSyncFlags & PGM_GLOBAL_SYNC_CLEAR_PGM_POOL)); */
4040
4041	pgmLock(pVM);
4042
4043	#ifdef PGMPOOL_WITH_CACHE
4044	if (pPool->fCacheEnabled)
4045	{
4046	int rc2 = pgmPoolCacheAlloc(pPool, GCPhys, enmKind, iUser, iUserTable, ppPage);
4047	if (RT_SUCCESS(rc2))
4048	{
4049	pgmUnlock(pVM);
4050	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4051	LogFlow(("pgmPoolAlloc: cached returns %Rrc ppPage=%p:{.Key=%RHp, .idx=%d}\n", rc2, ppPage, (ppPage)->Core.Key, (ppPage)->idx));
4052	return rc2;
4053	}
4054	}
4055	#endif
4056
4057	/*
4058	* Allocate a new one.
4059	*/
4060	int rc = VINF_SUCCESS;
4061	uint16_t iNew = pPool->iFreeHead;
4062	if (iNew == NIL_PGMPOOL_IDX)
4063	{
4064	rc = pgmPoolMakeMoreFreePages(pPool, enmKind, iUser);
4065	if (RT_FAILURE(rc))
4066	{
4067	pgmUnlock(pVM);
4068	Log(("pgmPoolAlloc: returns %Rrc (Free)\n", rc));
4069	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4070	return rc;
4071	}
4072	iNew = pPool->iFreeHead;
4073	AssertReleaseReturn(iNew != NIL_PGMPOOL_IDX, VERR_INTERNAL_ERROR);
4074	}
4075
4076	/* unlink the free head */
4077	PPGMPOOLPAGE pPage = &pPool->aPages[iNew];
4078	pPool->iFreeHead = pPage->iNext;
4079	pPage->iNext = NIL_PGMPOOL_IDX;
4080
4081	/*
4082	* Initialize it.
4083	*/
4084	pPool->cUsedPages++; /* physical handler registration / pgmPoolTrackFlushGCPhysPTsSlow requirement. */
4085	pPage->enmKind = enmKind;
4086	pPage->GCPhys = GCPhys;
4087	pPage->fSeenNonGlobal = false; /* Set this to 'true' to disable this feature. */
4088	pPage->fMonitored = false;
4089	pPage->fCached = false;
4090	pPage->fReusedFlushPending = false;
4091	#ifdef PGMPOOL_WITH_MONITORING
4092	pPage->cModifications = 0;
4093	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4094	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4095	#else
4096	pPage->fCR3Mix = false;
4097	#endif
4098	#ifdef PGMPOOL_WITH_USER_TRACKING
4099	pPage->cPresent = 0;
4100	pPage->iFirstPresent = ~0;
4101
4102	/*
4103	* Insert into the tracking and cache. If this fails, free the page.
4104	*/
4105	int rc3 = pgmPoolTrackInsert(pPool, pPage, GCPhys, iUser, iUserTable);
4106	if (RT_FAILURE(rc3))
4107	{
4108	pPool->cUsedPages--;
4109	pPage->enmKind = PGMPOOLKIND_FREE;
4110	pPage->GCPhys = NIL_RTGCPHYS;
4111	pPage->iNext = pPool->iFreeHead;
4112	pPool->iFreeHead = pPage->idx;
4113	pgmUnlock(pVM);
4114	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4115	Log(("pgmPoolAlloc: returns %Rrc (Insert)\n", rc3));
4116	return rc3;
4117	}
4118	#endif /* PGMPOOL_WITH_USER_TRACKING */
4119
4120	/*
4121	* Commit the allocation, clear the page and return.
4122	*/
4123	#ifdef VBOX_WITH_STATISTICS
4124	if (pPool->cUsedPages > pPool->cUsedPagesHigh)
4125	pPool->cUsedPagesHigh = pPool->cUsedPages;
4126	#endif
4127
4128	if (!pPage->fZeroed)
4129	{
4130	STAM_PROFILE_START(&pPool->StatZeroPage, z);
4131	void *pv = PGMPOOL_PAGE_2_PTR(pVM, pPage);
4132	ASMMemZeroPage(pv);
4133	STAM_PROFILE_STOP(&pPool->StatZeroPage, z);
4134	}
4135
4136	*ppPage = pPage;
4137	pgmUnlock(pVM);
4138	LogFlow(("pgmPoolAlloc: returns %Rrc *ppPage=%p:{.Key=%RHp, .idx=%d, .fCached=%RTbool, .fMonitored=%RTbool}\n",
4139	rc, pPage, pPage->Core.Key, pPage->idx, pPage->fCached, pPage->fMonitored));
4140	STAM_PROFILE_ADV_STOP(&pPool->StatAlloc, a);
4141	return rc;
4142	}
4143
4144
4145	/**
4146	* Frees a usage of a pool page.
4147	*
4148	* @param pVM The VM handle.
4149	* @param HCPhys The HC physical address of the shadow page.
4150	* @param iUser The shadow page pool index of the user table.
4151	* @param iUserTable The index into the user table (shadowed).
4152	*/
4153	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable)
4154	{
4155	LogFlow(("pgmPoolFree: HCPhys=%RHp iUser=%#x iUserTable=%#x\n", HCPhys, iUser, iUserTable));
4156	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4157	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, HCPhys), iUser, iUserTable);
4158	}
4159
4160	/**
4161	* Internal worker for finding a 'in-use' shadow page give by it's physical address.
4162	*
4163	* @returns Pointer to the shadow page structure.
4164	* @param pPool The pool.
4165	* @param HCPhys The HC physical address of the shadow page.
4166	*/
4167	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys)
4168	{
4169	PVM pVM = pPool->CTX_SUFF(pVM);
4170
4171	/*
4172	* Look up the page.
4173	*/
4174	pgmLock(pVM);
4175	PPGMPOOLPAGE pPage = (PPGMPOOLPAGE)RTAvloHCPhysGet(&pPool->HCPhysTree, HCPhys & X86_PTE_PAE_PG_MASK);
4176	pgmUnlock(pVM);
4177
4178	AssertFatalMsg(pPage && pPage->enmKind != PGMPOOLKIND_FREE, ("HCPhys=%RHp pPage=%p idx=%d\n", HCPhys, pPage, (pPage) ? pPage->idx : 0));
4179	return pPage;
4180	}
4181
4182
4183	#ifdef IN_RING3
4184	/**
4185	* Flushes the entire cache.
4186	*
4187	* It will assert a global CR3 flush (FF) and assumes the caller is aware of this
4188	* and execute this CR3 flush.
4189	*
4190	* @param pPool The pool.
4191	*/
4192	void pgmR3PoolReset(PVM pVM)
4193	{
4194	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4195
4196	Assert(PGMIsLockOwner(pVM));
4197	STAM_PROFILE_START(&pPool->StatFlushAllInt, a);
4198	LogFlow(("pgmPoolFlushAllInt:\n"));
4199
4200	/*
4201	* If there are no pages in the pool, there is nothing to do.
4202	*/
4203	if (pPool->cCurPages <= PGMPOOL_IDX_FIRST)
4204	{
4205	STAM_PROFILE_STOP(&pPool->StatFlushAllInt, a);
4206	return;
4207	}
4208
4209	/*
4210	* Exit the shadow mode since we're going to clear everything,
4211	* including the root page.
4212	*/
4213	for (unsigned i=0;i<pVM->cCPUs;i++)
4214	{
4215	PVMCPU pVCpu = &pVM->aCpus[i];
4216	pgmR3ExitShadowModeBeforePoolFlush(pVM, pVCpu);
4217	}
4218
4219	/*
4220	* Nuke the free list and reinsert all pages into it.
4221	*/
4222	for (unsigned i = pPool->cCurPages - 1; i >= PGMPOOL_IDX_FIRST; i--)
4223	{
4224	PPGMPOOLPAGE pPage = &pPool->aPages[i];
4225
4226	Assert(pPage->Core.Key == MMPage2Phys(pVM, pPage->pvPageR3));
4227	#ifdef PGMPOOL_WITH_MONITORING
4228	if (pPage->fMonitored)
4229	pgmPoolMonitorFlush(pPool, pPage);
4230	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4231	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4232	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
4233	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
4234	pPage->cModifications = 0;
4235	#endif
4236	pPage->GCPhys = NIL_RTGCPHYS;
4237	pPage->enmKind = PGMPOOLKIND_FREE;
4238	Assert(pPage->idx == i);
4239	pPage->iNext = i + 1;
4240	pPage->fZeroed = false; /* This could probably be optimized, but better safe than sorry. */
4241	pPage->fSeenNonGlobal = false;
4242	pPage->fMonitored= false;
4243	pPage->fCached = false;
4244	pPage->fReusedFlushPending = false;
4245	#ifdef PGMPOOL_WITH_USER_TRACKING
4246	pPage->iUserHead = NIL_PGMPOOL_USER_INDEX;
4247	#else
4248	pPage->fCR3Mix = false;
4249	#endif
4250	#ifdef PGMPOOL_WITH_CACHE
4251	pPage->iAgeNext = NIL_PGMPOOL_IDX;
4252	pPage->iAgePrev = NIL_PGMPOOL_IDX;
4253	#endif
4254	pPage->cLocked = 0;
4255	}
4256	pPool->aPages[pPool->cCurPages - 1].iNext = NIL_PGMPOOL_IDX;
4257	pPool->iFreeHead = PGMPOOL_IDX_FIRST;
4258	pPool->cUsedPages = 0;
4259
4260	#ifdef PGMPOOL_WITH_USER_TRACKING
4261	/*
4262	* Zap and reinitialize the user records.
4263	*/
4264	pPool->cPresent = 0;
4265	pPool->iUserFreeHead = 0;
4266	PPGMPOOLUSER paUsers = pPool->CTX_SUFF(paUsers);
4267	const unsigned cMaxUsers = pPool->cMaxUsers;
4268	for (unsigned i = 0; i < cMaxUsers; i++)
4269	{
4270	paUsers[i].iNext = i + 1;
4271	paUsers[i].iUser = NIL_PGMPOOL_IDX;
4272	paUsers[i].iUserTable = 0xfffffffe;
4273	}
4274	paUsers[cMaxUsers - 1].iNext = NIL_PGMPOOL_USER_INDEX;
4275	#endif
4276
4277	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
4278	/*
4279	* Clear all the GCPhys links and rebuild the phys ext free list.
4280	*/
4281	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
4282	pRam;
4283	pRam = pRam->CTX_SUFF(pNext))
4284	{
4285	unsigned iPage = pRam->cb >> PAGE_SHIFT;
4286	while (iPage-- > 0)
4287	PGM_PAGE_SET_TRACKING(&pRam->aPages[iPage], 0);
4288	}
4289
4290	pPool->iPhysExtFreeHead = 0;
4291	PPGMPOOLPHYSEXT paPhysExts = pPool->CTX_SUFF(paPhysExts);
4292	const unsigned cMaxPhysExts = pPool->cMaxPhysExts;
4293	for (unsigned i = 0; i < cMaxPhysExts; i++)
4294	{
4295	paPhysExts[i].iNext = i + 1;
4296	paPhysExts[i].aidx[0] = NIL_PGMPOOL_IDX;
4297	paPhysExts[i].aidx[1] = NIL_PGMPOOL_IDX;
4298	paPhysExts[i].aidx[2] = NIL_PGMPOOL_IDX;
4299	}
4300	paPhysExts[cMaxPhysExts - 1].iNext = NIL_PGMPOOL_PHYSEXT_INDEX;
4301	#endif
4302
4303	#ifdef PGMPOOL_WITH_MONITORING
4304	/*
4305	* Just zap the modified list.
4306	*/
4307	pPool->cModifiedPages = 0;
4308	pPool->iModifiedHead = NIL_PGMPOOL_IDX;
4309	#endif
4310
4311	#ifdef PGMPOOL_WITH_CACHE
4312	/*
4313	* Clear the GCPhys hash and the age list.
4314	*/
4315	for (unsigned i = 0; i < RT_ELEMENTS(pPool->aiHash); i++)
4316	pPool->aiHash[i] = NIL_PGMPOOL_IDX;
4317	pPool->iAgeHead = NIL_PGMPOOL_IDX;
4318	pPool->iAgeTail = NIL_PGMPOOL_IDX;
4319	#endif
4320
4321	/*
4322	* Reinsert active pages into the hash and ensure monitoring chains are correct.
4323	*/
4324	for (unsigned i = PGMPOOL_IDX_FIRST_SPECIAL; i < PGMPOOL_IDX_FIRST; i++)
4325	{
4326	PPGMPOOLPAGE pPage = &pPool->aPages[i];
4327	pPage->iNext = NIL_PGMPOOL_IDX;
4328	#ifdef PGMPOOL_WITH_MONITORING
4329	pPage->iModifiedNext = NIL_PGMPOOL_IDX;
4330	pPage->iModifiedPrev = NIL_PGMPOOL_IDX;
4331	pPage->cModifications = 0;
4332	/* ASSUMES that we're not sharing with any of the other special pages (safe for now). */
4333	pPage->iMonitoredNext = NIL_PGMPOOL_IDX;
4334	pPage->iMonitoredPrev = NIL_PGMPOOL_IDX;
4335	if (pPage->fMonitored)
4336	{
4337	int rc = PGMHandlerPhysicalChangeCallbacks(pVM, pPage->GCPhys & ~(RTGCPHYS)(PAGE_SIZE - 1),
4338	pPool->pfnAccessHandlerR3, MMHyperCCToR3(pVM, pPage),
4339	pPool->pfnAccessHandlerR0, MMHyperCCToR0(pVM, pPage),
4340	pPool->pfnAccessHandlerRC, MMHyperCCToRC(pVM, pPage),
4341	pPool->pszAccessHandler);
4342	AssertFatalRCSuccess(rc);
4343	# ifdef PGMPOOL_WITH_CACHE
4344	pgmPoolHashInsert(pPool, pPage);
4345	# endif
4346	}
4347	#endif
4348	#ifdef PGMPOOL_WITH_USER_TRACKING
4349	Assert(pPage->iUserHead == NIL_PGMPOOL_USER_INDEX); /* for now */
4350	#endif
4351	#ifdef PGMPOOL_WITH_CACHE
4352	Assert(pPage->iAgeNext == NIL_PGMPOOL_IDX);
4353	Assert(pPage->iAgePrev == NIL_PGMPOOL_IDX);
4354	#endif
4355	}
4356
4357	for (unsigned i=0;i<pVM->cCPUs;i++)
4358	{
4359	PVMCPU pVCpu = &pVM->aCpus[i];
4360	/*
4361	* Re-enter the shadowing mode and assert Sync CR3 FF.
4362	*/
4363	pgmR3ReEnterShadowModeAfterPoolFlush(pVM, pVCpu);
4364	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4365	}
4366
4367	STAM_PROFILE_STOP(&pPool->StatFlushAllInt, a);
4368	}
4369	#endif /* IN_RING3 */
4370
4371	#ifdef LOG_ENABLED
4372	static const char *pgmPoolPoolKindToStr(uint8_t enmKind)
4373	{
4374	switch(enmKind)
4375	{
4376	case PGMPOOLKIND_INVALID:
4377	return "PGMPOOLKIND_INVALID";
4378	case PGMPOOLKIND_FREE:
4379	return "PGMPOOLKIND_FREE";
4380	case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
4381	return "PGMPOOLKIND_32BIT_PT_FOR_PHYS";
4382	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT:
4383	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT";
4384	case PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB:
4385	return "PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB";
4386	case PGMPOOLKIND_PAE_PT_FOR_PHYS:
4387	return "PGMPOOLKIND_PAE_PT_FOR_PHYS";
4388	case PGMPOOLKIND_PAE_PT_FOR_32BIT_PT:
4389	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_PT";
4390	case PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB:
4391	return "PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB";
4392	case PGMPOOLKIND_PAE_PT_FOR_PAE_PT:
4393	return "PGMPOOLKIND_PAE_PT_FOR_PAE_PT";
4394	case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
4395	return "PGMPOOLKIND_PAE_PT_FOR_PAE_2MB";
4396	case PGMPOOLKIND_32BIT_PD:
4397	return "PGMPOOLKIND_32BIT_PD";
4398	case PGMPOOLKIND_32BIT_PD_PHYS:
4399	return "PGMPOOLKIND_32BIT_PD_PHYS";
4400	case PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD:
4401	return "PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD";
4402	case PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD:
4403	return "PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD";
4404	case PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD:
4405	return "PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD";
4406	case PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD:
4407	return "PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD";
4408	case PGMPOOLKIND_PAE_PD_FOR_PAE_PD:
4409	return "PGMPOOLKIND_PAE_PD_FOR_PAE_PD";
4410	case PGMPOOLKIND_PAE_PD_PHYS:
4411	return "PGMPOOLKIND_PAE_PD_PHYS";
4412	case PGMPOOLKIND_PAE_PDPT_FOR_32BIT:
4413	return "PGMPOOLKIND_PAE_PDPT_FOR_32BIT";
4414	case PGMPOOLKIND_PAE_PDPT:
4415	return "PGMPOOLKIND_PAE_PDPT";
4416	case PGMPOOLKIND_PAE_PDPT_PHYS:
4417	return "PGMPOOLKIND_PAE_PDPT_PHYS";
4418	case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
4419	return "PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT";
4420	case PGMPOOLKIND_64BIT_PDPT_FOR_PHYS:
4421	return "PGMPOOLKIND_64BIT_PDPT_FOR_PHYS";
4422	case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
4423	return "PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD";
4424	case PGMPOOLKIND_64BIT_PD_FOR_PHYS:
4425	return "PGMPOOLKIND_64BIT_PD_FOR_PHYS";
4426	case PGMPOOLKIND_64BIT_PML4:
4427	return "PGMPOOLKIND_64BIT_PML4";
4428	case PGMPOOLKIND_EPT_PDPT_FOR_PHYS:
4429	return "PGMPOOLKIND_EPT_PDPT_FOR_PHYS";
4430	case PGMPOOLKIND_EPT_PD_FOR_PHYS:
4431	return "PGMPOOLKIND_EPT_PD_FOR_PHYS";
4432	case PGMPOOLKIND_EPT_PT_FOR_PHYS:
4433	return "PGMPOOLKIND_EPT_PT_FOR_PHYS";
4434	case PGMPOOLKIND_ROOT_NESTED:
4435	return "PGMPOOLKIND_ROOT_NESTED";
4436	}
4437	return "Unknown kind!";
4438	}
4439	#endif /* LOG_ENABLED*/

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp@ 19872

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