VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 15218

Last change on this file since 15218 was 15218, checked in by vboxsync, 16 years ago

HWACCM: some temporary profiling of sub-parts of SwitchFromGC_2.
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1/* $Id: HWACCM.cpp 15218 2008-12-10 00:23:49Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.215389.xyz. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdm.h>
30#include <VBox/pgm.h>
31#include <VBox/trpm.h>
32#include <VBox/dbgf.h>
33#include <VBox/patm.h>
34#include <VBox/csam.h>
35#include <VBox/selm.h>
36#include <VBox/rem.h>
37#include <VBox/hwacc_vmx.h>
38#include <VBox/hwacc_svm.h>
39#include "HWACCMInternal.h"
40#include <VBox/vm.h>
41#include <VBox/err.h>
42#include <VBox/param.h>
43
44#include <iprt/assert.h>
45#include <VBox/log.h>
46#include <iprt/asm.h>
47#include <iprt/string.h>
48#include <iprt/thread.h>
49
50/*******************************************************************************
51* Global Variables *
52*******************************************************************************/
53#ifdef VBOX_WITH_STATISTICS
54# define EXIT_REASON(def, val, str) #def " - " #val " - " str
55# define EXIT_REASON_NIL() NULL
56/** Exit reason descriptions for VT-x, used to describe statistics. */
57static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
58{
59 EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
60 EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
61 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
62 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
63 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
64 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
65 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
66 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
67 EXIT_REASON_NIL(),
68 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
69 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
70 EXIT_REASON_NIL(),
71 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
72 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
73 EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
74 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
75 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
76 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
77 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
78 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
79 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
80 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
81 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
82 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
83 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
84 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
85 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
86 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
87 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
88 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
89 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
90 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
91 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
92 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
93 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
94 EXIT_REASON_NIL(),
95 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
96 EXIT_REASON_NIL(),
97 EXIT_REASON_NIL(),
98 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
99 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
100 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
101 EXIT_REASON_NIL(),
102 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
103 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
104 EXIT_REASON_NIL(),
105 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
106 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
107 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
108 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
109 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
110 EXIT_REASON_NIL(),
111 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
112 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
113 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
114 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
115 EXIT_REASON_NIL()
116};
117/** Exit reason descriptions for AMD-V, used to describe statistics. */
118static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
119{
120 /** @todo fill in these. */
121 EXIT_REASON_NIL()
122};
123# undef EXIT_REASON
124# undef EXIT_REASON_NIL
125#endif /* VBOX_WITH_STATISTICS */
126
127/*******************************************************************************
128* Internal Functions *
129*******************************************************************************/
130static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
131static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
132
133
134/**
135 * Initializes the HWACCM.
136 *
137 * @returns VBox status code.
138 * @param pVM The VM to operate on.
139 */
140VMMR3DECL(int) HWACCMR3Init(PVM pVM)
141{
142 LogFlow(("HWACCMR3Init\n"));
143
144 /*
145 * Assert alignment and sizes.
146 */
147 AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
148 AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
149
150 /* Some structure checks. */
151 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
152 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
153 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
154 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
155
156 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
157 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
158 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
159 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
160 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
161 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
162 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
163
164
165 /*
166 * Register the saved state data unit.
167 */
168 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
169 NULL, hwaccmR3Save, NULL,
170 NULL, hwaccmR3Load, NULL);
171 if (RT_FAILURE(rc))
172 return rc;
173
174 /* Misc initialisation. */
175 pVM->hwaccm.s.vmx.fSupported = false;
176 pVM->hwaccm.s.svm.fSupported = false;
177 pVM->hwaccm.s.vmx.fEnabled = false;
178 pVM->hwaccm.s.svm.fEnabled = false;
179
180 pVM->hwaccm.s.fActive = false;
181 pVM->hwaccm.s.fNestedPaging = false;
182
183 /* Disabled by default. */
184 pVM->fHWACCMEnabled = false;
185
186 /*
187 * Check CFGM options.
188 */
189 /* Nested paging: disabled by default. */
190 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
191 AssertRC(rc);
192
193 /* VT-x VPID: disabled by default. */
194 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
195 AssertRC(rc);
196
197 /* HWACCM support must be explicitely enabled in the configuration file. */
198 rc = CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed, false);
199 AssertRC(rc);
200
201#ifdef RT_OS_DARWIN
202 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
203#else
204 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
205#endif
206 {
207 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
208 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
209 return VERR_HWACCM_CONFIG_MISMATCH;
210 }
211
212 if (VMMIsHwVirtExtForced(pVM))
213 pVM->fHWACCMEnabled = true;
214
215 return VINF_SUCCESS;
216}
217
218/**
219 * Initializes the per-VCPU HWACCM.
220 *
221 * @returns VBox status code.
222 * @param pVM The VM to operate on.
223 */
224VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
225{
226 LogFlow(("HWACCMR3InitCPU\n"));
227
228#ifdef VBOX_WITH_STATISTICS
229 /*
230 * Statistics.
231 */
232 for (unsigned i=0;i<pVM->cCPUs;i++)
233 {
234 PVMCPU pVCpu = &pVM->aCpus[i];
235 int rc;
236
237 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
238 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
239 AssertRC(rc);
240 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
241 "/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
242 AssertRC(rc);
243 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
244 "/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
245 AssertRC(rc);
246# if 1 /* temporary for tracking down darwin holdup. */
247 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
248 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
249 AssertRC(rc);
250 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
251 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
252 AssertRC(rc);
253 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
254 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
255 AssertRC(rc);
256# endif
257 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
258 "/PROF/HWACCM/CPU%d/InGC", i);
259 AssertRC(rc);
260
261# define HWACCM_REG_COUNTER(a, b) \
262 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
263 AssertRC(rc);
264
265 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
266 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
267 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
268 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
269 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
270 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
271 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
272 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
273 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
274 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
275 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
276 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
277 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
278 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
279 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
280 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
281 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
282 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
283 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
284 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
285 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
286 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
287 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
288 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
289 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
290
291 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
292 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
293
294 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
295 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
296 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
297
298 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
299 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
300 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
301 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
302 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
303 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
304 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
305 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
306 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
307
308 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
309 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
310
311 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
312 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
313 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
314
315 for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
316 {
317 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
318 "/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
319 AssertRC(rc);
320 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
321 "/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
322 AssertRC(rc);
323 }
324
325#undef HWACCM_REG_COUNTER
326
327 pVCpu->hwaccm.s.paStatExitReason = NULL;
328
329 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
330 AssertRC(rc);
331 if (RT_SUCCESS(rc))
332 {
333 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
334 for (int j=0;j<MAX_EXITREASON_STAT;j++)
335 {
336 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
337 papszDesc[j] ? papszDesc[j] : "Exit reason",
338 "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
339 AssertRC(rc);
340 }
341 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
342 AssertRC(rc);
343 }
344 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
345# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
346 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
347# else
348 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
349# endif
350 }
351#endif /* VBOX_WITH_STATISTICS */
352 return VINF_SUCCESS;
353}
354
355/**
356 * Turns off normal raw mode features
357 *
358 * @param pVM The VM to operate on.
359 */
360static void hwaccmR3DisableRawMode(PVM pVM)
361{
362 /* Disable PATM & CSAM. */
363 PATMR3AllowPatching(pVM, false);
364 CSAMDisableScanning(pVM);
365
366 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
367 SELMR3DisableMonitoring(pVM);
368 TRPMR3DisableMonitoring(pVM);
369
370 /* The hidden selector registers are now valid. */
371 CPUMSetHiddenSelRegsValid(pVM, true);
372
373 /* Disable the switcher code (safety precaution). */
374 VMMR3DisableSwitcher(pVM);
375
376 /* Disable mapping of the hypervisor into the shadow page table. */
377 PGMR3ChangeShwPDMappings(pVM, false);
378
379 /* Disable the switcher */
380 VMMR3DisableSwitcher(pVM);
381
382 if (pVM->hwaccm.s.fNestedPaging)
383 {
384 /* Reinit the paging mode to force the new shadow mode. */
385 PGMR3ChangeMode(pVM, PGMMODE_REAL);
386 }
387}
388
389/**
390 * Initialize VT-x or AMD-V.
391 *
392 * @returns VBox status code.
393 * @param pVM The VM handle.
394 */
395VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
396{
397 int rc;
398
399 if ( !pVM->hwaccm.s.vmx.fSupported
400 && !pVM->hwaccm.s.svm.fSupported)
401 {
402 LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
403 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
404#ifdef RT_OS_DARWIN
405 if (VMMIsHwVirtExtForced(pVM))
406 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
407#endif
408 return VINF_SUCCESS;
409 }
410
411 /*
412 * Note that we have a global setting for VT-x/AMD-V usage. VMX root mode changes the way the CPU operates. Our 64 bits switcher will trap
413 * because it turns off paging, which is not allowed in VMX root mode.
414 *
415 * To simplify matters we'll just force all running VMs to either use raw or VT-x mode. No mixing allowed in the VT-x case.
416 * There's no such problem with AMD-V. (@todo)
417 *
418 */
419 /* If we enabled or disabled hwaccm mode, then it can't be changed until all the VMs are shutdown. */
420 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, (pVM->hwaccm.s.fAllowed) ? HWACCMSTATE_ENABLED : HWACCMSTATE_DISABLED, NULL);
421 if (RT_FAILURE(rc))
422 {
423 LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
424 LogRel(("HWACCMR3InitFinalize: disallowed %s of HWACCM\n", pVM->hwaccm.s.fAllowed ? "enabling" : "disabling"));
425
426#ifdef RT_OS_DARWIN
427 /*
428 * This is 100% fatal if we didn't prepare for a HwVirtExt setup because of
429 * missing ring-0 allocations. For VMs that require HwVirtExt it doesn't normally
430 * make sense to try run them in software mode, so fail that too.
431 */
432 if (VMMIsHwVirtExtForced(pVM))
433 VM_SET_ERROR(pVM, rc, "An active VM already uses software virtualization. It is not allowed to "
434 "simultaneously use VT-x.");
435 else
436 VM_SET_ERROR(pVM, rc, "An active VM already uses Intel VT-x hardware acceleration. It is not "
437 "allowed to simultaneously use software virtualization.");
438 return rc;
439
440#else /* !RT_OS_DARWIN */
441
442 /* Invert the selection */
443 pVM->hwaccm.s.fAllowed ^= 1;
444 if (pVM->hwaccm.s.fAllowed)
445 {
446 if (pVM->hwaccm.s.vmx.fSupported)
447 VM_SET_ERROR(pVM, rc, "An active VM already uses Intel VT-x hardware acceleration. It is not allowed "
448 "to simultaneously use software virtualization.\n");
449 else
450 VM_SET_ERROR(pVM, rc, "An active VM already uses AMD-V hardware acceleration. It is not allowed to "
451 "simultaneously use software virtualization.\n");
452 }
453 else
454 VM_SET_ERROR(pVM, rc, "An active VM already uses software virtualization. It is not allowed to simultaneously "
455 "use VT-x or AMD-V.\n");
456 return rc;
457#endif /* !RT_OS_DARWIN */
458 }
459
460 if (pVM->hwaccm.s.fAllowed == false)
461 return VINF_SUCCESS; /* disabled */
462
463 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
464
465 if (pVM->hwaccm.s.vmx.fSupported)
466 {
467 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
468
469 if ( pVM->hwaccm.s.fInitialized == false
470 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
471 {
472 uint64_t val;
473 RTGCPHYS GCPhys = 0;
474
475 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
476 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
477 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
478 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
479 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
480 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
481 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
482 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
483
484 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
485 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
486 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
487 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
488 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
489 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
490 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
491 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
492 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
493 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
494 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
495
496 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
497 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
498 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
499 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
500 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
501 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
502 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
503 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
504 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
505 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
506 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
507 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
508 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
509 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
510 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
511 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
512 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
513 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
514 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
515 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
516 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
517 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
518 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
519 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
520 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
521 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
522 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
523 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
524 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
525 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
526 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
527 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
528 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
529 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
530 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
531 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
532 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
533 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
534 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
535 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
536 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
537 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
538
539 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
540 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
541 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
542 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
543 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
544 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
545 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
546 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
547 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
548 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
549 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
550 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
551 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
552 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
553 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
554 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
555 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
556 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
557 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
558 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
559 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
560 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
561 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
562 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
563 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
564 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
565 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
566 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
567 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
568 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
569 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
570 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
571 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
572 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
573 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
574 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
575 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
576 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
577 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
578 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
579 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
580
581 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
582 {
583 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
584 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
585 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
586 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
587 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
588 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
589 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
590 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
591 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
592 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
593
594 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
595 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
596 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
597 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
598 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
599 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
600 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
601 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
602 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
603 }
604
605 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
606 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
607 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
608 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
609 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
610 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
611 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
612 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
613 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
614 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
615 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
616 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
617 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
618 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
619 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
620 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
621 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
622 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
623 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
624 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
625 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
626 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
627 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
628 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
629 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
630 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
631 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
632 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
633 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
634 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
635 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
636
637 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
638 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
639 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
640 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
641 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
642 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
643 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
644 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
645 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
646 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
647 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
648 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
649 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
650 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
651 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
652 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
653 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
654 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
655 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
656 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
657 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
658 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
659 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
660 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
661 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
662 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
663 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
664 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
665 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
666 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
667 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
668 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
669 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
670 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
671 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
672
673 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
674 {
675 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
676
677 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
678 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
679 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
680 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
681 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
682 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
683 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
684 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
685 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
686 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
687 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
688 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
689 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
690 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
691 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
692 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
693 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
694 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
695 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
696 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
697 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
698 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
699 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
700 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
701 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
702 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
703 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
704 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
705 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
706 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
707 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
708 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
709 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
710 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
711 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
712 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
713 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
714 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
715 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
716 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
717 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
718 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
719 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
720 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
721 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
722 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
723 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
724 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
725 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
726 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
727 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
728 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
729 }
730
731 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
732 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
733 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
734 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
735 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
736
737 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
738 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
739 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
740 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
741 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
742
743 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
744 LogRel(("HWACCM: MSR bitmap physaddr = %RHp\n", pVM->hwaccm.s.vmx.pMSRBitmapPhys));
745
746 for (unsigned i=0;i<pVM->cCPUs;i++)
747 LogRel(("HWACCM: VMCS physaddr VCPU%d = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
748
749#ifdef HWACCM_VTX_WITH_EPT
750 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
751 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
752#endif /* HWACCM_VTX_WITH_EPT */
753#ifdef HWACCM_VTX_WITH_VPID
754 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
755 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
756 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
757#endif /* HWACCM_VTX_WITH_VPID */
758
759 /* Only try once. */
760 pVM->hwaccm.s.fInitialized = true;
761
762 /* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
763 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
764 AssertRC(rc);
765 if (RT_FAILURE(rc))
766 return rc;
767
768 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
769 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
770 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
771 /* Bit set to 0 means redirection enabled. */
772 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
773 /* Allow all port IO, so the VT-x IO intercepts do their job. */
774 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
775 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
776
777 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
778 * real and protected mode without paging with EPT.
779 */
780 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
781 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
782 {
783 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
784 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
785 }
786
787 /* We convert it here every time as pci regions could be reconfigured. */
788 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
789 AssertRC(rc);
790 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
791
792 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
793 AssertRC(rc);
794 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
795
796 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
797 AssertRC(rc);
798 if (rc == VINF_SUCCESS)
799 {
800 pVM->fHWACCMEnabled = true;
801 pVM->hwaccm.s.vmx.fEnabled = true;
802 hwaccmR3DisableRawMode(pVM);
803
804 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
805#ifdef VBOX_ENABLE_64_BITS_GUESTS
806 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
807 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
808 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
809 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
810 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
811#endif
812 LogRel(("HWACCM: VMX enabled!\n"));
813 if (pVM->hwaccm.s.fNestedPaging)
814 {
815 LogRel(("HWACCM: Enabled nested paging\n"));
816 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetEPTCR3(pVM)));
817 }
818 if (pVM->hwaccm.s.vmx.fVPID)
819 LogRel(("HWACCM: Enabled VPID\n"));
820
821 if ( pVM->hwaccm.s.fNestedPaging
822 || pVM->hwaccm.s.vmx.fVPID)
823 {
824 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
825 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
826 }
827 }
828 else
829 {
830 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
831 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
832 pVM->fHWACCMEnabled = false;
833 }
834 }
835 }
836 else
837 if (pVM->hwaccm.s.svm.fSupported)
838 {
839 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
840
841 if (pVM->hwaccm.s.fInitialized == false)
842 {
843 /* Erratum 170 which requires a forced TLB flush for each world switch:
844 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
845 *
846 * All BH-G1/2 and DH-G1/2 models include a fix:
847 * Athlon X2: 0x6b 1/2
848 * 0x68 1/2
849 * Athlon 64: 0x7f 1
850 * 0x6f 2
851 * Sempron: 0x7f 1/2
852 * 0x6f 2
853 * 0x6c 2
854 * 0x7c 2
855 * Turion 64: 0x68 2
856 *
857 */
858 uint32_t u32Dummy;
859 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
860 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
861 u32BaseFamily= (u32Version >> 8) & 0xf;
862 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
863 u32Model = ((u32Version >> 4) & 0xf);
864 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
865 u32Stepping = u32Version & 0xf;
866 if ( u32Family == 0xf
867 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
868 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
869 {
870 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
871 }
872
873 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
874 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
875 LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
876 LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
877 LogRel(("HWACCM: SVM features = %X\n", pVM->hwaccm.s.svm.u32Features));
878
879 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
880 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
881 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
882 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
883 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
884 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
885 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
886 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
887 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
888 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
889
890 /* Only try once. */
891 pVM->hwaccm.s.fInitialized = true;
892
893 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
894 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
895
896 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
897 AssertRC(rc);
898 if (rc == VINF_SUCCESS)
899 {
900 pVM->fHWACCMEnabled = true;
901 pVM->hwaccm.s.svm.fEnabled = true;
902
903 if (pVM->hwaccm.s.fNestedPaging)
904 LogRel(("HWACCM: Enabled nested paging\n"));
905
906 hwaccmR3DisableRawMode(pVM);
907 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
908 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
909 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
910#ifdef VBOX_ENABLE_64_BITS_GUESTS
911 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
912 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
913 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
914 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
915#endif
916 }
917 else
918 {
919 pVM->fHWACCMEnabled = false;
920 }
921 }
922 }
923
924#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
925 if (pVM->fHWACCMEnabled)
926 {
927 switch(PGMGetHostMode(pVM))
928 {
929 case PGMMODE_32_BIT:
930 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
931 break;
932
933 case PGMMODE_PAE:
934 case PGMMODE_PAE_NX:
935 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
936 break;
937
938 default:
939 AssertFailed();
940 break;
941 }
942
943 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
944 AssertMsgRCReturn(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc), rc);
945
946 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
947 AssertMsgRCReturn(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc), rc);
948
949 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
950 AssertMsgRCReturn(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc), rc);
951
952 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
953 AssertMsgRCReturn(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc), rc);
954
955# ifdef DEBUG
956 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
957 AssertMsgRCReturn(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc), rc);
958# endif
959 }
960#endif
961 return VINF_SUCCESS;
962}
963
964/**
965 * Applies relocations to data and code managed by this
966 * component. This function will be called at init and
967 * whenever the VMM need to relocate it self inside the GC.
968 *
969 * @param pVM The VM.
970 */
971VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
972{
973 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
974
975 /* Fetch the current paging mode during the relocate callback during state loading. */
976 if (VMR3GetState(pVM) == VMSTATE_LOADING)
977 {
978 for (unsigned i=0;i<pVM->cCPUs;i++)
979 {
980 PVMCPU pVCpu = &pVM->aCpus[i];
981 /* @todo SMP */
982 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVM);
983 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVM);
984 }
985 }
986
987 return;
988}
989
990/**
991 * Checks hardware accelerated raw mode is allowed.
992 *
993 * @returns boolean
994 * @param pVM The VM to operate on.
995 */
996VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
997{
998 return pVM->hwaccm.s.fAllowed;
999}
1000
1001/**
1002 * Notification callback which is called whenever there is a chance that a CR3
1003 * value might have changed.
1004 *
1005 * This is called by PGM.
1006 *
1007 * @param pVM The VM to operate on.
1008 * @param enmShadowMode New shadow paging mode.
1009 * @param enmGuestMode New guest paging mode.
1010 */
1011VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1012{
1013 /* Ignore page mode changes during state loading. */
1014 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1015 return;
1016
1017 PVMCPU pVCpu = VMMGetCpu(pVM);
1018 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1019
1020 if ( pVM->hwaccm.s.vmx.fEnabled
1021 && pVM->fHWACCMEnabled)
1022 {
1023 if ( pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
1024 && enmGuestMode >= PGMMODE_PROTECTED)
1025 {
1026 PCPUMCTX pCtx;
1027
1028 pCtx = CPUMQueryGuestCtxPtr(pVM);
1029
1030 /* After a real mode switch to protected mode we must force
1031 * CPL to 0. Our real mode emulation had to set it to 3.
1032 */
1033 pCtx->ssHid.Attr.n.u2Dpl = 0;
1034 }
1035 }
1036}
1037
1038/**
1039 * Terminates the HWACCM.
1040 *
1041 * Termination means cleaning up and freeing all resources,
1042 * the VM it self is at this point powered off or suspended.
1043 *
1044 * @returns VBox status code.
1045 * @param pVM The VM to operate on.
1046 */
1047VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1048{
1049 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1050 {
1051 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1052 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1053 }
1054 return 0;
1055}
1056
1057/**
1058 * Terminates the per-VCPU HWACCM.
1059 *
1060 * Termination means cleaning up and freeing all resources,
1061 * the VM it self is at this point powered off or suspended.
1062 *
1063 * @returns VBox status code.
1064 * @param pVM The VM to operate on.
1065 */
1066VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1067{
1068 for (unsigned i=0;i<pVM->cCPUs;i++)
1069 {
1070 PVMCPU pVCpu = &pVM->aCpus[i];
1071
1072 if (pVCpu->hwaccm.s.paStatExitReason)
1073 {
1074 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1075 pVCpu->hwaccm.s.paStatExitReason = NULL;
1076 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1077 }
1078 }
1079 return 0;
1080}
1081
1082/**
1083 * The VM is being reset.
1084 *
1085 * For the HWACCM component this means that any GDT/LDT/TSS monitors
1086 * needs to be removed.
1087 *
1088 * @param pVM VM handle.
1089 */
1090VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1091{
1092 LogFlow(("HWACCMR3Reset:\n"));
1093
1094 if (pVM->fHWACCMEnabled)
1095 hwaccmR3DisableRawMode(pVM);
1096
1097 for (unsigned i=0;i<pVM->cCPUs;i++)
1098 {
1099 PVMCPU pVCpu = &pVM->aCpus[i];
1100
1101 /* On first entry we'll sync everything. */
1102 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1103
1104 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1105 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1106
1107 pVCpu->hwaccm.s.Event.fPending = false;
1108
1109 /* Reset state information for real-mode emulation in VT-x. */
1110 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1111 }
1112}
1113
1114/**
1115 * Checks if we can currently use hardware accelerated raw mode.
1116 *
1117 * @returns boolean
1118 * @param pVM The VM to operate on.
1119 * @param pCtx Partial VM execution context
1120 */
1121VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
1122{
1123 Assert(pVM->fHWACCMEnabled);
1124
1125 /* AMD SVM supports real & protected mode with or without paging. */
1126 if (pVM->hwaccm.s.svm.fEnabled)
1127 {
1128 pVM->hwaccm.s.fActive = true;
1129 return true;
1130 }
1131
1132 pVM->hwaccm.s.fActive = false;
1133
1134 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
1135#ifdef HWACCM_VMX_EMULATE_REALMODE
1136 if (CPUMIsGuestInRealModeEx(pCtx))
1137 {
1138 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
1139 * The base must also be equal to (sel << 4).
1140 */
1141 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
1142 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
1143 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
1144 || pCtx->es != (pCtx->esHid.u64Base >> 4)
1145 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
1146 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
1147 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
1148 return false;
1149 }
1150 else
1151 {
1152 PGMMODE enmGuestMode = PGMGetGuestMode(pVM);
1153 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
1154 * from real to protected mode. (all sorts of RPL & DPL assumptions)
1155 */
1156 PVMCPU pVCpu = VMMGetCpu(pVM);
1157
1158 if ( pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
1159 && enmGuestMode >= PGMMODE_PROTECTED)
1160 {
1161 if ( (pCtx->cs & X86_SEL_RPL)
1162 || (pCtx->ds & X86_SEL_RPL)
1163 || (pCtx->es & X86_SEL_RPL)
1164 || (pCtx->fs & X86_SEL_RPL)
1165 || (pCtx->gs & X86_SEL_RPL)
1166 || (pCtx->ss & X86_SEL_RPL))
1167 {
1168 return false;
1169 }
1170 }
1171 }
1172#else
1173 if (!CPUMIsGuestInLongModeEx(pCtx))
1174 {
1175 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
1176 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
1177 return false;
1178
1179 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
1180 /* Windows XP; switch to protected mode; all selectors are marked not present in the
1181 * hidden registers (possible recompiler bug; see load_seg_vm) */
1182 if (pCtx->csHid.Attr.n.u1Present == 0)
1183 return false;
1184 if (pCtx->ssHid.Attr.n.u1Present == 0)
1185 return false;
1186 }
1187#endif
1188
1189 if (pVM->hwaccm.s.vmx.fEnabled)
1190 {
1191 uint32_t mask;
1192
1193 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
1194 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
1195 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
1196 mask &= ~X86_CR0_NE;
1197
1198#ifdef HWACCM_VMX_EMULATE_REALMODE
1199 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
1200 mask &= ~(X86_CR0_PG|X86_CR0_PE);
1201#else
1202 /* We support protected mode without paging using identity mapping. */
1203 mask &= ~X86_CR0_PG;
1204#endif
1205 if ((pCtx->cr0 & mask) != mask)
1206 return false;
1207
1208 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
1209 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
1210 if ((pCtx->cr0 & mask) != 0)
1211 return false;
1212
1213 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
1214 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1215 mask &= ~X86_CR4_VMXE;
1216 if ((pCtx->cr4 & mask) != mask)
1217 return false;
1218
1219 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
1220 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
1221 if ((pCtx->cr4 & mask) != 0)
1222 return false;
1223
1224 pVM->hwaccm.s.fActive = true;
1225 return true;
1226 }
1227
1228 return false;
1229}
1230
1231/**
1232 * Checks if we are currently using hardware accelerated raw mode.
1233 *
1234 * @returns boolean
1235 * @param pVM The VM to operate on.
1236 */
1237VMMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
1238{
1239 return pVM->hwaccm.s.fActive;
1240}
1241
1242/**
1243 * Checks if we are currently using nested paging.
1244 *
1245 * @returns boolean
1246 * @param pVM The VM to operate on.
1247 */
1248VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
1249{
1250 return pVM->hwaccm.s.fNestedPaging;
1251}
1252
1253/**
1254 * Checks if we are currently using VPID in VT-x mode.
1255 *
1256 * @returns boolean
1257 * @param pVM The VM to operate on.
1258 */
1259VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
1260{
1261 return pVM->hwaccm.s.vmx.fVPID;
1262}
1263
1264
1265/**
1266 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
1267 *
1268 * @returns boolean
1269 * @param pVM The VM to operate on.
1270 */
1271VMMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
1272{
1273 /* @todo SMP */
1274 return HWACCMIsEnabled(pVM) && pVM->aCpus[0].hwaccm.s.Event.fPending;
1275}
1276
1277
1278/**
1279 * Inject an NMI into a running VM
1280 *
1281 * @returns boolean
1282 * @param pVM The VM to operate on.
1283 */
1284VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
1285{
1286 pVM->hwaccm.s.fInjectNMI = true;
1287 return VINF_SUCCESS;
1288}
1289
1290/**
1291 * Check fatal VT-x/AMD-V error and produce some meaningful
1292 * log release message.
1293 *
1294 * @param pVM The VM to operate on.
1295 * @param iStatusCode VBox status code
1296 */
1297VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
1298{
1299 for (unsigned i=0;i<pVM->cCPUs;i++)
1300 {
1301 switch(iStatusCode)
1302 {
1303 case VERR_VMX_INVALID_VMCS_FIELD:
1304 break;
1305
1306 case VERR_VMX_INVALID_VMCS_PTR:
1307 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1308 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
1309 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
1310 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
1311 break;
1312
1313 case VERR_VMX_UNABLE_TO_START_VM:
1314 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1315 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1316#if 0 /* @todo dump the current control fields to the release log */
1317 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
1318 {
1319
1320 }
1321#endif
1322 break;
1323
1324 case VERR_VMX_UNABLE_TO_RESUME_VM:
1325 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1326 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1327 break;
1328
1329 case VERR_VMX_INVALID_VMXON_PTR:
1330 break;
1331 }
1332 }
1333}
1334
1335/**
1336 * Execute state save operation.
1337 *
1338 * @returns VBox status code.
1339 * @param pVM VM Handle.
1340 * @param pSSM SSM operation handle.
1341 */
1342static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
1343{
1344 int rc;
1345
1346 Log(("hwaccmR3Save:\n"));
1347
1348 for (unsigned i=0;i<pVM->cCPUs;i++)
1349 {
1350 /*
1351 * Save the basic bits - fortunately all the other things can be resynced on load.
1352 */
1353 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
1354 AssertRCReturn(rc, rc);
1355 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
1356 AssertRCReturn(rc, rc);
1357 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
1358 AssertRCReturn(rc, rc);
1359 }
1360
1361 return VINF_SUCCESS;
1362}
1363
1364/**
1365 * Execute state load operation.
1366 *
1367 * @returns VBox status code.
1368 * @param pVM VM Handle.
1369 * @param pSSM SSM operation handle.
1370 * @param u32Version Data layout version.
1371 */
1372static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1373{
1374 int rc;
1375
1376 Log(("hwaccmR3Load:\n"));
1377
1378 /*
1379 * Validate version.
1380 */
1381 if (u32Version != HWACCM_SSM_VERSION)
1382 {
1383 AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
1384 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1385 }
1386 for (unsigned i=0;i<pVM->cCPUs;i++)
1387 {
1388 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
1389 AssertRCReturn(rc, rc);
1390 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
1391 AssertRCReturn(rc, rc);
1392 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
1393 AssertRCReturn(rc, rc);
1394 }
1395 return VINF_SUCCESS;
1396}
1397
1398
1399
1400
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