VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 14888

Last change on this file since 14888 was 14888, checked in by vboxsync, 16 years ago

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1/* $Id: HWACCM.cpp 14888 2008-12-02 10:36:00Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.215389.xyz. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdm.h>
30#include <VBox/pgm.h>
31#include <VBox/trpm.h>
32#include <VBox/dbgf.h>
33#include <VBox/patm.h>
34#include <VBox/csam.h>
35#include <VBox/selm.h>
36#include <VBox/rem.h>
37#include <VBox/hwacc_vmx.h>
38#include <VBox/hwacc_svm.h>
39#include "HWACCMInternal.h"
40#include <VBox/vm.h>
41#include <VBox/err.h>
42#include <VBox/param.h>
43
44#include <iprt/assert.h>
45#include <VBox/log.h>
46#include <iprt/asm.h>
47#include <iprt/string.h>
48#include <iprt/thread.h>
49
50/*******************************************************************************
51* Internal Functions *
52*******************************************************************************/
53static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
54static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
55
56
57/**
58 * Initializes the HWACCM.
59 *
60 * @returns VBox status code.
61 * @param pVM The VM to operate on.
62 */
63VMMR3DECL(int) HWACCMR3Init(PVM pVM)
64{
65 LogFlow(("HWACCMR3Init\n"));
66
67 /*
68 * Assert alignment and sizes.
69 */
70 AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
71 AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
72
73 /* Some structure checks. */
74 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
75 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
76 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
77 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
78
79 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
80 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
81 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
82 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
83 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
84 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
85 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
86
87
88 /*
89 * Register the saved state data unit.
90 */
91 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
92 NULL, hwaccmR3Save, NULL,
93 NULL, hwaccmR3Load, NULL);
94 if (RT_FAILURE(rc))
95 return rc;
96
97 /* Misc initialisation. */
98 pVM->hwaccm.s.vmx.fSupported = false;
99 pVM->hwaccm.s.svm.fSupported = false;
100 pVM->hwaccm.s.vmx.fEnabled = false;
101 pVM->hwaccm.s.svm.fEnabled = false;
102
103 pVM->hwaccm.s.fActive = false;
104 pVM->hwaccm.s.fNestedPaging = false;
105
106 /* Disabled by default. */
107 pVM->fHWACCMEnabled = false;
108
109 /*
110 * Check CFGM options.
111 */
112 /* Nested paging: disabled by default. */
113 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
114 AssertRC(rc);
115
116 /* VT-x VPID: disabled by default. */
117 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
118 AssertRC(rc);
119
120 /* HWACCM support must be explicitely enabled in the configuration file. */
121 rc = CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed, false);
122 AssertRC(rc);
123
124#ifdef RT_OS_DARWIN
125 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
126#else
127 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
128#endif
129 {
130 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
131 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
132 return VERR_HWACCM_CONFIG_MISMATCH;
133 }
134
135 if (VMMIsHwVirtExtForced(pVM))
136 pVM->fHWACCMEnabled = true;
137
138 return VINF_SUCCESS;
139}
140
141/**
142 * Initializes the per-VCPU HWACCM.
143 *
144 * @returns VBox status code.
145 * @param pVM The VM to operate on.
146 */
147VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
148{
149 LogFlow(("HWACCMR3InitCPU\n"));
150
151#ifdef VBOX_WITH_STATISTICS
152 /*
153 * Statistics.
154 */
155 for (unsigned i=0;i<pVM->cCPUs;i++)
156 {
157 PVMCPU pVCpu = &pVM->aCpus[i];
158 int rc;
159
160 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
161 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
162 AssertRC(rc);
163 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit",
164 "/PROF/HWACCM/CPU%d/SwitchFromGC", i);
165 AssertRC(rc);
166 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
167 "/PROF/HWACCM/CPU%d/InGC", i);
168 AssertRC(rc);
169
170#define HWACCM_REG_COUNTER(a, b) \
171 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
172 AssertRC(rc);
173
174 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
175 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
176 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
177 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
178 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
179 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
180 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
181 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
182 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
183 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
184 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
185 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
186 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
187 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
188 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
189 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCRxWrite, "/HWACCM/CPU%d/Exit/Instr/CR/Write");
190 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCRxRead, "/HWACCM/CPU%d/Exit/Instr/CR/Read");
191 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
192 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
193 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
194 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
195 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
196 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
197 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
198 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
199 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
200 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
201
202 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
203 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
204
205 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
206 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
207 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
208
209 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
210 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
211 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
212 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
213 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
214 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
215 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
216 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
217 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
218
219 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
220 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
221
222 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
223 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
224 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
225
226#undef HWACCM_REG_COUNTER
227
228 pVCpu->hwaccm.s.paStatExitReason = NULL;
229
230 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
231 AssertRC(rc);
232 if (RT_SUCCESS(rc))
233 {
234 for (int j=0;j<MAX_EXITREASON_STAT;j++)
235 {
236 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Exit reason",
237 "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
238 AssertRC(rc);
239 }
240 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Exit reason", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
241 AssertRC(rc);
242 }
243 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
244 Assert(pVCpu->hwaccm.s.paStatExitReasonR0);
245 }
246#endif /* VBOX_WITH_STATISTICS */
247 return VINF_SUCCESS;
248}
249
250/**
251 * Turns off normal raw mode features
252 *
253 * @param pVM The VM to operate on.
254 */
255static void hwaccmR3DisableRawMode(PVM pVM)
256{
257 /* Disable PATM & CSAM. */
258 PATMR3AllowPatching(pVM, false);
259 CSAMDisableScanning(pVM);
260
261 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
262 SELMR3DisableMonitoring(pVM);
263 TRPMR3DisableMonitoring(pVM);
264
265 /* The hidden selector registers are now valid. */
266 CPUMSetHiddenSelRegsValid(pVM, true);
267
268 /* Disable the switcher code (safety precaution). */
269 VMMR3DisableSwitcher(pVM);
270
271 /* Disable mapping of the hypervisor into the shadow page table. */
272 PGMR3ChangeShwPDMappings(pVM, false);
273
274 /* Disable the switcher */
275 VMMR3DisableSwitcher(pVM);
276
277 if (pVM->hwaccm.s.fNestedPaging)
278 {
279 /* Reinit the paging mode to force the new shadow mode. */
280 PGMR3ChangeMode(pVM, PGMMODE_REAL);
281 }
282}
283
284/**
285 * Initialize VT-x or AMD-V.
286 *
287 * @returns VBox status code.
288 * @param pVM The VM handle.
289 */
290VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
291{
292 int rc;
293
294 if ( !pVM->hwaccm.s.vmx.fSupported
295 && !pVM->hwaccm.s.svm.fSupported)
296 {
297 LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
298 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
299 return VINF_SUCCESS;
300 }
301
302 /*
303 * Note that we have a global setting for VT-x/AMD-V usage. VMX root mode changes the way the CPU operates. Our 64 bits switcher will trap
304 * because it turns off paging, which is not allowed in VMX root mode.
305 *
306 * To simplify matters we'll just force all running VMs to either use raw or VT-x mode. No mixing allowed in the VT-x case.
307 * There's no such problem with AMD-V. (@todo)
308 *
309 */
310 /* If we enabled or disabled hwaccm mode, then it can't be changed until all the VMs are shutdown. */
311 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, (pVM->hwaccm.s.fAllowed) ? HWACCMSTATE_ENABLED : HWACCMSTATE_DISABLED, NULL);
312 if (RT_FAILURE(rc))
313 {
314 LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
315 LogRel(("HWACCMR3InitFinalize: disallowed %s of HWACCM\n", pVM->hwaccm.s.fAllowed ? "enabling" : "disabling"));
316
317#ifdef RT_OS_DARWIN
318 /*
319 * This is 100% fatal if we didn't prepare for a HwVirtExt setup because of
320 * missing ring-0 allocations. For VMs that require HwVirtExt it doesn't normally
321 * make sense to try run them in software mode, so fail that too.
322 */
323 if (VMMIsHwVirtExtForced(pVM))
324 VM_SET_ERROR(pVM, rc, "An active VM already uses software virtualization. It is not allowed to "
325 "simultaneously use VT-x.\n");
326 else
327 VM_SET_ERROR(pVM, rc, "An active VM already uses Intel VT-x hardware acceleration. It is not "
328 "allowed to simultaneously use software virtualization.\n");
329 return rc;
330
331#else /* !RT_OS_DARWIN */
332
333 if (pVM->hwaccm.s.fAllowed)
334 {
335 if (pVM->hwaccm.s.vmx.fSupported)
336 VM_SET_ERROR(pVM, rc, "An active VM already uses Intel VT-x hardware acceleration. It is not allowed "
337 "to simultaneously use software virtualization.\n");
338 else
339 VM_SET_ERROR(pVM, rc, "An active VM already uses AMD-V hardware acceleration. It is not allowed to "
340 "simultaneously use software virtualization.\n");
341 }
342 else
343 VM_SET_ERROR(pVM, rc, "An active VM already uses software virtualization. It is not allowed to simultaneously "
344 "use VT-x or AMD-V.\n");
345 return rc;
346#endif /* !RT_OS_DARWIN */
347 }
348
349 if (pVM->hwaccm.s.fAllowed == false)
350 return VINF_SUCCESS; /* disabled */
351
352 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
353
354 if (pVM->hwaccm.s.vmx.fSupported)
355 {
356 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
357
358 if ( pVM->hwaccm.s.fInitialized == false
359 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
360 {
361 uint64_t val;
362 RTGCPHYS GCPhys = 0;
363
364 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
365 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
366 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
367 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
368 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
369 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
370 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
371 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
372
373 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
374 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
375 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
376 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
377 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
378 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
379 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
380 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
381 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
382 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
383 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
384
385 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
386 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
387 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
388 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
389 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
390 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
391 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
392 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
393 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
394 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
395 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
396 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
397 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
398 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
399 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
400 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
401 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
402 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
403 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
404 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
405 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
406 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
407 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
408 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
409 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
410 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
411 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
412 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
413 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
414 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
415 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
416 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
417 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
418 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
419 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
420 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
421 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
422 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
423 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
424 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
425 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
426 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
427
428 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
429 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
430 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
431 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
432 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
433 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
434 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
435 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
436 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
437 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
438 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
439 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
440 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
441 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
442 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
443 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
444 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
445 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
446 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
447 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
448 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
449 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
450 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
451 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
452 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
453 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
454 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
455 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
456 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
457 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
458 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
459 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
460 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
461 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
462 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
463 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
464 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
465 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
466 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
467 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
468 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
469
470 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
471 {
472 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
473 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
474 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
475 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
476 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
477 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
478 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
479 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
480 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
481 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
482
483 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
484 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
485 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
486 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
487 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
488 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
489 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
490 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
491 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
492 }
493
494 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
495 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
496 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
497 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
498 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
499 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
500 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
501 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
502 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
503 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
504 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
505 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
506 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
507 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
508 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
509 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
510 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
511 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
512 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
513 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
514 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
515 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
516 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
517 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
518 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
519 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
520 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
521 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
522 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
523 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
524 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
525
526 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
527 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
528 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
529 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
530 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
531 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
532 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
533 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
534 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
535 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
536 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
537 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
538 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
539 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
540 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
541 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
542 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
543 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
544 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
545 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
546 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
547 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
548 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
549 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
550 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
551 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
552 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
553 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
554 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
555 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
556 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
557 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
558 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
559 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
560 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
561
562 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
563 {
564 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
565
566 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
567 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
568 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
569 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
570 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
571 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
572 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
573 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
574 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
575 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
576 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
577 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
578 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
579 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
580 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
581 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
582 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
583 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
584 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
585 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
586 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
587 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
588 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
589 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
590 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
591 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
592 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
593 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
594 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
595 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
596 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
597 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
598 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
599 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
600 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
601 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
602 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
603 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
604 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
605 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
606 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
607 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
608 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
609 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
610 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
611 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
612 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
613 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
614 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
615 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
616 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
617 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
618 }
619
620 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
621 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
622 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
623 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
624 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
625
626 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
627 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
628 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
629 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
630 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
631
632 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
633 LogRel(("HWACCM: MSR bitmap physaddr = %RHp\n", pVM->hwaccm.s.vmx.pMSRBitmapPhys));
634
635 for (unsigned i=0;i<pVM->cCPUs;i++)
636 LogRel(("HWACCM: VMCS physaddr VCPU%d = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
637
638#ifdef HWACCM_VTX_WITH_EPT
639 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
640 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
641#endif /* HWACCM_VTX_WITH_EPT */
642#ifdef HWACCM_VTX_WITH_VPID
643 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
644 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
645 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
646#endif /* HWACCM_VTX_WITH_VPID */
647
648 /* Only try once. */
649 pVM->hwaccm.s.fInitialized = true;
650
651 /* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
652 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
653 AssertRC(rc);
654 if (RT_FAILURE(rc))
655 return rc;
656
657 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
658 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
659 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
660 /* Bit set to 0 means redirection enabled. */
661 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
662 /* Allow all port IO, so the VT-x IO intercepts do their job. */
663 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
664 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
665
666 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
667 * real and protected mode without paging with EPT.
668 */
669 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
670 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
671 {
672 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
673 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
674 }
675
676 /* We convert it here every time as pci regions could be reconfigured. */
677 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
678 AssertRC(rc);
679 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
680
681 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
682 AssertRC(rc);
683 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
684
685 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
686 AssertRC(rc);
687 if (rc == VINF_SUCCESS)
688 {
689 pVM->fHWACCMEnabled = true;
690 pVM->hwaccm.s.vmx.fEnabled = true;
691 hwaccmR3DisableRawMode(pVM);
692
693 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
694#ifdef VBOX_ENABLE_64_BITS_GUESTS
695 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
696 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
697 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
698 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
699 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
700#endif
701 LogRel(("HWACCM: VMX enabled!\n"));
702 if (pVM->hwaccm.s.fNestedPaging)
703 {
704 LogRel(("HWACCM: Enabled nested paging\n"));
705 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetEPTCR3(pVM)));
706 }
707 if (pVM->hwaccm.s.vmx.fVPID)
708 LogRel(("HWACCM: Enabled VPID\n"));
709
710 if ( pVM->hwaccm.s.fNestedPaging
711 || pVM->hwaccm.s.vmx.fVPID)
712 {
713 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
714 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
715 }
716 }
717 else
718 {
719 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
720 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
721 pVM->fHWACCMEnabled = false;
722 }
723 }
724 }
725 else
726 if (pVM->hwaccm.s.svm.fSupported)
727 {
728 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
729
730 if (pVM->hwaccm.s.fInitialized == false)
731 {
732 /* Erratum 170 which requires a forced TLB flush for each world switch:
733 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
734 *
735 * All BH-G1/2 and DH-G1/2 models include a fix:
736 * Athlon X2: 0x6b 1/2
737 * 0x68 1/2
738 * Athlon 64: 0x7f 1
739 * 0x6f 2
740 * Sempron: 0x7f 1/2
741 * 0x6f 2
742 * 0x6c 2
743 * 0x7c 2
744 * Turion 64: 0x68 2
745 *
746 */
747 uint32_t u32Dummy;
748 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
749 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
750 u32BaseFamily= (u32Version >> 8) & 0xf;
751 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
752 u32Model = ((u32Version >> 4) & 0xf);
753 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
754 u32Stepping = u32Version & 0xf;
755 if ( u32Family == 0xf
756 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
757 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
758 {
759 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
760 }
761
762 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
763 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
764 LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
765 LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
766 LogRel(("HWACCM: SVM features = %X\n", pVM->hwaccm.s.svm.u32Features));
767
768 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
769 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
770 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
771 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
772 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
773 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
774 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
775 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
776 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
777 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
778
779 /* Only try once. */
780 pVM->hwaccm.s.fInitialized = true;
781
782 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
783 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
784
785 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
786 AssertRC(rc);
787 if (rc == VINF_SUCCESS)
788 {
789 pVM->fHWACCMEnabled = true;
790 pVM->hwaccm.s.svm.fEnabled = true;
791
792 if (pVM->hwaccm.s.fNestedPaging)
793 LogRel(("HWACCM: Enabled nested paging\n"));
794
795 hwaccmR3DisableRawMode(pVM);
796 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
797 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
798 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
799#ifdef VBOX_ENABLE_64_BITS_GUESTS
800 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
801 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
802 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
803 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
804#endif
805 }
806 else
807 {
808 pVM->fHWACCMEnabled = false;
809 }
810 }
811 }
812
813#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
814 if (pVM->fHWACCMEnabled)
815 {
816 switch(PGMGetHostMode(pVM))
817 {
818 case PGMMODE_32_BIT:
819 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
820 break;
821
822 case PGMMODE_PAE:
823 case PGMMODE_PAE_NX:
824 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
825 break;
826
827 default:
828 AssertFailed();
829 break;
830 }
831
832 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
833 AssertMsgRCReturn(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc), rc);
834
835 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
836 AssertMsgRCReturn(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc), rc);
837
838 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
839 AssertMsgRCReturn(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc), rc);
840
841 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
842 AssertMsgRCReturn(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc), rc);
843 }
844#endif
845 return VINF_SUCCESS;
846}
847
848/**
849 * Applies relocations to data and code managed by this
850 * component. This function will be called at init and
851 * whenever the VMM need to relocate it self inside the GC.
852 *
853 * @param pVM The VM.
854 */
855VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
856{
857 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
858
859 /* Fetch the current paging mode during the relocate callback during state loading. */
860 if (VMR3GetState(pVM) == VMSTATE_LOADING)
861 {
862 for (unsigned i=0;i<pVM->cCPUs;i++)
863 {
864 PVMCPU pVCpu = &pVM->aCpus[i];
865 /* @todo SMP */
866 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVM);
867 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVM);
868 }
869 }
870
871 return;
872}
873
874/**
875 * Checks hardware accelerated raw mode is allowed.
876 *
877 * @returns boolean
878 * @param pVM The VM to operate on.
879 */
880VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
881{
882 return pVM->hwaccm.s.fAllowed;
883}
884
885/**
886 * Notification callback which is called whenever there is a chance that a CR3
887 * value might have changed.
888 *
889 * This is called by PGM.
890 *
891 * @param pVM The VM to operate on.
892 * @param enmShadowMode New shadow paging mode.
893 * @param enmGuestMode New guest paging mode.
894 */
895VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
896{
897 /* Ignore page mode changes during state loading. */
898 if (VMR3GetState(pVM) == VMSTATE_LOADING)
899 return;
900
901 PVMCPU pVCpu = VMMGetCpu(pVM);
902 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
903
904 if ( pVM->hwaccm.s.vmx.fEnabled
905 && pVM->fHWACCMEnabled)
906 {
907 if ( pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
908 && enmGuestMode >= PGMMODE_PROTECTED)
909 {
910 PCPUMCTX pCtx;
911
912 pCtx = CPUMQueryGuestCtxPtr(pVM);
913
914 /* After a real mode switch to protected mode we must force
915 * CPL to 0. Our real mode emulation had to set it to 3.
916 */
917 pCtx->ssHid.Attr.n.u2Dpl = 0;
918 }
919 }
920}
921
922/**
923 * Terminates the HWACCM.
924 *
925 * Termination means cleaning up and freeing all resources,
926 * the VM it self is at this point powered off or suspended.
927 *
928 * @returns VBox status code.
929 * @param pVM The VM to operate on.
930 */
931VMMR3DECL(int) HWACCMR3Term(PVM pVM)
932{
933 if (pVM->hwaccm.s.vmx.pRealModeTSS)
934 {
935 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
936 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
937 }
938 return 0;
939}
940
941/**
942 * Terminates the per-VCPU HWACCM.
943 *
944 * Termination means cleaning up and freeing all resources,
945 * the VM it self is at this point powered off or suspended.
946 *
947 * @returns VBox status code.
948 * @param pVM The VM to operate on.
949 */
950VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
951{
952 for (unsigned i=0;i<pVM->cCPUs;i++)
953 {
954 PVMCPU pVCpu = &pVM->aCpus[i];
955
956 if (pVCpu->hwaccm.s.paStatExitReason)
957 {
958 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
959 pVCpu->hwaccm.s.paStatExitReason = NULL;
960 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
961 }
962 }
963 return 0;
964}
965
966/**
967 * The VM is being reset.
968 *
969 * For the HWACCM component this means that any GDT/LDT/TSS monitors
970 * needs to be removed.
971 *
972 * @param pVM VM handle.
973 */
974VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
975{
976 LogFlow(("HWACCMR3Reset:\n"));
977
978 if (pVM->fHWACCMEnabled)
979 hwaccmR3DisableRawMode(pVM);
980
981 for (unsigned i=0;i<pVM->cCPUs;i++)
982 {
983 PVMCPU pVCpu = &pVM->aCpus[i];
984
985 /* On first entry we'll sync everything. */
986 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
987
988 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
989 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
990
991 pVCpu->hwaccm.s.Event.fPending = false;
992
993 /* Reset state information for real-mode emulation in VT-x. */
994 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
995 }
996}
997
998/**
999 * Checks if we can currently use hardware accelerated raw mode.
1000 *
1001 * @returns boolean
1002 * @param pVM The VM to operate on.
1003 * @param pCtx Partial VM execution context
1004 */
1005VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
1006{
1007 Assert(pVM->fHWACCMEnabled);
1008
1009 /* AMD SVM supports real & protected mode with or without paging. */
1010 if (pVM->hwaccm.s.svm.fEnabled)
1011 {
1012 pVM->hwaccm.s.fActive = true;
1013 return true;
1014 }
1015
1016 pVM->hwaccm.s.fActive = false;
1017
1018 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
1019#ifdef HWACCM_VMX_EMULATE_REALMODE
1020 if (CPUMIsGuestInRealModeEx(pCtx))
1021 {
1022 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
1023 * The base must also be equal to (sel << 4).
1024 */
1025 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
1026 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
1027 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
1028 || pCtx->es != (pCtx->esHid.u64Base >> 4)
1029 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
1030 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
1031 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
1032 return false;
1033 }
1034 else
1035 {
1036 PGMMODE enmGuestMode = PGMGetGuestMode(pVM);
1037 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
1038 * from real to protected mode. (all sorts of RPL & DPL assumptions)
1039 */
1040 PVMCPU pVCpu = VMMGetCpu(pVM);
1041
1042 if ( pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
1043 && enmGuestMode >= PGMMODE_PROTECTED)
1044 {
1045 if ( (pCtx->cs & X86_SEL_RPL)
1046 || (pCtx->ds & X86_SEL_RPL)
1047 || (pCtx->es & X86_SEL_RPL)
1048 || (pCtx->fs & X86_SEL_RPL)
1049 || (pCtx->gs & X86_SEL_RPL)
1050 || (pCtx->ss & X86_SEL_RPL))
1051 {
1052 return false;
1053 }
1054 }
1055 }
1056#else
1057 if (!CPUMIsGuestInLongModeEx(pCtx))
1058 {
1059 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
1060 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
1061 return false;
1062
1063 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
1064 /* Windows XP; switch to protected mode; all selectors are marked not present in the
1065 * hidden registers (possible recompiler bug; see load_seg_vm) */
1066 if (pCtx->csHid.Attr.n.u1Present == 0)
1067 return false;
1068 if (pCtx->ssHid.Attr.n.u1Present == 0)
1069 return false;
1070 }
1071#endif
1072
1073 if (pVM->hwaccm.s.vmx.fEnabled)
1074 {
1075 uint32_t mask;
1076
1077 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
1078 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
1079 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
1080 mask &= ~X86_CR0_NE;
1081
1082#ifdef HWACCM_VMX_EMULATE_REALMODE
1083 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
1084 mask &= ~(X86_CR0_PG|X86_CR0_PE);
1085#else
1086 /* We support protected mode without paging using identity mapping. */
1087 mask &= ~X86_CR0_PG;
1088#endif
1089 if ((pCtx->cr0 & mask) != mask)
1090 return false;
1091
1092 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
1093 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
1094 if ((pCtx->cr0 & mask) != 0)
1095 return false;
1096
1097 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
1098 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1099 mask &= ~X86_CR4_VMXE;
1100 if ((pCtx->cr4 & mask) != mask)
1101 return false;
1102
1103 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
1104 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
1105 if ((pCtx->cr4 & mask) != 0)
1106 return false;
1107
1108 pVM->hwaccm.s.fActive = true;
1109 return true;
1110 }
1111
1112 return false;
1113}
1114
1115/**
1116 * Checks if we are currently using hardware accelerated raw mode.
1117 *
1118 * @returns boolean
1119 * @param pVM The VM to operate on.
1120 */
1121VMMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
1122{
1123 return pVM->hwaccm.s.fActive;
1124}
1125
1126/**
1127 * Checks if we are currently using nested paging.
1128 *
1129 * @returns boolean
1130 * @param pVM The VM to operate on.
1131 */
1132VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
1133{
1134 return pVM->hwaccm.s.fNestedPaging;
1135}
1136
1137/**
1138 * Checks if we are currently using VPID in VT-x mode.
1139 *
1140 * @returns boolean
1141 * @param pVM The VM to operate on.
1142 */
1143VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
1144{
1145 return pVM->hwaccm.s.vmx.fVPID;
1146}
1147
1148
1149/**
1150 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
1151 *
1152 * @returns boolean
1153 * @param pVM The VM to operate on.
1154 */
1155VMMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
1156{
1157 /* @todo SMP */
1158 return HWACCMIsEnabled(pVM) && pVM->aCpus[0].hwaccm.s.Event.fPending;
1159}
1160
1161
1162/**
1163 * Inject an NMI into a running VM
1164 *
1165 * @returns boolean
1166 * @param pVM The VM to operate on.
1167 */
1168VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
1169{
1170 pVM->hwaccm.s.fInjectNMI = true;
1171 return VINF_SUCCESS;
1172}
1173
1174/**
1175 * Check fatal VT-x/AMD-V error and produce some meaningful
1176 * log release message.
1177 *
1178 * @param pVM The VM to operate on.
1179 * @param iStatusCode VBox status code
1180 */
1181VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
1182{
1183 for (unsigned i=0;i<pVM->cCPUs;i++)
1184 {
1185 switch(iStatusCode)
1186 {
1187 case VERR_VMX_INVALID_VMCS_FIELD:
1188 break;
1189
1190 case VERR_VMX_INVALID_VMCS_PTR:
1191 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1192 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
1193 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
1194 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
1195 break;
1196
1197 case VERR_VMX_UNABLE_TO_START_VM:
1198 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1199 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1200#if 0 /* @todo dump the current control fields to the release log */
1201 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
1202 {
1203
1204 }
1205#endif
1206 break;
1207
1208 case VERR_VMX_UNABLE_TO_RESUME_VM:
1209 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1210 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1211 break;
1212
1213 case VERR_VMX_INVALID_VMXON_PTR:
1214 break;
1215 }
1216 }
1217}
1218
1219/**
1220 * Execute state save operation.
1221 *
1222 * @returns VBox status code.
1223 * @param pVM VM Handle.
1224 * @param pSSM SSM operation handle.
1225 */
1226static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
1227{
1228 int rc;
1229
1230 Log(("hwaccmR3Save:\n"));
1231
1232 for (unsigned i=0;i<pVM->cCPUs;i++)
1233 {
1234 /*
1235 * Save the basic bits - fortunately all the other things can be resynced on load.
1236 */
1237 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
1238 AssertRCReturn(rc, rc);
1239 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
1240 AssertRCReturn(rc, rc);
1241 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
1242 AssertRCReturn(rc, rc);
1243 }
1244
1245 return VINF_SUCCESS;
1246}
1247
1248/**
1249 * Execute state load operation.
1250 *
1251 * @returns VBox status code.
1252 * @param pVM VM Handle.
1253 * @param pSSM SSM operation handle.
1254 * @param u32Version Data layout version.
1255 */
1256static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1257{
1258 int rc;
1259
1260 Log(("hwaccmR3Load:\n"));
1261
1262 /*
1263 * Validate version.
1264 */
1265 if (u32Version != HWACCM_SSM_VERSION)
1266 {
1267 AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
1268 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1269 }
1270 for (unsigned i=0;i<pVM->cCPUs;i++)
1271 {
1272 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
1273 AssertRCReturn(rc, rc);
1274 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
1275 AssertRCReturn(rc, rc);
1276 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
1277 AssertRCReturn(rc, rc);
1278 }
1279 return VINF_SUCCESS;
1280}
1281
1282
1283
1284
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