VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 14887

Last change on this file since 14887 was 14887, checked in by vboxsync, 16 years ago

Disallow any mixed use of hwaccm & software virtualization. Don't override the setting anymore.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 61.6 KB
Line 
1/* $Id: HWACCM.cpp 14887 2008-12-02 10:15:21Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.215389.xyz. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdm.h>
30#include <VBox/pgm.h>
31#include <VBox/trpm.h>
32#include <VBox/dbgf.h>
33#include <VBox/patm.h>
34#include <VBox/csam.h>
35#include <VBox/selm.h>
36#include <VBox/rem.h>
37#include <VBox/hwacc_vmx.h>
38#include <VBox/hwacc_svm.h>
39#include "HWACCMInternal.h"
40#include <VBox/vm.h>
41#include <VBox/err.h>
42#include <VBox/param.h>
43
44#include <iprt/assert.h>
45#include <VBox/log.h>
46#include <iprt/asm.h>
47#include <iprt/string.h>
48#include <iprt/thread.h>
49
50/*******************************************************************************
51* Internal Functions *
52*******************************************************************************/
53static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
54static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
55
56
57/**
58 * Initializes the HWACCM.
59 *
60 * @returns VBox status code.
61 * @param pVM The VM to operate on.
62 */
63VMMR3DECL(int) HWACCMR3Init(PVM pVM)
64{
65 LogFlow(("HWACCMR3Init\n"));
66
67 /*
68 * Assert alignment and sizes.
69 */
70 AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
71 AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
72
73 /* Some structure checks. */
74 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
75 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
76 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
77 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
78
79 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
80 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
81 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
82 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
83 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
84 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
85 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
86
87
88 /*
89 * Register the saved state data unit.
90 */
91 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
92 NULL, hwaccmR3Save, NULL,
93 NULL, hwaccmR3Load, NULL);
94 if (RT_FAILURE(rc))
95 return rc;
96
97 /* Misc initialisation. */
98 pVM->hwaccm.s.vmx.fSupported = false;
99 pVM->hwaccm.s.svm.fSupported = false;
100 pVM->hwaccm.s.vmx.fEnabled = false;
101 pVM->hwaccm.s.svm.fEnabled = false;
102
103 pVM->hwaccm.s.fActive = false;
104 pVM->hwaccm.s.fNestedPaging = false;
105
106 /* Disabled by default. */
107 pVM->fHWACCMEnabled = false;
108
109 /*
110 * Check CFGM options.
111 */
112 /* Nested paging: disabled by default. */
113 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
114 AssertRC(rc);
115
116 /* VT-x VPID: disabled by default. */
117 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
118 AssertRC(rc);
119
120 /* HWACCM support must be explicitely enabled in the configuration file. */
121 rc = CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed, false);
122 AssertRC(rc);
123
124#ifdef RT_OS_DARWIN
125 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
126#else
127 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
128#endif
129 {
130 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
131 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
132 return VERR_HWACCM_CONFIG_MISMATCH;
133 }
134
135 if (VMMIsHwVirtExtForced(pVM))
136 pVM->fHWACCMEnabled = true;
137
138 return VINF_SUCCESS;
139}
140
141/**
142 * Initializes the per-VCPU HWACCM.
143 *
144 * @returns VBox status code.
145 * @param pVM The VM to operate on.
146 */
147VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
148{
149 LogFlow(("HWACCMR3InitCPU\n"));
150
151#ifdef VBOX_WITH_STATISTICS
152 /*
153 * Statistics.
154 */
155 for (unsigned i=0;i<pVM->cCPUs;i++)
156 {
157 PVMCPU pVCpu = &pVM->aCpus[i];
158 int rc;
159
160 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
161 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
162 AssertRC(rc);
163 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit",
164 "/PROF/HWACCM/CPU%d/SwitchFromGC", i);
165 AssertRC(rc);
166 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
167 "/PROF/HWACCM/CPU%d/InGC", i);
168 AssertRC(rc);
169
170#define HWACCM_REG_COUNTER(a, b) \
171 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
172 AssertRC(rc);
173
174 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
175 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
176 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
177 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
178 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
179 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
180 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
181 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
182 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
183 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
184 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
185 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
186 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
187 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
188 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
189 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCRxWrite, "/HWACCM/CPU%d/Exit/Instr/CR/Write");
190 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCRxRead, "/HWACCM/CPU%d/Exit/Instr/CR/Read");
191 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
192 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
193 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
194 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
195 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
196 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
197 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
198 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
199 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
200 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
201
202 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
203 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
204
205 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
206 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
207 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
208
209 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
210 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
211 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
212 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
213 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
214 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
215 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
216 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
217 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
218
219 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
220 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
221
222 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
223 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
224 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
225
226#undef HWACCM_REG_COUNTER
227
228 pVCpu->hwaccm.s.paStatExitReason = NULL;
229
230 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
231 AssertRC(rc);
232 if (RT_SUCCESS(rc))
233 {
234 for (int j=0;j<MAX_EXITREASON_STAT;j++)
235 {
236 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Exit reason",
237 "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
238 AssertRC(rc);
239 }
240 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Exit reason", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
241 AssertRC(rc);
242 }
243 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
244 Assert(pVCpu->hwaccm.s.paStatExitReasonR0);
245 }
246#endif /* VBOX_WITH_STATISTICS */
247 return VINF_SUCCESS;
248}
249
250/**
251 * Turns off normal raw mode features
252 *
253 * @param pVM The VM to operate on.
254 */
255static void hwaccmR3DisableRawMode(PVM pVM)
256{
257 /* Disable PATM & CSAM. */
258 PATMR3AllowPatching(pVM, false);
259 CSAMDisableScanning(pVM);
260
261 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
262 SELMR3DisableMonitoring(pVM);
263 TRPMR3DisableMonitoring(pVM);
264
265 /* The hidden selector registers are now valid. */
266 CPUMSetHiddenSelRegsValid(pVM, true);
267
268 /* Disable the switcher code (safety precaution). */
269 VMMR3DisableSwitcher(pVM);
270
271 /* Disable mapping of the hypervisor into the shadow page table. */
272 PGMR3ChangeShwPDMappings(pVM, false);
273
274 /* Disable the switcher */
275 VMMR3DisableSwitcher(pVM);
276
277 if (pVM->hwaccm.s.fNestedPaging)
278 {
279 /* Reinit the paging mode to force the new shadow mode. */
280 PGMR3ChangeMode(pVM, PGMMODE_REAL);
281 }
282}
283
284/**
285 * Initialize VT-x or AMD-V.
286 *
287 * @returns VBox status code.
288 * @param pVM The VM handle.
289 */
290VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
291{
292 int rc;
293
294 if ( !pVM->hwaccm.s.vmx.fSupported
295 && !pVM->hwaccm.s.svm.fSupported)
296 {
297 LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
298 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
299 return VINF_SUCCESS;
300 }
301
302 /*
303 * Note that we have a global setting for VT-x/AMD-V usage. VMX root mode changes the way the CPU operates. Our 64 bits switcher will trap
304 * because it turns off paging, which is not allowed in VMX root mode.
305 *
306 * To simplify matters we'll just force all running VMs to either use raw or VT-x mode. No mixing allowed in the VT-x case.
307 * There's no such problem with AMD-V. (@todo)
308 *
309 */
310 /* If we enabled or disabled hwaccm mode, then it can't be changed until all the VMs are shutdown. */
311 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, (pVM->hwaccm.s.fAllowed) ? HWACCMSTATE_ENABLED : HWACCMSTATE_DISABLED, NULL);
312 if (RT_FAILURE(rc))
313 {
314 LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
315 LogRel(("HWACCMR3InitFinalize: disallowed %s of HWACCM\n", pVM->hwaccm.s.fAllowed ? "enabling" : "disabling"));
316
317#ifdef RT_OS_DARWIN
318 /*
319 * This is 100% fatal if we didn't prepare for a HwVirtExt setup because of
320 * missing ring-0 allocations. For VMs that require HwVirtExt it doesn't normally
321 * make sense to try run them in software mode, so fail that too.
322 */
323 if (VMMIsHwVirtExtForced(pVM))
324 VM_SET_ERROR(pVM, rc, "An active VM already uses software virtualization. It is not allowed to "
325 "simultaneously use VT-x.\n");
326 else
327 VM_SET_ERROR(pVM, rc, "An active VM already uses Intel VT-x hardware acceleration. It is not "
328 "allowed to simultaneously use software virtualization.\n");
329 return rc;
330
331#else /* !RT_OS_DARWIN */
332
333 /* Invert the selection */
334 pVM->hwaccm.s.fAllowed ^= 1;
335 LogRel(("HWACCMR3InitFinalize: new HWACCM status = %s\n", pVM->hwaccm.s.fAllowed ? "enabled" : "disabled"));
336
337 if (pVM->hwaccm.s.fAllowed)
338 {
339 if (pVM->hwaccm.s.vmx.fSupported)
340 VM_SET_ERROR(pVM, rc, "An active VM already uses Intel VT-x hardware acceleration. It is not allowed "
341 "to simultaneously use software virtualization.\n");
342 else
343 VM_SET_ERROR(pVM, rc, "An active VM already uses AMD-V hardware acceleration. It is not allowed to "
344 "simultaneously use software virtualization.\n");
345 }
346 else
347 VM_SET_ERROR(pVM, rc, "An active VM already uses software virtualization. It is not allowed to simultaneously "
348 "use VT-x or AMD-V.\n");
349 return rc;
350#endif /* !RT_OS_DARWIN */
351 }
352
353 if (pVM->hwaccm.s.fAllowed == false)
354 return VINF_SUCCESS; /* disabled */
355
356 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
357
358 if (pVM->hwaccm.s.vmx.fSupported)
359 {
360 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
361
362 if ( pVM->hwaccm.s.fInitialized == false
363 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
364 {
365 uint64_t val;
366 RTGCPHYS GCPhys = 0;
367
368 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
369 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
370 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
371 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
372 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
373 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
374 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
375 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
376
377 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
378 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
379 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
380 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
381 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
382 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
383 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
384 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
385 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
386 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
387 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
388
389 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
390 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
391 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
392 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
393 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
394 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
395 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
396 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
397 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
398 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
399 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
400 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
401 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
402 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
403 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
404 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
405 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
406 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
407 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
408 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
409 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
410 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
411 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
412 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
413 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
414 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
415 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
416 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
417 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
418 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
419 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
420 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
421 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
422 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
423 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
424 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
425 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
426 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
427 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
428 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
429 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
430 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
431
432 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
433 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
434 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
435 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
436 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
437 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
438 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
439 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
440 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
441 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
442 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
443 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
444 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
445 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
446 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
447 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
448 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
449 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
450 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
451 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
452 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
453 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
454 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
455 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
456 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
457 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
458 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
459 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
460 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
461 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
462 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
463 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
464 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
465 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
466 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
467 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
468 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
469 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
470 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
471 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
472 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
473
474 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
475 {
476 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
477 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
478 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
479 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
480 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
481 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
482 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
483 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
484 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
485 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
486
487 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
488 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
489 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
490 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
491 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
492 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
493 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
494 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
495 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
496 }
497
498 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
499 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
500 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
501 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
502 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
503 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
504 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
505 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
506 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
507 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
508 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
509 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
510 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
511 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
512 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
513 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
514 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
515 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
516 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
517 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
518 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
519 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
520 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
521 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
522 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
523 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
524 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
525 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
526 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
527 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
528 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
529
530 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
531 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
532 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
533 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
534 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
535 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
536 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
537 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
538 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
539 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
540 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
541 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
542 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
543 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
544 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
545 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
546 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
547 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
548 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
549 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
550 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
551 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
552 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
553 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
554 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
555 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
556 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
557 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
558 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
559 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
560 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
561 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
562 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
563 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
564 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
565
566 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
567 {
568 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
569
570 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
571 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
572 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
573 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
574 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
575 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
576 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
577 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
578 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
579 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
580 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
581 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
582 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
583 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
584 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
585 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
586 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
587 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
588 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
589 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
590 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
591 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
592 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
593 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
594 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
595 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
596 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
597 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
598 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
599 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
600 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
601 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
602 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
603 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
604 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
605 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
606 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
607 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
608 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
609 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
610 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
611 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
612 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
613 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
614 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
615 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
616 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
617 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
618 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
619 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
620 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
621 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
622 }
623
624 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
625 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
626 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
627 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
628 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
629
630 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
631 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
632 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
633 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
634 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
635
636 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
637 LogRel(("HWACCM: MSR bitmap physaddr = %RHp\n", pVM->hwaccm.s.vmx.pMSRBitmapPhys));
638
639 for (unsigned i=0;i<pVM->cCPUs;i++)
640 LogRel(("HWACCM: VMCS physaddr VCPU%d = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
641
642#ifdef HWACCM_VTX_WITH_EPT
643 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
644 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
645#endif /* HWACCM_VTX_WITH_EPT */
646#ifdef HWACCM_VTX_WITH_VPID
647 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
648 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
649 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
650#endif /* HWACCM_VTX_WITH_VPID */
651
652 /* Only try once. */
653 pVM->hwaccm.s.fInitialized = true;
654
655 /* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
656 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
657 AssertRC(rc);
658 if (RT_FAILURE(rc))
659 return rc;
660
661 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
662 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
663 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
664 /* Bit set to 0 means redirection enabled. */
665 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
666 /* Allow all port IO, so the VT-x IO intercepts do their job. */
667 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
668 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
669
670 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
671 * real and protected mode without paging with EPT.
672 */
673 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
674 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
675 {
676 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
677 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
678 }
679
680 /* We convert it here every time as pci regions could be reconfigured. */
681 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
682 AssertRC(rc);
683 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
684
685 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
686 AssertRC(rc);
687 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
688
689 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
690 AssertRC(rc);
691 if (rc == VINF_SUCCESS)
692 {
693 pVM->fHWACCMEnabled = true;
694 pVM->hwaccm.s.vmx.fEnabled = true;
695 hwaccmR3DisableRawMode(pVM);
696
697 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
698#ifdef VBOX_ENABLE_64_BITS_GUESTS
699 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
700 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
701 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
702 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
703 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
704#endif
705 LogRel(("HWACCM: VMX enabled!\n"));
706 if (pVM->hwaccm.s.fNestedPaging)
707 {
708 LogRel(("HWACCM: Enabled nested paging\n"));
709 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetEPTCR3(pVM)));
710 }
711 if (pVM->hwaccm.s.vmx.fVPID)
712 LogRel(("HWACCM: Enabled VPID\n"));
713
714 if ( pVM->hwaccm.s.fNestedPaging
715 || pVM->hwaccm.s.vmx.fVPID)
716 {
717 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
718 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
719 }
720 }
721 else
722 {
723 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
724 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
725 pVM->fHWACCMEnabled = false;
726 }
727 }
728 }
729 else
730 if (pVM->hwaccm.s.svm.fSupported)
731 {
732 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
733
734 if (pVM->hwaccm.s.fInitialized == false)
735 {
736 /* Erratum 170 which requires a forced TLB flush for each world switch:
737 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
738 *
739 * All BH-G1/2 and DH-G1/2 models include a fix:
740 * Athlon X2: 0x6b 1/2
741 * 0x68 1/2
742 * Athlon 64: 0x7f 1
743 * 0x6f 2
744 * Sempron: 0x7f 1/2
745 * 0x6f 2
746 * 0x6c 2
747 * 0x7c 2
748 * Turion 64: 0x68 2
749 *
750 */
751 uint32_t u32Dummy;
752 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
753 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
754 u32BaseFamily= (u32Version >> 8) & 0xf;
755 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
756 u32Model = ((u32Version >> 4) & 0xf);
757 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
758 u32Stepping = u32Version & 0xf;
759 if ( u32Family == 0xf
760 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
761 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
762 {
763 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
764 }
765
766 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
767 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
768 LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
769 LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
770 LogRel(("HWACCM: SVM features = %X\n", pVM->hwaccm.s.svm.u32Features));
771
772 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
773 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
774 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
775 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
776 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
777 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
778 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
779 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
780 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
781 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
782
783 /* Only try once. */
784 pVM->hwaccm.s.fInitialized = true;
785
786 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
787 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
788
789 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
790 AssertRC(rc);
791 if (rc == VINF_SUCCESS)
792 {
793 pVM->fHWACCMEnabled = true;
794 pVM->hwaccm.s.svm.fEnabled = true;
795
796 if (pVM->hwaccm.s.fNestedPaging)
797 LogRel(("HWACCM: Enabled nested paging\n"));
798
799 hwaccmR3DisableRawMode(pVM);
800 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
801 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
802 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
803#ifdef VBOX_ENABLE_64_BITS_GUESTS
804 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
805 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
806 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
807 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
808#endif
809 }
810 else
811 {
812 pVM->fHWACCMEnabled = false;
813 }
814 }
815 }
816
817#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
818 if (pVM->fHWACCMEnabled)
819 {
820 switch(PGMGetHostMode(pVM))
821 {
822 case PGMMODE_32_BIT:
823 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
824 break;
825
826 case PGMMODE_PAE:
827 case PGMMODE_PAE_NX:
828 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
829 break;
830
831 default:
832 AssertFailed();
833 break;
834 }
835
836 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
837 AssertMsgRCReturn(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc), rc);
838
839 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
840 AssertMsgRCReturn(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc), rc);
841
842 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
843 AssertMsgRCReturn(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc), rc);
844
845 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
846 AssertMsgRCReturn(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc), rc);
847 }
848#endif
849 return VINF_SUCCESS;
850}
851
852/**
853 * Applies relocations to data and code managed by this
854 * component. This function will be called at init and
855 * whenever the VMM need to relocate it self inside the GC.
856 *
857 * @param pVM The VM.
858 */
859VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
860{
861 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
862
863 /* Fetch the current paging mode during the relocate callback during state loading. */
864 if (VMR3GetState(pVM) == VMSTATE_LOADING)
865 {
866 for (unsigned i=0;i<pVM->cCPUs;i++)
867 {
868 PVMCPU pVCpu = &pVM->aCpus[i];
869 /* @todo SMP */
870 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVM);
871 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVM);
872 }
873 }
874
875 return;
876}
877
878/**
879 * Checks hardware accelerated raw mode is allowed.
880 *
881 * @returns boolean
882 * @param pVM The VM to operate on.
883 */
884VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
885{
886 return pVM->hwaccm.s.fAllowed;
887}
888
889/**
890 * Notification callback which is called whenever there is a chance that a CR3
891 * value might have changed.
892 *
893 * This is called by PGM.
894 *
895 * @param pVM The VM to operate on.
896 * @param enmShadowMode New shadow paging mode.
897 * @param enmGuestMode New guest paging mode.
898 */
899VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
900{
901 /* Ignore page mode changes during state loading. */
902 if (VMR3GetState(pVM) == VMSTATE_LOADING)
903 return;
904
905 PVMCPU pVCpu = VMMGetCpu(pVM);
906 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
907
908 if ( pVM->hwaccm.s.vmx.fEnabled
909 && pVM->fHWACCMEnabled)
910 {
911 if ( pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
912 && enmGuestMode >= PGMMODE_PROTECTED)
913 {
914 PCPUMCTX pCtx;
915
916 pCtx = CPUMQueryGuestCtxPtr(pVM);
917
918 /* After a real mode switch to protected mode we must force
919 * CPL to 0. Our real mode emulation had to set it to 3.
920 */
921 pCtx->ssHid.Attr.n.u2Dpl = 0;
922 }
923 }
924}
925
926/**
927 * Terminates the HWACCM.
928 *
929 * Termination means cleaning up and freeing all resources,
930 * the VM it self is at this point powered off or suspended.
931 *
932 * @returns VBox status code.
933 * @param pVM The VM to operate on.
934 */
935VMMR3DECL(int) HWACCMR3Term(PVM pVM)
936{
937 if (pVM->hwaccm.s.vmx.pRealModeTSS)
938 {
939 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
940 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
941 }
942 return 0;
943}
944
945/**
946 * Terminates the per-VCPU HWACCM.
947 *
948 * Termination means cleaning up and freeing all resources,
949 * the VM it self is at this point powered off or suspended.
950 *
951 * @returns VBox status code.
952 * @param pVM The VM to operate on.
953 */
954VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
955{
956 for (unsigned i=0;i<pVM->cCPUs;i++)
957 {
958 PVMCPU pVCpu = &pVM->aCpus[i];
959
960 if (pVCpu->hwaccm.s.paStatExitReason)
961 {
962 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
963 pVCpu->hwaccm.s.paStatExitReason = NULL;
964 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
965 }
966 }
967 return 0;
968}
969
970/**
971 * The VM is being reset.
972 *
973 * For the HWACCM component this means that any GDT/LDT/TSS monitors
974 * needs to be removed.
975 *
976 * @param pVM VM handle.
977 */
978VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
979{
980 LogFlow(("HWACCMR3Reset:\n"));
981
982 if (pVM->fHWACCMEnabled)
983 hwaccmR3DisableRawMode(pVM);
984
985 for (unsigned i=0;i<pVM->cCPUs;i++)
986 {
987 PVMCPU pVCpu = &pVM->aCpus[i];
988
989 /* On first entry we'll sync everything. */
990 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
991
992 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
993 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
994
995 pVCpu->hwaccm.s.Event.fPending = false;
996
997 /* Reset state information for real-mode emulation in VT-x. */
998 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
999 }
1000}
1001
1002/**
1003 * Checks if we can currently use hardware accelerated raw mode.
1004 *
1005 * @returns boolean
1006 * @param pVM The VM to operate on.
1007 * @param pCtx Partial VM execution context
1008 */
1009VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
1010{
1011 Assert(pVM->fHWACCMEnabled);
1012
1013 /* AMD SVM supports real & protected mode with or without paging. */
1014 if (pVM->hwaccm.s.svm.fEnabled)
1015 {
1016 pVM->hwaccm.s.fActive = true;
1017 return true;
1018 }
1019
1020 pVM->hwaccm.s.fActive = false;
1021
1022 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
1023#ifdef HWACCM_VMX_EMULATE_REALMODE
1024 if (CPUMIsGuestInRealModeEx(pCtx))
1025 {
1026 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
1027 * The base must also be equal to (sel << 4).
1028 */
1029 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
1030 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
1031 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
1032 || pCtx->es != (pCtx->esHid.u64Base >> 4)
1033 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
1034 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
1035 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
1036 return false;
1037 }
1038 else
1039 {
1040 PGMMODE enmGuestMode = PGMGetGuestMode(pVM);
1041 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
1042 * from real to protected mode. (all sorts of RPL & DPL assumptions)
1043 */
1044 PVMCPU pVCpu = VMMGetCpu(pVM);
1045
1046 if ( pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
1047 && enmGuestMode >= PGMMODE_PROTECTED)
1048 {
1049 if ( (pCtx->cs & X86_SEL_RPL)
1050 || (pCtx->ds & X86_SEL_RPL)
1051 || (pCtx->es & X86_SEL_RPL)
1052 || (pCtx->fs & X86_SEL_RPL)
1053 || (pCtx->gs & X86_SEL_RPL)
1054 || (pCtx->ss & X86_SEL_RPL))
1055 {
1056 return false;
1057 }
1058 }
1059 }
1060#else
1061 if (!CPUMIsGuestInLongModeEx(pCtx))
1062 {
1063 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
1064 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
1065 return false;
1066
1067 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
1068 /* Windows XP; switch to protected mode; all selectors are marked not present in the
1069 * hidden registers (possible recompiler bug; see load_seg_vm) */
1070 if (pCtx->csHid.Attr.n.u1Present == 0)
1071 return false;
1072 if (pCtx->ssHid.Attr.n.u1Present == 0)
1073 return false;
1074 }
1075#endif
1076
1077 if (pVM->hwaccm.s.vmx.fEnabled)
1078 {
1079 uint32_t mask;
1080
1081 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
1082 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
1083 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
1084 mask &= ~X86_CR0_NE;
1085
1086#ifdef HWACCM_VMX_EMULATE_REALMODE
1087 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
1088 mask &= ~(X86_CR0_PG|X86_CR0_PE);
1089#else
1090 /* We support protected mode without paging using identity mapping. */
1091 mask &= ~X86_CR0_PG;
1092#endif
1093 if ((pCtx->cr0 & mask) != mask)
1094 return false;
1095
1096 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
1097 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
1098 if ((pCtx->cr0 & mask) != 0)
1099 return false;
1100
1101 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
1102 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1103 mask &= ~X86_CR4_VMXE;
1104 if ((pCtx->cr4 & mask) != mask)
1105 return false;
1106
1107 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
1108 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
1109 if ((pCtx->cr4 & mask) != 0)
1110 return false;
1111
1112 pVM->hwaccm.s.fActive = true;
1113 return true;
1114 }
1115
1116 return false;
1117}
1118
1119/**
1120 * Checks if we are currently using hardware accelerated raw mode.
1121 *
1122 * @returns boolean
1123 * @param pVM The VM to operate on.
1124 */
1125VMMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
1126{
1127 return pVM->hwaccm.s.fActive;
1128}
1129
1130/**
1131 * Checks if we are currently using nested paging.
1132 *
1133 * @returns boolean
1134 * @param pVM The VM to operate on.
1135 */
1136VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
1137{
1138 return pVM->hwaccm.s.fNestedPaging;
1139}
1140
1141/**
1142 * Checks if we are currently using VPID in VT-x mode.
1143 *
1144 * @returns boolean
1145 * @param pVM The VM to operate on.
1146 */
1147VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
1148{
1149 return pVM->hwaccm.s.vmx.fVPID;
1150}
1151
1152
1153/**
1154 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
1155 *
1156 * @returns boolean
1157 * @param pVM The VM to operate on.
1158 */
1159VMMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
1160{
1161 /* @todo SMP */
1162 return HWACCMIsEnabled(pVM) && pVM->aCpus[0].hwaccm.s.Event.fPending;
1163}
1164
1165
1166/**
1167 * Inject an NMI into a running VM
1168 *
1169 * @returns boolean
1170 * @param pVM The VM to operate on.
1171 */
1172VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
1173{
1174 pVM->hwaccm.s.fInjectNMI = true;
1175 return VINF_SUCCESS;
1176}
1177
1178/**
1179 * Check fatal VT-x/AMD-V error and produce some meaningful
1180 * log release message.
1181 *
1182 * @param pVM The VM to operate on.
1183 * @param iStatusCode VBox status code
1184 */
1185VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
1186{
1187 for (unsigned i=0;i<pVM->cCPUs;i++)
1188 {
1189 switch(iStatusCode)
1190 {
1191 case VERR_VMX_INVALID_VMCS_FIELD:
1192 break;
1193
1194 case VERR_VMX_INVALID_VMCS_PTR:
1195 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1196 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
1197 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
1198 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
1199 break;
1200
1201 case VERR_VMX_UNABLE_TO_START_VM:
1202 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1203 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1204#if 0 /* @todo dump the current control fields to the release log */
1205 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
1206 {
1207
1208 }
1209#endif
1210 break;
1211
1212 case VERR_VMX_UNABLE_TO_RESUME_VM:
1213 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
1214 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
1215 break;
1216
1217 case VERR_VMX_INVALID_VMXON_PTR:
1218 break;
1219 }
1220 }
1221}
1222
1223/**
1224 * Execute state save operation.
1225 *
1226 * @returns VBox status code.
1227 * @param pVM VM Handle.
1228 * @param pSSM SSM operation handle.
1229 */
1230static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
1231{
1232 int rc;
1233
1234 Log(("hwaccmR3Save:\n"));
1235
1236 for (unsigned i=0;i<pVM->cCPUs;i++)
1237 {
1238 /*
1239 * Save the basic bits - fortunately all the other things can be resynced on load.
1240 */
1241 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
1242 AssertRCReturn(rc, rc);
1243 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
1244 AssertRCReturn(rc, rc);
1245 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
1246 AssertRCReturn(rc, rc);
1247 }
1248
1249 return VINF_SUCCESS;
1250}
1251
1252/**
1253 * Execute state load operation.
1254 *
1255 * @returns VBox status code.
1256 * @param pVM VM Handle.
1257 * @param pSSM SSM operation handle.
1258 * @param u32Version Data layout version.
1259 */
1260static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1261{
1262 int rc;
1263
1264 Log(("hwaccmR3Load:\n"));
1265
1266 /*
1267 * Validate version.
1268 */
1269 if (u32Version != HWACCM_SSM_VERSION)
1270 {
1271 AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
1272 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1273 }
1274 for (unsigned i=0;i<pVM->cCPUs;i++)
1275 {
1276 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
1277 AssertRCReturn(rc, rc);
1278 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
1279 AssertRCReturn(rc, rc);
1280 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
1281 AssertRCReturn(rc, rc);
1282 }
1283 return VINF_SUCCESS;
1284}
1285
1286
1287
1288
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