VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 8112

Last change on this file since 8112 was 8112, checked in by vboxsync, 17 years ago

Another attempt at a proper check. (init order messed up the previous one)
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 86.0 KB
Line 
1/* $Id: CPUM.cpp 8112 2008-04-17 16:19:18Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager)
4 */
5
6/*
7 * Copyright (C) 2006-2007 innotek GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.215389.xyz. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/cpum.h>
24#include <VBox/cpumdis.h>
25#include <VBox/pgm.h>
26#include <VBox/mm.h>
27#include <VBox/selm.h>
28#include <VBox/dbgf.h>
29#include <VBox/patm.h>
30#include <VBox/ssm.h>
31#include "CPUMInternal.h"
32#include <VBox/vm.h>
33
34#include <VBox/param.h>
35#include <VBox/dis.h>
36#include <VBox/err.h>
37#include <VBox/log.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#include <iprt/string.h>
41#include <iprt/system.h>
42
43
44/*******************************************************************************
45* Defined Constants And Macros *
46*******************************************************************************/
47/** The saved state version. */
48#define CPUM_SAVED_STATE_VERSION 6
49
50
51/*******************************************************************************
52* Structures and Typedefs *
53*******************************************************************************/
54
55/**
56 * What kind of cpu info dump to performe.
57 */
58typedef enum CPUMDUMPTYPE
59{
60 CPUMDUMPTYPE_TERSE,
61 CPUMDUMPTYPE_DEFAULT,
62 CPUMDUMPTYPE_VERBOSE
63
64} CPUMDUMPTYPE, *PCPUMDUMPTYPE;
65
66
67/*******************************************************************************
68* Internal Functions *
69*******************************************************************************/
70static int cpumR3CpuIdInit(PVM pVM);
71static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
72static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
73static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
74static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
75static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
76static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
77static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
78
79
80/**
81 * Initializes the CPUM.
82 *
83 * @returns VBox status code.
84 * @param pVM The VM to operate on.
85 */
86CPUMR3DECL(int) CPUMR3Init(PVM pVM)
87{
88 LogFlow(("CPUMR3Init\n"));
89
90 /*
91 * Assert alignment and sizes.
92 */
93 AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
94 AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
95
96 /*
97 * Setup any fixed pointers and offsets.
98 */
99 pVM->cpum.s.offVM = RT_OFFSETOF(VM, cpum);
100 pVM->cpum.s.pCPUMHC = &pVM->cpum.s;
101 pVM->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
102 pVM->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVM->cpum.s.Hyper));
103
104 /* Hidden selector registers are invalid by default. */
105 pVM->cpum.s.fValidHiddenSelRegs = false;
106
107 /*
108 * Check that the CPU supports the minimum features we require.
109 */
110 /** @todo check the contract! */
111 if (!ASMHasCpuId())
112 {
113 Log(("The CPU doesn't support CPUID!\n"));
114 return VERR_UNSUPPORTED_CPU;
115 }
116 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
117
118 /* Setup the CR4 AND and OR masks used in the switcher */
119 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
120 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
121 {
122 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
123 /* No FXSAVE implies no SSE */
124 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
125 pVM->cpum.s.CR4.OrMask = 0;
126 }
127 else
128 {
129 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
130 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
131 }
132
133 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
134 {
135 Log(("The CPU doesn't support MMX!\n"));
136 return VERR_UNSUPPORTED_CPU;
137 }
138 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
139 {
140 Log(("The CPU doesn't support TSC!\n"));
141 return VERR_UNSUPPORTED_CPU;
142 }
143 /* Bogus on AMD? */
144 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
145 {
146 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
147 }
148
149 /*
150 * Setup hypervisor startup values.
151 */
152
153 /*
154 * Register saved state data item.
155 */
156 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
157 NULL, cpumR3Save, NULL,
158 NULL, cpumR3Load, NULL);
159 if (VBOX_FAILURE(rc))
160 return rc;
161
162 /*
163 * Register info handlers.
164 */
165 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
166 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
167 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
168 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
169 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
170
171 /*
172 * Initialize the Guest CPU state.
173 */
174 rc = cpumR3CpuIdInit(pVM);
175 if (VBOX_FAILURE(rc))
176 return rc;
177 CPUMR3Reset(pVM);
178 return VINF_SUCCESS;
179}
180
181
182/**
183 * Initializes the emulated CPU's cpuid information.
184 *
185 * @returns VBox status code.
186 * @param pVM The VM to operate on.
187 */
188static int cpumR3CpuIdInit(PVM pVM)
189{
190 PCPUM pCPUM = &pVM->cpum.s;
191 uint32_t i;
192
193 /*
194 * Get the host CPUIDs.
195 */
196 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
197 ASMCpuId_Idx_ECX(i, 0,
198 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
199 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
200 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
201 ASMCpuId(0x80000000 + i,
202 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
203 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
204 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
205 ASMCpuId(0xc0000000 + i,
206 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
207 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
208
209
210 /*
211 * Only report features we can support.
212 */
213 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
214 | X86_CPUID_FEATURE_EDX_VME
215 | X86_CPUID_FEATURE_EDX_DE
216 | X86_CPUID_FEATURE_EDX_PSE
217 | X86_CPUID_FEATURE_EDX_TSC
218 | X86_CPUID_FEATURE_EDX_MSR
219 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
220 | X86_CPUID_FEATURE_EDX_MCE
221 | X86_CPUID_FEATURE_EDX_CX8
222 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
223 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
224 //| X86_CPUID_FEATURE_EDX_SEP
225 //| X86_CPUID_FEATURE_EDX_MTRR - no MTRRs.
226 | X86_CPUID_FEATURE_EDX_PGE
227 //| X86_CPUID_FEATURE_EDX_MCA - not virtualized.
228 | X86_CPUID_FEATURE_EDX_CMOV
229 //| X86_CPUID_FEATURE_EDX_PAT - not virtualized.
230 //| X86_CPUID_FEATURE_EDX_PSE36 - not virtualized.
231 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
232 | X86_CPUID_FEATURE_EDX_CLFSH
233 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
234 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
235 | X86_CPUID_FEATURE_EDX_MMX
236 | X86_CPUID_FEATURE_EDX_FXSR
237 | X86_CPUID_FEATURE_EDX_SSE
238 | X86_CPUID_FEATURE_EDX_SSE2
239 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
240 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
241 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
242 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
243 | 0;
244 pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
245 | X86_CPUID_FEATURE_ECX_MONITOR
246 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
247 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
248 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
249 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
250 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
251 | 0;
252
253 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
254 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
255 | X86_CPUID_AMD_FEATURE_EDX_VME
256 | X86_CPUID_AMD_FEATURE_EDX_DE
257 | X86_CPUID_AMD_FEATURE_EDX_PSE
258 | X86_CPUID_AMD_FEATURE_EDX_TSC
259 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
260 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
261 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
262 | X86_CPUID_AMD_FEATURE_EDX_CX8
263 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
264 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
265 //| X86_CPUID_AMD_FEATURE_EDX_SEP
266 //| X86_CPUID_AMD_FEATURE_EDX_MTRR - not virtualized.
267 | X86_CPUID_AMD_FEATURE_EDX_PGE
268 //| X86_CPUID_AMD_FEATURE_EDX_MCA - not virtualized.
269 | X86_CPUID_AMD_FEATURE_EDX_CMOV
270 | X86_CPUID_AMD_FEATURE_EDX_PAT
271 //| X86_CPUID_AMD_FEATURE_EDX_PSE36 - not virtualized.
272 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
273 | X86_CPUID_AMD_FEATURE_EDX_MMX
274 | X86_CPUID_AMD_FEATURE_EDX_FXSR
275 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
276 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - not yet.
277 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
278 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
279 | 0;
280 pCPUM->aGuestCpuIdExt[1].ecx &= 0//X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
281 | 0;
282
283 /*
284 * Hide HTT, multicode, SMP, whatever.
285 * (APIC-ID := 0 and #LogCpus := 0)
286 */
287 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
288
289 /*
290 * Determin the default.
291 *
292 * Intel returns values of the highest standard function, while AMD
293 * returns zeros. VIA on the other hand seems to returning nothing or
294 * perhaps some random garbage, we don't try duplicate this behavior.
295 */
296 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
297 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
298 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
299
300 /*
301 * Limit it the number of entries and fill the remaining with the defaults.
302 *
303 * The limits are masking off stuff about power saving and similar, this
304 * is perhaps a bit crudely done as there is probably some relatively harmless
305 * info too in these leaves (like words about having a constant TSC).
306 */
307 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
308 pCPUM->aGuestCpuIdStd[0].eax = 2;
309 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
310 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
311
312 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000004))
313 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000004);
314 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
315 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
316 : 0;
317 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
318 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
319
320 /*
321 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
322 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
323 * We don't support more than 1 processor.
324 */
325 pCPUM->aGuestCpuIdStd[4].eax = 0;
326
327 /*
328 * Centaur stuff (VIA).
329 *
330 * The important part here (we think) is to make sure the 0xc0000000
331 * function returns 0xc0000001. As for the features, we don't currently
332 * let on about any of those... 0xc0000002 seems to be some
333 * temperature/hz/++ stuff, include it as well (static).
334 */
335 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
336 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
337 {
338 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
339 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
340 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
341 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
342 i++)
343 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
344 }
345 else
346 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
347 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
348
349
350 /*
351 * Load CPUID overrides from configuration.
352 */
353 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
354 uint32_t cElements = ELEMENTS(pCPUM->aGuestCpuIdStd);
355 for (i=0;; )
356 {
357 while (cElements-- > 0)
358 {
359 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
360 if (pNode)
361 {
362 uint32_t u32;
363 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
364 if (VBOX_SUCCESS(rc))
365 pCpuId->eax = u32;
366 else
367 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
368
369 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
370 if (VBOX_SUCCESS(rc))
371 pCpuId->ebx = u32;
372 else
373 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
374
375 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
376 if (VBOX_SUCCESS(rc))
377 pCpuId->ecx = u32;
378 else
379 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
380
381 rc = CFGMR3QueryU32(pNode, "edx", &u32);
382 if (VBOX_SUCCESS(rc))
383 pCpuId->edx = u32;
384 else
385 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
386 }
387 pCpuId++;
388 i++;
389 }
390
391 /* next */
392 if ((i & UINT32_C(0xc0000000)) == 0)
393 {
394 pCpuId = &pCPUM->aGuestCpuIdExt[0];
395 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
396 i = UINT32_C(0x80000000);
397 }
398 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
399 {
400 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
401 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
402 i = UINT32_C(0xc0000000);
403 }
404 else
405 break;
406 }
407
408#ifndef PGM_WITH_BROKEN_32PAE_SWITCHER
409 /* Check if PAE was explicitely enabled by the user. */
410 bool fEnable = false;
411 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
412 if (VBOX_SUCCESS(rc) && fEnable)
413 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
414#endif
415
416 /*
417 * Log the cpuid and we're good.
418 */
419 LogRel(("Logical host processors: %d, processor active mask: %08x\n",
420 RTSystemProcessorGetCount(), RTSystemProcessorGetActiveMask()));
421 LogRel(("************************* CPUID dump ************************\n"));
422 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
423 LogRel(("\n"));
424 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
425 LogRel(("******************** End of CPUID dump **********************\n"));
426 return VINF_SUCCESS;
427}
428
429
430
431
432/**
433 * Applies relocations to data and code managed by this
434 * component. This function will be called at init and
435 * whenever the VMM need to relocate it self inside the GC.
436 *
437 * The CPUM will update the addresses used by the switcher.
438 *
439 * @param pVM The VM.
440 */
441CPUMR3DECL(void) CPUMR3Relocate(PVM pVM)
442{
443 LogFlow(("CPUMR3Relocate\n"));
444 /*
445 * Switcher pointers.
446 */
447 pVM->cpum.s.pCPUMGC = VM_GUEST_ADDR(pVM, &pVM->cpum.s);
448 pVM->cpum.s.pHyperCoreGC = MMHyperCCToGC(pVM, pVM->cpum.s.pHyperCoreR3);
449 Assert(pVM->cpum.s.pHyperCoreGC != NIL_RTGCPTR);
450}
451
452
453/**
454 * Queries the pointer to the internal CPUMCTX structure
455 *
456 * @returns VBox status code.
457 * @param pVM Handle to the virtual machine.
458 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
459 */
460CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, GCPTRTYPE(PCPUMCTX) *ppCtx)
461{
462 LogFlow(("CPUMR3QueryGuestCtxGCPtr\n"));
463 /*
464 * Store the address. (Later we might check how's calling, thus the RC.)
465 */
466 *ppCtx = VM_GUEST_ADDR(pVM, &pVM->cpum.s.Guest);
467 return VINF_SUCCESS;
468}
469
470
471/**
472 * Terminates the CPUM.
473 *
474 * Termination means cleaning up and freeing all resources,
475 * the VM it self is at this point powered off or suspended.
476 *
477 * @returns VBox status code.
478 * @param pVM The VM to operate on.
479 */
480CPUMR3DECL(int) CPUMR3Term(PVM pVM)
481{
482 /** @todo */
483 return 0;
484}
485
486
487/**
488 * Resets the CPU.
489 *
490 * @returns VINF_SUCCESS.
491 * @param pVM The VM handle.
492 */
493CPUMR3DECL(void) CPUMR3Reset(PVM pVM)
494{
495 PCPUMCTX pCtx = &pVM->cpum.s.Guest;
496
497 /*
498 * Initialize everything to ZERO first.
499 */
500 uint32_t fUseFlags = pVM->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
501 memset(pCtx, 0, sizeof(*pCtx));
502 pVM->cpum.s.fUseFlags = fUseFlags;
503
504 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
505 pCtx->eip = 0x0000fff0;
506 pCtx->edx = 0x00000600; /* P6 processor */
507 pCtx->eflags.Bits.u1Reserved0 = 1;
508
509 pCtx->cs = 0xf000;
510 pCtx->csHid.u32Base = 0xffff0000;
511 pCtx->csHid.u32Limit = 0x0000ffff;
512 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
513 pCtx->csHid.Attr.n.u1Present = 1;
514 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
515
516 pCtx->dsHid.u32Limit = 0x0000ffff;
517 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
518 pCtx->dsHid.Attr.n.u1Present = 1;
519 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
520
521 pCtx->esHid.u32Limit = 0x0000ffff;
522 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
523 pCtx->esHid.Attr.n.u1Present = 1;
524 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
525
526 pCtx->fsHid.u32Limit = 0x0000ffff;
527 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
528 pCtx->fsHid.Attr.n.u1Present = 1;
529 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
530
531 pCtx->gsHid.u32Limit = 0x0000ffff;
532 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
533 pCtx->gsHid.Attr.n.u1Present = 1;
534 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
535
536 pCtx->ssHid.u32Limit = 0x0000ffff;
537 pCtx->ssHid.Attr.n.u1Present = 1;
538 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
539 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
540
541 pCtx->idtr.cbIdt = 0xffff;
542 pCtx->gdtr.cbGdt = 0xffff;
543
544 pCtx->ldtrHid.u32Limit = 0xffff;
545 pCtx->ldtrHid.Attr.n.u1Present = 1;
546 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
547
548 pCtx->trHid.u32Limit = 0xffff;
549 pCtx->trHid.Attr.n.u1Present = 1;
550 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
551
552 pCtx->dr6 = 0xFFFF0FF0;
553 pCtx->dr7 = 0x400;
554
555 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
556 pCtx->fpu.FCW = 0x37f;
557
558 /* Init PAT MSR */
559 pCtx->msrPAT = 0x0007040600070406ULL; /* @todo correct? */
560}
561
562
563
564/**
565 * Execute state save operation.
566 *
567 * @returns VBox status code.
568 * @param pVM VM Handle.
569 * @param pSSM SSM operation handle.
570 */
571static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
572{
573 /*
574 * Save.
575 */
576 SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
577 SSMR3PutMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
578 SSMR3PutU32(pSSM, pVM->cpum.s.fUseFlags);
579 SSMR3PutU32(pSSM, pVM->cpum.s.fChanged);
580
581 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
582 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
583
584 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
585 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
586
587 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
588 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
589
590 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
591
592 /* Add the cpuid for checking that the cpu is unchanged. */
593 uint32_t au32CpuId[8] = {0};
594 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
595 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
596 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
597}
598
599
600/**
601 * Execute state load operation.
602 *
603 * @returns VBox status code.
604 * @param pVM VM Handle.
605 * @param pSSM SSM operation handle.
606 * @param u32Version Data layout version.
607 */
608static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
609{
610 /*
611 * Validate version.
612 */
613 if (u32Version != CPUM_SAVED_STATE_VERSION)
614 {
615 Log(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
616 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
617 }
618
619 /*
620 * Restore.
621 */
622 uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
623 uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
624 SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
625 pVM->cpum.s.Hyper.cr3 = uCR3;
626 pVM->cpum.s.Hyper.esp = uESP;
627 SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
628 SSMR3GetU32(pSSM, &pVM->cpum.s.fUseFlags);
629 SSMR3GetU32(pSSM, &pVM->cpum.s.fChanged);
630
631 uint32_t cElements;
632 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
633 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
634 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
635 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
636
637 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
638 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
639 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
640 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
641
642 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
643 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
644 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
645 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
646
647 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
648
649 /*
650 * Check that the basic cpuid id information is unchanged.
651 */
652 uint32_t au32CpuId[8] = {0};
653 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
654 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
655 uint32_t au32CpuIdSaved[8];
656 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
657 if (VBOX_SUCCESS(rc))
658 {
659 /* Ignore APIC ID (AMD specs). */
660 au32CpuId[5] &= ~0xff000000;
661 au32CpuIdSaved[5] &= ~0xff000000;
662 /* Ignore the number of Logical CPUs (AMD specs). */
663 au32CpuId[5] &= ~0x00ff0000;
664 au32CpuIdSaved[5] &= ~0x00ff0000;
665
666 /* do the compare */
667 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
668 {
669 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
670 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
671 "Saved=%.*Vhxs\n"
672 "Real =%.*Vhxs\n",
673 sizeof(au32CpuIdSaved), au32CpuIdSaved,
674 sizeof(au32CpuId), au32CpuId));
675 else
676 {
677 LogRel(("cpumR3Load: CpuId mismatch!\n"
678 "Saved=%.*Vhxs\n"
679 "Real =%.*Vhxs\n",
680 sizeof(au32CpuIdSaved), au32CpuIdSaved,
681 sizeof(au32CpuId), au32CpuId));
682 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
683 }
684 }
685 }
686
687 return rc;
688}
689
690
691/**
692 * Formats the EFLAGS value into mnemonics.
693 *
694 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
695 * @param efl The EFLAGS value.
696 */
697static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
698{
699 /*
700 * Format the flags.
701 */
702 static struct
703 {
704 const char *pszSet; const char *pszClear; uint32_t fFlag;
705 } s_aFlags[] =
706 {
707 { "vip",NULL, X86_EFL_VIP },
708 { "vif",NULL, X86_EFL_VIF },
709 { "ac", NULL, X86_EFL_AC },
710 { "vm", NULL, X86_EFL_VM },
711 { "rf", NULL, X86_EFL_RF },
712 { "nt", NULL, X86_EFL_NT },
713 { "ov", "nv", X86_EFL_OF },
714 { "dn", "up", X86_EFL_DF },
715 { "ei", "di", X86_EFL_IF },
716 { "tf", NULL, X86_EFL_TF },
717 { "nt", "pl", X86_EFL_SF },
718 { "nz", "zr", X86_EFL_ZF },
719 { "ac", "na", X86_EFL_AF },
720 { "po", "pe", X86_EFL_PF },
721 { "cy", "nc", X86_EFL_CF },
722 };
723 char *psz = pszEFlags;
724 for (unsigned i = 0; i < ELEMENTS(s_aFlags); i++)
725 {
726 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
727 if (pszAdd)
728 {
729 strcpy(psz, pszAdd);
730 psz += strlen(pszAdd);
731 *psz++ = ' ';
732 }
733 }
734 psz[-1] = '\0';
735}
736
737
738/**
739 * Formats a full register dump.
740 *
741 * @param pCtx The context to format.
742 * @param pCtxCore The context core to format.
743 * @param pHlp Output functions.
744 * @param enmType The dump type.
745 * @param pszPrefix Register name prefix.
746 */
747static void cpumR3InfoOne(PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
748{
749 /*
750 * Format the EFLAGS.
751 */
752 uint32_t efl = pCtxCore->eflags.u32;
753 char szEFlags[80];
754 cpumR3InfoFormatFlags(&szEFlags[0], efl);
755
756 /*
757 * Format the registers.
758 */
759 switch (enmType)
760 {
761 case CPUMDUMPTYPE_TERSE:
762 pHlp->pfnPrintf(pHlp,
763 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
764 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
765 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
766 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
767 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
768 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
769 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
770 break;
771
772 case CPUMDUMPTYPE_DEFAULT:
773 pHlp->pfnPrintf(pHlp,
774 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
775 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
776 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
777 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08x:%04x %sldtr=%04x\n"
778 ,
779 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
780 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
781 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
782 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
783 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
784 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
785 break;
786
787 case CPUMDUMPTYPE_VERBOSE:
788 pHlp->pfnPrintf(pHlp,
789 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
790 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
791 "%scs={%04x base=%08x limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
792 "%sds={%04x base=%08x limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
793 "%ses={%04x base=%08x limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
794 "%sfs={%04x base=%08x limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
795 "%sgs={%04x base=%08x limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
796 "%sss={%04x base=%08x limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
797 "%sgdtr=%08x:%04x %sidtr=%08x:%04x %seflags=%08x\n"
798 "%sldtr={%04x base=%08x limit=%08x flags=%08x}\n"
799 "%str ={%04x base=%08x limit=%08x flags=%08x}\n"
800 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
801 ,
802 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
803 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
804 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u32Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1,
805 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u32Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
806 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u32Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5,
807 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u32Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
808 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u32Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
809 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u32Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
810 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
811 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u32Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
812 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u32Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
813 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
814
815 pHlp->pfnPrintf(pHlp,
816 "FPU:\n"
817 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
818 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
819 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
820 ,
821 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
822 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
823 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
824 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
825
826
827 break;
828 }
829}
830
831
832/**
833 * Display all cpu states and any other cpum info.
834 *
835 * @param pVM VM Handle.
836 * @param pHlp The info helper functions.
837 * @param pszArgs Arguments, ignored.
838 */
839static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
840{
841 cpumR3InfoGuest(pVM, pHlp, pszArgs);
842 cpumR3InfoHyper(pVM, pHlp, pszArgs);
843 cpumR3InfoHost(pVM, pHlp, pszArgs);
844}
845
846
847/**
848 * Parses the info argument.
849 *
850 * The argument starts with 'verbose', 'terse' or 'default' and then
851 * continues with the comment string.
852 *
853 * @param pszArgs The pointer to the argument string.
854 * @param penmType Where to store the dump type request.
855 * @param ppszComment Where to store the pointer to the comment string.
856 */
857static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
858{
859 if (!pszArgs)
860 {
861 *penmType = CPUMDUMPTYPE_DEFAULT;
862 *ppszComment = "";
863 }
864 else
865 {
866 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
867 {
868 pszArgs += 5;
869 *penmType = CPUMDUMPTYPE_VERBOSE;
870 }
871 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
872 {
873 pszArgs += 5;
874 *penmType = CPUMDUMPTYPE_TERSE;
875 }
876 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
877 {
878 pszArgs += 7;
879 *penmType = CPUMDUMPTYPE_DEFAULT;
880 }
881 else
882 *penmType = CPUMDUMPTYPE_DEFAULT;
883 *ppszComment = RTStrStripL(pszArgs);
884 }
885}
886
887
888/**
889 * Display the guest cpu state.
890 *
891 * @param pVM VM Handle.
892 * @param pHlp The info helper functions.
893 * @param pszArgs Arguments, ignored.
894 */
895static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
896{
897 CPUMDUMPTYPE enmType;
898 const char *pszComment;
899 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
900 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
901 cpumR3InfoOne(&pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
902}
903
904
905/**
906 * Display the hypervisor cpu state.
907 *
908 * @param pVM VM Handle.
909 * @param pHlp The info helper functions.
910 * @param pszArgs Arguments, ignored.
911 */
912static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
913{
914 CPUMDUMPTYPE enmType;
915 const char *pszComment;
916 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
917 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
918 cpumR3InfoOne(&pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
919 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
920}
921
922
923/**
924 * Display the host cpu state.
925 *
926 * @param pVM VM Handle.
927 * @param pHlp The info helper functions.
928 * @param pszArgs Arguments, ignored.
929 */
930static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
931{
932 CPUMDUMPTYPE enmType;
933 const char *pszComment;
934 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
935 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
936
937 /*
938 * Format the EFLAGS.
939 */
940 PCPUMHOSTCTX pCtx = &pVM->cpum.s.Host;
941#if HC_ARCH_BITS == 32
942 uint32_t efl = pCtx->eflags.u32;
943#else
944 uint64_t efl = pCtx->rflags;
945#endif
946 char szEFlags[80];
947 cpumR3InfoFormatFlags(&szEFlags[0], efl);
948
949 /*
950 * Format the registers.
951 */
952#if HC_ARCH_BITS == 32
953# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
954 if (!(pCtx->efer & MSR_K6_EFER_LMA))
955# endif
956 {
957 pHlp->pfnPrintf(pHlp,
958 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
959 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
960 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
961 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
962 "dr0=%08RX64 dr1=%08RX64x dr2=%08RX64 dr3=%08RX64x dr6=%08RX64 dr7=%08RX64\n"
963 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
964 ,
965 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
966 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
967 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
968 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
969 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
970 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
971 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
972 }
973# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
974 else
975# endif
976#endif
977#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
978 {
979 pHlp->pfnPrintf(pHlp,
980 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
981 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
982 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
983 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
984 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
985 "r14=%016RX64 r15=%016RX64\n"
986 "iopl=%d %31s\n"
987 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
988 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
989 "cr4=%016RX64 cr8=%016RX64 ldtr=%04x tr=%04x\n"
990 "dr0=%016RX64 dr1=%016RX64 dr2=%016RX64\n"
991 "dr3=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
992 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
993 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
994 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
995 ,
996 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
997 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
998 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
999 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1000 pCtx->r11, pCtx->r12, pCtx->r13,
1001 pCtx->r14, pCtx->r15,
1002 X86_EFL_GET_IOPL(efl), szEFlags,
1003 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1004 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1005 pCtx->cr4, pCtx->cr8, pCtx->ldtr, pCtx->tr,
1006 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1007 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1008 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1009 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1010 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1011 }
1012#endif
1013}
1014
1015/**
1016 * Get L1 cache / TLS associativity.
1017 */
1018static const char *getCacheAss(unsigned u, char *pszBuf)
1019{
1020 if (u == 0)
1021 return "res0 ";
1022 if (u == 1)
1023 return "direct";
1024 if (u >= 256)
1025 return "???";
1026
1027 RTStrPrintf(pszBuf, 16, "%d way", u);
1028 return pszBuf;
1029}
1030
1031
1032/**
1033 * Get L2 cache soociativity.
1034 */
1035const char *getL2CacheAss(unsigned u)
1036{
1037 switch (u)
1038 {
1039 case 0: return "off ";
1040 case 1: return "direct";
1041 case 2: return "2 way ";
1042 case 3: return "res3 ";
1043 case 4: return "4 way ";
1044 case 5: return "res5 ";
1045 case 6: return "8 way ";
1046 case 7: return "res7 ";
1047 case 8: return "16 way";
1048 case 9: return "res9 ";
1049 case 10: return "res10 ";
1050 case 11: return "res11 ";
1051 case 12: return "res12 ";
1052 case 13: return "res13 ";
1053 case 14: return "res14 ";
1054 case 15: return "fully ";
1055 default:
1056 return "????";
1057 }
1058}
1059
1060
1061/**
1062 * Display the guest CpuId leaves.
1063 *
1064 * @param pVM VM Handle.
1065 * @param pHlp The info helper functions.
1066 * @param pszArgs "terse", "default" or "verbose".
1067 */
1068static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1069{
1070 /*
1071 * Parse the argument.
1072 */
1073 unsigned iVerbosity = 1;
1074 if (pszArgs)
1075 {
1076 pszArgs = RTStrStripL(pszArgs);
1077 if (!strcmp(pszArgs, "terse"))
1078 iVerbosity--;
1079 else if (!strcmp(pszArgs, "verbose"))
1080 iVerbosity++;
1081 }
1082
1083 /*
1084 * Start cracking.
1085 */
1086 CPUMCPUID Host;
1087 CPUMCPUID Guest;
1088 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1089
1090 pHlp->pfnPrintf(pHlp,
1091 " RAW Standard CPUIDs\n"
1092 " Function eax ebx ecx edx\n");
1093 for (unsigned i = 0; i < ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1094 {
1095 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1096 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1097
1098 pHlp->pfnPrintf(pHlp,
1099 "Gst: %08x %08x %08x %08x %08x%s\n"
1100 "Hst: %08x %08x %08x %08x\n",
1101 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1102 i <= cStdMax ? "" : "*",
1103 Host.eax, Host.ebx, Host.ecx, Host.edx);
1104 }
1105
1106 /*
1107 * If verbose, decode it.
1108 */
1109 if (iVerbosity)
1110 {
1111 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1112 pHlp->pfnPrintf(pHlp,
1113 "Name: %.04s%.04s%.04s\n"
1114 "Supports: 0-%x\n",
1115 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1116 }
1117
1118 /*
1119 * Get Features.
1120 */
1121 if (cStdMax >= 1 && iVerbosity)
1122 {
1123 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1124 uint32_t uEAX = Guest.eax;
1125
1126 pHlp->pfnPrintf(pHlp,
1127 "Family: %d \tExtended: %d \tEffectiv: %d\n"
1128 "Model: %d \tExtended: %d \tEffectiv: %d\n"
1129 "Stepping: %d\n"
1130 "APIC ID: %#04x\n"
1131 "Logical CPUs: %d\n"
1132 "CLFLUSH Size: %d\n"
1133 "Brand ID: %#04x\n",
1134 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ((uEAX >> 8) & 0xf) + (((uEAX >> 8) & 0xf) == 0xf ? (uEAX >> 20) & 0x7f : 0),
1135 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ((uEAX >> 4) & 0xf) | (((uEAX >> 4) & 0xf) == 0xf ? (uEAX >> 16) & 0x0f : 0),
1136 (uEAX >> 0) & 0xf,
1137 (Guest.ebx >> 24) & 0xff,
1138 (Guest.ebx >> 16) & 0xff,
1139 (Guest.ebx >> 8) & 0xff,
1140 (Guest.ebx >> 0) & 0xff);
1141 if (iVerbosity == 1)
1142 {
1143 uint32_t uEDX = Guest.edx;
1144 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1145 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1146 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1147 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1148 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1149 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1150 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1151 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1152 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1153 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1154 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1155 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1156 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1157 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1158 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1159 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1160 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1161 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1162 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1163 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1164 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1165 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1166 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1167 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1168 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1169 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1170 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1171 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1172 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1173 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1174 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1175 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1176 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1177 pHlp->pfnPrintf(pHlp, "\n");
1178
1179 uint32_t uECX = Guest.ecx;
1180 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1181 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1182 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1183 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1184 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1185 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1186 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1187 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1188 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1189 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1190 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1191 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1192 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1193 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1194 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1195 for (unsigned iBit = 14; iBit < 32; iBit++)
1196 if (uECX & RT_BIT(iBit))
1197 pHlp->pfnPrintf(pHlp, " %d", iBit);
1198 pHlp->pfnPrintf(pHlp, "\n");
1199 }
1200 else
1201 {
1202 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1203
1204 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1205 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1206 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1207 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1208
1209 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1210 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1211 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1212 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1213 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1214 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1215 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1216 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1217 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1218 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1219 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1220 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1221 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1222 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1223 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1224 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1225 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1226 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1227 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1228 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1229 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1230 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1231 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1232 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1233 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1234 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1235 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1236 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1237 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1238 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1239 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1240 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1241 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1242
1243 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1244 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1245 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1246 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1247 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1248 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1249 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1250 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1251 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1252 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1253 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1254 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1255 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1256 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1257 }
1258 }
1259 if (cStdMax >= 2 && iVerbosity)
1260 {
1261 /** @todo */
1262 }
1263
1264 /*
1265 * Extended.
1266 * Implemented after AMD specs.
1267 */
1268 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1269
1270 pHlp->pfnPrintf(pHlp,
1271 "\n"
1272 " RAW Extended CPUIDs\n"
1273 " Function eax ebx ecx edx\n");
1274 for (unsigned i = 0; i < ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1275 {
1276 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1277 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1278
1279 pHlp->pfnPrintf(pHlp,
1280 "Gst: %08x %08x %08x %08x %08x%s\n"
1281 "Hst: %08x %08x %08x %08x\n",
1282 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1283 i <= cExtMax ? "" : "*",
1284 Host.eax, Host.ebx, Host.ecx, Host.edx);
1285 }
1286
1287 /*
1288 * Understandable output
1289 */
1290 if (iVerbosity && cExtMax >= 0)
1291 {
1292 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1293 pHlp->pfnPrintf(pHlp,
1294 "Ext Name: %.4s%.4s%.4s\n"
1295 "Ext Supports: 0x80000000-%#010x\n",
1296 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1297 }
1298
1299 if (iVerbosity && cExtMax >= 1)
1300 {
1301 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1302 uint32_t uEAX = Guest.eax;
1303 pHlp->pfnPrintf(pHlp,
1304 "Family: %d \tExtended: %d \tEffectiv: %d\n"
1305 "Model: %d \tExtended: %d \tEffectiv: %d\n"
1306 "Stepping: %d\n"
1307 "Brand ID: %#05x\n",
1308 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ((uEAX >> 8) & 0xf) + (((uEAX >> 8) & 0xf) == 0xf ? (uEAX >> 20) & 0x7f : 0),
1309 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ((uEAX >> 4) & 0xf) | (((uEAX >> 4) & 0xf) == 0xf ? (uEAX >> 16) & 0x0f : 0),
1310 (uEAX >> 0) & 0xf,
1311 Guest.ebx & 0xfff);
1312
1313 if (iVerbosity == 1)
1314 {
1315 uint32_t uEDX = Guest.edx;
1316 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1317 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1318 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1319 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1320 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1321 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1322 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1323 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1324 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1325 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1326 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1327 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1328 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1329 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1330 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1331 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1332 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1333 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1334 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1335 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1336 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1337 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1338 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1339 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1340 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1341 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1342 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1343 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1344 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1345 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1346 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1347 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1348 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1349 pHlp->pfnPrintf(pHlp, "\n");
1350
1351 uint32_t uECX = Guest.ecx;
1352 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1353 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1354 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1355 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1356 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1357 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1358 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1359 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1360 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1361 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1362 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1363 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1364 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1365 for (unsigned iBit = 5; iBit < 32; iBit++)
1366 if (uECX & RT_BIT(iBit))
1367 pHlp->pfnPrintf(pHlp, " %d", iBit);
1368 pHlp->pfnPrintf(pHlp, "\n");
1369 }
1370 else
1371 {
1372 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1373
1374 uint32_t uEdxGst = Guest.edx;
1375 uint32_t uEdxHst = Host.edx;
1376 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1377 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1378 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1379 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1380 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1381 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1382 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1383 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1384 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1385 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1386 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1387 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1388 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1389 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1390 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1391 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1392 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1393 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1394 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1395 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1396 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1397 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1398 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1399 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1400 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1401 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1402 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1403 pHlp->pfnPrintf(pHlp, "26 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1404 pHlp->pfnPrintf(pHlp, "27 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1405 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1406 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1407 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1408 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1409
1410 uint32_t uEcxGst = Guest.ecx;
1411 uint32_t uEcxHst = Host.ecx;
1412 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1413 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1414 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1415 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1416 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1417 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1418 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1419 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1420 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1421 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1422 pHlp->pfnPrintf(pHlp, "11:10 - Reserved = %#x (%#x)\n", (uEcxGst >> 10) & 3, (uEcxHst >> 10) & 3);
1423 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1424 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1425 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1426 }
1427 }
1428
1429 if (iVerbosity && cExtMax >= 2)
1430 {
1431 char szString[4*4*3+1] = {0};
1432 uint32_t *pu32 = (uint32_t *)szString;
1433 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1434 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1435 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1436 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1437 if (cExtMax >= 3)
1438 {
1439 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1440 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1441 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1442 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1443 }
1444 if (cExtMax >= 4)
1445 {
1446 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1447 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1448 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1449 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1450 }
1451 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1452 }
1453
1454 if (iVerbosity && cExtMax >= 5)
1455 {
1456 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1457 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1458 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1459 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1460 char sz1[32];
1461 char sz2[32];
1462
1463 pHlp->pfnPrintf(pHlp,
1464 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1465 "TLB 2/4M Data: %s %3d entries\n",
1466 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1467 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1468 pHlp->pfnPrintf(pHlp,
1469 "TLB 4K Instr/Uni: %s %3d entries\n"
1470 "TLB 4K Data: %s %3d entries\n",
1471 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1472 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1473 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1474 "L1 Instr Cache Lines Per Tag: %d\n"
1475 "L1 Instr Cache Associativity: %s\n"
1476 "L1 Instr Cache Size: %d KB\n",
1477 (uEDX >> 0) & 0xff,
1478 (uEDX >> 8) & 0xff,
1479 getCacheAss((uEDX >> 16) & 0xff, sz1),
1480 (uEDX >> 24) & 0xff);
1481 pHlp->pfnPrintf(pHlp,
1482 "L1 Data Cache Line Size: %d bytes\n"
1483 "L1 Data Cache Lines Per Tag: %d\n"
1484 "L1 Data Cache Associativity: %s\n"
1485 "L1 Data Cache Size: %d KB\n",
1486 (uECX >> 0) & 0xff,
1487 (uECX >> 8) & 0xff,
1488 getCacheAss((uECX >> 16) & 0xff, sz1),
1489 (uECX >> 24) & 0xff);
1490 }
1491
1492 if (iVerbosity && cExtMax >= 6)
1493 {
1494 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1495 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1496 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1497
1498 pHlp->pfnPrintf(pHlp,
1499 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1500 "L2 TLB 2/4M Data: %s %4d entries\n",
1501 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1502 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1503 pHlp->pfnPrintf(pHlp,
1504 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
1505 "L2 TLB 4K Data: %s %4d entries\n",
1506 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1507 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1508 pHlp->pfnPrintf(pHlp,
1509 "L2 Cache Line Size: %d bytes\n"
1510 "L2 Cache Lines Per Tag: %d\n"
1511 "L2 Cache Associativity: %s\n"
1512 "L2 Cache Size: %d KB\n",
1513 (uEDX >> 0) & 0xff,
1514 (uEDX >> 8) & 0xf,
1515 getL2CacheAss((uEDX >> 12) & 0xf),
1516 (uEDX >> 16) & 0xffff);
1517 }
1518
1519 if (iVerbosity && cExtMax >= 7)
1520 {
1521 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1522
1523 pHlp->pfnPrintf(pHlp, "APM Features: ");
1524 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1525 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1526 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1527 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1528 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1529 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1530 for (unsigned iBit = 6; iBit < 32; iBit++)
1531 if (uEDX & RT_BIT(iBit))
1532 pHlp->pfnPrintf(pHlp, " %d", iBit);
1533 pHlp->pfnPrintf(pHlp, "\n");
1534 }
1535
1536 if (iVerbosity && cExtMax >= 8)
1537 {
1538 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
1539 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
1540
1541 pHlp->pfnPrintf(pHlp,
1542 "Physical Address Width: %d bits\n"
1543 "Virtual Address Width: %d bits\n",
1544 (uEAX >> 0) & 0xff,
1545 (uEAX >> 8) & 0xff);
1546 pHlp->pfnPrintf(pHlp,
1547 "Physical Core Count: %d\n",
1548 (uECX >> 0) & 0xff);
1549 }
1550
1551
1552 /*
1553 * Centaur.
1554 */
1555 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
1556
1557 pHlp->pfnPrintf(pHlp,
1558 "\n"
1559 " RAW Centaur CPUIDs\n"
1560 " Function eax ebx ecx edx\n");
1561 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
1562 {
1563 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
1564 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1565
1566 pHlp->pfnPrintf(pHlp,
1567 "Gst: %08x %08x %08x %08x %08x%s\n"
1568 "Hst: %08x %08x %08x %08x\n",
1569 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1570 i <= cCentaurMax ? "" : "*",
1571 Host.eax, Host.ebx, Host.ecx, Host.edx);
1572 }
1573
1574 /*
1575 * Understandable output
1576 */
1577 if (iVerbosity && cCentaurMax >= 0)
1578 {
1579 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
1580 pHlp->pfnPrintf(pHlp,
1581 "Centaur Supports: 0xc0000000-%#010x\n",
1582 Guest.eax);
1583 }
1584
1585 if (iVerbosity && cCentaurMax >= 1)
1586 {
1587 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1588 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
1589 uint32_t uEdxHst = Host.edx;
1590
1591 if (iVerbosity == 1)
1592 {
1593 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
1594 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
1595 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
1596 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
1597 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
1598 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
1599 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
1600 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
1601 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
1602 /* possibly indicating MM/HE and MM/HE-E on older chips... */
1603 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
1604 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
1605 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
1606 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
1607 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
1608 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
1609 for (unsigned iBit = 14; iBit < 32; iBit++)
1610 if (uEdxGst & RT_BIT(iBit))
1611 pHlp->pfnPrintf(pHlp, " %d", iBit);
1612 pHlp->pfnPrintf(pHlp, "\n");
1613 }
1614 else
1615 {
1616 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1617 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1618 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1619 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1620 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1621 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1622 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1623 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1624 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1625 /* possibly indicating MM/HE and MM/HE-E on older chips... */
1626 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1627 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1628 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1629 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1630 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1631 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1632 for (unsigned iBit = 14; iBit < 32; iBit++)
1633 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
1634 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
1635 pHlp->pfnPrintf(pHlp, "\n");
1636 }
1637 }
1638}
1639
1640
1641/**
1642 * Structure used when disassembling and instructions in DBGF.
1643 * This is used so the reader function can get the stuff it needs.
1644 */
1645typedef struct CPUMDISASSTATE
1646{
1647 /** Pointer to the CPU structure. */
1648 PDISCPUSTATE pCpu;
1649 /** The VM handle. */
1650 PVM pVM;
1651 /** Pointer to the first byte in the segemnt. */
1652 RTGCUINTPTR GCPtrSegBase;
1653 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
1654 RTGCUINTPTR GCPtrSegEnd;
1655 /** The size of the segment minus 1. */
1656 RTGCUINTPTR cbSegLimit;
1657 /** Pointer to the current page - HC Ptr. */
1658 void const *pvPageHC;
1659 /** Pointer to the current page - GC Ptr. */
1660 RTGCPTR pvPageGC;
1661 /** The lock information that PGMPhysReleasePageMappingLock needs. */
1662 PGMPAGEMAPLOCK PageMapLock;
1663 /** Whether the PageMapLock is valid or not. */
1664 bool fLocked;
1665} CPUMDISASSTATE, *PCPUMDISASSTATE;
1666
1667
1668/**
1669 * Instruction reader.
1670 *
1671 * @returns VBox status code.
1672 * @param PtrSrc Address to read from.
1673 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
1674 * @param pu8Dst Where to store the bytes.
1675 * @param cbRead Number of bytes to read.
1676 * @param uDisCpu Pointer to the disassembler cpu state.
1677 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
1678 */
1679static DECLCALLBACK(int) cpumR3DisasInstrRead(RTHCUINTPTR PtrSrc, uint8_t *pu8Dst, uint32_t cbRead, void *uDisCpu)
1680{
1681 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
1682 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
1683 Assert(cbRead > 0);
1684 for (;;)
1685 {
1686 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
1687
1688 /* Need to update the page translation? */
1689 if ( !pState->pvPageHC
1690 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
1691 {
1692 int rc = VINF_SUCCESS;
1693
1694 /* translate the address */
1695 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
1696 if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
1697 {
1698 pState->pvPageHC = MMHyperGC2HC(pState->pVM, pState->pvPageGC);
1699 if (!pState->pvPageHC)
1700 rc = VERR_INVALID_POINTER;
1701 }
1702 else
1703 {
1704 /* Release mapping lock previously acquired. */
1705 if (pState->fLocked)
1706 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
1707 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageHC, &pState->PageMapLock);
1708 pState->fLocked = RT_SUCCESS_NP(rc);
1709 }
1710 if (VBOX_FAILURE(rc))
1711 {
1712 pState->pvPageHC = NULL;
1713 return rc;
1714 }
1715 }
1716
1717 /* check the segemnt limit */
1718 if (PtrSrc > pState->cbSegLimit)
1719 return VERR_OUT_OF_SELECTOR_BOUNDS;
1720
1721 /* calc how much we can read */
1722 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
1723 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
1724 if (cb > cbSeg && !cbSeg)
1725 cb = cbSeg;
1726 if (cb > cbRead)
1727 cb = cbRead;
1728
1729 /* read and advance */
1730 memcpy(pu8Dst, (char *)pState->pvPageHC + (GCPtr & PAGE_OFFSET_MASK), cb);
1731 cbRead -= cb;
1732 if (!cbRead)
1733 return VINF_SUCCESS;
1734 pu8Dst += cb;
1735 PtrSrc += cb;
1736 }
1737}
1738
1739
1740/**
1741 * Disassemble an instruction and return the information in the provided structure.
1742 *
1743 * @returns VBox status code.
1744 * @param pVM VM Handle
1745 * @param pCtx CPU context
1746 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
1747 * @param pCpu Disassembly state
1748 * @param pszPrefix String prefix for logging (debug only)
1749 *
1750 */
1751CPUMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
1752{
1753 CPUMDISASSTATE State;
1754 int rc;
1755
1756 State.pCpu = pCpu;
1757 State.pvPageGC = 0;
1758 State.pvPageHC = NULL;
1759 State.pVM = pVM;
1760 State.fLocked = false;
1761
1762 /*
1763 * Get selector information.
1764 */
1765 if ( (pCtx->cr0 & X86_CR0_PE)
1766 && pCtx->eflags.Bits.u1VM == 0)
1767 {
1768 if (CPUMAreHiddenSelRegsValid(pVM))
1769 {
1770 State.GCPtrSegBase = pCtx->csHid.u32Base;
1771 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u32Base;
1772 State.cbSegLimit = pCtx->csHid.u32Limit;
1773 pCpu->mode = pCtx->csHid.Attr.n.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
1774 }
1775 else
1776 {
1777 SELMSELINFO SelInfo;
1778
1779 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
1780 if (!VBOX_SUCCESS(rc))
1781 {
1782 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1783 return rc;
1784 }
1785
1786 /*
1787 * Validate the selector.
1788 */
1789 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
1790 if (!VBOX_SUCCESS(rc))
1791 {
1792 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1793 return rc;
1794 }
1795 State.GCPtrSegBase = SelInfo.GCPtrBase;
1796 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
1797 State.cbSegLimit = SelInfo.cbLimit;
1798 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
1799 }
1800 }
1801 else
1802 {
1803 /* real or V86 mode */
1804 pCpu->mode = CPUMODE_16BIT;
1805 State.GCPtrSegBase = pCtx->cs * 16;
1806 State.GCPtrSegEnd = 0xFFFFFFFF;
1807 State.cbSegLimit = 0xFFFFFFFF;
1808 }
1809
1810 /*
1811 * Disassemble the instruction.
1812 */
1813 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
1814 pCpu->apvUserData[0] = &State;
1815
1816 uint32_t cbInstr;
1817#ifdef LOG_ENABLED
1818 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
1819 if (VBOX_SUCCESS(rc))
1820 {
1821#else
1822 char szOutput[160];
1823 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
1824 if (VBOX_SUCCESS(rc))
1825 {
1826 /* log it */
1827 if (pszPrefix)
1828 Log(("%s: %s", pszPrefix, szOutput));
1829 else
1830 Log(("%s", szOutput));
1831#endif
1832 rc = VINF_SUCCESS;
1833 }
1834 else
1835 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv rc=%Vrc\n", pCtx->cs, GCPtrPC, rc));
1836
1837 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
1838 if (State.fLocked)
1839 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
1840
1841 return rc;
1842}
1843
1844
1845#ifdef DEBUG
1846/**
1847 * Disassemble an instruction and dump it to the log
1848 *
1849 * @returns VBox status code.
1850 * @param pVM VM Handle
1851 * @param pCtx CPU context
1852 * @param pc GC instruction pointer
1853 * @param prefix String prefix for logging
1854 * @deprecated Use DBGFR3DisasInstrCurrentLog().
1855 *
1856 */
1857CPUMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix)
1858{
1859 DISCPUSTATE cpu;
1860
1861 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
1862}
1863
1864/**
1865 * Disassemble an instruction and dump it to the log
1866 *
1867 * @returns VBox status code.
1868 * @param pVM VM Handle
1869 * @param pCtx CPU context
1870 * @param pc GC instruction pointer
1871 * @param prefix String prefix for logging
1872 * @param nrInstructions
1873 *
1874 */
1875CPUMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix, int nrInstructions)
1876{
1877 for(int i=0;i<nrInstructions;i++)
1878 {
1879 DISCPUSTATE cpu;
1880
1881 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
1882 pc += cpu.opsize;
1883 }
1884}
1885
1886#endif
1887
1888#ifdef DEBUG
1889/**
1890 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
1891 *
1892 * @internal
1893 */
1894CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
1895{
1896 pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
1897}
1898#endif
1899
1900
1901/**
1902 * API for controlling a few of the CPU features found in CR4.
1903 *
1904 * Currently only X86_CR4_TSD is accepted as input.
1905 *
1906 * @returns VBox status code.
1907 *
1908 * @param pVM The VM handle.
1909 * @param fOr The CR4 OR mask.
1910 * @param fAnd The CR4 AND mask.
1911 */
1912CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
1913{
1914 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
1915 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
1916
1917 pVM->cpum.s.CR4.OrMask &= fAnd;
1918 pVM->cpum.s.CR4.OrMask |= fOr;
1919
1920 return VINF_SUCCESS;
1921}
1922
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