ConsoleImplConfigArmV8.cpp@ 108746

Last change on this file since 108746 was 108746, checked in by vboxsync, 2 months ago
Main: bugref:10877 Enable LPIs when GITS is configured for the VM.
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1	/* $Id: ConsoleImplConfigArmV8.cpp 108746 2025-03-26 07:46:17Z vboxsync $ */
2	/** @file
3	* VBox Console COM Class implementation - VM Configuration Bits for ARMv8.
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.215389.xyz.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_MAIN_CONSOLE
33	#include "LoggingNew.h"
34
35	#include "ConsoleImpl.h"
36	#include "ResourceStoreImpl.h"
37	#include "Global.h"
38	#include "VMMDev.h"
39
40	// generated header
41	#include "SchemaDefs.h"
42
43	#include "AutoCaller.h"
44
45	#include <iprt/buildconfig.h>
46	#include <iprt/ctype.h>
47	#include <iprt/dir.h>
48	#include <iprt/fdt.h>
49	#include <iprt/file.h>
50	#include <iprt/param.h>
51	#include <iprt/path.h>
52	#include <iprt/string.h>
53	#include <iprt/system.h>
54	#if 0 /* enable to play with lots of memory. */
55	# include <iprt/env.h>
56	#endif
57	#include <iprt/stream.h>
58
59	#include <iprt/formats/arm-psci.h>
60
61	#include <VBox/vmm/vmmr3vtable.h>
62	#include <VBox/vmm/vmapi.h>
63	#include <VBox/err.h>
64	#include <VBox/param.h>
65	#include <VBox/version.h>
66	#include <VBox/platforms/vbox-armv8.h>
67
68	#include "BusAssignmentManager.h"
69	#include "ResourceAssignmentManager.h"
70	#include "SystemTableBuilder.h"
71	#ifdef VBOX_WITH_EXTPACK
72	# include "ExtPackManagerImpl.h"
73	#endif
74
75
76	/*********************************************************************************************************************************
77	* Internal Functions *
78	*********************************************************************************************************************************/
79
80	/* Darwin compile kludge */
81	#undef PVM
82
83	#ifdef VBOX_WITH_VIRT_ARMV8
84	/**
85	* Worker for configConstructor.
86	*
87	* @return VBox status code.
88	* @param pUVM The user mode VM handle.
89	* @param pVM The cross context VM handle.
90	* @param pVMM The VMM vtable.
91	* @param pAlock The automatic lock instance. This is for when we have
92	* to leave it in order to avoid deadlocks (ext packs and
93	* more).
94	*/
95	int Console::i_configConstructorArmV8(PUVM pUVM, PVM pVM, PCVMMR3VTABLE pVMM, AutoWriteLock *pAlock)
96	{
97	RT_NOREF(pVM /* when everything is disabled */);
98	ComPtr<IMachine> pMachine = i_machine();
99
100	HRESULT hrc;
101	Utf8Str strTmp;
102	Bstr bstr;
103
104	RTFDT hFdt = NIL_RTFDT;
105	int vrc = RTFdtCreateEmpty(&hFdt);
106	AssertRCReturn(vrc, vrc);
107
108	#define H() AssertLogRelMsgReturnStmt(!FAILED(hrc), ("hrc=%Rhrc\n", hrc), RTFdtDestroy(hFdt), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR)
109	#define VRC() AssertLogRelMsgReturnStmt(RT_SUCCESS(vrc), ("vrc=%Rrc\n", vrc), RTFdtDestroy(hFdt), vrc)
110
111	/*
112	* Get necessary objects and frequently used parameters.
113	*/
114	ComPtr<IVirtualBox> virtualBox;
115	hrc = pMachine->COMGETTER(Parent)(virtualBox.asOutParam()); H();
116
117	ComPtr<IHost> host;
118	hrc = virtualBox->COMGETTER(Host)(host.asOutParam()); H();
119
120	PlatformArchitecture_T platformArchHost;
121	hrc = host->COMGETTER(Architecture)(&platformArchHost); H();
122
123	ComPtr<ISystemProperties> systemProperties;
124	hrc = virtualBox->COMGETTER(SystemProperties)(systemProperties.asOutParam()); H();
125
126	ComPtr<IFirmwareSettings> firmwareSettings;
127	hrc = pMachine->COMGETTER(FirmwareSettings)(firmwareSettings.asOutParam()); H();
128
129	ComPtr<INvramStore> nvramStore;
130	hrc = pMachine->COMGETTER(NonVolatileStore)(nvramStore.asOutParam()); H();
131
132	hrc = pMachine->COMGETTER(HardwareUUID)(bstr.asOutParam()); H();
133	RTUUID HardwareUuid;
134	vrc = RTUuidFromUtf16(&HardwareUuid, bstr.raw());
135	AssertRCReturn(vrc, vrc);
136
137	ULONG cRamMBs;
138	hrc = pMachine->COMGETTER(MemorySize)(&cRamMBs); H();
139	uint64_t const cbRam = cRamMBs * (uint64_t)_1M;
140
141	ComPtr<IPlatform> platform;
142	hrc = pMachine->COMGETTER(Platform)(platform.asOutParam()); H();
143
144	/* Note: Should be guarded by VBOX_WITH_VIRT_ARMV8, but we check this anyway here. */
145	#if 1 /* For now we only support running ARM VMs on ARM hosts. */
146	PlatformArchitecture_T platformArchMachine;
147	hrc = platform->COMGETTER(Architecture)(&platformArchMachine); H();
148	if (platformArchMachine != platformArchHost)
149	return pVMM->pfnVMR3SetError(pUVM, VERR_PLATFORM_ARCH_NOT_SUPPORTED, RT_SRC_POS,
150	N_("VM platform architecture (%s) not supported on this host (%s)."),
151	Global::stringifyPlatformArchitecture(platformArchMachine),
152	Global::stringifyPlatformArchitecture(platformArchHost));
153	#endif
154
155	/* Get the ARM platform object. */
156	ComPtr<IPlatformARM> platformARM;
157	hrc = platform->COMGETTER(ARM)(platformARM.asOutParam()); H();
158
159	ComPtr<IPlatformProperties> pPlatformProperties;
160	hrc = platform->COMGETTER(Properties)(pPlatformProperties.asOutParam()); H();
161
162	ChipsetType_T chipsetType;
163	hrc = platform->COMGETTER(ChipsetType)(&chipsetType); H();
164
165	ULONG cCpus = 1;
166	hrc = pMachine->COMGETTER(CPUCount)(&cCpus); H();
167	Assert(cCpus);
168
169	ULONG ulCpuExecutionCap = 100;
170	hrc = pMachine->COMGETTER(CPUExecutionCap)(&ulCpuExecutionCap); H();
171
172	VMExecutionEngine_T enmExecEngine = VMExecutionEngine_NotSet;
173	hrc = pMachine->COMGETTER(VMExecutionEngine)(&enmExecEngine); H();
174
175	if ( enmExecEngine != VMExecutionEngine_Default
176	&& enmExecEngine != VMExecutionEngine_NativeApi)
177	{
178	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
179	N_("The ARM backend doesn't support any other execution engine than 'default' or 'native-api' right now."));
180	}
181
182	LogRel(("Guest architecture: ARM\n"));
183
184	Bstr osTypeId;
185	hrc = pMachine->COMGETTER(OSTypeId)(osTypeId.asOutParam()); H();
186	LogRel(("Guest OS type: '%s'\n", Utf8Str(osTypeId).c_str()));
187
188	BusAssignmentManager *pBusMgr = mBusMgr = BusAssignmentManager::createInstance(pVMM, chipsetType, IommuType_None);
189	ResourceAssignmentManager pResMgr = ResourceAssignmentManager::createInstance(pVMM, chipsetType, IommuType_None, 32 /cInterrupts*/,
190	_4G); /* Start looking for free MMIO regions at 4GiB downwards. */
191	SystemTableBuilder *pSysTblsBldAcpi = NULL;
192
193	/*
194	* ACPI
195	*/
196	BOOL fACPI;
197	hrc = firmwareSettings->COMGETTER(ACPIEnabled)(&fACPI); H();
198	if (fACPI)
199	pSysTblsBldAcpi = SystemTableBuilder::createInstance(kSystemTableType_Acpi);
200
201
202	/*
203	* Get root node first.
204	* This is the only node in the tree.
205	*/
206	PCFGMNODE pRoot = pVMM->pfnCFGMR3GetRootU(pUVM);
207	Assert(pRoot);
208
209	/*
210	* The VBox platform descriptor, FDT and ACPI tables will reside at the end of the 4GiB
211	* address space and we reserve 2MiB for those.
212	*/
213	RTGCPHYS cbPlatformDesc = _2M;
214	RTGCPHYS GCPhysPlatformDesc = VBOXPLATFORMARMV8_PHYS_ADDR - (cbPlatformDesc - _64K);
215
216	RTGCPHYS GCPhysRamBase = 128 * _1M;
217	RTGCPHYS cbRamBase = RT_MIN(cbRam, _4G - _512M - 128 * _1M);
218
219	RTGCPHYS GCPhysFw = 0;
220	RTGCPHYS cbFw = _64M;
221
222	// catching throws from InsertConfigString and friends.
223	try
224	{
225
226	/*
227	* Set the root (and VMM) level values.
228	*/
229	hrc = pMachine->COMGETTER(Name)(bstr.asOutParam()); H();
230	InsertConfigString(pRoot, "Name", bstr);
231	InsertConfigBytes(pRoot, "UUID", &HardwareUuid, sizeof(HardwareUuid));
232	InsertConfigInteger(pRoot, "NumCPUs", cCpus);
233	InsertConfigInteger(pRoot, "CpuExecutionCap", ulCpuExecutionCap);
234	InsertConfigInteger(pRoot, "TimerMillies", 10);
235
236	/*
237	* NEM
238	*/
239	PCFGMNODE pNEM;
240	InsertConfigNode(pRoot, "NEM", &pNEM);
241
242	uint32_t idPHandleIntCtrl = RTFdtPHandleAllocate(hFdt);
243	Assert(idPHandleIntCtrl != UINT32_MAX);
244	uint32_t idPHandleIntCtrlMsi = RTFdtPHandleAllocate(hFdt);
245	Assert(idPHandleIntCtrlMsi != UINT32_MAX); RT_NOREF(idPHandleIntCtrlMsi);
246	uint32_t idPHandleAbpPClk = RTFdtPHandleAllocate(hFdt);
247	Assert(idPHandleAbpPClk != UINT32_MAX);
248	uint32_t idPHandleGpio = RTFdtPHandleAllocate(hFdt);
249	Assert(idPHandleGpio != UINT32_MAX);
250
251	uint32_t aidPHandleCpus[VMM_MAX_CPU_COUNT];
252	for (uint32_t i = 0; i < cCpus; i++)
253	{
254	aidPHandleCpus[i] = RTFdtPHandleAllocate(hFdt);
255	Assert(aidPHandleCpus[i] != UINT32_MAX);
256	}
257
258	vrc = RTFdtNodePropertyAddU32( hFdt, "interrupt-parent", idPHandleIntCtrl); VRC();
259	vrc = RTFdtNodePropertyAddString(hFdt, "model", "linux,dummy-virt"); VRC();
260	vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
261	vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 2); VRC();
262	vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "linux,dummy-virt"); VRC();
263
264	/* Configure the Power State Coordination Interface. */
265	vrc = RTFdtNodeAdd(hFdt, "psci"); VRC();
266	vrc = RTFdtNodePropertyAddU32( hFdt, "migrate", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_MIGRATE)); VRC();
267	vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_on", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_ON)); VRC();
268	vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_off", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_OFF)); VRC();
269	vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_suspend", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_SUSPEND)); VRC();
270	vrc = RTFdtNodePropertyAddString(hFdt, "method", "hvc"); VRC();
271	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 3,
272	"arm,psci-1.0", "arm,psci-0.2", "arm,psci"); VRC();
273	vrc = RTFdtNodeFinalize(hFdt); VRC();
274
275	/* Configure the timer and clock. */
276	InsertConfigInteger(pNEM, "VTimerInterrupt", 0xb);
277	vrc = RTFdtNodeAdd(hFdt, "timer"); VRC();
278	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 12,
279	0x01, 0x0d, 0x104,
280	0x01, 0x0e, 0x104,
281	0x01, 0x0b, 0x104,
282	0x01, 0x0a, 0x104); VRC();
283	vrc = RTFdtNodePropertyAddEmpty( hFdt, "always-on"); VRC();
284	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,armv8-timer"); VRC();
285	vrc = RTFdtNodeFinalize(hFdt); VRC();
286
287	vrc = RTFdtNodeAdd(hFdt, "apb-clk"); VRC();
288	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleAbpPClk); VRC();
289	vrc = RTFdtNodePropertyAddString( hFdt, "clock-output-names", "clk24mhz"); VRC();
290	vrc = RTFdtNodePropertyAddU32( hFdt, "clock-frequency", ASMReadCntFrqEl0()); VRC();
291	vrc = RTFdtNodePropertyAddU32( hFdt, "#clock-cells", 0); VRC();
292	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "fixed-clock"); VRC();
293	vrc = RTFdtNodeFinalize(hFdt); VRC();
294
295	if (pSysTblsBldAcpi)
296	{
297	vrc = pSysTblsBldAcpi->configureClock();
298	VRC();
299	}
300
301	/*
302	* MM values.
303	*/
304	PCFGMNODE pMM;
305	InsertConfigNode(pRoot, "MM", &pMM);
306
307	/*
308	* Memory setup.
309	*/
310	PCFGMNODE pMem = NULL;
311	InsertConfigNode(pMM, "MemRegions", &pMem);
312
313	/*
314	* Windows requires the TPM to be available at 0xfed40000 so reserve this region first, even
315	* if no TPM is configured.
316	*/
317	RTGCPHYS GCPhysTpm = 0xfed40000;
318	RTGCPHYS cbTpm = 0x5000 + 0x1000; /* TPM + PPI region. */
319	hrc = pResMgr->assignFixedMmioRegion("tpm", GCPhysTpm, cbTpm); H();
320
321	/*
322	* The firmware ROM will start at the beginning of the address space and span 64MiB
323	* After that comes the flash and spans another 64MiB (even if the real size is smaller).
324	*/
325	hrc = pResMgr->assignFixedRomRegion("firmware", GCPhysFw, cbFw); H();
326
327	RTGCPHYS GCPhysFlash = _64M;
328	RTGCPHYS cbFlash = _64M;
329	hrc = pResMgr->assignFixedMmioRegion("flash", GCPhysFlash, cbFlash); H();
330
331	hrc = pResMgr->assignFixedRomRegion("platform-tables", GCPhysPlatformDesc, cbPlatformDesc); H();
332
333	/*
334	* The base RAM will start at 128MiB (end of flash region) and goes up to 4GiB - 512MiB
335	* (for the MMIO hole).
336	* If more RAM is configured the high region will start at 4GiB.
337	*/
338	hrc = pResMgr->assignFixedRamRegion("RAM Base", GCPhysRamBase, cbRamBase); H();
339
340	PCFGMNODE pMemRegion = NULL;
341	InsertConfigNode(pMem, "Base", &pMemRegion);
342	InsertConfigInteger(pMemRegion, "GCPhysStart", GCPhysRamBase);
343	InsertConfigInteger(pMemRegion, "Size", cbRamBase);
344
345	vrc = RTFdtNodeAddF(hFdt, "memory@%RGp", GCPhysRamBase); VRC();
346	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysRamBase, cbRamBase); VRC();
347	vrc = RTFdtNodePropertyAddString( hFdt, "device_type", "memory"); VRC();
348	vrc = RTFdtNodeFinalize(hFdt); VRC();
349
350	if (pSysTblsBldAcpi)
351	{
352	vrc = pSysTblsBldAcpi->addMemory(GCPhysRamBase, cbRamBase);
353	VRC();
354	}
355
356	if (cbRamBase < cbRam)
357	{
358	RTGCPHYS GCPhysRamHigh = _4G;
359	RTGCPHYS cbRamHigh = cbRam - cbRamBase;
360
361	hrc = pResMgr->assignFixedRamRegion("RAM High", GCPhysRamHigh, cbRamHigh); H();
362
363	InsertConfigNode(pMem, "High", &pMemRegion);
364	InsertConfigInteger(pMemRegion, "GCPhysStart", GCPhysRamHigh);
365	InsertConfigInteger(pMemRegion, "Size", cbRamHigh);
366
367	vrc = RTFdtNodeAddF(hFdt, "memory@%RGp", GCPhysRamHigh); VRC();
368	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysRamHigh, cbRamHigh); VRC();
369	vrc = RTFdtNodePropertyAddString( hFdt, "device_type", "memory"); VRC();
370	vrc = RTFdtNodeFinalize(hFdt); VRC();
371
372	if (pSysTblsBldAcpi)
373	{
374	vrc = pSysTblsBldAcpi->addMemory(GCPhysRamHigh, cbRamHigh);
375	VRC();
376	}
377	}
378
379	/* Configure the CPUs in the system, only one socket and cluster at the moment. */
380	vrc = RTFdtNodeAdd(hFdt, "cpus"); VRC();
381	vrc = RTFdtNodePropertyAddU32(hFdt, "#size-cells", 0); VRC();
382	vrc = RTFdtNodePropertyAddU32(hFdt, "#address-cells", 1); VRC();
383
384	vrc = RTFdtNodeAdd(hFdt, "socket0"); VRC();
385	vrc = RTFdtNodeAdd(hFdt, "cluster0"); VRC();
386
387	for (uint32_t i = 0; i < cCpus; i++)
388	{
389	vrc = RTFdtNodeAddF(hFdt, "core%u", i); VRC();
390	vrc = RTFdtNodePropertyAddU32(hFdt, "cpu", aidPHandleCpus[i]); VRC();
391	vrc = RTFdtNodeFinalize(hFdt); VRC();
392	}
393
394	vrc = RTFdtNodeFinalize(hFdt); VRC();
395	vrc = RTFdtNodeFinalize(hFdt); VRC();
396
397	for (uint32_t i = 0; i < cCpus; i++)
398	{
399	vrc = RTFdtNodeAddF(hFdt, "cpu@%u", i); VRC();
400	vrc = RTFdtNodePropertyAddU32(hFdt, "phandle", aidPHandleCpus[i]); VRC();
401	vrc = RTFdtNodePropertyAddU32(hFdt, "reg", i); VRC();
402	vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "arm,cortex-a15"); VRC();
403	vrc = RTFdtNodePropertyAddString(hFdt, "device_type", "cpu"); VRC();
404	if (cCpus > 1)
405	{
406	vrc = RTFdtNodePropertyAddString(hFdt, "enable-method", "psci"); VRC();
407	}
408	vrc = RTFdtNodeFinalize(hFdt); VRC();
409
410	if (pSysTblsBldAcpi)
411	{
412	vrc = pSysTblsBldAcpi->addCpu(i);
413	VRC();
414	}
415	}
416
417	vrc = RTFdtNodeFinalize(hFdt); VRC();
418
419
420	/*
421	* CPUM values.
422	*/
423	PCFGMNODE pCpum;
424	InsertConfigNode(pRoot, "CPUM", &pCpum);
425
426	/* Nested Virtualization. */
427	BOOL fNestedHWVirt = FALSE;
428	hrc = platformARM->GetCPUProperty(CPUPropertyTypeARM_HWVirt, &fNestedHWVirt); H();
429	InsertConfigInteger(pCpum, "NestedHWVirt", fNestedHWVirt ? true : false);
430
431
432	/*
433	* PDM config.
434	* Load drivers in VBoxC.[so\|dll]
435	*/
436	vrc = i_configPdm(pMachine, pVMM, pUVM, pRoot); VRC();
437
438
439	/*
440	* VGA.
441	*/
442	ComPtr<IGraphicsAdapter> pGraphicsAdapter;
443	hrc = pMachine->COMGETTER(GraphicsAdapter)(pGraphicsAdapter.asOutParam()); H();
444	GraphicsControllerType_T enmGraphicsController;
445	hrc = pGraphicsAdapter->COMGETTER(GraphicsControllerType)(&enmGraphicsController); H();
446
447	/*
448	* Devices
449	*/
450	PCFGMNODE pDevices = NULL; /* /Devices */
451	PCFGMNODE pDev = NULL; /* /Devices/Dev/ */
452	PCFGMNODE pInst = NULL; /* /Devices/Dev/0/ */
453	PCFGMNODE pCfg = NULL; /* /Devices/Dev/.../Config/ */
454	PCFGMNODE pLunL0 = NULL; /* /Devices/Dev/0/LUN#0/ */
455
456	InsertConfigNode(pRoot, "Devices", &pDevices);
457
458	InsertConfigNode(pDevices, "pci-generic-ecam-bridge", NULL);
459
460	InsertConfigNode(pDevices, "platform", &pDev);
461	InsertConfigNode(pDev, "0", &pInst);
462	InsertConfigNode(pInst, "Config", &pCfg);
463	InsertConfigNode(pInst, "LUN#0", &pLunL0);
464	InsertConfigString(pLunL0, "Driver", "ResourceStore");
465
466	/* Add the resources. */
467	PCFGMNODE pResources = NULL; /* /Devices/platform/Config/Resources */
468	PCFGMNODE pRes = NULL; /* /Devices/platform/Config/Resources/<Resource> */
469	InsertConfigString(pCfg, "ResourceNamespace", "resources");
470	InsertConfigNode(pCfg, "Resources", &pResources);
471	InsertConfigNode(pResources, "EfiRom", &pRes);
472	InsertConfigInteger(pRes, "RegisterAsRom", 1);
473	InsertConfigInteger(pRes, "GCPhysLoadAddress", 0);
474
475	/** @todo r=aeichner 32-bit guests and query the firmware type from VBoxSVC. */
476	/*
477	* Firmware.
478	*/
479	FirmwareType_T eFwType = FirmwareType_EFI64;
480	#ifdef VBOX_WITH_EFI_IN_DD2
481	const char *pszEfiRomFile = eFwType == FirmwareType_EFIDUAL ? "<INVALID>"
482	: eFwType == FirmwareType_EFI32 ? "VBoxEFI-arm32.fd"
483	: "VBoxEFI-arm64.fd";
484	const char *pszKey = "ResourceId";
485	#else
486	Utf8Str efiRomFile;
487	vrc = findEfiRom(virtualBox, PlatformArchitecture_ARM, eFwType, &efiRomFile);
488	AssertRCReturn(vrc, vrc);
489	const char *pszEfiRomFile = efiRomFile.c_str();
490	const char *pszKey = "Filename";
491	#endif
492	InsertConfigString(pRes, pszKey, pszEfiRomFile);
493
494	InsertConfigNode(pResources, "ArmV8Desc", &pRes);
495	InsertConfigInteger(pRes, "RegisterAsRom", 1);
496	InsertConfigInteger(pRes, "GCPhysLoadAddress", GCPhysPlatformDesc);
497	InsertConfigString(pRes, "ResourceId", "VBoxArmV8Desc");
498
499	/*
500	* Configure the interrupt controller.
501	*/
502	RTGCPHYS GCPhysIntcDist;
503	RTGCPHYS GCPhysIntcIts;
504	RTGCPHYS cbMmioIntcDist;
505	RTGCPHYS cbMmioIntcIts;
506	RTGCPHYS GCPhysIntcReDist;
507	RTGCPHYS cbMmioIntcReDist;
508
509	/** @todo Add API for configuring a GIC ITS for the VM and init this value from
510	* there. */
511	BOOL fGicIts = FALSE;
512
513	/* Allow for up to 256 vCPUs in the future without changing the address space layout. */
514	hrc = pResMgr->assignMmioRegion("gic", _64K + 256 * _128K, &GCPhysIntcDist, &cbMmioIntcDist); H();
515	GCPhysIntcReDist = GCPhysIntcDist + _64K;
516	cbMmioIntcReDist = 256 * _128K;
517	cbMmioIntcDist = _64K;
518
519	/* Reserve an MMIO region for the GIC ITS even if it might not be configured for the VM. */
520	hrc = pResMgr->assignMmioRegion("gic-its", 2 * _64K, &GCPhysIntcIts, &cbMmioIntcIts); H();
521
522	#ifdef RT_OS_DARWIN
523	InsertConfigNode(pDevices, "gic", &pDev);
524	#else
525	/* On Linux we default to the KVM in-kernel GIC and on Windows we are forced to the Hyper-V GIC for now. */
526	InsertConfigNode(pDevices, "gic-nem", &pDev);
527	#endif
528	InsertConfigNode(pDev, "0", &pInst);
529	InsertConfigInteger(pInst, "Trusted", 1);
530	InsertConfigNode(pInst, "Config", &pCfg);
531	InsertConfigInteger(pCfg, "DistributorMmioBase", GCPhysIntcDist);
532	InsertConfigInteger(pCfg, "RedistributorMmioBase", GCPhysIntcReDist);
533	if (fGicIts == TRUE)
534	{
535	InsertConfigInteger(pCfg, "ItsMmioBase", GCPhysIntcIts);
536	InsertConfigInteger(pCfg, "Lpi", 1);
537	}
538
539	vrc = RTFdtNodeAddF(hFdt, "intc@%RGp", GCPhysIntcDist); VRC();
540	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleIntCtrl); VRC();
541	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 4,
542	GCPhysIntcDist, cbMmioIntcDist, /* Distributor */
543	GCPhysIntcReDist, cbMmioIntcReDist); /* Re-Distributor */ VRC();
544	vrc = RTFdtNodePropertyAddU32( hFdt, "#redistributor-regions", 1); VRC();
545	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,gic-v3"); VRC();
546	vrc = RTFdtNodePropertyAddEmpty( hFdt, "ranges"); VRC();
547	vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
548	vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 2); VRC();
549	vrc = RTFdtNodePropertyAddEmpty( hFdt, "interrupt-controller"); VRC();
550	vrc = RTFdtNodePropertyAddU32( hFdt, "#interrupt-cells", 3); VRC();
551
552	if (pSysTblsBldAcpi)
553	{
554	vrc = pSysTblsBldAcpi->configureGic(cCpus, GCPhysIntcDist, cbMmioIntcDist,
555	GCPhysIntcReDist, cbMmioIntcReDist, GCPhysIntcIts, cbMmioIntcIts);
556	VRC();
557	}
558
559	#if 0
560	vrc = RTFdtNodeAddF(hFdt, "its@%RX32", 0x08080000); VRC();
561	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleIntCtrlMsi); VRC();
562	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "reg", 4, 0, 0x08080000, 0, 0x20000); VRC();
563	vrc = RTFdtNodePropertyAddU32( hFdt, "#msi-cells", 1); VRC();
564	vrc = RTFdtNodePropertyAddEmpty( hFdt, "msi-controller"); VRC();
565	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,gic-v3-its"); VRC();
566	vrc = RTFdtNodeFinalize(hFdt); VRC();
567	#endif
568
569	vrc = RTFdtNodeFinalize(hFdt); VRC();
570
571	/*
572	* Configure the performance monitoring unit.
573	*/
574	/** @todo Make this configurable and enable as default for Windows VMs because they assume a working PMU
575	* (which is not available in hardware on AppleSilicon).
576	*/
577	InsertConfigNode(pDevices, "pmu", &pDev);
578	InsertConfigNode(pDev, "0", &pInst);
579	InsertConfigInteger(pInst, "Trusted", 1);
580	InsertConfigNode(pInst, "Config", &pCfg);
581
582	RTGCPHYS GCPhysMmioStart;
583	RTGCPHYS cbMmio;
584	if (enmGraphicsController == GraphicsControllerType_QemuRamFB)
585	{
586	hrc = pResMgr->assignMmioRegion("qemu-fw-cfg", _4K, &GCPhysMmioStart, &cbMmio); H();
587
588	InsertConfigNode(pDevices, "qemu-fw-cfg", &pDev);
589	InsertConfigNode(pDev, "0", &pInst);
590	InsertConfigNode(pInst, "Config", &pCfg);
591	InsertConfigInteger(pCfg, "MmioSize", cbMmio);
592	InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
593	InsertConfigInteger(pCfg, "DmaEnabled", 1);
594	InsertConfigInteger(pCfg, "QemuRamfbSupport", 1);
595	InsertConfigNode(pInst, "LUN#0", &pLunL0);
596	InsertConfigString(pLunL0, "Driver", "MainDisplay");
597
598	vrc = RTFdtNodeAddF(hFdt, "fw-cfg@%RGp", GCPhysMmioStart); VRC();
599	vrc = RTFdtNodePropertyAddEmpty( hFdt, "dma-coherent"); VRC();
600	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
601	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "qemu,fw-cfg-mmio"); VRC();
602	vrc = RTFdtNodeFinalize(hFdt); VRC();
603
604	if (pSysTblsBldAcpi)
605	{
606	vrc = pSysTblsBldAcpi->addMmioDeviceNoIrq("qemu-fw-cfg", 0, GCPhysMmioStart, cbMmio);
607	VRC();
608	}
609	}
610
611	InsertConfigNode(pDevices, "flash-cfi", &pDev);
612	InsertConfigNode(pDev, "0", &pInst);
613	InsertConfigNode(pInst, "Config", &pCfg);
614	InsertConfigInteger(pCfg, "BaseAddress", GCPhysFlash);
615	InsertConfigInteger(pCfg, "Size", 768 * _1K);
616	InsertConfigString(pCfg, "FlashFile", "nvram");
617	/* Attach the NVRAM storage driver. */
618	InsertConfigNode(pInst, "LUN#0", &pLunL0);
619	InsertConfigString(pLunL0, "Driver", "NvramStore");
620
621	vrc = RTFdtNodeAddF(hFdt, "flash@%RX32", 0); VRC();
622	vrc = RTFdtNodePropertyAddU32( hFdt, "bank-width", 4); VRC();
623	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 4,
624	GCPhysFw, cbFw, /* First region (EFI). */
625	GCPhysFlash, 3 * _256K); /* Second region (NVRAM), see NvramStoreImpl.cpp for an explanation of the size choice. */ VRC();
626	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "cfi-flash"); VRC();
627	vrc = RTFdtNodeFinalize(hFdt); VRC();
628
629	InsertConfigNode(pDevices, "arm-pl011", &pDev);
630	for (ULONG ulInstance = 0; ulInstance < 1 /** @todo SchemaDefs::SerialPortCount*/; ++ulInstance)
631	{
632	ComPtr<ISerialPort> serialPort;
633	hrc = pMachine->GetSerialPort(ulInstance, serialPort.asOutParam()); H();
634	BOOL fEnabledSerPort = FALSE;
635	if (serialPort)
636	{
637	hrc = serialPort->COMGETTER(Enabled)(&fEnabledSerPort); H();
638	}
639	if (!fEnabledSerPort)
640	{
641	m_aeSerialPortMode[ulInstance] = PortMode_Disconnected;
642	continue;
643	}
644
645	InsertConfigNode(pDev, Utf8StrFmt("%u", ulInstance).c_str(), &pInst);
646	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
647	InsertConfigNode(pInst, "Config", &pCfg);
648
649	uint32_t iIrq = 0;
650	hrc = pResMgr->assignSingleInterrupt("arm-pl011", &iIrq); H();
651	hrc = pResMgr->assignMmioRegion("arm-pl011", _4K, &GCPhysMmioStart, &cbMmio); H();
652
653	InsertConfigInteger(pCfg, "Irq", iIrq);
654	InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
655
656	vrc = RTFdtNodeAddF(hFdt, "pl011@%RGp", GCPhysMmioStart); VRC();
657	vrc = RTFdtNodePropertyAddStringList(hFdt, "clock-names", 2, "uartclk", "apb_pclk"); VRC();
658	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "clocks", 2,
659	idPHandleAbpPClk, idPHandleAbpPClk); VRC();
660	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, iIrq, 0x04); VRC();
661	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
662	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
663	"arm,pl011", "arm,primecell"); VRC();
664	vrc = RTFdtNodeFinalize(hFdt); VRC();
665
666	if (pSysTblsBldAcpi)
667	{
668	vrc = pSysTblsBldAcpi->addMmioDevice("arm-pl011", ulInstance, GCPhysMmioStart, cbMmio, iIrq);
669	VRC();
670	}
671
672	BOOL fServer;
673	hrc = serialPort->COMGETTER(Server)(&fServer); H();
674	hrc = serialPort->COMGETTER(Path)(bstr.asOutParam()); H();
675
676	PortMode_T eHostMode;
677	hrc = serialPort->COMGETTER(HostMode)(&eHostMode); H();
678
679	m_aeSerialPortMode[ulInstance] = eHostMode;
680	if (eHostMode != PortMode_Disconnected)
681	{
682	vrc = i_configSerialPort(pInst, eHostMode, Utf8Str(bstr).c_str(), RT_BOOL(fServer));
683	if (RT_FAILURE(vrc))
684	return vrc;
685	}
686	}
687
688	BOOL fRTCUseUTC;
689	hrc = platform->COMGETTER(RTCUseUTC)(&fRTCUseUTC); H();
690
691	uint32_t iIrq = 0;
692	hrc = pResMgr->assignSingleInterrupt("arm-pl031-rtc", &iIrq); H();
693	hrc = pResMgr->assignMmioRegion("arm-pl031-rtc", _4K, &GCPhysMmioStart, &cbMmio); H();
694	InsertConfigNode(pDevices, "arm-pl031-rtc", &pDev);
695	InsertConfigNode(pDev, "0", &pInst);
696	InsertConfigNode(pInst, "Config", &pCfg);
697	InsertConfigInteger(pCfg, "Irq", iIrq);
698	InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
699	InsertConfigInteger(pCfg, "UtcOffset", fRTCUseUTC ? 1 : 0);
700
701	vrc = RTFdtNodeAddF(hFdt, "pl032@%RGp", GCPhysMmioStart); VRC();
702	vrc = RTFdtNodePropertyAddString( hFdt, "clock-names", "apb_pclk"); VRC();
703	vrc = RTFdtNodePropertyAddU32( hFdt, "clocks", idPHandleAbpPClk); VRC();
704	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, iIrq, 0x04); VRC();
705	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
706	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
707	"arm,pl031", "arm,primecell"); VRC();
708	vrc = RTFdtNodeFinalize(hFdt); VRC();
709
710	/* Configure gpio keys (The Windows GPIO PL061 driver doesn't like 64-bit MMIO addresses...). */
711	hrc = pResMgr->assignSingleInterrupt("arm-pl061-gpio", &iIrq); H();
712	hrc = pResMgr->assignMmio32Region("arm-pl061-gpio", _4K, &GCPhysMmioStart, &cbMmio); H();
713	InsertConfigNode(pDevices, "arm-pl061-gpio",&pDev);
714	InsertConfigNode(pDev, "0", &pInst);
715	InsertConfigNode(pInst, "Config", &pCfg);
716	InsertConfigInteger(pCfg, "Irq", iIrq);
717	InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
718	vrc = RTFdtNodeAddF(hFdt, "pl061@%RGp", GCPhysMmioStart); VRC();
719	vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleGpio); VRC();
720	vrc = RTFdtNodePropertyAddString( hFdt, "clock-names", "apb_pclk"); VRC();
721	vrc = RTFdtNodePropertyAddU32( hFdt, "clocks", idPHandleAbpPClk); VRC();
722	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, iIrq, 0x04); VRC();
723	vrc = RTFdtNodePropertyAddEmpty( hFdt, "gpio-controller"); VRC();
724	vrc = RTFdtNodePropertyAddU32( hFdt, "#gpio-cells", 2); VRC();
725	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
726	"arm,pl061", "arm,primecell"); VRC();
727	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
728	vrc = RTFdtNodeFinalize(hFdt); VRC();
729
730	InsertConfigNode(pInst, "LUN#0", &pLunL0);
731	InsertConfigString(pLunL0, "Driver", "GpioButton");
732	InsertConfigNode(pLunL0, "Config", &pCfg);
733	InsertConfigInteger(pCfg, "PowerButtonGpio", 3);
734	InsertConfigInteger(pCfg, "SleepButtonGpio", 4);
735
736	vrc = RTFdtNodeAdd(hFdt, "gpio-keys"); VRC();
737	vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "gpio-keys"); VRC();
738
739	vrc = RTFdtNodeAdd(hFdt, "poweroff"); VRC();
740	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "gpios", 3, idPHandleGpio, 3, 0); VRC();
741	vrc = RTFdtNodePropertyAddU32( hFdt, "linux,code", 0x74); VRC();
742	vrc = RTFdtNodePropertyAddString( hFdt, "label", "GPIO Key Poweroff"); VRC();
743	vrc = RTFdtNodeFinalize(hFdt); VRC();
744
745	vrc = RTFdtNodeAdd(hFdt, "suspend"); VRC();
746	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "gpios", 3, idPHandleGpio, 4, 0); VRC();
747	vrc = RTFdtNodePropertyAddU32( hFdt, "linux,code", 0xcd); VRC();
748	vrc = RTFdtNodePropertyAddString( hFdt, "label", "GPIO Key Suspend"); VRC();
749	vrc = RTFdtNodeFinalize(hFdt); VRC();
750
751	vrc = RTFdtNodeFinalize(hFdt); VRC();
752
753	if (pSysTblsBldAcpi)
754	{
755	vrc = pSysTblsBldAcpi->configureGpioDevice("arm-pl061-gpio", 0, GCPhysMmioStart, cbMmio, iIrq,
756	3 /u16PinShutdown/, 4 /u16PinSuspend/);
757	VRC();
758	}
759
760	#if defined(VBOX_WITH_TPM)
761	/*
762	* Configure the Trusted Platform Module.
763	*/
764	ComObjPtr<ITrustedPlatformModule> ptrTpm;
765	TpmType_T enmTpmType = TpmType_None;
766
767	hrc = pMachine->COMGETTER(TrustedPlatformModule)(ptrTpm.asOutParam()); H();
768	hrc = ptrTpm->COMGETTER(Type)(&enmTpmType); H();
769	if (enmTpmType != TpmType_None)
770	{
771	hrc = pResMgr->assignSingleInterrupt("tpm", &iIrq); H();
772
773	vrc = i_configTpm(ptrTpm, enmTpmType, pDevices, GCPhysTpm, iIrq /uIrq/,
774	GCPhysTpm + 0x5000, true /fCrb/); VRC();
775
776	vrc = RTFdtNodeAddF(hFdt, "tpm@%RGp", GCPhysTpm); VRC();
777	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, iIrq, 0x04); VRC();
778	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysTpm, cbTpm); VRC();
779	vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 1, "tcg,tpm-tis-mmio"); VRC();
780	vrc = RTFdtNodeFinalize(hFdt); VRC();
781
782	if (pSysTblsBldAcpi)
783	{
784	vrc = pSysTblsBldAcpi->configureTpm2(true /fCrb/, GCPhysTpm, cbTpm, iIrq);
785	VRC();
786	}
787	}
788	#endif
789
790	hrc = pResMgr->assignInterrupts("pci-generic-ecam", 4 /cInterrupts/, &iIrq); H();
791	uint32_t aPinIrqs[] = { iIrq, iIrq + 1, iIrq + 2, iIrq + 3 };
792	RTGCPHYS GCPhysPciMmioEcam, GCPhysPciMmio, GCPhysPciMmio32;
793	RTGCPHYS cbPciMmioEcam, cbPciMmio, cbPciMmio32;
794
795	hrc = pResMgr->assignMmioRegionAligned("pci-pio", _64K, _64K, &GCPhysMmioStart, &cbMmio, false /fOnly32Bit/); H();
796	hrc = pResMgr->assignMmioRegion( "pci-ecam", 16 * _1M, &GCPhysPciMmioEcam, &cbPciMmioEcam); H();
797	hrc = pResMgr->assignMmio64Region( "pci-mmio", _2G, &GCPhysPciMmio, &cbPciMmio); H();
798	hrc = pResMgr->assignMmio32Region( "pci-mmio32", _256M, &GCPhysPciMmio32, &cbPciMmio32); H();
799
800	InsertConfigNode(pDevices, "pci-generic-ecam", &pDev);
801	InsertConfigNode(pDev, "0", &pInst);
802	InsertConfigNode(pInst, "Config", &pCfg);
803	InsertConfigInteger(pCfg, "MmioEcamBase", GCPhysPciMmioEcam);
804	InsertConfigInteger(pCfg, "MmioEcamLength", cbPciMmioEcam);
805	InsertConfigInteger(pCfg, "MmioPioBase", GCPhysMmioStart);
806	InsertConfigInteger(pCfg, "MmioPioSize", cbMmio);
807	InsertConfigInteger(pCfg, "IntPinA", aPinIrqs[0]);
808	InsertConfigInteger(pCfg, "IntPinB", aPinIrqs[1]);
809	InsertConfigInteger(pCfg, "IntPinC", aPinIrqs[2]);
810	InsertConfigInteger(pCfg, "IntPinD", aPinIrqs[3]);
811	vrc = RTFdtNodeAddF(hFdt, "pcie@%RGp", GCPhysPciMmio); VRC();
812	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupt-map-mask", 4, 0xf800, 0, 0, 7); VRC();
813
814	uint32_t aIrqCells[32 * 4 * 10]; RT_ZERO(aIrqCells); /* Maximum of 32 devices on the root bus, each supporting 4 interrupts (INTA# ... INTD#). */
815	uint32_t *pau32IrqCell = &aIrqCells[0];
816	uint32_t iIrqPinSwizzle = 0;
817
818	for (uint32_t i = 0; i < 32; i++)
819	{
820	for (uint32_t iIrqPin = 0; iIrqPin < 4; iIrqPin++)
821	{
822	pau32IrqCell[0] = i << 11; /* The dev part, composed as dev.fn. */
823	pau32IrqCell[1] = 0;
824	pau32IrqCell[2] = 0;
825	pau32IrqCell[3] = iIrqPin + 1;
826	pau32IrqCell[4] = idPHandleIntCtrl;
827	pau32IrqCell[5] = 0;
828	pau32IrqCell[6] = 0;
829	pau32IrqCell[7] = 0;
830	pau32IrqCell[8] = aPinIrqs[(iIrqPinSwizzle + iIrqPin) % RT_ELEMENTS(aPinIrqs)];
831	pau32IrqCell[9] = 0x04;
832	pau32IrqCell += 10;
833	}
834
835	iIrqPinSwizzle++;
836	}
837
838	vrc = RTFdtNodePropertyAddCellsU32AsArray(hFdt, "interrupt-map", RT_ELEMENTS(aIrqCells), &aIrqCells[0]); VRC();
839	vrc = RTFdtNodePropertyAddU32( hFdt, "#interrupt-cells", 1); VRC();
840	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "ranges", 21,
841	0x1000000, 0, 0,
842	GCPhysMmioStart >> 32, GCPhysMmioStart, cbMmio >> 32, cbMmio,
843	0x2000000, GCPhysPciMmio32 >> 32, GCPhysPciMmio32, GCPhysPciMmio32 >> 32, GCPhysPciMmio32,
844	cbPciMmio32 >> 32, cbPciMmio32,
845	0x3000000, GCPhysPciMmio >> 32, GCPhysPciMmio, GCPhysPciMmio >> 32, GCPhysPciMmio,
846	cbPciMmio >> 32, cbPciMmio); VRC();
847	vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysPciMmioEcam, cbPciMmioEcam); VRC();
848	/** @todo msi-map */
849	vrc = RTFdtNodePropertyAddEmpty( hFdt, "dma-coherent"); VRC();
850	vrc = RTFdtNodePropertyAddCellsU32(hFdt, "bus-range", 2, 0, 0xf); VRC();
851	vrc = RTFdtNodePropertyAddU32( hFdt, "linux,pci-domain", 0); VRC();
852	vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
853	vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 3); VRC();
854	vrc = RTFdtNodePropertyAddString( hFdt, "device_type", "pci"); VRC();
855	vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "pci-host-ecam-generic"); VRC();
856	vrc = RTFdtNodeFinalize(hFdt); VRC();
857
858	if (pSysTblsBldAcpi)
859	{
860	vrc = pSysTblsBldAcpi->configurePcieRootBus("pci-generic-ecam", aPinIrqs, GCPhysMmioStart, GCPhysPciMmioEcam,
861	cbPciMmioEcam, GCPhysMmioStart, cbMmio, GCPhysPciMmio32, cbPciMmio32);
862	VRC();
863	}
864
865	/*
866	* VMSVGA compliant graphics controller.
867	*/
868	if ( enmGraphicsController != GraphicsControllerType_QemuRamFB
869	&& enmGraphicsController != GraphicsControllerType_Null)
870	{
871	vrc = i_configGraphicsController(pDevices, enmGraphicsController, pBusMgr, pMachine,
872	pGraphicsAdapter, firmwareSettings,
873	true /fForceVmSvga3/, false /fExposeLegacyVga/); VRC();
874	}
875
876	/*
877	* The USB Controllers and input devices.
878	*/
879	#if 0 /** @todo Make us of this and disallow PS/2 for ARM VMs for now. */
880	KeyboardHIDType_T aKbdHID;
881	hrc = pMachine->COMGETTER(KeyboardHIDType)(&aKbdHID); H();
882	#endif
883
884	PointingHIDType_T aPointingHID;
885	hrc = pMachine->COMGETTER(PointingHIDType)(&aPointingHID); H();
886
887	PCFGMNODE pUsbDevices = NULL;
888	vrc = i_configUsb(pMachine, pBusMgr, pRoot, pDevices, KeyboardHIDType_USBKeyboard, aPointingHID, &pUsbDevices);
889
890	/*
891	* Storage controllers.
892	*/
893	bool fFdcEnabled = false;
894	vrc = i_configStorageCtrls(pMachine, pBusMgr, pVMM, pUVM,
895	pDevices, pUsbDevices, NULL /pBiosCfg/, &fFdcEnabled); VRC();
896
897	/*
898	* Network adapters
899	*/
900	std::list<BootNic> llBootNics;
901	vrc = i_configNetworkCtrls(pMachine, pPlatformProperties, chipsetType, pBusMgr,
902	pVMM, pUVM, pDevices, pUsbDevices, llBootNics); VRC();
903
904	/*
905	* The VMM device.
906	*/
907	vrc = i_configVmmDev(pMachine, pBusMgr, pDevices, true /fMmioReq/); VRC();
908
909	/*
910	* Audio configuration.
911	*/
912	bool fAudioEnabled = false;
913	vrc = i_configAudioCtrl(virtualBox, pMachine, pBusMgr, pDevices,
914	false /fOsXGuest/, &fAudioEnabled); VRC();
915
916	/*
917	* Configure DBGF (Debug(ger) Facility) and DBGC (Debugger Console).
918	*/
919	vrc = i_configGuestDbg(virtualBox, pMachine, pRoot); VRC();
920	}
921	catch (ConfigError &x)
922	{
923	RTFdtDestroy(hFdt);
924
925	// InsertConfig threw something:
926	pVMM->pfnVMR3SetError(pUVM, x.m_vrc, RT_SRC_POS, "Caught ConfigError: %Rrc - %s", x.m_vrc, x.what());
927	return x.m_vrc;
928	}
929	catch (HRESULT hrcXcpt)
930	{
931	RTFdtDestroy(hFdt);
932	AssertLogRelMsgFailedReturn(("hrc=%Rhrc\n", hrcXcpt), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR);
933	}
934
935	#ifdef VBOX_WITH_EXTPACK
936	/*
937	* Call the extension pack hooks if everything went well thus far.
938	*/
939	if (RT_SUCCESS(vrc))
940	{
941	pAlock->release();
942	vrc = mptrExtPackManager->i_callAllVmConfigureVmmHooks(this, pVM, pVMM);
943	pAlock->acquire();
944	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
945	}
946	#endif
947
948	#if 0
949	vrc = RTFdtNodeAdd(hFdt, "chosen"); VRC();
950	vrc = RTFdtNodePropertyAddString( hFdt, "stdout-path", "pl011@9000000"); VRC();
951	vrc = RTFdtNodePropertyAddString( hFdt, "stdin-path", "pl011@9000000"); VRC();
952	vrc = RTFdtNodeFinalize(hFdt);
953	#endif
954
955	/* Finalize the FDT and add it to the resource store. */
956	vrc = RTFdtFinalize(hFdt);
957	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
958
959	RTVFSFILE hVfsFileDesc = NIL_RTVFSFILE;
960	vrc = RTVfsMemFileCreate(NIL_RTVFSIOSTREAM, 0 /cbEstimate/, &hVfsFileDesc);
961	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
962	RTVFSIOSTREAM hVfsIosDesc = RTVfsFileToIoStream(hVfsFileDesc);
963	AssertRelease(hVfsIosDesc != NIL_RTVFSIOSTREAM);
964
965	/* Initialize the VBox platform descriptor. */
966	VBOXPLATFORMARMV8 ArmV8Platform; RT_ZERO(ArmV8Platform);
967
968	vrc = RTFdtDumpToVfsIoStrm(hFdt, RTFDTTYPE_DTB, 0 /fFlags/, hVfsIosDesc, NULL /pErrInfo/);
969	uint64_t cbFdt = 0;
970	if (RT_SUCCESS(vrc))
971	vrc = RTVfsFileQuerySize(hVfsFileDesc, &cbFdt);
972	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
973
974	vrc = RTVfsIoStrmZeroFill(hVfsIosDesc, (RTFOFF)(RT_ALIGN_64(cbFdt, _64K) - cbFdt));
975	AssertRCReturn(vrc, vrc);
976
977	cbFdt = RT_ALIGN_64(cbFdt, _64K);
978
979	RTGCPHYS GCPhysMmioStart;
980	RTGCPHYS cbMmio;
981	hrc = pResMgr->queryMmioRegion(&GCPhysMmioStart, &cbMmio);
982	Assert(SUCCEEDED(hrc));
983
984	RTGCPHYS GCPhysMmio32Start;
985	RTGCPHYS cbMmio32;
986	hrc = pResMgr->queryMmio32Region(&GCPhysMmio32Start, &cbMmio32);
987	Assert(SUCCEEDED(hrc));
988
989	RTGCPHYS GCPhysXsdp = NIL_RTGCPHYS;
990	size_t cbAcpiXsdp = 0;
991	size_t cbAcpi = 0;
992	if (pSysTblsBldAcpi)
993	{
994	vrc = pSysTblsBldAcpi->finishTables(GCPhysPlatformDesc + cbFdt,
995	hVfsIosDesc, &GCPhysXsdp, &cbAcpiXsdp, &cbAcpi);
996	AssertRCReturn(vrc, vrc);
997	Assert( GCPhysXsdp > GCPhysPlatformDesc
998	&& GCPhysXsdp < VBOXPLATFORMARMV8_PHYS_ADDR);
999
1000	/* Dump the ACPI table for debugging purposes if requested. */
1001	Bstr SysTblsDumpVal;
1002	hrc = mMachine->GetExtraData(Bstr("VBoxInternal2/DumpSysTables").raw(),
1003	SysTblsDumpVal.asOutParam());
1004	if ( hrc == S_OK
1005	&& SysTblsDumpVal.isNotEmpty())
1006	{
1007	vrc = pSysTblsBldAcpi->dumpTables(Utf8Str(SysTblsDumpVal).c_str());
1008	AssertRCReturn(vrc, vrc);
1009	}
1010
1011	delete pSysTblsBldAcpi;
1012
1013	vrc = RTVfsIoStrmZeroFill(hVfsIosDesc, (RTFOFF)(RT_ALIGN_64(cbAcpi, _64K) - cbAcpi));
1014	AssertRCReturn(vrc, vrc);
1015
1016	cbAcpi = RT_ALIGN_64(cbAcpi, _64K);
1017	}
1018
1019	/* Fill the room until the end where the platform descriptor lives. */
1020	vrc = RTVfsIoStrmZeroFill(hVfsIosDesc, cbPlatformDesc - sizeof(ArmV8Platform) - cbFdt - cbAcpi);
1021	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
1022
1023	RTGCPHYS GCPhysMmio = 0;
1024	RTGCPHYS cbMmioAbove4G = 0;
1025	pResMgr->queryMmioRegion(&GCPhysMmio, &cbMmioAbove4G);
1026
1027	ArmV8Platform.u32Magic = VBOXPLATFORMARMV8_MAGIC;
1028	ArmV8Platform.u32Version = VBOXPLATFORMARMV8_VERSION;
1029	ArmV8Platform.cbDesc = sizeof(ArmV8Platform);
1030	ArmV8Platform.fFlags = 0;
1031	ArmV8Platform.u64PhysAddrRamBase = GCPhysRamBase;
1032	ArmV8Platform.cbRamBase = cbRamBase;
1033	ArmV8Platform.i64OffFdt = (int64_t)GCPhysPlatformDesc - VBOXPLATFORMARMV8_PHYS_ADDR;
1034	ArmV8Platform.cbFdt = cbFdt;
1035	if (cbAcpi)
1036	{
1037	ArmV8Platform.i64OffAcpi = (int64_t)(GCPhysPlatformDesc + cbFdt) - VBOXPLATFORMARMV8_PHYS_ADDR;
1038	ArmV8Platform.cbAcpi = cbAcpi;
1039	ArmV8Platform.i64OffAcpiXsdp = (int64_t)GCPhysXsdp - VBOXPLATFORMARMV8_PHYS_ADDR;
1040	ArmV8Platform.cbAcpiXsdp = cbAcpiXsdp;
1041	}
1042	ArmV8Platform.i64OffUefiRom = (int64_t)GCPhysFw - VBOXPLATFORMARMV8_PHYS_ADDR;
1043	ArmV8Platform.cbUefiRom = _64M;
1044	ArmV8Platform.i64OffMmio = GCPhysMmio ? (int64_t)GCPhysMmio - VBOXPLATFORMARMV8_PHYS_ADDR : 0;
1045	ArmV8Platform.cbMmio = cbMmioAbove4G;
1046	ArmV8Platform.i64OffMmio32 = (int64_t)(_4G - _512M) - VBOXPLATFORMARMV8_PHYS_ADDR;
1047	ArmV8Platform.cbMmio32 = _512M - _2M; /* Just assign the whole MMIO hole (except for the platform descriptor region). */
1048
1049	/* Add the VBox platform descriptor to the resource store. */
1050	vrc = RTVfsIoStrmWrite(hVfsIosDesc, &ArmV8Platform, sizeof(ArmV8Platform), true /fBlocking/, NULL /pcbWritten/);
1051	RTVfsIoStrmRelease(hVfsIosDesc);
1052	AssertRCReturnStmt(vrc, RTVfsFileRelease(hVfsFileDesc), vrc);
1053
1054	vrc = mptrResourceStore->i_addItem("resources", "VBoxArmV8Desc", hVfsFileDesc);
1055	RTVfsFileRelease(hVfsFileDesc);
1056	AssertRCReturn(vrc, vrc);
1057
1058	/* Dump the DTB for debugging purposes if requested. */
1059	Bstr DtbDumpVal;
1060	hrc = mMachine->GetExtraData(Bstr("VBoxInternal2/DumpDtb").raw(),
1061	DtbDumpVal.asOutParam());
1062	if ( hrc == S_OK
1063	&& DtbDumpVal.isNotEmpty())
1064	{
1065	vrc = RTFdtDumpToFile(hFdt, RTFDTTYPE_DTB, 0 /fFlags/, Utf8Str(DtbDumpVal).c_str(), NULL /pErrInfo/);
1066	AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
1067	}
1068
1069	pResMgr->dumpMemoryRegionsToReleaseLog();
1070
1071	delete pResMgr; /* Delete the address/interrupt assignment manager. */
1072
1073	/*
1074	* Apply the CFGM overlay.
1075	*/
1076	if (RT_SUCCESS(vrc))
1077	vrc = i_configCfgmOverlay(pRoot, virtualBox, pMachine);
1078
1079	/*
1080	* Dump all extradata API settings tweaks, both global and per VM.
1081	*/
1082	if (RT_SUCCESS(vrc))
1083	vrc = i_configDumpAPISettingsTweaks(virtualBox, pMachine);
1084
1085	#undef H
1086
1087	pAlock->release(); /* Avoid triggering the lock order inversion check. */
1088
1089	/*
1090	* Register VM state change handler.
1091	*/
1092	int vrc2 = pVMM->pfnVMR3AtStateRegister(pUVM, Console::i_vmstateChangeCallback, this);
1093	AssertRC(vrc2);
1094	if (RT_SUCCESS(vrc))
1095	vrc = vrc2;
1096
1097	/*
1098	* Register VM runtime error handler.
1099	*/
1100	vrc2 = pVMM->pfnVMR3AtRuntimeErrorRegister(pUVM, Console::i_atVMRuntimeErrorCallback, this);
1101	AssertRC(vrc2);
1102	if (RT_SUCCESS(vrc))
1103	vrc = vrc2;
1104
1105	pAlock->acquire();
1106
1107	LogFlowFunc(("vrc = %Rrc\n", vrc));
1108	LogFlowFuncLeave();
1109
1110	return vrc;
1111	}
1112	#endif /* !VBOX_WITH_VIRT_ARMV8 */
1113

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source: vbox/trunk/src/VBox/Main/src-client/ConsoleImplConfigArmV8.cpp@ 108746

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