VirtualBox

source: vbox/trunk/src/VBox/Main/src-client/ConsoleImplConfigArmV8.cpp

Last change on this file was 109212, checked in by vboxsync, 13 days ago

GIC: bugref:10877 Add MSI registeration callbacks in PCI ECAM configured when the ITS is enabled. Added invoking of the GIC backend's MSI handler from PDM.
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1/* $Id: ConsoleImplConfigArmV8.cpp 109212 2025-05-09 06:25:38Z vboxsync $ */
2/** @file
3 * VBox Console COM Class implementation - VM Configuration Bits for ARMv8.
4 */
5
6/*
7 * Copyright (C) 2023-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.215389.xyz.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_MAIN_CONSOLE
33#include "LoggingNew.h"
34
35#include "ConsoleImpl.h"
36#include "ResourceStoreImpl.h"
37#include "Global.h"
38#include "VMMDev.h"
39
40// generated header
41#include "SchemaDefs.h"
42
43#include "AutoCaller.h"
44
45#include <iprt/buildconfig.h>
46#include <iprt/ctype.h>
47#include <iprt/dir.h>
48#include <iprt/fdt.h>
49#include <iprt/file.h>
50#include <iprt/param.h>
51#include <iprt/path.h>
52#include <iprt/string.h>
53#include <iprt/system.h>
54#if 0 /* enable to play with lots of memory. */
55# include <iprt/env.h>
56#endif
57#include <iprt/stream.h>
58
59#include <iprt/formats/arm-psci.h>
60
61#include <VBox/vmm/vmmr3vtable.h>
62#include <VBox/vmm/vmapi.h>
63#include <VBox/err.h>
64#include <VBox/gic.h>
65#include <VBox/param.h>
66#include <VBox/version.h>
67#include <VBox/platforms/vbox-armv8.h>
68
69#include "BusAssignmentManager.h"
70#include "ResourceAssignmentManager.h"
71#include "SystemTableBuilder.h"
72#ifdef VBOX_WITH_EXTPACK
73# include "ExtPackManagerImpl.h"
74#endif
75
76
77/*********************************************************************************************************************************
78* Internal Functions *
79*********************************************************************************************************************************/
80
81/* Darwin compile kludge */
82#undef PVM
83
84#ifdef VBOX_WITH_VIRT_ARMV8
85/**
86 * Worker for configConstructor.
87 *
88 * @return VBox status code.
89 * @param pUVM The user mode VM handle.
90 * @param pVM The cross context VM handle.
91 * @param pVMM The VMM vtable.
92 * @param pAlock The automatic lock instance. This is for when we have
93 * to leave it in order to avoid deadlocks (ext packs and
94 * more).
95 */
96int Console::i_configConstructorArmV8(PUVM pUVM, PVM pVM, PCVMMR3VTABLE pVMM, AutoWriteLock *pAlock)
97{
98 RT_NOREF(pVM /* when everything is disabled */);
99 ComPtr<IMachine> pMachine = i_machine();
100
101 HRESULT hrc;
102 Utf8Str strTmp;
103 Bstr bstr;
104
105 RTFDT hFdt = NIL_RTFDT;
106 int vrc = RTFdtCreateEmpty(&hFdt);
107 AssertRCReturn(vrc, vrc);
108
109#define H() AssertLogRelMsgReturnStmt(!FAILED(hrc), ("hrc=%Rhrc\n", hrc), RTFdtDestroy(hFdt), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR)
110#define VRC() AssertLogRelMsgReturnStmt(RT_SUCCESS(vrc), ("vrc=%Rrc\n", vrc), RTFdtDestroy(hFdt), vrc)
111
112 /*
113 * Get necessary objects and frequently used parameters.
114 */
115 ComPtr<IVirtualBox> virtualBox;
116 hrc = pMachine->COMGETTER(Parent)(virtualBox.asOutParam()); H();
117
118 ComPtr<IHost> host;
119 hrc = virtualBox->COMGETTER(Host)(host.asOutParam()); H();
120
121 PlatformArchitecture_T platformArchHost;
122 hrc = host->COMGETTER(Architecture)(&platformArchHost); H();
123
124 ComPtr<ISystemProperties> systemProperties;
125 hrc = virtualBox->COMGETTER(SystemProperties)(systemProperties.asOutParam()); H();
126
127 ComPtr<IFirmwareSettings> firmwareSettings;
128 hrc = pMachine->COMGETTER(FirmwareSettings)(firmwareSettings.asOutParam()); H();
129
130 ComPtr<INvramStore> nvramStore;
131 hrc = pMachine->COMGETTER(NonVolatileStore)(nvramStore.asOutParam()); H();
132
133 hrc = pMachine->COMGETTER(HardwareUUID)(bstr.asOutParam()); H();
134 RTUUID HardwareUuid;
135 vrc = RTUuidFromUtf16(&HardwareUuid, bstr.raw());
136 AssertRCReturn(vrc, vrc);
137
138 ULONG cRamMBs;
139 hrc = pMachine->COMGETTER(MemorySize)(&cRamMBs); H();
140 uint64_t const cbRam = cRamMBs * (uint64_t)_1M;
141
142 ComPtr<IPlatform> platform;
143 hrc = pMachine->COMGETTER(Platform)(platform.asOutParam()); H();
144
145 /* Note: Should be guarded by VBOX_WITH_VIRT_ARMV8, but we check this anyway here.
146 Update: It is guarded by VBOX_WITH_VIRT_ARMV8, see line 84 and caller. Duh. */
147#if 0 /* For now we only support running ARM VMs on ARM hosts. */
148 PlatformArchitecture_T platformArchMachine;
149 hrc = platform->COMGETTER(Architecture)(&platformArchMachine); H();
150 if (platformArchMachine != platformArchHost)
151 return pVMM->pfnVMR3SetError(pUVM, VERR_PLATFORM_ARCH_NOT_SUPPORTED, RT_SRC_POS,
152 N_("VM platform architecture (%s) not supported on this host (%s)."),
153 Global::stringifyPlatformArchitecture(platformArchMachine),
154 Global::stringifyPlatformArchitecture(platformArchHost));
155#endif
156
157 /* Get the ARM platform object. */
158 ComPtr<IPlatformARM> platformARM;
159 hrc = platform->COMGETTER(ARM)(platformARM.asOutParam()); H();
160
161 ComPtr<IPlatformProperties> pPlatformProperties;
162 hrc = platform->COMGETTER(Properties)(pPlatformProperties.asOutParam()); H();
163
164 ChipsetType_T chipsetType;
165 hrc = platform->COMGETTER(ChipsetType)(&chipsetType); H();
166
167 ULONG cCpus = 1;
168 hrc = pMachine->COMGETTER(CPUCount)(&cCpus); H();
169 Assert(cCpus);
170
171 ULONG ulCpuExecutionCap = 100;
172 hrc = pMachine->COMGETTER(CPUExecutionCap)(&ulCpuExecutionCap); H();
173
174 VMExecutionEngine_T enmExecEngine = VMExecutionEngine_NotSet;
175 hrc = pMachine->COMGETTER(VMExecutionEngine)(&enmExecEngine); H();
176
177 if ( enmExecEngine != VMExecutionEngine_Default
178 && enmExecEngine != VMExecutionEngine_NativeApi)
179 {
180 return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
181 N_("The ARM backend doesn't support any other execution engine than 'default' or 'native-api' right now."));
182 }
183
184 LogRel(("Guest architecture: ARM\n"));
185
186 Bstr osTypeId;
187 hrc = pMachine->COMGETTER(OSTypeId)(osTypeId.asOutParam()); H();
188 LogRel(("Guest OS type: '%s'\n", Utf8Str(osTypeId).c_str()));
189
190 BusAssignmentManager *pBusMgr = mBusMgr = BusAssignmentManager::createInstance(pVMM, chipsetType, IommuType_None);
191 ResourceAssignmentManager *pResMgr = ResourceAssignmentManager::createInstance(pVMM, chipsetType, IommuType_None, 32 /*cInterrupts*/,
192 _4G); /* Start looking for free MMIO regions at 4GiB downwards. */
193 SystemTableBuilder *pSysTblsBldAcpi = NULL;
194
195 /*
196 * ACPI
197 */
198 BOOL fACPI;
199 hrc = firmwareSettings->COMGETTER(ACPIEnabled)(&fACPI); H();
200 if (fACPI)
201 pSysTblsBldAcpi = SystemTableBuilder::createInstance(kSystemTableType_Acpi);
202
203
204 /*
205 * Get root node first.
206 * This is the only node in the tree.
207 */
208 PCFGMNODE pRoot = pVMM->pfnCFGMR3GetRootU(pUVM);
209 Assert(pRoot);
210
211 /*
212 * The VBox platform descriptor, FDT and ACPI tables will reside at the end of the 4GiB
213 * address space and we reserve 2MiB for those.
214 */
215 RTGCPHYS cbPlatformDesc = _2M;
216 RTGCPHYS GCPhysPlatformDesc = VBOXPLATFORMARMV8_PHYS_ADDR - (cbPlatformDesc - _64K);
217
218 RTGCPHYS GCPhysRamBase = 128 * _1M;
219 RTGCPHYS cbRamBase = RT_MIN(cbRam, _4G - _512M - 128 * _1M);
220
221 RTGCPHYS GCPhysFw = 0;
222 RTGCPHYS cbFw = _64M;
223
224 // catching throws from InsertConfigString and friends.
225 try
226 {
227
228 /*
229 * Set the root (and VMM) level values.
230 */
231 hrc = pMachine->COMGETTER(Name)(bstr.asOutParam()); H();
232 InsertConfigString(pRoot, "Name", bstr);
233 InsertConfigBytes(pRoot, "UUID", &HardwareUuid, sizeof(HardwareUuid));
234 InsertConfigInteger(pRoot, "NumCPUs", cCpus);
235 InsertConfigInteger(pRoot, "CpuExecutionCap", ulCpuExecutionCap);
236 InsertConfigInteger(pRoot, "TimerMillies", 10);
237
238 /*
239 * NEM
240 */
241 PCFGMNODE pNEM;
242 InsertConfigNode(pRoot, "NEM", &pNEM);
243
244 uint32_t idPHandleIntCtrl = RTFdtPHandleAllocate(hFdt);
245 Assert(idPHandleIntCtrl != UINT32_MAX);
246 uint32_t idPHandleIntCtrlMsi = RTFdtPHandleAllocate(hFdt);
247 Assert(idPHandleIntCtrlMsi != UINT32_MAX); RT_NOREF(idPHandleIntCtrlMsi);
248 uint32_t idPHandleAbpPClk = RTFdtPHandleAllocate(hFdt);
249 Assert(idPHandleAbpPClk != UINT32_MAX);
250 uint32_t idPHandleGpio = RTFdtPHandleAllocate(hFdt);
251 Assert(idPHandleGpio != UINT32_MAX);
252
253 uint32_t aidPHandleCpus[VMM_MAX_CPU_COUNT];
254 for (uint32_t i = 0; i < cCpus; i++)
255 {
256 aidPHandleCpus[i] = RTFdtPHandleAllocate(hFdt);
257 Assert(aidPHandleCpus[i] != UINT32_MAX);
258 }
259
260 vrc = RTFdtNodePropertyAddU32( hFdt, "interrupt-parent", idPHandleIntCtrl); VRC();
261 vrc = RTFdtNodePropertyAddString(hFdt, "model", "linux,dummy-virt"); VRC();
262 vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
263 vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 2); VRC();
264 vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "linux,dummy-virt"); VRC();
265
266 /* Configure the Power State Coordination Interface. */
267 vrc = RTFdtNodeAdd(hFdt, "psci"); VRC();
268 vrc = RTFdtNodePropertyAddU32( hFdt, "migrate", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_MIGRATE)); VRC();
269 vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_on", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_ON)); VRC();
270 vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_off", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_OFF)); VRC();
271 vrc = RTFdtNodePropertyAddU32( hFdt, "cpu_suspend", ARM_PSCI_FUNC_ID_CREATE_FAST_32(ARM_PSCI_FUNC_ID_CPU_SUSPEND)); VRC();
272 vrc = RTFdtNodePropertyAddString(hFdt, "method", "hvc"); VRC();
273 vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 3,
274 "arm,psci-1.0", "arm,psci-0.2", "arm,psci"); VRC();
275 vrc = RTFdtNodeFinalize(hFdt); VRC();
276
277 /* Configure the timer and clock. */
278 InsertConfigInteger(pNEM, "VTimerInterrupt", 0xb);
279 vrc = RTFdtNodeAdd(hFdt, "timer"); VRC();
280 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 12,
281 0x01, 0x0d, 0x104,
282 0x01, 0x0e, 0x104,
283 0x01, 0x0b, 0x104,
284 0x01, 0x0a, 0x104); VRC();
285 vrc = RTFdtNodePropertyAddEmpty( hFdt, "always-on"); VRC();
286 vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,armv8-timer"); VRC();
287 vrc = RTFdtNodeFinalize(hFdt); VRC();
288
289 vrc = RTFdtNodeAdd(hFdt, "apb-clk"); VRC();
290 vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleAbpPClk); VRC();
291 vrc = RTFdtNodePropertyAddString( hFdt, "clock-output-names", "clk24mhz"); VRC();
292# ifdef RT_ARCH_ARM64
293 vrc = RTFdtNodePropertyAddU32( hFdt, "clock-frequency", ASMReadCntFrqEl0()); VRC();
294# else
295 vrc = RTFdtNodePropertyAddU32( hFdt, "clock-frequency", 24000000); VRC(); /** @todo clock-frequency hack*/
296# endif
297 vrc = RTFdtNodePropertyAddU32( hFdt, "#clock-cells", 0); VRC();
298 vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "fixed-clock"); VRC();
299 vrc = RTFdtNodeFinalize(hFdt); VRC();
300
301 if (pSysTblsBldAcpi)
302 {
303 vrc = pSysTblsBldAcpi->configureClock();
304 VRC();
305 }
306
307 /*
308 * MM values.
309 */
310 PCFGMNODE pMM;
311 InsertConfigNode(pRoot, "MM", &pMM);
312
313 /*
314 * Memory setup.
315 */
316 PCFGMNODE pMem = NULL;
317 InsertConfigNode(pMM, "MemRegions", &pMem);
318
319 /*
320 * Windows requires the TPM to be available at 0xfed40000 so reserve this region first, even
321 * if no TPM is configured.
322 */
323 RTGCPHYS GCPhysTpm = 0xfed40000;
324 RTGCPHYS cbTpm = 0x5000 + 0x1000; /* TPM + PPI region. */
325 hrc = pResMgr->assignFixedMmioRegion("tpm", GCPhysTpm, cbTpm); H();
326
327 /*
328 * The firmware ROM will start at the beginning of the address space and span 64MiB
329 * After that comes the flash and spans another 64MiB (even if the real size is smaller).
330 */
331 hrc = pResMgr->assignFixedRomRegion("firmware", GCPhysFw, cbFw); H();
332
333 RTGCPHYS GCPhysFlash = _64M;
334 RTGCPHYS cbFlash = _64M;
335 hrc = pResMgr->assignFixedMmioRegion("flash", GCPhysFlash, cbFlash); H();
336
337 hrc = pResMgr->assignFixedRomRegion("platform-tables", GCPhysPlatformDesc, cbPlatformDesc); H();
338
339 /*
340 * The base RAM will start at 128MiB (end of flash region) and goes up to 4GiB - 512MiB
341 * (for the MMIO hole).
342 * If more RAM is configured the high region will start at 4GiB.
343 */
344 hrc = pResMgr->assignFixedRamRegion("RAM Base", GCPhysRamBase, cbRamBase); H();
345
346 PCFGMNODE pMemRegion = NULL;
347 InsertConfigNode(pMem, "Base", &pMemRegion);
348 InsertConfigInteger(pMemRegion, "GCPhysStart", GCPhysRamBase);
349 InsertConfigInteger(pMemRegion, "Size", cbRamBase);
350
351 vrc = RTFdtNodeAddF(hFdt, "memory@%RGp", GCPhysRamBase); VRC();
352 vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysRamBase, cbRamBase); VRC();
353 vrc = RTFdtNodePropertyAddString( hFdt, "device_type", "memory"); VRC();
354 vrc = RTFdtNodeFinalize(hFdt); VRC();
355
356 if (pSysTblsBldAcpi)
357 {
358 vrc = pSysTblsBldAcpi->addMemory(GCPhysRamBase, cbRamBase);
359 VRC();
360 }
361
362 if (cbRamBase < cbRam)
363 {
364 RTGCPHYS GCPhysRamHigh = _4G;
365 RTGCPHYS cbRamHigh = cbRam - cbRamBase;
366
367 hrc = pResMgr->assignFixedRamRegion("RAM High", GCPhysRamHigh, cbRamHigh); H();
368
369 InsertConfigNode(pMem, "High", &pMemRegion);
370 InsertConfigInteger(pMemRegion, "GCPhysStart", GCPhysRamHigh);
371 InsertConfigInteger(pMemRegion, "Size", cbRamHigh);
372
373 vrc = RTFdtNodeAddF(hFdt, "memory@%RGp", GCPhysRamHigh); VRC();
374 vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysRamHigh, cbRamHigh); VRC();
375 vrc = RTFdtNodePropertyAddString( hFdt, "device_type", "memory"); VRC();
376 vrc = RTFdtNodeFinalize(hFdt); VRC();
377
378 if (pSysTblsBldAcpi)
379 {
380 vrc = pSysTblsBldAcpi->addMemory(GCPhysRamHigh, cbRamHigh);
381 VRC();
382 }
383 }
384
385 /* Configure the CPUs in the system, only one socket and cluster at the moment. */
386 vrc = RTFdtNodeAdd(hFdt, "cpus"); VRC();
387 vrc = RTFdtNodePropertyAddU32(hFdt, "#size-cells", 0); VRC();
388 vrc = RTFdtNodePropertyAddU32(hFdt, "#address-cells", 1); VRC();
389
390 vrc = RTFdtNodeAdd(hFdt, "socket0"); VRC();
391 vrc = RTFdtNodeAdd(hFdt, "cluster0"); VRC();
392
393 for (uint32_t i = 0; i < cCpus; i++)
394 {
395 vrc = RTFdtNodeAddF(hFdt, "core%u", i); VRC();
396 vrc = RTFdtNodePropertyAddU32(hFdt, "cpu", aidPHandleCpus[i]); VRC();
397 vrc = RTFdtNodeFinalize(hFdt); VRC();
398 }
399
400 vrc = RTFdtNodeFinalize(hFdt); VRC();
401 vrc = RTFdtNodeFinalize(hFdt); VRC();
402
403 for (uint32_t i = 0; i < cCpus; i++)
404 {
405 vrc = RTFdtNodeAddF(hFdt, "cpu@%u", i); VRC();
406 vrc = RTFdtNodePropertyAddU32(hFdt, "phandle", aidPHandleCpus[i]); VRC();
407 vrc = RTFdtNodePropertyAddU32(hFdt, "reg", i); VRC();
408 vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "arm,cortex-a15"); VRC();
409 vrc = RTFdtNodePropertyAddString(hFdt, "device_type", "cpu"); VRC();
410 if (cCpus > 1)
411 {
412 vrc = RTFdtNodePropertyAddString(hFdt, "enable-method", "psci"); VRC();
413 }
414 vrc = RTFdtNodeFinalize(hFdt); VRC();
415
416 if (pSysTblsBldAcpi)
417 {
418 vrc = pSysTblsBldAcpi->addCpu(i);
419 VRC();
420 }
421 }
422
423 vrc = RTFdtNodeFinalize(hFdt); VRC();
424
425
426 /*
427 * CPUM values.
428 */
429 PCFGMNODE pCpum;
430 InsertConfigNode(pRoot, "CPUM", &pCpum);
431
432 /* Nested Virtualization. */
433 BOOL fNestedHWVirt = FALSE;
434 hrc = platformARM->GetCPUProperty(CPUPropertyTypeARM_HWVirt, &fNestedHWVirt); H();
435 InsertConfigInteger(pCpum, "NestedHWVirt", fNestedHWVirt ? true : false);
436
437 /* GIC. */
438 uint8_t const uGicArchRev = GIC_DIST_REG_PIDR2_ARCHREV_GICV3;
439 InsertConfigInteger(pCpum, "GicArchRev", uGicArchRev);
440
441 /* GIC ITS. */
442 BOOL fGicIts = FALSE;
443 hrc = platformARM->GetCPUProperty(CPUPropertyTypeARM_GICITS, &fGicIts); H();
444
445 /*
446 * PDM config.
447 * Load drivers in VBoxC.[so|dll]
448 */
449 vrc = i_configPdm(pMachine, pVMM, pUVM, pRoot); VRC();
450
451
452 /*
453 * VGA.
454 */
455 ComPtr<IGraphicsAdapter> pGraphicsAdapter;
456 hrc = pMachine->COMGETTER(GraphicsAdapter)(pGraphicsAdapter.asOutParam()); H();
457 GraphicsControllerType_T enmGraphicsController;
458 hrc = pGraphicsAdapter->COMGETTER(GraphicsControllerType)(&enmGraphicsController); H();
459
460 /*
461 * Devices
462 */
463 PCFGMNODE pDevices = NULL; /* /Devices */
464 PCFGMNODE pDev = NULL; /* /Devices/Dev/ */
465 PCFGMNODE pInst = NULL; /* /Devices/Dev/0/ */
466 PCFGMNODE pCfg = NULL; /* /Devices/Dev/.../Config/ */
467 PCFGMNODE pLunL0 = NULL; /* /Devices/Dev/0/LUN#0/ */
468
469 InsertConfigNode(pRoot, "Devices", &pDevices);
470
471 InsertConfigNode(pDevices, "pci-generic-ecam-bridge", &pDev);
472 InsertConfigNode(pDev, "0", &pInst);
473 InsertConfigNode(pInst, "Config", &pCfg);
474 if (fGicIts == TRUE)
475 InsertConfigInteger(pCfg, "Msi", 1);
476
477 InsertConfigNode(pDevices, "platform", &pDev);
478 InsertConfigNode(pDev, "0", &pInst);
479 InsertConfigNode(pInst, "Config", &pCfg);
480 InsertConfigNode(pInst, "LUN#0", &pLunL0);
481 InsertConfigString(pLunL0, "Driver", "ResourceStore");
482
483 /* Add the resources. */
484 PCFGMNODE pResources = NULL; /* /Devices/platform/Config/Resources */
485 PCFGMNODE pRes = NULL; /* /Devices/platform/Config/Resources/<Resource> */
486 InsertConfigString(pCfg, "ResourceNamespace", "resources");
487 InsertConfigNode(pCfg, "Resources", &pResources);
488 InsertConfigNode(pResources, "EfiRom", &pRes);
489 InsertConfigInteger(pRes, "RegisterAsRom", 1);
490 InsertConfigInteger(pRes, "GCPhysLoadAddress", 0);
491
492 /** @todo r=aeichner 32-bit guests and query the firmware type from VBoxSVC. */
493 /*
494 * Firmware.
495 */
496 FirmwareType_T eFwType = FirmwareType_EFI64;
497#ifdef VBOX_WITH_EFI_IN_DD2
498 const char *pszEfiRomFile = eFwType == FirmwareType_EFIDUAL ? "<INVALID>"
499 : eFwType == FirmwareType_EFI32 ? "VBoxEFI-arm32.fd"
500 : "VBoxEFI-arm64.fd";
501 const char *pszKey = "ResourceId";
502#else
503 Utf8Str efiRomFile;
504 vrc = findEfiRom(virtualBox, PlatformArchitecture_ARM, eFwType, &efiRomFile);
505 AssertRCReturn(vrc, vrc);
506 const char *pszEfiRomFile = efiRomFile.c_str();
507 const char *pszKey = "Filename";
508#endif
509 InsertConfigString(pRes, pszKey, pszEfiRomFile);
510
511 InsertConfigNode(pResources, "ArmV8Desc", &pRes);
512 InsertConfigInteger(pRes, "RegisterAsRom", 1);
513 InsertConfigInteger(pRes, "GCPhysLoadAddress", GCPhysPlatformDesc);
514 InsertConfigString(pRes, "ResourceId", "VBoxArmV8Desc");
515
516 /*
517 * Configure the interrupt controller.
518 */
519 RTGCPHYS GCPhysIntcDist;
520 RTGCPHYS GCPhysIntcIts;
521 RTGCPHYS cbMmioIntcDist;
522 RTGCPHYS cbMmioIntcIts;
523 RTGCPHYS GCPhysIntcReDist;
524 RTGCPHYS cbMmioIntcReDist;
525
526 /* Allow for up to 256 vCPUs in the future without changing the address space layout. */
527 hrc = pResMgr->assignMmioRegion("gic", _64K + 256 * _128K, &GCPhysIntcDist, &cbMmioIntcDist); H();
528 GCPhysIntcReDist = GCPhysIntcDist + _64K;
529 cbMmioIntcReDist = 256 * _128K;
530 cbMmioIntcDist = _64K;
531
532 /* Reserve an MMIO region for the GIC ITS even if it might not be configured for the VM. */
533 hrc = pResMgr->assignMmioRegion("gic-its", 2 * _64K, &GCPhysIntcIts, &cbMmioIntcIts); H();
534
535#if defined(RT_OS_DARWIN) || !defined(RT_ARCH_ARM64)
536 InsertConfigNode(pDevices, "gic", &pDev);
537#else
538 /* On Linux we default to the KVM in-kernel GIC and on Windows we are forced to the Hyper-V GIC for now. */
539 InsertConfigNode(pDevices, "gic-nem", &pDev);
540#endif
541 InsertConfigNode(pDev, "0", &pInst);
542 InsertConfigInteger(pInst, "Trusted", 1);
543 InsertConfigNode(pInst, "Config", &pCfg);
544 InsertConfigInteger(pCfg, "ArchRev", uGicArchRev);
545 InsertConfigInteger(pCfg, "DistributorMmioBase", GCPhysIntcDist);
546 InsertConfigInteger(pCfg, "RedistributorMmioBase", GCPhysIntcReDist);
547 if (fGicIts == TRUE)
548 {
549 InsertConfigInteger(pCfg, "ItsMmioBase", GCPhysIntcIts);
550 InsertConfigInteger(pCfg, "Lpi", 1);
551 InsertConfigInteger(pCfg, "Mbi", 1);
552 }
553 else
554 GCPhysIntcIts = cbMmioIntcIts = 0;
555
556 vrc = RTFdtNodeAddF(hFdt, "intc@%RGp", GCPhysIntcDist); VRC();
557 vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleIntCtrl); VRC();
558 vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 4,
559 GCPhysIntcDist, cbMmioIntcDist, /* Distributor */
560 GCPhysIntcReDist, cbMmioIntcReDist); /* Re-Distributor */ VRC();
561 vrc = RTFdtNodePropertyAddU32( hFdt, "#redistributor-regions", 1); VRC();
562 vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,gic-v3"); VRC();
563 vrc = RTFdtNodePropertyAddEmpty( hFdt, "ranges"); VRC();
564 vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
565 vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 2); VRC();
566 vrc = RTFdtNodePropertyAddEmpty( hFdt, "interrupt-controller"); VRC();
567 vrc = RTFdtNodePropertyAddU32( hFdt, "#interrupt-cells", 3); VRC();
568
569 if (pSysTblsBldAcpi)
570 {
571 vrc = pSysTblsBldAcpi->configureGic(cCpus, GCPhysIntcDist, cbMmioIntcDist,
572 GCPhysIntcReDist, cbMmioIntcReDist, GCPhysIntcIts, cbMmioIntcIts);
573 VRC();
574 }
575
576#if 0
577 if (fGicIts == TRUE)
578 {
579 vrc = RTFdtNodePropertyAddEmpty(hFdt, "msi-controller"); VRC();
580 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "mbi-ranges", 2, 256, 128); VRC();
581
582 vrc = RTFdtNodeAddF(hFdt, "gic-its@%RGp", GCPhysIntcIts); VRC();
583 vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleIntCtrlMsi); VRC();
584 vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysIntcIts, cbMmioIntcIts); VRC();
585 vrc = RTFdtNodePropertyAddU32( hFdt, "#msi-cells", 1); VRC();
586 vrc = RTFdtNodePropertyAddEmpty( hFdt, "msi-controller"); VRC();
587 vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "arm,gic-v3-its"); VRC();
588 vrc = RTFdtNodeFinalize(hFdt); VRC();
589 }
590#endif
591
592 vrc = RTFdtNodeFinalize(hFdt); VRC();
593
594 /*
595 * Configure the performance monitoring unit.
596 */
597 /** @todo Make this configurable and enable as default for Windows VMs because they assume a working PMU
598 * (which is not available in hardware on AppleSilicon).
599 */
600 InsertConfigNode(pDevices, "pmu", &pDev);
601 InsertConfigNode(pDev, "0", &pInst);
602 InsertConfigInteger(pInst, "Trusted", 1);
603 InsertConfigNode(pInst, "Config", &pCfg);
604
605 RTGCPHYS GCPhysMmioStart;
606 RTGCPHYS cbMmio;
607 if (enmGraphicsController == GraphicsControllerType_QemuRamFB)
608 {
609 hrc = pResMgr->assignMmioRegion("qemu-fw-cfg", _4K, &GCPhysMmioStart, &cbMmio); H();
610
611 InsertConfigNode(pDevices, "qemu-fw-cfg", &pDev);
612 InsertConfigNode(pDev, "0", &pInst);
613 InsertConfigNode(pInst, "Config", &pCfg);
614 InsertConfigInteger(pCfg, "MmioSize", cbMmio);
615 InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
616 InsertConfigInteger(pCfg, "DmaEnabled", 1);
617 InsertConfigInteger(pCfg, "QemuRamfbSupport", 1);
618 InsertConfigNode(pInst, "LUN#0", &pLunL0);
619 InsertConfigString(pLunL0, "Driver", "MainDisplay");
620
621 vrc = RTFdtNodeAddF(hFdt, "fw-cfg@%RGp", GCPhysMmioStart); VRC();
622 vrc = RTFdtNodePropertyAddEmpty( hFdt, "dma-coherent"); VRC();
623 vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
624 vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "qemu,fw-cfg-mmio"); VRC();
625 vrc = RTFdtNodeFinalize(hFdt); VRC();
626
627 if (pSysTblsBldAcpi)
628 {
629 vrc = pSysTblsBldAcpi->addMmioDeviceNoIrq("qemu-fw-cfg", 0, GCPhysMmioStart, cbMmio);
630 VRC();
631 }
632 }
633
634 InsertConfigNode(pDevices, "flash-cfi", &pDev);
635 InsertConfigNode(pDev, "0", &pInst);
636 InsertConfigNode(pInst, "Config", &pCfg);
637 InsertConfigInteger(pCfg, "BaseAddress", GCPhysFlash);
638 InsertConfigInteger(pCfg, "Size", 768 * _1K);
639 InsertConfigString(pCfg, "FlashFile", "nvram");
640 /* Attach the NVRAM storage driver. */
641 InsertConfigNode(pInst, "LUN#0", &pLunL0);
642 InsertConfigString(pLunL0, "Driver", "NvramStore");
643
644 vrc = RTFdtNodeAddF(hFdt, "flash@%RX32", 0); VRC();
645 vrc = RTFdtNodePropertyAddU32( hFdt, "bank-width", 4); VRC();
646 vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 4,
647 GCPhysFw, cbFw, /* First region (EFI). */
648 GCPhysFlash, 3 * _256K); /* Second region (NVRAM), see NvramStoreImpl.cpp for an explanation of the size choice. */ VRC();
649 vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "cfi-flash"); VRC();
650 vrc = RTFdtNodeFinalize(hFdt); VRC();
651
652 InsertConfigNode(pDevices, "arm-pl011", &pDev);
653 for (ULONG ulInstance = 0; ulInstance < 1 /** @todo SchemaDefs::SerialPortCount*/; ++ulInstance)
654 {
655 ComPtr<ISerialPort> serialPort;
656 hrc = pMachine->GetSerialPort(ulInstance, serialPort.asOutParam()); H();
657 BOOL fEnabledSerPort = FALSE;
658 if (serialPort)
659 {
660 hrc = serialPort->COMGETTER(Enabled)(&fEnabledSerPort); H();
661 }
662 if (!fEnabledSerPort)
663 {
664 m_aeSerialPortMode[ulInstance] = PortMode_Disconnected;
665 continue;
666 }
667
668 InsertConfigNode(pDev, Utf8StrFmt("%u", ulInstance).c_str(), &pInst);
669 InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
670 InsertConfigNode(pInst, "Config", &pCfg);
671
672 uint32_t iIrq = 0;
673 hrc = pResMgr->assignSingleInterrupt("arm-pl011", &iIrq); H();
674 hrc = pResMgr->assignMmioRegion("arm-pl011", _4K, &GCPhysMmioStart, &cbMmio); H();
675
676 InsertConfigInteger(pCfg, "Irq", iIrq);
677 InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
678
679 vrc = RTFdtNodeAddF(hFdt, "pl011@%RGp", GCPhysMmioStart); VRC();
680 vrc = RTFdtNodePropertyAddStringList(hFdt, "clock-names", 2, "uartclk", "apb_pclk"); VRC();
681 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "clocks", 2,
682 idPHandleAbpPClk, idPHandleAbpPClk); VRC();
683 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, iIrq, 0x04); VRC();
684 vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
685 vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
686 "arm,pl011", "arm,primecell"); VRC();
687 vrc = RTFdtNodeFinalize(hFdt); VRC();
688
689 if (pSysTblsBldAcpi)
690 {
691 vrc = pSysTblsBldAcpi->addMmioDevice("arm-pl011", ulInstance, GCPhysMmioStart, cbMmio, iIrq);
692 VRC();
693 }
694
695 BOOL fServer;
696 hrc = serialPort->COMGETTER(Server)(&fServer); H();
697 hrc = serialPort->COMGETTER(Path)(bstr.asOutParam()); H();
698
699 PortMode_T eHostMode;
700 hrc = serialPort->COMGETTER(HostMode)(&eHostMode); H();
701
702 m_aeSerialPortMode[ulInstance] = eHostMode;
703 if (eHostMode != PortMode_Disconnected)
704 {
705 vrc = i_configSerialPort(pInst, eHostMode, Utf8Str(bstr).c_str(), RT_BOOL(fServer));
706 if (RT_FAILURE(vrc))
707 return vrc;
708 }
709 }
710
711 BOOL fRTCUseUTC;
712 hrc = platform->COMGETTER(RTCUseUTC)(&fRTCUseUTC); H();
713
714 uint32_t iIrq = 0;
715 hrc = pResMgr->assignSingleInterrupt("arm-pl031-rtc", &iIrq); H();
716 hrc = pResMgr->assignMmioRegion("arm-pl031-rtc", _4K, &GCPhysMmioStart, &cbMmio); H();
717 InsertConfigNode(pDevices, "arm-pl031-rtc", &pDev);
718 InsertConfigNode(pDev, "0", &pInst);
719 InsertConfigNode(pInst, "Config", &pCfg);
720 InsertConfigInteger(pCfg, "Irq", iIrq);
721 InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
722 InsertConfigInteger(pCfg, "UtcOffset", fRTCUseUTC ? 1 : 0);
723
724 vrc = RTFdtNodeAddF(hFdt, "pl032@%RGp", GCPhysMmioStart); VRC();
725 vrc = RTFdtNodePropertyAddString( hFdt, "clock-names", "apb_pclk"); VRC();
726 vrc = RTFdtNodePropertyAddU32( hFdt, "clocks", idPHandleAbpPClk); VRC();
727 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, iIrq, 0x04); VRC();
728 vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
729 vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
730 "arm,pl031", "arm,primecell"); VRC();
731 vrc = RTFdtNodeFinalize(hFdt); VRC();
732
733 /* Configure gpio keys (The Windows GPIO PL061 driver doesn't like 64-bit MMIO addresses...). */
734 hrc = pResMgr->assignSingleInterrupt("arm-pl061-gpio", &iIrq); H();
735 hrc = pResMgr->assignMmio32Region("arm-pl061-gpio", _4K, &GCPhysMmioStart, &cbMmio); H();
736 InsertConfigNode(pDevices, "arm-pl061-gpio",&pDev);
737 InsertConfigNode(pDev, "0", &pInst);
738 InsertConfigNode(pInst, "Config", &pCfg);
739 InsertConfigInteger(pCfg, "Irq", iIrq);
740 InsertConfigInteger(pCfg, "MmioBase", GCPhysMmioStart);
741 vrc = RTFdtNodeAddF(hFdt, "pl061@%RGp", GCPhysMmioStart); VRC();
742 vrc = RTFdtNodePropertyAddU32( hFdt, "phandle", idPHandleGpio); VRC();
743 vrc = RTFdtNodePropertyAddString( hFdt, "clock-names", "apb_pclk"); VRC();
744 vrc = RTFdtNodePropertyAddU32( hFdt, "clocks", idPHandleAbpPClk); VRC();
745 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, iIrq, 0x04); VRC();
746 vrc = RTFdtNodePropertyAddEmpty( hFdt, "gpio-controller"); VRC();
747 vrc = RTFdtNodePropertyAddU32( hFdt, "#gpio-cells", 2); VRC();
748 vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 2,
749 "arm,pl061", "arm,primecell"); VRC();
750 vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysMmioStart, cbMmio); VRC();
751 vrc = RTFdtNodeFinalize(hFdt); VRC();
752
753 InsertConfigNode(pInst, "LUN#0", &pLunL0);
754 InsertConfigString(pLunL0, "Driver", "GpioButton");
755 InsertConfigNode(pLunL0, "Config", &pCfg);
756 InsertConfigInteger(pCfg, "PowerButtonGpio", 3);
757 InsertConfigInteger(pCfg, "SleepButtonGpio", 4);
758
759 vrc = RTFdtNodeAdd(hFdt, "gpio-keys"); VRC();
760 vrc = RTFdtNodePropertyAddString(hFdt, "compatible", "gpio-keys"); VRC();
761
762 vrc = RTFdtNodeAdd(hFdt, "poweroff"); VRC();
763 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "gpios", 3, idPHandleGpio, 3, 0); VRC();
764 vrc = RTFdtNodePropertyAddU32( hFdt, "linux,code", 0x74); VRC();
765 vrc = RTFdtNodePropertyAddString( hFdt, "label", "GPIO Key Poweroff"); VRC();
766 vrc = RTFdtNodeFinalize(hFdt); VRC();
767
768 vrc = RTFdtNodeAdd(hFdt, "suspend"); VRC();
769 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "gpios", 3, idPHandleGpio, 4, 0); VRC();
770 vrc = RTFdtNodePropertyAddU32( hFdt, "linux,code", 0xcd); VRC();
771 vrc = RTFdtNodePropertyAddString( hFdt, "label", "GPIO Key Suspend"); VRC();
772 vrc = RTFdtNodeFinalize(hFdt); VRC();
773
774 vrc = RTFdtNodeFinalize(hFdt); VRC();
775
776 if (pSysTblsBldAcpi)
777 {
778 vrc = pSysTblsBldAcpi->configureGpioDevice("arm-pl061-gpio", 0, GCPhysMmioStart, cbMmio, iIrq,
779 3 /*u16PinShutdown*/, 4 /*u16PinSuspend*/);
780 VRC();
781 }
782
783#if defined(VBOX_WITH_TPM)
784 /*
785 * Configure the Trusted Platform Module.
786 */
787 ComObjPtr<ITrustedPlatformModule> ptrTpm;
788 TpmType_T enmTpmType = TpmType_None;
789
790 hrc = pMachine->COMGETTER(TrustedPlatformModule)(ptrTpm.asOutParam()); H();
791 hrc = ptrTpm->COMGETTER(Type)(&enmTpmType); H();
792 if (enmTpmType != TpmType_None)
793 {
794 hrc = pResMgr->assignSingleInterrupt("tpm", &iIrq); H();
795
796 vrc = i_configTpm(ptrTpm, enmTpmType, pDevices, GCPhysTpm, iIrq /*uIrq*/,
797 GCPhysTpm + 0x5000, true /*fCrb*/); VRC();
798
799 vrc = RTFdtNodeAddF(hFdt, "tpm@%RGp", GCPhysTpm); VRC();
800 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupts", 3, 0x00, iIrq, 0x04); VRC();
801 vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysTpm, cbTpm); VRC();
802 vrc = RTFdtNodePropertyAddStringList(hFdt, "compatible", 1, "tcg,tpm-tis-mmio"); VRC();
803 vrc = RTFdtNodeFinalize(hFdt); VRC();
804
805 if (pSysTblsBldAcpi)
806 {
807 vrc = pSysTblsBldAcpi->configureTpm2(true /*fCrb*/, GCPhysTpm, cbTpm, iIrq);
808 VRC();
809 }
810 }
811#endif
812
813 hrc = pResMgr->assignInterrupts("pci-generic-ecam", 4 /*cInterrupts*/, &iIrq); H();
814 uint32_t aPinIrqs[] = { iIrq, iIrq + 1, iIrq + 2, iIrq + 3 };
815 RTGCPHYS GCPhysPciMmioEcam, GCPhysPciMmio, GCPhysPciMmio32;
816 RTGCPHYS cbPciMmioEcam, cbPciMmio, cbPciMmio32;
817
818 hrc = pResMgr->assignMmioRegionAligned("pci-pio", _64K, _64K, &GCPhysMmioStart, &cbMmio, false /*fOnly32Bit*/); H();
819 hrc = pResMgr->assignMmioRegion( "pci-ecam", 16 * _1M, &GCPhysPciMmioEcam, &cbPciMmioEcam); H();
820 hrc = pResMgr->assignMmio64Region( "pci-mmio", _2G, &GCPhysPciMmio, &cbPciMmio); H();
821 hrc = pResMgr->assignMmio32Region( "pci-mmio32", _256M, &GCPhysPciMmio32, &cbPciMmio32); H();
822
823 InsertConfigNode(pDevices, "pci-generic-ecam", &pDev);
824 InsertConfigNode(pDev, "0", &pInst);
825 InsertConfigNode(pInst, "Config", &pCfg);
826 InsertConfigInteger(pCfg, "MmioEcamBase", GCPhysPciMmioEcam);
827 InsertConfigInteger(pCfg, "MmioEcamLength", cbPciMmioEcam);
828 InsertConfigInteger(pCfg, "MmioPioBase", GCPhysMmioStart);
829 InsertConfigInteger(pCfg, "MmioPioSize", cbMmio);
830 InsertConfigInteger(pCfg, "IntPinA", aPinIrqs[0]);
831 InsertConfigInteger(pCfg, "IntPinB", aPinIrqs[1]);
832 InsertConfigInteger(pCfg, "IntPinC", aPinIrqs[2]);
833 InsertConfigInteger(pCfg, "IntPinD", aPinIrqs[3]);
834 if (fGicIts == TRUE)
835 InsertConfigInteger(pCfg, "Msi", 1);
836 vrc = RTFdtNodeAddF(hFdt, "pcie@%RGp", GCPhysPciMmio); VRC();
837 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "interrupt-map-mask", 4, 0xf800, 0, 0, 7); VRC();
838
839 uint32_t aIrqCells[32 * 4 * 10]; RT_ZERO(aIrqCells); /* Maximum of 32 devices on the root bus, each supporting 4 interrupts (INTA# ... INTD#). */
840 uint32_t *pau32IrqCell = &aIrqCells[0];
841 uint32_t iIrqPinSwizzle = 0;
842
843 for (uint32_t i = 0; i < 32; i++)
844 {
845 for (uint32_t iIrqPin = 0; iIrqPin < 4; iIrqPin++)
846 {
847 pau32IrqCell[0] = i << 11; /* The dev part, composed as dev.fn. */
848 pau32IrqCell[1] = 0;
849 pau32IrqCell[2] = 0;
850 pau32IrqCell[3] = iIrqPin + 1;
851 pau32IrqCell[4] = idPHandleIntCtrl;
852 pau32IrqCell[5] = 0;
853 pau32IrqCell[6] = 0;
854 pau32IrqCell[7] = 0;
855 pau32IrqCell[8] = aPinIrqs[(iIrqPinSwizzle + iIrqPin) % RT_ELEMENTS(aPinIrqs)];
856 pau32IrqCell[9] = 0x04;
857 pau32IrqCell += 10;
858 }
859
860 iIrqPinSwizzle++;
861 }
862
863 vrc = RTFdtNodePropertyAddCellsU32AsArray(hFdt, "interrupt-map", RT_ELEMENTS(aIrqCells), &aIrqCells[0]); VRC();
864 vrc = RTFdtNodePropertyAddU32( hFdt, "#interrupt-cells", 1); VRC();
865 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "ranges", 21,
866 0x1000000, 0, 0,
867 GCPhysMmioStart >> 32, GCPhysMmioStart, cbMmio >> 32, cbMmio,
868 0x2000000, GCPhysPciMmio32 >> 32, GCPhysPciMmio32, GCPhysPciMmio32 >> 32, GCPhysPciMmio32,
869 cbPciMmio32 >> 32, cbPciMmio32,
870 0x3000000, GCPhysPciMmio >> 32, GCPhysPciMmio, GCPhysPciMmio >> 32, GCPhysPciMmio,
871 cbPciMmio >> 32, cbPciMmio); VRC();
872 vrc = RTFdtNodePropertyAddCellsU64(hFdt, "reg", 2, GCPhysPciMmioEcam, cbPciMmioEcam); VRC();
873 /** @todo msi-map */
874#if 0
875 if (fGicIts == TRUE)
876 {
877 vrc = RTFdtNodePropertyAddCellsU64(hFdt, "msi-map", 4, 0, GCPhysIntcIts, 0, cbMmioIntcIts);
878 VRC();
879 }
880#endif
881 vrc = RTFdtNodePropertyAddEmpty( hFdt, "dma-coherent"); VRC();
882 vrc = RTFdtNodePropertyAddCellsU32(hFdt, "bus-range", 2, 0, 0xf); VRC();
883 vrc = RTFdtNodePropertyAddU32( hFdt, "linux,pci-domain", 0); VRC();
884 vrc = RTFdtNodePropertyAddU32( hFdt, "#size-cells", 2); VRC();
885 vrc = RTFdtNodePropertyAddU32( hFdt, "#address-cells", 3); VRC();
886 vrc = RTFdtNodePropertyAddString( hFdt, "device_type", "pci"); VRC();
887 vrc = RTFdtNodePropertyAddString( hFdt, "compatible", "pci-host-ecam-generic"); VRC();
888 vrc = RTFdtNodeFinalize(hFdt); VRC();
889
890 if (pSysTblsBldAcpi)
891 {
892 vrc = pSysTblsBldAcpi->configurePcieRootBus("pci-generic-ecam", aPinIrqs, GCPhysMmioStart, GCPhysPciMmioEcam,
893 cbPciMmioEcam, GCPhysMmioStart, cbMmio, GCPhysPciMmio32, cbPciMmio32);
894 VRC();
895 }
896
897 /*
898 * VMSVGA compliant graphics controller.
899 */
900 if ( enmGraphicsController != GraphicsControllerType_QemuRamFB
901 && enmGraphicsController != GraphicsControllerType_Null)
902 {
903 vrc = i_configGraphicsController(pDevices, enmGraphicsController, pBusMgr, pMachine,
904 pGraphicsAdapter, firmwareSettings,
905 true /*fForceVmSvga3*/, false /*fExposeLegacyVga*/); VRC();
906 }
907
908 /*
909 * The USB Controllers and input devices.
910 */
911#if 0 /** @todo Make us of this and disallow PS/2 for ARM VMs for now. */
912 KeyboardHIDType_T aKbdHID;
913 hrc = pMachine->COMGETTER(KeyboardHIDType)(&aKbdHID); H();
914#endif
915
916 PointingHIDType_T aPointingHID;
917 hrc = pMachine->COMGETTER(PointingHIDType)(&aPointingHID); H();
918
919 PCFGMNODE pUsbDevices = NULL;
920 vrc = i_configUsb(pMachine, pBusMgr, pRoot, pDevices, KeyboardHIDType_USBKeyboard, aPointingHID, &pUsbDevices);
921
922 /*
923 * Storage controllers.
924 */
925 bool fFdcEnabled = false;
926 vrc = i_configStorageCtrls(pMachine, pBusMgr, pVMM, pUVM,
927 pDevices, pUsbDevices, NULL /*pBiosCfg*/, &fFdcEnabled); VRC();
928
929 /*
930 * Network adapters
931 */
932 std::list<BootNic> llBootNics;
933 vrc = i_configNetworkCtrls(pMachine, pPlatformProperties, chipsetType, pBusMgr,
934 pVMM, pUVM, pDevices, pUsbDevices, llBootNics); VRC();
935
936 /*
937 * The VMM device.
938 */
939 vrc = i_configVmmDev(pMachine, pBusMgr, pDevices, true /*fMmioReq*/); VRC();
940
941 /*
942 * Audio configuration.
943 */
944 bool fAudioEnabled = false;
945 vrc = i_configAudioCtrl(virtualBox, pMachine, pBusMgr, pDevices,
946 false /*fOsXGuest*/, &fAudioEnabled); VRC();
947
948 /*
949 * Configure DBGF (Debug(ger) Facility) and DBGC (Debugger Console).
950 */
951 vrc = i_configGuestDbg(virtualBox, pMachine, pRoot); VRC();
952 }
953 catch (ConfigError &x)
954 {
955 RTFdtDestroy(hFdt);
956
957 // InsertConfig threw something:
958 pVMM->pfnVMR3SetError(pUVM, x.m_vrc, RT_SRC_POS, "Caught ConfigError: %Rrc - %s", x.m_vrc, x.what());
959 return x.m_vrc;
960 }
961 catch (HRESULT hrcXcpt)
962 {
963 RTFdtDestroy(hFdt);
964 AssertLogRelMsgFailedReturn(("hrc=%Rhrc\n", hrcXcpt), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR);
965 }
966
967#ifdef VBOX_WITH_EXTPACK
968 /*
969 * Call the extension pack hooks if everything went well thus far.
970 */
971 if (RT_SUCCESS(vrc))
972 {
973 pAlock->release();
974 vrc = mptrExtPackManager->i_callAllVmConfigureVmmHooks(this, pVM, pVMM);
975 pAlock->acquire();
976 AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
977 }
978#endif
979
980#if 0
981 vrc = RTFdtNodeAdd(hFdt, "chosen"); VRC();
982 vrc = RTFdtNodePropertyAddString( hFdt, "stdout-path", "pl011@9000000"); VRC();
983 vrc = RTFdtNodePropertyAddString( hFdt, "stdin-path", "pl011@9000000"); VRC();
984 vrc = RTFdtNodeFinalize(hFdt);
985#endif
986
987 /* Finalize the FDT and add it to the resource store. */
988 vrc = RTFdtFinalize(hFdt);
989 AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
990
991 RTVFSFILE hVfsFileDesc = NIL_RTVFSFILE;
992 vrc = RTVfsMemFileCreate(NIL_RTVFSIOSTREAM, 0 /*cbEstimate*/, &hVfsFileDesc);
993 AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
994 RTVFSIOSTREAM hVfsIosDesc = RTVfsFileToIoStream(hVfsFileDesc);
995 AssertRelease(hVfsIosDesc != NIL_RTVFSIOSTREAM);
996
997 /* Initialize the VBox platform descriptor. */
998 VBOXPLATFORMARMV8 ArmV8Platform; RT_ZERO(ArmV8Platform);
999
1000 vrc = RTFdtDumpToVfsIoStrm(hFdt, RTFDTTYPE_DTB, 0 /*fFlags*/, hVfsIosDesc, NULL /*pErrInfo*/);
1001 uint64_t cbFdt = 0;
1002 if (RT_SUCCESS(vrc))
1003 vrc = RTVfsFileQuerySize(hVfsFileDesc, &cbFdt);
1004 AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
1005
1006 vrc = RTVfsIoStrmZeroFill(hVfsIosDesc, (RTFOFF)(RT_ALIGN_64(cbFdt, _64K) - cbFdt));
1007 AssertRCReturn(vrc, vrc);
1008
1009 cbFdt = RT_ALIGN_64(cbFdt, _64K);
1010
1011 RTGCPHYS GCPhysMmioStart;
1012 RTGCPHYS cbMmio;
1013 hrc = pResMgr->queryMmioRegion(&GCPhysMmioStart, &cbMmio);
1014 Assert(SUCCEEDED(hrc));
1015
1016 RTGCPHYS GCPhysMmio32Start;
1017 RTGCPHYS cbMmio32;
1018 hrc = pResMgr->queryMmio32Region(&GCPhysMmio32Start, &cbMmio32);
1019 Assert(SUCCEEDED(hrc));
1020
1021 RTGCPHYS GCPhysXsdp = NIL_RTGCPHYS;
1022 size_t cbAcpiXsdp = 0;
1023 size_t cbAcpi = 0;
1024 if (pSysTblsBldAcpi)
1025 {
1026 vrc = pSysTblsBldAcpi->finishTables(GCPhysPlatformDesc + cbFdt,
1027 hVfsIosDesc, &GCPhysXsdp, &cbAcpiXsdp, &cbAcpi);
1028 AssertRCReturn(vrc, vrc);
1029 Assert( GCPhysXsdp > GCPhysPlatformDesc
1030 && GCPhysXsdp < VBOXPLATFORMARMV8_PHYS_ADDR);
1031
1032 /* Dump the ACPI table for debugging purposes if requested. */
1033 Bstr SysTblsDumpVal;
1034 hrc = mMachine->GetExtraData(Bstr("VBoxInternal2/DumpSysTables").raw(),
1035 SysTblsDumpVal.asOutParam());
1036 if ( hrc == S_OK
1037 && SysTblsDumpVal.isNotEmpty())
1038 {
1039 vrc = pSysTblsBldAcpi->dumpTables(Utf8Str(SysTblsDumpVal).c_str());
1040 AssertRCReturn(vrc, vrc);
1041 }
1042
1043 delete pSysTblsBldAcpi;
1044
1045 vrc = RTVfsIoStrmZeroFill(hVfsIosDesc, (RTFOFF)(RT_ALIGN_64(cbAcpi, _64K) - cbAcpi));
1046 AssertRCReturn(vrc, vrc);
1047
1048 cbAcpi = RT_ALIGN_64(cbAcpi, _64K);
1049 }
1050
1051 /* Fill the room until the end where the platform descriptor lives. */
1052 vrc = RTVfsIoStrmZeroFill(hVfsIosDesc, cbPlatformDesc - sizeof(ArmV8Platform) - cbFdt - cbAcpi);
1053 AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
1054
1055 RTGCPHYS GCPhysMmio = 0;
1056 RTGCPHYS cbMmioAbove4G = 0;
1057 pResMgr->queryMmioRegion(&GCPhysMmio, &cbMmioAbove4G);
1058
1059 ArmV8Platform.u32Magic = VBOXPLATFORMARMV8_MAGIC;
1060 ArmV8Platform.u32Version = VBOXPLATFORMARMV8_VERSION;
1061 ArmV8Platform.cbDesc = sizeof(ArmV8Platform);
1062 ArmV8Platform.fFlags = 0;
1063 ArmV8Platform.u64PhysAddrRamBase = GCPhysRamBase;
1064 ArmV8Platform.cbRamBase = cbRamBase;
1065 ArmV8Platform.i64OffFdt = (int64_t)GCPhysPlatformDesc - VBOXPLATFORMARMV8_PHYS_ADDR;
1066 ArmV8Platform.cbFdt = cbFdt;
1067 if (cbAcpi)
1068 {
1069 ArmV8Platform.i64OffAcpi = (int64_t)(GCPhysPlatformDesc + cbFdt) - VBOXPLATFORMARMV8_PHYS_ADDR;
1070 ArmV8Platform.cbAcpi = cbAcpi;
1071 ArmV8Platform.i64OffAcpiXsdp = (int64_t)GCPhysXsdp - VBOXPLATFORMARMV8_PHYS_ADDR;
1072 ArmV8Platform.cbAcpiXsdp = cbAcpiXsdp;
1073 }
1074 ArmV8Platform.i64OffUefiRom = (int64_t)GCPhysFw - VBOXPLATFORMARMV8_PHYS_ADDR;
1075 ArmV8Platform.cbUefiRom = _64M;
1076 ArmV8Platform.i64OffMmio = GCPhysMmio ? (int64_t)GCPhysMmio - VBOXPLATFORMARMV8_PHYS_ADDR : 0;
1077 ArmV8Platform.cbMmio = cbMmioAbove4G;
1078 ArmV8Platform.i64OffMmio32 = (int64_t)(_4G - _512M) - VBOXPLATFORMARMV8_PHYS_ADDR;
1079 ArmV8Platform.cbMmio32 = _512M - _2M; /* Just assign the whole MMIO hole (except for the platform descriptor region). */
1080
1081 /* Add the VBox platform descriptor to the resource store. */
1082 vrc = RTVfsIoStrmWrite(hVfsIosDesc, &ArmV8Platform, sizeof(ArmV8Platform), true /*fBlocking*/, NULL /*pcbWritten*/);
1083 RTVfsIoStrmRelease(hVfsIosDesc);
1084 AssertRCReturnStmt(vrc, RTVfsFileRelease(hVfsFileDesc), vrc);
1085
1086 vrc = mptrResourceStore->i_addItem("resources", "VBoxArmV8Desc", hVfsFileDesc);
1087 RTVfsFileRelease(hVfsFileDesc);
1088 AssertRCReturn(vrc, vrc);
1089
1090 /* Dump the DTB for debugging purposes if requested. */
1091 Bstr DtbDumpVal;
1092 hrc = mMachine->GetExtraData(Bstr("VBoxInternal2/DumpDtb").raw(),
1093 DtbDumpVal.asOutParam());
1094 if ( hrc == S_OK
1095 && DtbDumpVal.isNotEmpty())
1096 {
1097 vrc = RTFdtDumpToFile(hFdt, RTFDTTYPE_DTB, 0 /*fFlags*/, Utf8Str(DtbDumpVal).c_str(), NULL /*pErrInfo*/);
1098 AssertRCReturnStmt(vrc, RTFdtDestroy(hFdt), vrc);
1099 }
1100
1101 pResMgr->dumpMemoryRegionsToReleaseLog();
1102
1103 delete pResMgr; /* Delete the address/interrupt assignment manager. */
1104
1105 /*
1106 * Apply the CFGM overlay.
1107 */
1108 if (RT_SUCCESS(vrc))
1109 vrc = i_configCfgmOverlay(pRoot, virtualBox, pMachine);
1110
1111 /*
1112 * Dump all extradata API settings tweaks, both global and per VM.
1113 */
1114 if (RT_SUCCESS(vrc))
1115 vrc = i_configDumpAPISettingsTweaks(virtualBox, pMachine);
1116
1117#undef H
1118
1119 pAlock->release(); /* Avoid triggering the lock order inversion check. */
1120
1121 /*
1122 * Register VM state change handler.
1123 */
1124 int vrc2 = pVMM->pfnVMR3AtStateRegister(pUVM, Console::i_vmstateChangeCallback, this);
1125 AssertRC(vrc2);
1126 if (RT_SUCCESS(vrc))
1127 vrc = vrc2;
1128
1129 /*
1130 * Register VM runtime error handler.
1131 */
1132 vrc2 = pVMM->pfnVMR3AtRuntimeErrorRegister(pUVM, Console::i_atVMRuntimeErrorCallback, this);
1133 AssertRC(vrc2);
1134 if (RT_SUCCESS(vrc))
1135 vrc = vrc2;
1136
1137 pAlock->acquire();
1138
1139 LogFlowFunc(("vrc = %Rrc\n", vrc));
1140 LogFlowFuncLeave();
1141
1142 return vrc;
1143}
1144#endif /* !VBOX_WITH_VIRT_ARMV8 */
1145
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