VirtualBox

source: vbox/trunk/src/VBox/HostDrivers/Support/testcase/tstGIP-2.cpp@ 57060

Last change on this file since 57060 was 57060, checked in by vboxsync, 10 years ago

testcase/tstGIP-2: Allow continuous comparison of computed GIP TSC frequency with a supplied reference value.
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1/* $Id: tstGIP-2.cpp 57060 2015-07-23 13:18:58Z vboxsync $ */
2/** @file
3 * SUP Testcase - Global Info Page interface (ring 3).
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.215389.xyz. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * The contents of this file may alternatively be used under the terms
18 * of the Common Development and Distribution License Version 1.0
19 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20 * VirtualBox OSE distribution, in which case the provisions of the
21 * CDDL are applicable instead of those of the GPL.
22 *
23 * You may elect to license modified versions of this file under the
24 * terms and conditions of either the GPL or the CDDL or both.
25 */
26
27/*******************************************************************************
28* Header Files *
29*******************************************************************************/
30#include <VBox/sup.h>
31#include <VBox/err.h>
32#include <VBox/param.h>
33#include <iprt/asm.h>
34#include <iprt/assert.h>
35#include <iprt/alloc.h>
36#include <iprt/thread.h>
37#include <iprt/stream.h>
38#include <iprt/string.h>
39#include <iprt/initterm.h>
40#include <iprt/getopt.h>
41#include <iprt/x86.h>
42
43
44/**
45 * Checks whether the CPU advertises an invariant TSC or not.
46 *
47 * @returns true if invariant, false otherwise.
48 */
49bool tstIsInvariantTsc(void)
50{
51 if (ASMHasCpuId())
52 {
53 uint32_t uEax, uEbx, uEcx, uEdx;
54 ASMCpuId(0x80000000, &uEax, &uEbx, &uEcx, &uEdx);
55 if (uEax >= 0x80000007)
56 {
57 ASMCpuId(0x80000007, &uEax, &uEbx, &uEcx, &uEdx);
58 if (uEdx & X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR)
59 return true;
60 }
61 }
62 return false;
63}
64
65
66int main(int argc, char **argv)
67{
68 RTR3InitExe(argc, &argv, 0);
69
70 /*
71 * Parse args
72 */
73 static const RTGETOPTDEF g_aOptions[] =
74 {
75 { "--iterations", 'i', RTGETOPT_REQ_INT32 },
76 { "--hex", 'h', RTGETOPT_REQ_NOTHING },
77 { "--decimal", 'd', RTGETOPT_REQ_NOTHING },
78 { "--spin", 's', RTGETOPT_REQ_NOTHING },
79 { "--reference", 'r', RTGETOPT_REQ_UINT64 }, /* reference value of CpuHz, display the
80 * CpuHz deviation in a separate column. */
81 };
82
83 uint32_t cIterations = 40;
84 bool fHex = true;
85 bool fSpin = false;
86 bool fCompat = true;
87 int ch;
88 uint64_t uCpuHzRef = 0;
89 uint64_t uCpuHzOverallDeviation = 0;
90 uint32_t cCpuHzNotCompat = 0;
91 int64_t iCpuHzMaxDeviation = 0;
92 int32_t cCpuHzOverallDevCnt = 0;
93 RTGETOPTUNION ValueUnion;
94 RTGETOPTSTATE GetState;
95 RTGetOptInit(&GetState, argc, argv, g_aOptions, RT_ELEMENTS(g_aOptions), 1, RTGETOPTINIT_FLAGS_NO_STD_OPTS);
96 while ((ch = RTGetOpt(&GetState, &ValueUnion)))
97 {
98 switch (ch)
99 {
100 case 'i':
101 cIterations = ValueUnion.u32;
102 break;
103
104 case 'd':
105 fHex = false;
106 break;
107
108 case 'h':
109 fHex = true;
110 break;
111
112 case 's':
113 fSpin = true;
114 break;
115
116 case 'r':
117 uCpuHzRef = ValueUnion.u64;
118 break;
119
120 default:
121 return RTGetOptPrintError(ch, &ValueUnion);
122 }
123 }
124
125 /*
126 * Init
127 */
128 PSUPDRVSESSION pSession = NIL_RTR0PTR;
129 int rc = SUPR3Init(&pSession);
130 if (RT_SUCCESS(rc))
131 {
132 if (g_pSUPGlobalInfoPage)
133 {
134 RTPrintf("tstGIP-2: cCpus=%d u32UpdateHz=%RU32 u32UpdateIntervalNS=%RU32 u64NanoTSLastUpdateHz=%RX64 u64CpuHz=%RU64 uCpuHzRef=%RU64 u32Mode=%d (%s) u32Version=%#x\n",
135 g_pSUPGlobalInfoPage->cCpus,
136 g_pSUPGlobalInfoPage->u32UpdateHz,
137 g_pSUPGlobalInfoPage->u32UpdateIntervalNS,
138 g_pSUPGlobalInfoPage->u64NanoTSLastUpdateHz,
139 g_pSUPGlobalInfoPage->u64CpuHz,
140 uCpuHzRef,
141 g_pSUPGlobalInfoPage->u32Mode,
142 SUPGetGIPModeName(g_pSUPGlobalInfoPage),
143 g_pSUPGlobalInfoPage->u32Version);
144 RTPrintf(fHex
145 ? "tstGIP-2: it: u64NanoTS delta u64TSC UpIntTSC H TransId CpuHz %sTSC Interval History...\n"
146 : "tstGIP-2: it: u64NanoTS delta u64TSC UpIntTSC H TransId CpuHz %sTSC Interval History...\n",
147 uCpuHzRef ? " CpuHz deviation Compat " : "");
148 static SUPGIPCPU s_aaCPUs[2][256];
149 for (uint32_t i = 0; i < cIterations; i++)
150 {
151 /* copy the data */
152 memcpy(&s_aaCPUs[i & 1][0], &g_pSUPGlobalInfoPage->aCPUs[0], g_pSUPGlobalInfoPage->cCpus * sizeof(g_pSUPGlobalInfoPage->aCPUs[0]));
153
154 /* display it & find something to spin on. */
155 uint32_t u32TransactionId = 0;
156 uint32_t volatile *pu32TransactionId = NULL;
157 for (unsigned iCpu = 0; iCpu < g_pSUPGlobalInfoPage->cCpus; iCpu++)
158 if (g_pSUPGlobalInfoPage->aCPUs[iCpu].enmState == SUPGIPCPUSTATE_ONLINE)
159 {
160 char szCpuHzDeviation[32];
161 PSUPGIPCPU pPrevCpu = &s_aaCPUs[!(i & 1)][iCpu];
162 PSUPGIPCPU pCpu = &s_aaCPUs[i & 1][iCpu];
163 if (uCpuHzRef)
164 {
165 int64_t iCpuHzDeviation = pCpu->u64CpuHz - uCpuHzRef;
166 uint64_t uCpuHzDeviation = RT_ABS(iCpuHzDeviation);
167 if (uCpuHzDeviation > 999999999)
168 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%17s ", "?");
169 else
170 {
171 /* Wait until the history validation code takes effect. */
172 if (pCpu->u32TransactionId > 23 + (8 * 2) + 1)
173 {
174 if (RT_ABS(iCpuHzDeviation) > RT_ABS(iCpuHzMaxDeviation))
175 iCpuHzMaxDeviation = iCpuHzDeviation;
176 uCpuHzOverallDeviation += uCpuHzDeviation;
177 cCpuHzOverallDevCnt++;
178 }
179 bool fCurHzCompat = SUPIsTscFreqCompatibleEx(uCpuHzRef, pCpu->u64CpuHz, false /* fRelax */);
180 uint32_t uPct = (uint32_t)(uCpuHzDeviation * 100000 / uCpuHzRef + 5);
181 RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%10RI64%3d.%02d%% %RTbool ",
182 iCpuHzDeviation, uPct / 1000, (uPct % 1000) / 10, fCurHzCompat);
183 if (!fCurHzCompat)
184 ++cCpuHzNotCompat;
185 fCompat &= fCurHzCompat;
186 }
187 }
188 else
189 szCpuHzDeviation[0] = '\0';
190 RTPrintf(fHex
191 ? "tstGIP-2: %4d/%d: %016llx %09llx %016llx %08x %d %08x %15llu %s%08x %08x %08x %08x %08x %08x %08x %08x (%d)\n"
192 : "tstGIP-2: %4d/%d: %016llu %09llu %016llu %010u %d %010u %15llu %s%08x %08x %08x %08x %08x %08x %08x %08x (%d)\n",
193 i, iCpu,
194 pCpu->u64NanoTS,
195 i ? pCpu->u64NanoTS - pPrevCpu->u64NanoTS : 0,
196 pCpu->u64TSC,
197 pCpu->u32UpdateIntervalTSC,
198 pCpu->iTSCHistoryHead,
199 pCpu->u32TransactionId,
200 pCpu->u64CpuHz,
201 szCpuHzDeviation,
202 pCpu->au32TSCHistory[0],
203 pCpu->au32TSCHistory[1],
204 pCpu->au32TSCHistory[2],
205 pCpu->au32TSCHistory[3],
206 pCpu->au32TSCHistory[4],
207 pCpu->au32TSCHistory[5],
208 pCpu->au32TSCHistory[6],
209 pCpu->au32TSCHistory[7],
210 pCpu->cErrors);
211 if (!pu32TransactionId)
212 {
213 pu32TransactionId = &g_pSUPGlobalInfoPage->aCPUs[iCpu].u32TransactionId;
214 u32TransactionId = pCpu->u32TransactionId;
215 }
216 }
217
218 /* wait a bit / spin */
219 if (!fSpin)
220 RTThreadSleep(9);
221 else
222 {
223 if (pu32TransactionId)
224 {
225 uint32_t uTmp;
226 while ( u32TransactionId == (uTmp = *pu32TransactionId)
227 || (uTmp & 1))
228 ASMNopPause();
229 }
230 else
231 RTThreadSleep(1);
232 }
233 }
234
235 /*
236 * Display TSC deltas.
237 *
238 * First iterative over the APIC ID array to get mostly consistent CPUID to APIC ID mapping.
239 * Then iterate over the offline CPUs. It is possible that there's a race between the online/offline
240 * states between the two iterations, but that cannot be helped from ring-3 anyway and not a biggie.
241 */
242 RTPrintf("tstGIP-2: TSC deltas:\n");
243 RTPrintf("tstGIP-2: idApic: i64TSCDelta\n");
244 for (unsigned i = 0; i < RT_ELEMENTS(g_pSUPGlobalInfoPage->aiCpuFromApicId); i++)
245 {
246 uint16_t iCpu = g_pSUPGlobalInfoPage->aiCpuFromApicId[i];
247 if (iCpu != UINT16_MAX)
248 {
249 RTPrintf("tstGIP-2: %7d: %lld\n", g_pSUPGlobalInfoPage->aCPUs[iCpu].idApic,
250 g_pSUPGlobalInfoPage->aCPUs[iCpu].i64TSCDelta);
251 }
252 }
253
254 for (unsigned iCpu = 0; iCpu < g_pSUPGlobalInfoPage->cCpus; iCpu++)
255 if (g_pSUPGlobalInfoPage->aCPUs[iCpu].idApic == UINT16_MAX)
256 RTPrintf("tstGIP-2: offline: %lld\n", g_pSUPGlobalInfoPage->aCPUs[iCpu].i64TSCDelta);
257
258 RTPrintf("tstGIP-2: enmUseTscDelta=%d fGetGipCpu=%#x\n",
259 g_pSUPGlobalInfoPage->enmUseTscDelta, g_pSUPGlobalInfoPage->fGetGipCpu);
260 if ( uCpuHzRef
261 && cCpuHzOverallDevCnt)
262 {
263 uint32_t uPct = (uint32_t)(uCpuHzOverallDeviation * 100000 / cCpuHzOverallDevCnt / uCpuHzRef + 5);
264 RTPrintf("tstGIP-2: Average CpuHz deviation: %d.%02d%%\n",
265 uPct / 1000, (uPct % 1000) / 10);
266
267 uint32_t uMaxPct = (uint32_t)(RT_ABS(iCpuHzMaxDeviation) * 100000 / uCpuHzRef + 5);
268 RTPrintf("tstGIP-2: Maximum CpuHz deviation: %d.%02d%% (%RI64 ticks)\n",
269 uMaxPct / 1000, (uMaxPct % 1000) / 10, iCpuHzMaxDeviation);
270
271 RTPrintf("tstGIP-2: CpuHz compatibility: %RTbool (incompatible %u of %u times w/ %RU64 Hz)\n", fCompat,
272 cCpuHzNotCompat, cIterations * g_pSUPGlobalInfoPage->cCpus, uCpuHzRef);
273 }
274 }
275 else
276 {
277 RTPrintf("tstGIP-2: g_pSUPGlobalInfoPage is NULL\n");
278 rc = -1;
279 }
280
281 SUPR3Term(false /*fForced*/);
282 }
283 else
284 RTPrintf("tstGIP-2: SUPR3Init failed: %Rrc\n", rc);
285 return !!rc;
286}
287
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