VirtualBox

source: vbox/trunk/src/VBox/Devices/Storage/DevATA.cpp@ 25999

Last change on this file since 25999 was 25999, checked in by vboxsync, 15 years ago

ATA: enable SCSI_READ_DVD_STRUCTURE for all controller types (seems safe)
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1/* $Id: DevATA.cpp 25999 2010-01-25 13:10:51Z vboxsync $ */
2/** @file
3 * VBox storage devices: ATA/ATAPI controller device (disk and cdrom).
4 */
5
6/*
7 * Copyright (C) 2006-2008 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.215389.xyz. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Defined Constants And Macros *
24*******************************************************************************/
25/** Temporary instrumentation for tracking down potential virtual disk
26 * write performance issues. */
27#undef VBOX_INSTRUMENT_DMA_WRITES
28
29/** @name The SSM saved state versions.
30 * @{
31 */
32/** The current saved state version. */
33#define ATA_SAVED_STATE_VERSION 20
34/** The saved state version used by VirtualBox 3.0.
35 * This lacks the config part and has the type at the and. */
36#define ATA_SAVED_STATE_VERSION_VBOX_30 19
37#define ATA_SAVED_STATE_VERSION_WITH_BOOL_TYPE 18
38#define ATA_SAVED_STATE_VERSION_WITHOUT_FULL_SENSE 16
39#define ATA_SAVED_STATE_VERSION_WITHOUT_EVENT_STATUS 17
40/** @} */
41
42/*******************************************************************************
43* Header Files *
44*******************************************************************************/
45#define LOG_GROUP LOG_GROUP_DEV_IDE
46#include <VBox/pdmdev.h>
47#include <iprt/assert.h>
48#include <iprt/string.h>
49#ifdef IN_RING3
50# include <iprt/uuid.h>
51# include <iprt/semaphore.h>
52# include <iprt/thread.h>
53# include <iprt/time.h>
54# include <iprt/alloc.h>
55#endif /* IN_RING3 */
56#include <iprt/critsect.h>
57#include <iprt/asm.h>
58#include <VBox/stam.h>
59#include <VBox/mm.h>
60#include <VBox/pgm.h>
61
62#include <VBox/scsi.h>
63
64#include "PIIX3ATABmDma.h"
65#include "ide.h"
66#include "../Builtins.h"
67
68/*******************************************************************************
69* Defined Constants And Macros *
70*******************************************************************************/
71/**
72 * Maximum number of sectors to transfer in a READ/WRITE MULTIPLE request.
73 * Set to 1 to disable multi-sector read support. According to the ATA
74 * specification this must be a power of 2 and it must fit in an 8 bit
75 * value. Thus the only valid values are 1, 2, 4, 8, 16, 32, 64 and 128.
76 */
77#define ATA_MAX_MULT_SECTORS 128
78
79/**
80 * Fastest PIO mode supported by the drive.
81 */
82#define ATA_PIO_MODE_MAX 4
83/**
84 * Fastest MDMA mode supported by the drive.
85 */
86#define ATA_MDMA_MODE_MAX 2
87/**
88 * Fastest UDMA mode supported by the drive.
89 */
90#define ATA_UDMA_MODE_MAX 6
91
92/** ATAPI sense info size. */
93#define ATAPI_SENSE_SIZE 64
94
95/** The maximum number of release log entries per device. */
96#define MAX_LOG_REL_ERRORS 1024
97
98/* MediaEventStatus */
99#define ATA_EVENT_STATUS_UNCHANGED 0 /**< medium event status not changed */
100#define ATA_EVENT_STATUS_MEDIA_NEW 1 /**< new medium inserted */
101#define ATA_EVENT_STATUS_MEDIA_REMOVED 2 /**< medium removed */
102#define ATA_EVENT_STATUS_MEDIA_CHANGED 3 /**< medium was removed + new medium was inserted */
103
104/**
105 * Length of the configurable VPD data (without termination)
106 */
107#define ATA_SERIAL_NUMBER_LENGTH 20
108#define ATA_FIRMWARE_REVISION_LENGTH 8
109#define ATA_MODEL_NUMBER_LENGTH 40
110#define ATAPI_INQUIRY_VENDOR_ID_LENGTH 8
111#define ATAPI_INQUIRY_PRODUCT_ID_LENGTH 16
112#define ATAPI_INQUIRY_REVISION_LENGTH 4
113
114/*******************************************************************************
115* Structures and Typedefs *
116*******************************************************************************/
117/**
118 * The state of an ATA device.
119 *
120 * @implements PDMIBASE
121 * @implements PDMIBLOCKPORT
122 * @implements PDMIMOUNTNOTIFY
123 */
124typedef struct ATADevState
125{
126 /** Flag indicating whether the current command uses LBA48 mode. */
127 bool fLBA48;
128 /** Flag indicating whether this drive implements the ATAPI command set. */
129 bool fATAPI;
130 /** Set if this interface has asserted the IRQ. */
131 bool fIrqPending;
132 /** Currently configured number of sectors in a multi-sector transfer. */
133 uint8_t cMultSectors;
134 /** PCHS disk geometry. */
135 PDMMEDIAGEOMETRY PCHSGeometry;
136 /** Total number of sectors on this disk. */
137 uint64_t cTotalSectors;
138 /** Number of sectors to transfer per IRQ. */
139 uint32_t cSectorsPerIRQ;
140
141 /** ATA/ATAPI register 1: feature (write-only). */
142 uint8_t uATARegFeature;
143 /** ATA/ATAPI register 1: feature, high order byte. */
144 uint8_t uATARegFeatureHOB;
145 /** ATA/ATAPI register 1: error (read-only). */
146 uint8_t uATARegError;
147 /** ATA/ATAPI register 2: sector count (read/write). */
148 uint8_t uATARegNSector;
149 /** ATA/ATAPI register 2: sector count, high order byte. */
150 uint8_t uATARegNSectorHOB;
151 /** ATA/ATAPI register 3: sector (read/write). */
152 uint8_t uATARegSector;
153 /** ATA/ATAPI register 3: sector, high order byte. */
154 uint8_t uATARegSectorHOB;
155 /** ATA/ATAPI register 4: cylinder low (read/write). */
156 uint8_t uATARegLCyl;
157 /** ATA/ATAPI register 4: cylinder low, high order byte. */
158 uint8_t uATARegLCylHOB;
159 /** ATA/ATAPI register 5: cylinder high (read/write). */
160 uint8_t uATARegHCyl;
161 /** ATA/ATAPI register 5: cylinder high, high order byte. */
162 uint8_t uATARegHCylHOB;
163 /** ATA/ATAPI register 6: select drive/head (read/write). */
164 uint8_t uATARegSelect;
165 /** ATA/ATAPI register 7: status (read-only). */
166 uint8_t uATARegStatus;
167 /** ATA/ATAPI register 7: command (write-only). */
168 uint8_t uATARegCommand;
169 /** ATA/ATAPI drive control register (write-only). */
170 uint8_t uATARegDevCtl;
171
172 /** Currently active transfer mode (MDMA/UDMA) and speed. */
173 uint8_t uATATransferMode;
174 /** Current transfer direction. */
175 uint8_t uTxDir;
176 /** Index of callback for begin transfer. */
177 uint8_t iBeginTransfer;
178 /** Index of callback for source/sink of data. */
179 uint8_t iSourceSink;
180 /** Flag indicating whether the current command transfers data in DMA mode. */
181 bool fDMA;
182 /** Set to indicate that ATAPI transfer semantics must be used. */
183 bool fATAPITransfer;
184
185 /** Total ATA/ATAPI transfer size, shared PIO/DMA. */
186 uint32_t cbTotalTransfer;
187 /** Elementary ATA/ATAPI transfer size, shared PIO/DMA. */
188 uint32_t cbElementaryTransfer;
189 /** Current read/write buffer position, shared PIO/DMA. */
190 uint32_t iIOBufferCur;
191 /** First element beyond end of valid buffer content, shared PIO/DMA. */
192 uint32_t iIOBufferEnd;
193
194 /** ATA/ATAPI current PIO read/write transfer position. Not shared with DMA for safety reasons. */
195 uint32_t iIOBufferPIODataStart;
196 /** ATA/ATAPI current PIO read/write transfer end. Not shared with DMA for safety reasons. */
197 uint32_t iIOBufferPIODataEnd;
198
199 /** ATAPI current LBA position. */
200 uint32_t iATAPILBA;
201 /** ATAPI current sector size. */
202 uint32_t cbATAPISector;
203 /** ATAPI current command. */
204 uint8_t aATAPICmd[ATAPI_PACKET_SIZE];
205 /** ATAPI sense data. */
206 uint8_t abATAPISense[ATAPI_SENSE_SIZE];
207 /** HACK: Countdown till we report a newly unmounted drive as mounted. */
208 uint8_t cNotifiedMediaChange;
209 /** The same for GET_EVENT_STATUS for mechanism */
210 volatile uint32_t MediaEventStatus;
211
212 uint32_t Alignment0;
213
214 /** The status LED state for this drive. */
215 PDMLED Led;
216
217 /** Size of I/O buffer. */
218 uint32_t cbIOBuffer;
219 /** Pointer to the I/O buffer. */
220 R3PTRTYPE(uint8_t *) pbIOBufferR3;
221 /** Pointer to the I/O buffer. */
222 R0PTRTYPE(uint8_t *) pbIOBufferR0;
223 /** Pointer to the I/O buffer. */
224 RCPTRTYPE(uint8_t *) pbIOBufferRC;
225
226 RTRCPTR Aligmnent1; /**< Align the statistics at an 8-byte boundrary. */
227
228 /*
229 * No data that is part of the saved state after this point!!!!!
230 */
231
232 /* Release statistics: number of ATA DMA commands. */
233 STAMCOUNTER StatATADMA;
234 /* Release statistics: number of ATA PIO commands. */
235 STAMCOUNTER StatATAPIO;
236 /* Release statistics: number of ATAPI PIO commands. */
237 STAMCOUNTER StatATAPIDMA;
238 /* Release statistics: number of ATAPI PIO commands. */
239 STAMCOUNTER StatATAPIPIO;
240#ifdef VBOX_INSTRUMENT_DMA_WRITES
241 /* Release statistics: number of DMA sector writes and the time spent. */
242 STAMPROFILEADV StatInstrVDWrites;
243#endif
244
245 /** Statistics: number of read operations and the time spent reading. */
246 STAMPROFILEADV StatReads;
247 /** Statistics: number of bytes read. */
248 STAMCOUNTER StatBytesRead;
249 /** Statistics: number of write operations and the time spent writing. */
250 STAMPROFILEADV StatWrites;
251 /** Statistics: number of bytes written. */
252 STAMCOUNTER StatBytesWritten;
253 /** Statistics: number of flush operations and the time spend flushing. */
254 STAMPROFILE StatFlushes;
255
256 /** Enable passing through commands directly to the ATAPI drive. */
257 bool fATAPIPassthrough;
258 /** Number of errors we've reported to the release log.
259 * This is to prevent flooding caused by something going horribly wrong.
260 * this value against MAX_LOG_REL_ERRORS in places likely to cause floods
261 * like the ones we currently seeing on the linux smoke tests (2006-11-10). */
262 uint32_t cErrors;
263 /** Timestamp of last started command. 0 if no command pending. */
264 uint64_t u64CmdTS;
265
266 /** Pointer to the attached driver's base interface. */
267 R3PTRTYPE(PPDMIBASE) pDrvBase;
268 /** Pointer to the attached driver's block interface. */
269 R3PTRTYPE(PPDMIBLOCK) pDrvBlock;
270 /** Pointer to the attached driver's block bios interface. */
271 R3PTRTYPE(PPDMIBLOCKBIOS) pDrvBlockBios;
272 /** Pointer to the attached driver's mount interface.
273 * This is NULL if the driver isn't a removable unit. */
274 R3PTRTYPE(PPDMIMOUNT) pDrvMount;
275 /** The base interface. */
276 PDMIBASE IBase;
277 /** The block port interface. */
278 PDMIBLOCKPORT IPort;
279 /** The mount notify interface. */
280 PDMIMOUNTNOTIFY IMountNotify;
281 /** The LUN #. */
282 RTUINT iLUN;
283 RTUINT Alignment2; /**< Align pDevInsR3 correctly. */
284 /** Pointer to device instance. */
285 PPDMDEVINSR3 pDevInsR3;
286 /** Pointer to controller instance. */
287 R3PTRTYPE(struct ATACONTROLLER *) pControllerR3;
288 /** Pointer to device instance. */
289 PPDMDEVINSR0 pDevInsR0;
290 /** Pointer to controller instance. */
291 R0PTRTYPE(struct ATACONTROLLER *) pControllerR0;
292 /** Pointer to device instance. */
293 PPDMDEVINSRC pDevInsRC;
294 /** Pointer to controller instance. */
295 RCPTRTYPE(struct ATACONTROLLER *) pControllerRC;
296
297 /** The serial number to use for IDENTIFY DEVICE commands. */
298 char szSerialNumber[ATA_SERIAL_NUMBER_LENGTH+1];
299 /** The firmware revision to use for IDENTIFY DEVICE commands. */
300 char szFirmwareRevision[ATA_FIRMWARE_REVISION_LENGTH+1];
301 /** The model number to use for IDENTIFY DEVICE commands. */
302 char szModelNumber[ATA_MODEL_NUMBER_LENGTH+1];
303 /** The vendor identification string for SCSI INQUIRY commands. */
304 char szInquiryVendorId[ATAPI_INQUIRY_VENDOR_ID_LENGTH+1];
305 /** The product identification string for SCSI INQUIRY commands. */
306 char szInquiryProductId[ATAPI_INQUIRY_PRODUCT_ID_LENGTH+1];
307 /** The revision string for SCSI INQUIRY commands. */
308 char szInquiryRevision[ATAPI_INQUIRY_REVISION_LENGTH+1];
309
310 uint8_t abAlignment3[7];
311} ATADevState;
312AssertCompileMemberAlignment(ATADevState, cTotalSectors, 8);
313AssertCompileMemberAlignment(ATADevState, StatATADMA, 8);
314AssertCompileMemberAlignment(ATADevState, u64CmdTS, 8);
315AssertCompileMemberAlignment(ATADevState, pDevInsR3, 8);
316AssertCompileMemberAlignment(ATADevState, szSerialNumber, 8);
317AssertCompileSizeAlignment(ATADevState, 8);
318
319
320typedef struct ATATransferRequest
321{
322 uint8_t iIf;
323 uint8_t iBeginTransfer;
324 uint8_t iSourceSink;
325 uint32_t cbTotalTransfer;
326 uint8_t uTxDir;
327} ATATransferRequest;
328
329
330typedef struct ATAAbortRequest
331{
332 uint8_t iIf;
333 bool fResetDrive;
334} ATAAbortRequest;
335
336
337typedef enum
338{
339 /** Begin a new transfer. */
340 ATA_AIO_NEW = 0,
341 /** Continue a DMA transfer. */
342 ATA_AIO_DMA,
343 /** Continue a PIO transfer. */
344 ATA_AIO_PIO,
345 /** Reset the drives on current controller, stop all transfer activity. */
346 ATA_AIO_RESET_ASSERTED,
347 /** Reset the drives on current controller, resume operation. */
348 ATA_AIO_RESET_CLEARED,
349 /** Abort the current transfer of a particular drive. */
350 ATA_AIO_ABORT
351} ATAAIO;
352
353
354typedef struct ATARequest
355{
356 ATAAIO ReqType;
357 union
358 {
359 ATATransferRequest t;
360 ATAAbortRequest a;
361 } u;
362} ATARequest;
363
364
365typedef struct ATACONTROLLER
366{
367 /** The base of the first I/O Port range. */
368 RTIOPORT IOPortBase1;
369 /** The base of the second I/O Port range. (0 if none) */
370 RTIOPORT IOPortBase2;
371 /** The assigned IRQ. */
372 RTUINT irq;
373 /** Access critical section */
374 PDMCRITSECT lock;
375
376 /** Selected drive. */
377 uint8_t iSelectedIf;
378 /** The interface on which to handle async I/O. */
379 uint8_t iAIOIf;
380 /** The state of the async I/O thread. */
381 uint8_t uAsyncIOState;
382 /** Flag indicating whether the next transfer is part of the current command. */
383 bool fChainedTransfer;
384 /** Set when the reset processing is currently active on this controller. */
385 bool fReset;
386 /** Flag whether the current transfer needs to be redone. */
387 bool fRedo;
388 /** Flag whether the redo suspend has been finished. */
389 bool fRedoIdle;
390 /** Flag whether the DMA operation to be redone is the final transfer. */
391 bool fRedoDMALastDesc;
392 /** The BusMaster DMA state. */
393 BMDMAState BmDma;
394 /** Pointer to first DMA descriptor. */
395 RTGCPHYS32 pFirstDMADesc;
396 /** Pointer to last DMA descriptor. */
397 RTGCPHYS32 pLastDMADesc;
398 /** Pointer to current DMA buffer (for redo operations). */
399 RTGCPHYS32 pRedoDMABuffer;
400 /** Size of current DMA buffer (for redo operations). */
401 uint32_t cbRedoDMABuffer;
402
403 /** The ATA/ATAPI interfaces of this controller. */
404 ATADevState aIfs[2];
405
406 /** Pointer to device instance. */
407 PPDMDEVINSR3 pDevInsR3;
408 /** Pointer to device instance. */
409 PPDMDEVINSR0 pDevInsR0;
410 /** Pointer to device instance. */
411 PPDMDEVINSRC pDevInsRC;
412
413 /** Set when the destroying the device instance and the thread must exit. */
414 uint32_t volatile fShutdown;
415 /** The async I/O thread handle. NIL_RTTHREAD if no thread. */
416 RTTHREAD AsyncIOThread;
417 /** The event semaphore the thread is waiting on for requests. */
418 RTSEMEVENT AsyncIOSem;
419 /** The request queue for the AIO thread. One element is always unused. */
420 ATARequest aAsyncIORequests[4];
421 /** The position at which to insert a new request for the AIO thread. */
422 uint8_t AsyncIOReqHead;
423 /** The position at which to get a new request for the AIO thread. */
424 uint8_t AsyncIOReqTail;
425 /** Whether to call PDMDevHlpAsyncNotificationCompleted when idle. */
426 bool volatile fSignalIdle;
427 uint8_t Alignment3[1]; /**< Explicit padding of the 1 byte gap. */
428 /** Magic delay before triggering interrupts in DMA mode. */
429 uint32_t DelayIRQMillies;
430 /** The mutex protecting the request queue. */
431 RTSEMMUTEX AsyncIORequestMutex;
432 /** The event semaphore the thread is waiting on during suspended I/O. */
433 RTSEMEVENT SuspendIOSem;
434#if 0 /*HC_ARCH_BITS == 32*/
435 uint32_t Alignment0;
436#endif
437
438 /** Timestamp we started the reset. */
439 uint64_t u64ResetTime;
440
441 /* Statistics */
442 STAMCOUNTER StatAsyncOps;
443 uint64_t StatAsyncMinWait;
444 uint64_t StatAsyncMaxWait;
445 STAMCOUNTER StatAsyncTimeUS;
446 STAMPROFILEADV StatAsyncTime;
447 STAMPROFILE StatLockWait;
448} ATACONTROLLER, *PATACONTROLLER;
449AssertCompileMemberAlignment(ATACONTROLLER, lock, 8);
450AssertCompileMemberAlignment(ATACONTROLLER, aIfs, 8);
451AssertCompileMemberAlignment(ATACONTROLLER, u64ResetTime, 8);
452AssertCompileMemberAlignment(ATACONTROLLER, StatAsyncOps, 8);
453
454typedef enum CHIPSET
455{
456 /** PIIX3 chipset, must be 0 for saved state compatibility */
457 CHIPSET_PIIX3 = 0,
458 /** PIIX4 chipset, must be 1 for saved state compatibility */
459 CHIPSET_PIIX4 = 1,
460 /** ICH6 chipset */
461 CHIPSET_ICH6 = 2
462} CHIPSET;
463
464/**
465 * The state of the ATA PCI device.
466 *
467 * @extends PCIDEVICE
468 * @implements PDMILEDPORTS
469 */
470typedef struct PCIATAState
471{
472 PCIDEVICE dev;
473 /** The controllers. */
474 ATACONTROLLER aCts[2];
475 /** Pointer to device instance. */
476 PPDMDEVINSR3 pDevIns;
477 /** Status LUN: Base interface. */
478 PDMIBASE IBase;
479 /** Status LUN: Leds interface. */
480 PDMILEDPORTS ILeds;
481 /** Status LUN: Partner of ILeds. */
482 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
483 /** Flag whether GC is enabled. */
484 bool fGCEnabled;
485 /** Flag whether R0 is enabled. */
486 bool fR0Enabled;
487 /** Flag indicating chipset being emulated. */
488 uint8_t u8Type;
489 bool Alignment0[HC_ARCH_BITS == 64 ? 5 : 1 ]; /**< Align the struct size. */
490} PCIATAState;
491
492#define PDMIBASE_2_PCIATASTATE(pInterface) ( (PCIATAState *)((uintptr_t)(pInterface) - RT_OFFSETOF(PCIATAState, IBase)) )
493#define PDMILEDPORTS_2_PCIATASTATE(pInterface) ( (PCIATAState *)((uintptr_t)(pInterface) - RT_OFFSETOF(PCIATAState, ILeds)) )
494#define PDMIBLOCKPORT_2_ATASTATE(pInterface) ( (ATADevState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ATADevState, IPort)) )
495#define PDMIMOUNT_2_ATASTATE(pInterface) ( (ATADevState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ATADevState, IMount)) )
496#define PDMIMOUNTNOTIFY_2_ATASTATE(pInterface) ( (ATADevState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ATADevState, IMountNotify)) )
497#define PCIDEV_2_PCIATASTATE(pPciDev) ( (PCIATAState *)(pPciDev) )
498
499#define ATACONTROLLER_IDX(pController) ( (pController) - PDMINS_2_DATA(CONTROLLER_2_DEVINS(pController), PCIATAState *)->aCts )
500
501#define ATADEVSTATE_2_CONTROLLER(pIf) ( (pIf)->CTX_SUFF(pController) )
502#define ATADEVSTATE_2_DEVINS(pIf) ( (pIf)->CTX_SUFF(pDevIns) )
503#define CONTROLLER_2_DEVINS(pController) ( (pController)->CTX_SUFF(pDevIns) )
504#define PDMIBASE_2_ATASTATE(pInterface) ( (ATADevState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ATADevState, IBase)) )
505
506#ifndef VBOX_DEVICE_STRUCT_TESTCASE
507/*******************************************************************************
508 * Internal Functions *
509 ******************************************************************************/
510RT_C_DECLS_BEGIN
511PDMBOTHCBDECL(int) ataIOPortWrite1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
512PDMBOTHCBDECL(int) ataIOPortRead1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *u32, unsigned cb);
513PDMBOTHCBDECL(int) ataIOPortWriteStr1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrSrc, PRTGCUINTREG pcTransfer, unsigned cb);
514PDMBOTHCBDECL(int) ataIOPortReadStr1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrDst, PRTGCUINTREG pcTransfer, unsigned cb);
515PDMBOTHCBDECL(int) ataIOPortWrite2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
516PDMBOTHCBDECL(int) ataIOPortRead2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *u32, unsigned cb);
517PDMBOTHCBDECL(int) ataBMDMAIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
518PDMBOTHCBDECL(int) ataBMDMAIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
519RT_C_DECLS_END
520
521
522
523DECLINLINE(void) ataSetStatusValue(ATADevState *s, uint8_t stat)
524{
525 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
526
527 /* Freeze status register contents while processing RESET. */
528 if (!pCtl->fReset)
529 {
530 s->uATARegStatus = stat;
531 Log2(("%s: LUN#%d status %#04x\n", __FUNCTION__, s->iLUN, s->uATARegStatus));
532 }
533}
534
535
536DECLINLINE(void) ataSetStatus(ATADevState *s, uint8_t stat)
537{
538 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
539
540 /* Freeze status register contents while processing RESET. */
541 if (!pCtl->fReset)
542 {
543 s->uATARegStatus |= stat;
544 Log2(("%s: LUN#%d status %#04x\n", __FUNCTION__, s->iLUN, s->uATARegStatus));
545 }
546}
547
548
549DECLINLINE(void) ataUnsetStatus(ATADevState *s, uint8_t stat)
550{
551 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
552
553 /* Freeze status register contents while processing RESET. */
554 if (!pCtl->fReset)
555 {
556 s->uATARegStatus &= ~stat;
557 Log2(("%s: LUN#%d status %#04x\n", __FUNCTION__, s->iLUN, s->uATARegStatus));
558 }
559}
560
561#ifdef IN_RING3
562
563typedef void (*PBeginTransferFunc)(ATADevState *);
564typedef bool (*PSourceSinkFunc)(ATADevState *);
565
566static void ataReadWriteSectorsBT(ATADevState *);
567static void ataPacketBT(ATADevState *);
568static void atapiCmdBT(ATADevState *);
569static void atapiPassthroughCmdBT(ATADevState *);
570
571static bool ataIdentifySS(ATADevState *);
572static bool ataFlushSS(ATADevState *);
573static bool ataReadSectorsSS(ATADevState *);
574static bool ataWriteSectorsSS(ATADevState *);
575static bool ataExecuteDeviceDiagnosticSS(ATADevState *);
576static bool ataPacketSS(ATADevState *);
577static bool atapiGetConfigurationSS(ATADevState *);
578static bool atapiGetEventStatusNotificationSS(ATADevState *);
579static bool atapiIdentifySS(ATADevState *);
580static bool atapiInquirySS(ATADevState *);
581static bool atapiMechanismStatusSS(ATADevState *);
582static bool atapiModeSenseErrorRecoverySS(ATADevState *);
583static bool atapiModeSenseCDStatusSS(ATADevState *);
584static bool atapiReadSS(ATADevState *);
585static bool atapiReadCapacitySS(ATADevState *);
586static bool atapiReadDiscInformationSS(ATADevState *);
587static bool atapiReadTOCNormalSS(ATADevState *);
588static bool atapiReadTOCMultiSS(ATADevState *);
589static bool atapiReadTOCRawSS(ATADevState *);
590static bool atapiReadTrackInformationSS(ATADevState *);
591static bool atapiRequestSenseSS(ATADevState *);
592static bool atapiPassthroughSS(ATADevState *);
593static bool atapiReadDVDStructureSS(ATADevState *);
594
595/**
596 * Begin of transfer function indexes for g_apfnBeginTransFuncs.
597 */
598typedef enum ATAFNBT
599{
600 ATAFN_BT_NULL = 0,
601 ATAFN_BT_READ_WRITE_SECTORS,
602 ATAFN_BT_PACKET,
603 ATAFN_BT_ATAPI_CMD,
604 ATAFN_BT_ATAPI_PASSTHROUGH_CMD,
605 ATAFN_BT_MAX
606} ATAFNBT;
607
608/**
609 * Array of end transfer functions, the index is ATAFNET.
610 * Make sure ATAFNET and this array match!
611 */
612static const PBeginTransferFunc g_apfnBeginTransFuncs[ATAFN_BT_MAX] =
613{
614 NULL,
615 ataReadWriteSectorsBT,
616 ataPacketBT,
617 atapiCmdBT,
618 atapiPassthroughCmdBT,
619};
620
621/**
622 * Source/sink function indexes for g_apfnSourceSinkFuncs.
623 */
624typedef enum ATAFNSS
625{
626 ATAFN_SS_NULL = 0,
627 ATAFN_SS_IDENTIFY,
628 ATAFN_SS_FLUSH,
629 ATAFN_SS_READ_SECTORS,
630 ATAFN_SS_WRITE_SECTORS,
631 ATAFN_SS_EXECUTE_DEVICE_DIAGNOSTIC,
632 ATAFN_SS_PACKET,
633 ATAFN_SS_ATAPI_GET_CONFIGURATION,
634 ATAFN_SS_ATAPI_GET_EVENT_STATUS_NOTIFICATION,
635 ATAFN_SS_ATAPI_IDENTIFY,
636 ATAFN_SS_ATAPI_INQUIRY,
637 ATAFN_SS_ATAPI_MECHANISM_STATUS,
638 ATAFN_SS_ATAPI_MODE_SENSE_ERROR_RECOVERY,
639 ATAFN_SS_ATAPI_MODE_SENSE_CD_STATUS,
640 ATAFN_SS_ATAPI_READ,
641 ATAFN_SS_ATAPI_READ_CAPACITY,
642 ATAFN_SS_ATAPI_READ_DISC_INFORMATION,
643 ATAFN_SS_ATAPI_READ_TOC_NORMAL,
644 ATAFN_SS_ATAPI_READ_TOC_MULTI,
645 ATAFN_SS_ATAPI_READ_TOC_RAW,
646 ATAFN_SS_ATAPI_READ_TRACK_INFORMATION,
647 ATAFN_SS_ATAPI_REQUEST_SENSE,
648 ATAFN_SS_ATAPI_PASSTHROUGH,
649 ATAFN_SS_ATAPI_READ_DVD_STRUCTURE,
650 ATAFN_SS_MAX
651} ATAFNSS;
652
653/**
654 * Array of source/sink functions, the index is ATAFNSS.
655 * Make sure ATAFNSS and this array match!
656 */
657static const PSourceSinkFunc g_apfnSourceSinkFuncs[ATAFN_SS_MAX] =
658{
659 NULL,
660 ataIdentifySS,
661 ataFlushSS,
662 ataReadSectorsSS,
663 ataWriteSectorsSS,
664 ataExecuteDeviceDiagnosticSS,
665 ataPacketSS,
666 atapiGetConfigurationSS,
667 atapiGetEventStatusNotificationSS,
668 atapiIdentifySS,
669 atapiInquirySS,
670 atapiMechanismStatusSS,
671 atapiModeSenseErrorRecoverySS,
672 atapiModeSenseCDStatusSS,
673 atapiReadSS,
674 atapiReadCapacitySS,
675 atapiReadDiscInformationSS,
676 atapiReadTOCNormalSS,
677 atapiReadTOCMultiSS,
678 atapiReadTOCRawSS,
679 atapiReadTrackInformationSS,
680 atapiRequestSenseSS,
681 atapiPassthroughSS,
682 atapiReadDVDStructureSS
683};
684
685
686static const ATARequest g_ataDMARequest = { ATA_AIO_DMA, };
687static const ATARequest g_ataPIORequest = { ATA_AIO_PIO, };
688static const ATARequest g_ataResetARequest = { ATA_AIO_RESET_ASSERTED, };
689static const ATARequest g_ataResetCRequest = { ATA_AIO_RESET_CLEARED, };
690
691
692static void ataAsyncIOClearRequests(PATACONTROLLER pCtl)
693{
694 int rc;
695
696 rc = RTSemMutexRequest(pCtl->AsyncIORequestMutex, RT_INDEFINITE_WAIT);
697 AssertRC(rc);
698 pCtl->AsyncIOReqHead = 0;
699 pCtl->AsyncIOReqTail = 0;
700 rc = RTSemMutexRelease(pCtl->AsyncIORequestMutex);
701 AssertRC(rc);
702}
703
704
705static void ataAsyncIOPutRequest(PATACONTROLLER pCtl, const ATARequest *pReq)
706{
707 int rc;
708
709 rc = RTSemMutexRequest(pCtl->AsyncIORequestMutex, RT_INDEFINITE_WAIT);
710 AssertRC(rc);
711 Assert((pCtl->AsyncIOReqHead + 1) % RT_ELEMENTS(pCtl->aAsyncIORequests) != pCtl->AsyncIOReqTail);
712 memcpy(&pCtl->aAsyncIORequests[pCtl->AsyncIOReqHead], pReq, sizeof(*pReq));
713 pCtl->AsyncIOReqHead++;
714 pCtl->AsyncIOReqHead %= RT_ELEMENTS(pCtl->aAsyncIORequests);
715 rc = RTSemMutexRelease(pCtl->AsyncIORequestMutex);
716 AssertRC(rc);
717 rc = PDMR3CritSectScheduleExitEvent(&pCtl->lock, pCtl->AsyncIOSem);
718 if (RT_FAILURE(rc))
719 {
720 rc = RTSemEventSignal(pCtl->AsyncIOSem);
721 AssertRC(rc);
722 }
723}
724
725
726static const ATARequest *ataAsyncIOGetCurrentRequest(PATACONTROLLER pCtl)
727{
728 int rc;
729 const ATARequest *pReq;
730
731 rc = RTSemMutexRequest(pCtl->AsyncIORequestMutex, RT_INDEFINITE_WAIT);
732 AssertRC(rc);
733 if (pCtl->AsyncIOReqHead != pCtl->AsyncIOReqTail)
734 pReq = &pCtl->aAsyncIORequests[pCtl->AsyncIOReqTail];
735 else
736 pReq = NULL;
737 rc = RTSemMutexRelease(pCtl->AsyncIORequestMutex);
738 AssertRC(rc);
739 return pReq;
740}
741
742
743/**
744 * Remove the request with the given type, as it's finished. The request
745 * is not removed blindly, as this could mean a RESET request that is not
746 * yet processed (but has cleared the request queue) is lost.
747 *
748 * @param pCtl Controller for which to remove the request.
749 * @param ReqType Type of the request to remove.
750 */
751static void ataAsyncIORemoveCurrentRequest(PATACONTROLLER pCtl, ATAAIO ReqType)
752{
753 int rc;
754
755 rc = RTSemMutexRequest(pCtl->AsyncIORequestMutex, RT_INDEFINITE_WAIT);
756 AssertRC(rc);
757 if (pCtl->AsyncIOReqHead != pCtl->AsyncIOReqTail && pCtl->aAsyncIORequests[pCtl->AsyncIOReqTail].ReqType == ReqType)
758 {
759 pCtl->AsyncIOReqTail++;
760 pCtl->AsyncIOReqTail %= RT_ELEMENTS(pCtl->aAsyncIORequests);
761 }
762 rc = RTSemMutexRelease(pCtl->AsyncIORequestMutex);
763 AssertRC(rc);
764}
765
766
767/**
768 * Dump the request queue for a particular controller. First dump the queue
769 * contents, then the already processed entries, as long as they haven't been
770 * overwritten.
771 *
772 * @param pCtl Controller for which to dump the queue.
773 */
774static void ataAsyncIODumpRequests(PATACONTROLLER pCtl)
775{
776 int rc;
777 uint8_t curr;
778
779 rc = RTSemMutexRequest(pCtl->AsyncIORequestMutex, RT_INDEFINITE_WAIT);
780 AssertRC(rc);
781 LogRel(("PIIX3 ATA: Ctl#%d: request queue dump (topmost is current):\n", ATACONTROLLER_IDX(pCtl)));
782 curr = pCtl->AsyncIOReqTail;
783 do
784 {
785 if (curr == pCtl->AsyncIOReqHead)
786 LogRel(("PIIX3 ATA: Ctl#%d: processed requests (topmost is oldest):\n", ATACONTROLLER_IDX(pCtl)));
787 switch (pCtl->aAsyncIORequests[curr].ReqType)
788 {
789 case ATA_AIO_NEW:
790 LogRel(("new transfer request, iIf=%d iBeginTransfer=%d iSourceSink=%d cbTotalTransfer=%d uTxDir=%d\n", pCtl->aAsyncIORequests[curr].u.t.iIf, pCtl->aAsyncIORequests[curr].u.t.iBeginTransfer, pCtl->aAsyncIORequests[curr].u.t.iSourceSink, pCtl->aAsyncIORequests[curr].u.t.cbTotalTransfer, pCtl->aAsyncIORequests[curr].u.t.uTxDir));
791 break;
792 case ATA_AIO_DMA:
793 LogRel(("dma transfer continuation\n"));
794 break;
795 case ATA_AIO_PIO:
796 LogRel(("pio transfer continuation\n"));
797 break;
798 case ATA_AIO_RESET_ASSERTED:
799 LogRel(("reset asserted request\n"));
800 break;
801 case ATA_AIO_RESET_CLEARED:
802 LogRel(("reset cleared request\n"));
803 break;
804 case ATA_AIO_ABORT:
805 LogRel(("abort request, iIf=%d fResetDrive=%d\n", pCtl->aAsyncIORequests[curr].u.a.iIf, pCtl->aAsyncIORequests[curr].u.a.fResetDrive));
806 break;
807 default:
808 LogRel(("unknown request %d\n", pCtl->aAsyncIORequests[curr].ReqType));
809 }
810 curr = (curr + 1) % RT_ELEMENTS(pCtl->aAsyncIORequests);
811 } while (curr != pCtl->AsyncIOReqTail);
812 rc = RTSemMutexRelease(pCtl->AsyncIORequestMutex);
813 AssertRC(rc);
814}
815
816
817/**
818 * Checks whether the request queue for a particular controller is empty
819 * or whether a particular controller is idle.
820 *
821 * @param pCtl Controller for which to check the queue.
822 * @param fStrict If set then the controller is checked to be idle.
823 */
824static bool ataAsyncIOIsIdle(PATACONTROLLER pCtl, bool fStrict)
825{
826 int rc;
827 bool fIdle;
828
829 rc = RTSemMutexRequest(pCtl->AsyncIORequestMutex, RT_INDEFINITE_WAIT);
830 AssertRC(rc);
831 fIdle = pCtl->fRedoIdle;
832 if (!fIdle)
833 fIdle = (pCtl->AsyncIOReqHead == pCtl->AsyncIOReqTail);
834 if (fStrict)
835 fIdle &= (pCtl->uAsyncIOState == ATA_AIO_NEW);
836 rc = RTSemMutexRelease(pCtl->AsyncIORequestMutex);
837 AssertRC(rc);
838 return fIdle;
839}
840
841
842/**
843 * Send a transfer request to the async I/O thread.
844 *
845 * @param s Pointer to the ATA device state data.
846 * @param cbTotalTransfer Data transfer size.
847 * @param uTxDir Data transfer direction.
848 * @param iBeginTransfer Index of BeginTransfer callback.
849 * @param iSourceSink Index of SourceSink callback.
850 * @param fChainedTransfer Whether this is a transfer that is part of the previous command/transfer.
851 */
852static void ataStartTransfer(ATADevState *s, uint32_t cbTotalTransfer, uint8_t uTxDir, ATAFNBT iBeginTransfer, ATAFNSS iSourceSink, bool fChainedTransfer)
853{
854 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
855 ATARequest Req;
856
857 Assert(PDMCritSectIsOwner(&pCtl->lock));
858
859 /* Do not issue new requests while the RESET line is asserted. */
860 if (pCtl->fReset)
861 {
862 Log2(("%s: Ctl#%d: suppressed new request as RESET is active\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
863 return;
864 }
865
866 /* If the controller is already doing something else right now, ignore
867 * the command that is being submitted. Some broken guests issue commands
868 * twice (e.g. the Linux kernel that comes with Acronis True Image 8). */
869 if (!fChainedTransfer && !ataAsyncIOIsIdle(pCtl, true /*fStrict*/))
870 {
871 Log(("%s: Ctl#%d: ignored command %#04x, controller state %d\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl), s->uATARegCommand, pCtl->uAsyncIOState));
872 LogRel(("PIIX3 IDE: guest issued command %#04x while controller busy\n", s->uATARegCommand));
873 return;
874 }
875
876 Req.ReqType = ATA_AIO_NEW;
877 if (fChainedTransfer)
878 Req.u.t.iIf = pCtl->iAIOIf;
879 else
880 Req.u.t.iIf = pCtl->iSelectedIf;
881 Req.u.t.cbTotalTransfer = cbTotalTransfer;
882 Req.u.t.uTxDir = uTxDir;
883 Req.u.t.iBeginTransfer = iBeginTransfer;
884 Req.u.t.iSourceSink = iSourceSink;
885 ataSetStatusValue(s, ATA_STAT_BUSY);
886 pCtl->fChainedTransfer = fChainedTransfer;
887
888 /*
889 * Kick the worker thread into action.
890 */
891 Log2(("%s: Ctl#%d: message to async I/O thread, new request\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
892 ataAsyncIOPutRequest(pCtl, &Req);
893}
894
895
896/**
897 * Send an abort command request to the async I/O thread.
898 *
899 * @param s Pointer to the ATA device state data.
900 * @param fResetDrive Whether to reset the drive or just abort a command.
901 */
902static void ataAbortCurrentCommand(ATADevState *s, bool fResetDrive)
903{
904 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
905 ATARequest Req;
906
907 Assert(PDMCritSectIsOwner(&pCtl->lock));
908
909 /* Do not issue new requests while the RESET line is asserted. */
910 if (pCtl->fReset)
911 {
912 Log2(("%s: Ctl#%d: suppressed aborting command as RESET is active\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
913 return;
914 }
915
916 Req.ReqType = ATA_AIO_ABORT;
917 Req.u.a.iIf = pCtl->iSelectedIf;
918 Req.u.a.fResetDrive = fResetDrive;
919 ataSetStatus(s, ATA_STAT_BUSY);
920 Log2(("%s: Ctl#%d: message to async I/O thread, abort command on LUN#%d\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl), s->iLUN));
921 ataAsyncIOPutRequest(pCtl, &Req);
922}
923
924
925static void ataSetIRQ(ATADevState *s)
926{
927 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
928 PPDMDEVINS pDevIns = ATADEVSTATE_2_DEVINS(s);
929
930 if (!(s->uATARegDevCtl & ATA_DEVCTL_DISABLE_IRQ))
931 {
932 Log2(("%s: LUN#%d asserting IRQ\n", __FUNCTION__, s->iLUN));
933 /* The BMDMA unit unconditionally sets BM_STATUS_INT if the interrupt
934 * line is asserted. It monitors the line for a rising edge. */
935 if (!s->fIrqPending)
936 pCtl->BmDma.u8Status |= BM_STATUS_INT;
937 /* Only actually set the IRQ line if updating the currently selected drive. */
938 if (s == &pCtl->aIfs[pCtl->iSelectedIf])
939 {
940 /** @todo experiment with adaptive IRQ delivery: for reads it is
941 * better to wait for IRQ delivery, as it reduces latency. */
942 if (pCtl->irq == 16)
943 PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
944 else
945 PDMDevHlpISASetIrqNoWait(pDevIns, pCtl->irq, 1);
946 }
947 }
948 s->fIrqPending = true;
949}
950
951#endif /* IN_RING3 */
952
953static void ataUnsetIRQ(ATADevState *s)
954{
955 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
956 PPDMDEVINS pDevIns = ATADEVSTATE_2_DEVINS(s);
957
958 if (!(s->uATARegDevCtl & ATA_DEVCTL_DISABLE_IRQ))
959 {
960 Log2(("%s: LUN#%d deasserting IRQ\n", __FUNCTION__, s->iLUN));
961 /* Only actually unset the IRQ line if updating the currently selected drive. */
962 if (s == &pCtl->aIfs[pCtl->iSelectedIf])
963 {
964 if (pCtl->irq == 16)
965 PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
966 else
967 PDMDevHlpISASetIrqNoWait(pDevIns, pCtl->irq, 0);
968 }
969 }
970 s->fIrqPending = false;
971}
972
973#ifdef IN_RING3
974
975static void ataPIOTransferStart(ATADevState *s, uint32_t start, uint32_t size)
976{
977 Log2(("%s: LUN#%d start %d size %d\n", __FUNCTION__, s->iLUN, start, size));
978 s->iIOBufferPIODataStart = start;
979 s->iIOBufferPIODataEnd = start + size;
980 ataSetStatus(s, ATA_STAT_DRQ);
981}
982
983
984static void ataPIOTransferStop(ATADevState *s)
985{
986 Log2(("%s: LUN#%d\n", __FUNCTION__, s->iLUN));
987 if (s->fATAPITransfer)
988 {
989 s->uATARegNSector = (s->uATARegNSector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
990 Log2(("%s: interrupt reason %#04x\n", __FUNCTION__, s->uATARegNSector));
991 ataSetIRQ(s);
992 s->fATAPITransfer = false;
993 }
994 s->cbTotalTransfer = 0;
995 s->cbElementaryTransfer = 0;
996 s->iIOBufferPIODataStart = 0;
997 s->iIOBufferPIODataEnd = 0;
998 s->iBeginTransfer = ATAFN_BT_NULL;
999 s->iSourceSink = ATAFN_SS_NULL;
1000}
1001
1002
1003static void ataPIOTransferLimitATAPI(ATADevState *s)
1004{
1005 uint32_t cbLimit, cbTransfer;
1006
1007 cbLimit = s->uATARegLCyl | (s->uATARegHCyl << 8);
1008 /* Use maximum transfer size if the guest requested 0. Avoids a hang. */
1009 if (cbLimit == 0)
1010 cbLimit = 0xfffe;
1011 Log2(("%s: byte count limit=%d\n", __FUNCTION__, cbLimit));
1012 if (cbLimit == 0xffff)
1013 cbLimit--;
1014 cbTransfer = RT_MIN(s->cbTotalTransfer, s->iIOBufferEnd - s->iIOBufferCur);
1015 if (cbTransfer > cbLimit)
1016 {
1017 /* Byte count limit for clipping must be even in this case */
1018 if (cbLimit & 1)
1019 cbLimit--;
1020 cbTransfer = cbLimit;
1021 }
1022 s->uATARegLCyl = cbTransfer;
1023 s->uATARegHCyl = cbTransfer >> 8;
1024 s->cbElementaryTransfer = cbTransfer;
1025}
1026
1027
1028static uint32_t ataGetNSectors(ATADevState *s)
1029{
1030 /* 0 means either 256 (LBA28) or 65536 (LBA48) sectors. */
1031 if (s->fLBA48)
1032 {
1033 if (!s->uATARegNSector && !s->uATARegNSectorHOB)
1034 return 65536;
1035 else
1036 return s->uATARegNSectorHOB << 8 | s->uATARegNSector;
1037 }
1038 else
1039 {
1040 if (!s->uATARegNSector)
1041 return 256;
1042 else
1043 return s->uATARegNSector;
1044 }
1045}
1046
1047
1048static void ataPadString(uint8_t *pbDst, const char *pbSrc, uint32_t cbSize)
1049{
1050 for (uint32_t i = 0; i < cbSize; i++)
1051 {
1052 if (*pbSrc)
1053 pbDst[i ^ 1] = *pbSrc++;
1054 else
1055 pbDst[i ^ 1] = ' ';
1056 }
1057}
1058
1059
1060static void ataSCSIPadStr(uint8_t *pbDst, const char *pbSrc, uint32_t cbSize)
1061{
1062 for (uint32_t i = 0; i < cbSize; i++)
1063 {
1064 if (*pbSrc)
1065 pbDst[i] = *pbSrc++;
1066 else
1067 pbDst[i] = ' ';
1068 }
1069}
1070
1071
1072DECLINLINE(void) ataH2BE_U16(uint8_t *pbBuf, uint16_t val)
1073{
1074 pbBuf[0] = val >> 8;
1075 pbBuf[1] = val;
1076}
1077
1078
1079DECLINLINE(void) ataH2BE_U24(uint8_t *pbBuf, uint32_t val)
1080{
1081 pbBuf[0] = val >> 16;
1082 pbBuf[1] = val >> 8;
1083 pbBuf[2] = val;
1084}
1085
1086
1087DECLINLINE(void) ataH2BE_U32(uint8_t *pbBuf, uint32_t val)
1088{
1089 pbBuf[0] = val >> 24;
1090 pbBuf[1] = val >> 16;
1091 pbBuf[2] = val >> 8;
1092 pbBuf[3] = val;
1093}
1094
1095
1096DECLINLINE(uint16_t) ataBE2H_U16(const uint8_t *pbBuf)
1097{
1098 return (pbBuf[0] << 8) | pbBuf[1];
1099}
1100
1101
1102DECLINLINE(uint32_t) ataBE2H_U24(const uint8_t *pbBuf)
1103{
1104 return (pbBuf[0] << 16) | (pbBuf[1] << 8) | pbBuf[2];
1105}
1106
1107
1108DECLINLINE(uint32_t) ataBE2H_U32(const uint8_t *pbBuf)
1109{
1110 return (pbBuf[0] << 24) | (pbBuf[1] << 16) | (pbBuf[2] << 8) | pbBuf[3];
1111}
1112
1113
1114DECLINLINE(void) ataLBA2MSF(uint8_t *pbBuf, uint32_t iATAPILBA)
1115{
1116 iATAPILBA += 150;
1117 pbBuf[0] = (iATAPILBA / 75) / 60;
1118 pbBuf[1] = (iATAPILBA / 75) % 60;
1119 pbBuf[2] = iATAPILBA % 75;
1120}
1121
1122
1123DECLINLINE(uint32_t) ataMSF2LBA(const uint8_t *pbBuf)
1124{
1125 return (pbBuf[0] * 60 + pbBuf[1]) * 75 + pbBuf[2];
1126}
1127
1128
1129static void ataCmdOK(ATADevState *s, uint8_t status)
1130{
1131 s->uATARegError = 0; /* Not needed by ATA spec, but cannot hurt. */
1132 ataSetStatusValue(s, ATA_STAT_READY | status);
1133}
1134
1135
1136static void ataCmdError(ATADevState *s, uint8_t uErrorCode)
1137{
1138 Log(("%s: code=%#x\n", __FUNCTION__, uErrorCode));
1139 s->uATARegError = uErrorCode;
1140 ataSetStatusValue(s, ATA_STAT_READY | ATA_STAT_ERR);
1141 s->cbTotalTransfer = 0;
1142 s->cbElementaryTransfer = 0;
1143 s->iIOBufferCur = 0;
1144 s->iIOBufferEnd = 0;
1145 s->uTxDir = PDMBLOCKTXDIR_NONE;
1146 s->iBeginTransfer = ATAFN_BT_NULL;
1147 s->iSourceSink = ATAFN_SS_NULL;
1148}
1149
1150static uint32_t ataChecksum(void* p, size_t count)
1151{
1152 uint8_t sum = 0xa5, *pp = (uint8_t*)p;
1153 size_t i;
1154
1155 for (i = 0; i < count; i++)
1156 {
1157 sum += pp[i];
1158 count--;
1159 }
1160
1161 return (uint8_t)-(int32_t)sum;
1162}
1163
1164static bool ataIdentifySS(ATADevState *s)
1165{
1166 uint16_t *p;
1167
1168 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
1169 Assert(s->cbElementaryTransfer == 512);
1170
1171 p = (uint16_t *)s->CTX_SUFF(pbIOBuffer);
1172 memset(p, 0, 512);
1173 p[0] = RT_H2LE_U16(0x0040);
1174 p[1] = RT_H2LE_U16(RT_MIN(s->PCHSGeometry.cCylinders, 16383));
1175 p[3] = RT_H2LE_U16(s->PCHSGeometry.cHeads);
1176 /* Block size; obsolete, but required for the BIOS. */
1177 p[5] = RT_H2LE_U16(512);
1178 p[6] = RT_H2LE_U16(s->PCHSGeometry.cSectors);
1179 ataPadString((uint8_t *)(p + 10), s->szSerialNumber, ATA_SERIAL_NUMBER_LENGTH); /* serial number */
1180 p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
1181 p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
1182 p[22] = RT_H2LE_U16(0); /* ECC bytes per sector */
1183 ataPadString((uint8_t *)(p + 23), s->szFirmwareRevision, ATA_FIRMWARE_REVISION_LENGTH); /* firmware version */
1184 ataPadString((uint8_t *)(p + 27), s->szModelNumber, ATA_MODEL_NUMBER_LENGTH); /* model */
1185#if ATA_MAX_MULT_SECTORS > 1
1186 p[47] = RT_H2LE_U16(0x8000 | ATA_MAX_MULT_SECTORS);
1187#endif
1188 p[48] = RT_H2LE_U16(1); /* dword I/O, used by the BIOS */
1189 p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
1190 p[50] = RT_H2LE_U16(1 << 14); /* No drive specific standby timer minimum */
1191 p[51] = RT_H2LE_U16(240); /* PIO transfer cycle */
1192 p[52] = RT_H2LE_U16(240); /* DMA transfer cycle */
1193 p[53] = RT_H2LE_U16(1 | 1 << 1 | 1 << 2); /* words 54-58,64-70,88 valid */
1194 p[54] = RT_H2LE_U16(RT_MIN(s->PCHSGeometry.cCylinders, 16383));
1195 p[55] = RT_H2LE_U16(s->PCHSGeometry.cHeads);
1196 p[56] = RT_H2LE_U16(s->PCHSGeometry.cSectors);
1197 p[57] = RT_H2LE_U16( RT_MIN(s->PCHSGeometry.cCylinders, 16383)
1198 * s->PCHSGeometry.cHeads
1199 * s->PCHSGeometry.cSectors);
1200 p[58] = RT_H2LE_U16( RT_MIN(s->PCHSGeometry.cCylinders, 16383)
1201 * s->PCHSGeometry.cHeads
1202 * s->PCHSGeometry.cSectors >> 16);
1203 if (s->cMultSectors)
1204 p[59] = RT_H2LE_U16(0x100 | s->cMultSectors);
1205 if (s->cTotalSectors <= (1 << 28) - 1)
1206 {
1207 p[60] = RT_H2LE_U16(s->cTotalSectors);
1208 p[61] = RT_H2LE_U16(s->cTotalSectors >> 16);
1209 }
1210 else
1211 {
1212 /* Report maximum number of sectors possible with LBA28 */
1213 p[60] = RT_H2LE_U16(((1 << 28) - 1) & 0xffff);
1214 p[61] = RT_H2LE_U16(((1 << 28) - 1) >> 16);
1215 }
1216 p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, s->uATATransferMode)); /* MDMA modes supported / mode enabled */
1217 p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
1218 p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
1219 p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
1220 p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
1221 p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
1222 p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
1223 p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
1224 p[82] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* supports power management, write cache and look-ahead */
1225 if (s->cTotalSectors <= (1 << 28) - 1)
1226 p[83] = RT_H2LE_U16(1 << 14 | 1 << 12); /* supports FLUSH CACHE */
1227 else
1228 p[83] = RT_H2LE_U16(1 << 14 | 1 << 10 | 1 << 12 | 1 << 13); /* supports LBA48, FLUSH CACHE and FLUSH CACHE EXT */
1229 p[84] = RT_H2LE_U16(1 << 14);
1230 p[85] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* enabled power management, write cache and look-ahead */
1231 if (s->cTotalSectors <= (1 << 28) - 1)
1232 p[86] = RT_H2LE_U16(1 << 12); /* enabled FLUSH CACHE */
1233 else
1234 p[86] = RT_H2LE_U16(1 << 10 | 1 << 12 | 1 << 13); /* enabled LBA48, FLUSH CACHE and FLUSH CACHE EXT */
1235 p[87] = RT_H2LE_U16(1 << 14);
1236 p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, s->uATATransferMode)); /* UDMA modes supported / mode enabled */
1237 p[93] = RT_H2LE_U16((1 | 1 << 1) << ((s->iLUN & 1) == 0 ? 0 : 8) | 1 << 13 | 1 << 14);
1238 if (s->cTotalSectors > (1 << 28) - 1)
1239 {
1240 p[100] = RT_H2LE_U16(s->cTotalSectors);
1241 p[101] = RT_H2LE_U16(s->cTotalSectors >> 16);
1242 p[102] = RT_H2LE_U16(s->cTotalSectors >> 32);
1243 p[103] = RT_H2LE_U16(s->cTotalSectors >> 48);
1244 }
1245 uint32_t uCsum = ataChecksum(p, 510);
1246 p[255] = RT_H2LE_U16(0xa5 | (uCsum << 8)); /* Integrity word */
1247 s->iSourceSink = ATAFN_SS_NULL;
1248 ataCmdOK(s, ATA_STAT_SEEK);
1249 return false;
1250}
1251
1252
1253static bool ataFlushSS(ATADevState *s)
1254{
1255 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
1256 int rc;
1257
1258 Assert(s->uTxDir == PDMBLOCKTXDIR_NONE);
1259 Assert(!s->cbElementaryTransfer);
1260
1261 PDMCritSectLeave(&pCtl->lock);
1262
1263 STAM_PROFILE_START(&s->StatFlushes, f);
1264 rc = s->pDrvBlock->pfnFlush(s->pDrvBlock);
1265 AssertRC(rc);
1266 STAM_PROFILE_STOP(&s->StatFlushes, f);
1267
1268 STAM_PROFILE_START(&pCtl->StatLockWait, a);
1269 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
1270 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
1271 ataCmdOK(s, 0);
1272 return false;
1273}
1274
1275static bool atapiIdentifySS(ATADevState *s)
1276{
1277 uint16_t *p;
1278
1279 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
1280 Assert(s->cbElementaryTransfer == 512);
1281
1282 p = (uint16_t *)s->CTX_SUFF(pbIOBuffer);
1283 memset(p, 0, 512);
1284 /* Removable CDROM, 50us response, 12 byte packets */
1285 p[0] = RT_H2LE_U16(2 << 14 | 5 << 8 | 1 << 7 | 2 << 5 | 0 << 0);
1286 ataPadString((uint8_t *)(p + 10), s->szSerialNumber, ATA_SERIAL_NUMBER_LENGTH); /* serial number */
1287 p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
1288 p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
1289 ataPadString((uint8_t *)(p + 23), s->szFirmwareRevision, ATA_FIRMWARE_REVISION_LENGTH); /* firmware version */
1290 ataPadString((uint8_t *)(p + 27), s->szModelNumber, ATA_MODEL_NUMBER_LENGTH); /* model */
1291 p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
1292 p[50] = RT_H2LE_U16(1 << 14); /* No drive specific standby timer minimum */
1293 p[51] = RT_H2LE_U16(240); /* PIO transfer cycle */
1294 p[52] = RT_H2LE_U16(240); /* DMA transfer cycle */
1295 p[53] = RT_H2LE_U16(1 << 1 | 1 << 2); /* words 64-70,88 are valid */
1296 p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, s->uATATransferMode)); /* MDMA modes supported / mode enabled */
1297 p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
1298 p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
1299 p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
1300 p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
1301 p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
1302 p[73] = RT_H2LE_U16(0x003e); /* ATAPI CDROM major */
1303 p[74] = RT_H2LE_U16(9); /* ATAPI CDROM minor */
1304 p[75] = RT_H2LE_U16(1); /* queue depth 1 */
1305 p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
1306 p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
1307 p[82] = RT_H2LE_U16(1 << 4 | 1 << 9); /* supports packet command set and DEVICE RESET */
1308 p[83] = RT_H2LE_U16(1 << 14);
1309 p[84] = RT_H2LE_U16(1 << 14);
1310 p[85] = RT_H2LE_U16(1 << 4 | 1 << 9); /* enabled packet command set and DEVICE RESET */
1311 p[86] = RT_H2LE_U16(0);
1312 p[87] = RT_H2LE_U16(1 << 14);
1313 p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, s->uATATransferMode)); /* UDMA modes supported / mode enabled */
1314 p[93] = RT_H2LE_U16((1 | 1 << 1) << ((s->iLUN & 1) == 0 ? 0 : 8) | 1 << 13 | 1 << 14);
1315 /* According to ATAPI-5 spec:
1316 *
1317 * The use of this word is optional.
1318 * If bits 7:0 of this word contain the signature A5h, bits 15:8
1319 * contain the data
1320 * structure checksum.
1321 * The data structure checksum is the twos complement of the sum of
1322 * all bytes in words 0 through 254 and the byte consisting of
1323 * bits 7:0 in word 255.
1324 * Each byte shall be added with unsigned arithmetic,
1325 * and overflow shall be ignored.
1326 * The sum of all 512 bytes is zero when the checksum is correct.
1327 */
1328 uint32_t uCsum = ataChecksum(p, 510);
1329 p[255] = RT_H2LE_U16(0xa5 | (uCsum << 8)); /* Integrity word */
1330
1331 s->iSourceSink = ATAFN_SS_NULL;
1332 ataCmdOK(s, ATA_STAT_SEEK);
1333 return false;
1334}
1335
1336
1337static void ataSetSignature(ATADevState *s)
1338{
1339 s->uATARegSelect &= 0xf0; /* clear head */
1340 /* put signature */
1341 s->uATARegNSector = 1;
1342 s->uATARegSector = 1;
1343 if (s->fATAPI)
1344 {
1345 s->uATARegLCyl = 0x14;
1346 s->uATARegHCyl = 0xeb;
1347 }
1348 else if (s->pDrvBlock)
1349 {
1350 s->uATARegLCyl = 0;
1351 s->uATARegHCyl = 0;
1352 }
1353 else
1354 {
1355 s->uATARegLCyl = 0xff;
1356 s->uATARegHCyl = 0xff;
1357 }
1358}
1359
1360
1361static uint64_t ataGetSector(ATADevState *s)
1362{
1363 uint64_t iLBA;
1364 if (s->uATARegSelect & 0x40)
1365 {
1366 /* any LBA variant */
1367 if (s->fLBA48)
1368 {
1369 /* LBA48 */
1370 iLBA = ((uint64_t)s->uATARegHCylHOB << 40) |
1371 ((uint64_t)s->uATARegLCylHOB << 32) |
1372 ((uint64_t)s->uATARegSectorHOB << 24) |
1373 ((uint64_t)s->uATARegHCyl << 16) |
1374 ((uint64_t)s->uATARegLCyl << 8) |
1375 s->uATARegSector;
1376 }
1377 else
1378 {
1379 /* LBA */
1380 iLBA = ((s->uATARegSelect & 0x0f) << 24) | (s->uATARegHCyl << 16) |
1381 (s->uATARegLCyl << 8) | s->uATARegSector;
1382 }
1383 }
1384 else
1385 {
1386 /* CHS */
1387 iLBA = ((s->uATARegHCyl << 8) | s->uATARegLCyl) * s->PCHSGeometry.cHeads * s->PCHSGeometry.cSectors +
1388 (s->uATARegSelect & 0x0f) * s->PCHSGeometry.cSectors +
1389 (s->uATARegSector - 1);
1390 }
1391 return iLBA;
1392}
1393
1394static void ataSetSector(ATADevState *s, uint64_t iLBA)
1395{
1396 uint32_t cyl, r;
1397 if (s->uATARegSelect & 0x40)
1398 {
1399 /* any LBA variant */
1400 if (s->fLBA48)
1401 {
1402 /* LBA48 */
1403 s->uATARegHCylHOB = iLBA >> 40;
1404 s->uATARegLCylHOB = iLBA >> 32;
1405 s->uATARegSectorHOB = iLBA >> 24;
1406 s->uATARegHCyl = iLBA >> 16;
1407 s->uATARegLCyl = iLBA >> 8;
1408 s->uATARegSector = iLBA;
1409 }
1410 else
1411 {
1412 /* LBA */
1413 s->uATARegSelect = (s->uATARegSelect & 0xf0) | (iLBA >> 24);
1414 s->uATARegHCyl = (iLBA >> 16);
1415 s->uATARegLCyl = (iLBA >> 8);
1416 s->uATARegSector = (iLBA);
1417 }
1418 }
1419 else
1420 {
1421 /* CHS */
1422 cyl = iLBA / (s->PCHSGeometry.cHeads * s->PCHSGeometry.cSectors);
1423 r = iLBA % (s->PCHSGeometry.cHeads * s->PCHSGeometry.cSectors);
1424 s->uATARegHCyl = cyl >> 8;
1425 s->uATARegLCyl = cyl;
1426 s->uATARegSelect = (s->uATARegSelect & 0xf0) | ((r / s->PCHSGeometry.cSectors) & 0x0f);
1427 s->uATARegSector = (r % s->PCHSGeometry.cSectors) + 1;
1428 }
1429}
1430
1431
1432static void ataWarningDiskFull(PPDMDEVINS pDevIns)
1433{
1434 int rc;
1435 LogRel(("PIIX3 ATA: Host disk full\n"));
1436 rc = PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "DevATA_DISKFULL",
1437 N_("Host system reported disk full. VM execution is suspended. You can resume after freeing some space"));
1438 AssertRC(rc);
1439}
1440
1441static void ataWarningFileTooBig(PPDMDEVINS pDevIns)
1442{
1443 int rc;
1444 LogRel(("PIIX3 ATA: File too big\n"));
1445 rc = PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "DevATA_FILETOOBIG",
1446 N_("Host system reported that the file size limit of the host file system has been exceeded. VM execution is suspended. You need to move your virtual hard disk to a filesystem which allows bigger files"));
1447 AssertRC(rc);
1448}
1449
1450static void ataWarningISCSI(PPDMDEVINS pDevIns)
1451{
1452 int rc;
1453 LogRel(("PIIX3 ATA: iSCSI target unavailable\n"));
1454 rc = PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "DevATA_ISCSIDOWN",
1455 N_("The iSCSI target has stopped responding. VM execution is suspended. You can resume when it is available again"));
1456 AssertRC(rc);
1457}
1458
1459/**
1460 * Suspend I/O operations on a controller. Also suspends EMT, because it's
1461 * waiting for I/O to make progress. The next attempt to perform an I/O
1462 * operation will be made when EMT is resumed up again (as the resume
1463 * callback below restarts I/O).
1464 *
1465 * @param pCtl Controller for which to suspend I/O.
1466 */
1467static void ataSuspendRedo(PATACONTROLLER pCtl)
1468{
1469 PPDMDEVINS pDevIns = CONTROLLER_2_DEVINS(pCtl);
1470 int rc;
1471
1472 pCtl->fRedoIdle = true;
1473 rc = VMR3ReqCallWait(PDMDevHlpGetVM(pDevIns), VMCPUID_ANY,
1474 (PFNRT)PDMDevHlpVMSuspend, 1, pDevIns);
1475 AssertReleaseRC(rc);
1476}
1477
1478bool ataIsRedoSetWarning(ATADevState *s, int rc)
1479{
1480 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
1481 Assert(!PDMCritSectIsOwner(&pCtl->lock));
1482 if (rc == VERR_DISK_FULL)
1483 {
1484 ataWarningDiskFull(ATADEVSTATE_2_DEVINS(s));
1485 ataSuspendRedo(pCtl);
1486 return true;
1487 }
1488 if (rc == VERR_FILE_TOO_BIG)
1489 {
1490 ataWarningFileTooBig(ATADEVSTATE_2_DEVINS(s));
1491 ataSuspendRedo(pCtl);
1492 return true;
1493 }
1494 if (rc == VERR_BROKEN_PIPE || rc == VERR_NET_CONNECTION_REFUSED)
1495 {
1496 /* iSCSI connection abort (first error) or failure to reestablish
1497 * connection (second error). Pause VM. On resume we'll retry. */
1498 ataWarningISCSI(ATADEVSTATE_2_DEVINS(s));
1499 ataSuspendRedo(pCtl);
1500 return true;
1501 }
1502 return false;
1503}
1504
1505
1506static int ataReadSectors(ATADevState *s, uint64_t u64Sector, void *pvBuf, uint32_t cSectors, bool *fRedo)
1507{
1508 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
1509 int rc;
1510
1511 PDMCritSectLeave(&pCtl->lock);
1512
1513 STAM_PROFILE_ADV_START(&s->StatReads, r);
1514 s->Led.Asserted.s.fReading = s->Led.Actual.s.fReading = 1;
1515 rc = s->pDrvBlock->pfnRead(s->pDrvBlock, u64Sector * 512, pvBuf, cSectors * 512);
1516 s->Led.Actual.s.fReading = 0;
1517 STAM_PROFILE_ADV_STOP(&s->StatReads, r);
1518
1519 STAM_REL_COUNTER_ADD(&s->StatBytesRead, cSectors * 512);
1520
1521 if (RT_SUCCESS(rc))
1522 *fRedo = false;
1523 else
1524 *fRedo = ataIsRedoSetWarning(s, rc);
1525
1526 STAM_PROFILE_START(&pCtl->StatLockWait, a);
1527 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
1528 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
1529 return rc;
1530}
1531
1532
1533static int ataWriteSectors(ATADevState *s, uint64_t u64Sector, const void *pvBuf, uint32_t cSectors, bool *fRedo)
1534{
1535 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
1536 int rc;
1537
1538 PDMCritSectLeave(&pCtl->lock);
1539
1540 STAM_PROFILE_ADV_START(&s->StatWrites, w);
1541 s->Led.Asserted.s.fWriting = s->Led.Actual.s.fWriting = 1;
1542#ifdef VBOX_INSTRUMENT_DMA_WRITES
1543 if (s->fDMA)
1544 STAM_PROFILE_ADV_START(&s->StatInstrVDWrites, vw);
1545#endif
1546 rc = s->pDrvBlock->pfnWrite(s->pDrvBlock, u64Sector * 512, pvBuf, cSectors * 512);
1547#ifdef VBOX_INSTRUMENT_DMA_WRITES
1548 if (s->fDMA)
1549 STAM_PROFILE_ADV_STOP(&s->StatInstrVDWrites, vw);
1550#endif
1551 s->Led.Actual.s.fWriting = 0;
1552 STAM_PROFILE_ADV_STOP(&s->StatWrites, w);
1553
1554 STAM_REL_COUNTER_ADD(&s->StatBytesWritten, cSectors * 512);
1555
1556 if (RT_SUCCESS(rc))
1557 *fRedo = false;
1558 else
1559 *fRedo = ataIsRedoSetWarning(s, rc);
1560
1561 STAM_PROFILE_START(&pCtl->StatLockWait, a);
1562 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
1563 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
1564 return rc;
1565}
1566
1567
1568static void ataReadWriteSectorsBT(ATADevState *s)
1569{
1570 uint32_t cSectors;
1571
1572 cSectors = s->cbTotalTransfer / 512;
1573 if (cSectors > s->cSectorsPerIRQ)
1574 s->cbElementaryTransfer = s->cSectorsPerIRQ * 512;
1575 else
1576 s->cbElementaryTransfer = cSectors * 512;
1577 if (s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE)
1578 ataCmdOK(s, 0);
1579}
1580
1581
1582static bool ataReadSectorsSS(ATADevState *s)
1583{
1584 int rc;
1585 uint32_t cSectors;
1586 uint64_t iLBA;
1587 bool fRedo;
1588
1589 cSectors = s->cbElementaryTransfer / 512;
1590 Assert(cSectors);
1591 iLBA = ataGetSector(s);
1592 Log(("%s: %d sectors at LBA %d\n", __FUNCTION__, cSectors, iLBA));
1593 rc = ataReadSectors(s, iLBA, s->CTX_SUFF(pbIOBuffer), cSectors, &fRedo);
1594 if (RT_SUCCESS(rc))
1595 {
1596 ataSetSector(s, iLBA + cSectors);
1597 if (s->cbElementaryTransfer == s->cbTotalTransfer)
1598 s->iSourceSink = ATAFN_SS_NULL;
1599 ataCmdOK(s, ATA_STAT_SEEK);
1600 }
1601 else
1602 {
1603 if (fRedo)
1604 return fRedo;
1605 if (s->cErrors++ < MAX_LOG_REL_ERRORS)
1606 LogRel(("PIIX3 ATA: LUN#%d: disk read error (rc=%Rrc iSector=%#RX64 cSectors=%#RX32)\n",
1607 s->iLUN, rc, iLBA, cSectors));
1608
1609 /*
1610 * Check if we got interrupted. We don't need to set status variables
1611 * because the request was aborted.
1612 */
1613 if (rc != VERR_INTERRUPTED)
1614 ataCmdError(s, ID_ERR);
1615 }
1616 return false;
1617}
1618
1619
1620static bool ataWriteSectorsSS(ATADevState *s)
1621{
1622 int rc;
1623 uint32_t cSectors;
1624 uint64_t iLBA;
1625 bool fRedo;
1626
1627 cSectors = s->cbElementaryTransfer / 512;
1628 Assert(cSectors);
1629 iLBA = ataGetSector(s);
1630 Log(("%s: %d sectors at LBA %d\n", __FUNCTION__, cSectors, iLBA));
1631 rc = ataWriteSectors(s, iLBA, s->CTX_SUFF(pbIOBuffer), cSectors, &fRedo);
1632 if (RT_SUCCESS(rc))
1633 {
1634 ataSetSector(s, iLBA + cSectors);
1635 if (!s->cbTotalTransfer)
1636 s->iSourceSink = ATAFN_SS_NULL;
1637 ataCmdOK(s, ATA_STAT_SEEK);
1638 }
1639 else
1640 {
1641 if (fRedo)
1642 return fRedo;
1643 if (s->cErrors++ < MAX_LOG_REL_ERRORS)
1644 LogRel(("PIIX3 ATA: LUN#%d: disk write error (rc=%Rrc iSector=%#RX64 cSectors=%#RX32)\n",
1645 s->iLUN, rc, iLBA, cSectors));
1646
1647 /*
1648 * Check if we got interrupted. We don't need to set status variables
1649 * because the request was aborted.
1650 */
1651 if (rc != VERR_INTERRUPTED)
1652 ataCmdError(s, ID_ERR);
1653 }
1654 return false;
1655}
1656
1657
1658static void atapiCmdOK(ATADevState *s)
1659{
1660 s->uATARegError = 0;
1661 ataSetStatusValue(s, ATA_STAT_READY);
1662 s->uATARegNSector = (s->uATARegNSector & ~7)
1663 | ((s->uTxDir != PDMBLOCKTXDIR_TO_DEVICE) ? ATAPI_INT_REASON_IO : 0)
1664 | (!s->cbTotalTransfer ? ATAPI_INT_REASON_CD : 0);
1665 Log2(("%s: interrupt reason %#04x\n", __FUNCTION__, s->uATARegNSector));
1666
1667 memset(s->abATAPISense, '\0', sizeof(s->abATAPISense));
1668 s->abATAPISense[0] = 0x70 | (1 << 7);
1669 s->abATAPISense[7] = 10;
1670}
1671
1672
1673static void atapiCmdError(ATADevState *s, const uint8_t *pabATAPISense, size_t cbATAPISense)
1674{
1675 Log(("%s: sense=%#x (%s) asc=%#x ascq=%#x (%s)\n", __FUNCTION__, pabATAPISense[2] & 0x0f, SCSISenseText(pabATAPISense[2] & 0x0f),
1676 pabATAPISense[12], pabATAPISense[13], SCSISenseExtText(pabATAPISense[12], pabATAPISense[13])));
1677 s->uATARegError = pabATAPISense[2] << 4;
1678 ataSetStatusValue(s, ATA_STAT_READY | ATA_STAT_ERR);
1679 s->uATARegNSector = (s->uATARegNSector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
1680 Log2(("%s: interrupt reason %#04x\n", __FUNCTION__, s->uATARegNSector));
1681 memset(s->abATAPISense, '\0', sizeof(s->abATAPISense));
1682 memcpy(s->abATAPISense, pabATAPISense, RT_MIN(cbATAPISense, sizeof(s->abATAPISense)));
1683 s->cbTotalTransfer = 0;
1684 s->cbElementaryTransfer = 0;
1685 s->iIOBufferCur = 0;
1686 s->iIOBufferEnd = 0;
1687 s->uTxDir = PDMBLOCKTXDIR_NONE;
1688 s->iBeginTransfer = ATAFN_BT_NULL;
1689 s->iSourceSink = ATAFN_SS_NULL;
1690}
1691
1692
1693/** @todo deprecated function - doesn't provide enough info. Replace by direct
1694 * calls to atapiCmdError() with full data. */
1695static void atapiCmdErrorSimple(ATADevState *s, uint8_t uATAPISenseKey, uint8_t uATAPIASC)
1696{
1697 uint8_t abATAPISense[ATAPI_SENSE_SIZE];
1698 memset(abATAPISense, '\0', sizeof(abATAPISense));
1699 abATAPISense[0] = 0x70 | (1 << 7);
1700 abATAPISense[2] = uATAPISenseKey & 0x0f;
1701 abATAPISense[7] = 10;
1702 abATAPISense[12] = uATAPIASC;
1703 atapiCmdError(s, abATAPISense, sizeof(abATAPISense));
1704}
1705
1706
1707static void atapiCmdBT(ATADevState *s)
1708{
1709 s->fATAPITransfer = true;
1710 s->cbElementaryTransfer = s->cbTotalTransfer;
1711 if (s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE)
1712 atapiCmdOK(s);
1713}
1714
1715
1716static void atapiPassthroughCmdBT(ATADevState *s)
1717{
1718 /* @todo implement an algorithm for correctly determining the read and
1719 * write sector size without sending additional commands to the drive.
1720 * This should be doable by saving processing the configuration requests
1721 * and replies. */
1722#if 0
1723 if (s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE)
1724 {
1725 uint8_t cmd = s->aATAPICmd[0];
1726 if (cmd == SCSI_WRITE_10 || cmd == SCSI_WRITE_12 || cmd == SCSI_WRITE_AND_VERIFY_10)
1727 {
1728 uint8_t aModeSenseCmd[10];
1729 uint8_t aModeSenseResult[16];
1730 uint8_t uDummySense;
1731 uint32_t cbTransfer;
1732 int rc;
1733
1734 cbTransfer = sizeof(aModeSenseResult);
1735 aModeSenseCmd[0] = SCSI_MODE_SENSE_10;
1736 aModeSenseCmd[1] = 0x08; /* disable block descriptor = 1 */
1737 aModeSenseCmd[2] = (SCSI_PAGECONTROL_CURRENT << 6) | SCSI_MODEPAGE_WRITE_PARAMETER;
1738 aModeSenseCmd[3] = 0; /* subpage code */
1739 aModeSenseCmd[4] = 0; /* reserved */
1740 aModeSenseCmd[5] = 0; /* reserved */
1741 aModeSenseCmd[6] = 0; /* reserved */
1742 aModeSenseCmd[7] = cbTransfer >> 8;
1743 aModeSenseCmd[8] = cbTransfer & 0xff;
1744 aModeSenseCmd[9] = 0; /* control */
1745 rc = s->pDrvBlock->pfnSendCmd(s->pDrvBlock, aModeSenseCmd, PDMBLOCKTXDIR_FROM_DEVICE, aModeSenseResult, &cbTransfer, &uDummySense, 500);
1746 if (RT_FAILURE(rc))
1747 {
1748 atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_NONE);
1749 return;
1750 }
1751 /* Select sector size based on the current data block type. */
1752 switch (aModeSenseResult[12] & 0x0f)
1753 {
1754 case 0:
1755 s->cbATAPISector = 2352;
1756 break;
1757 case 1:
1758 s->cbATAPISector = 2368;
1759 break;
1760 case 2:
1761 case 3:
1762 s->cbATAPISector = 2448;
1763 break;
1764 case 8:
1765 case 10:
1766 s->cbATAPISector = 2048;
1767 break;
1768 case 9:
1769 s->cbATAPISector = 2336;
1770 break;
1771 case 11:
1772 s->cbATAPISector = 2056;
1773 break;
1774 case 12:
1775 s->cbATAPISector = 2324;
1776 break;
1777 case 13:
1778 s->cbATAPISector = 2332;
1779 break;
1780 default:
1781 s->cbATAPISector = 0;
1782 }
1783 Log2(("%s: sector size %d\n", __FUNCTION__, s->cbATAPISector));
1784 s->cbTotalTransfer *= s->cbATAPISector;
1785 if (s->cbTotalTransfer == 0)
1786 s->uTxDir = PDMBLOCKTXDIR_NONE;
1787 }
1788 }
1789#endif
1790 atapiCmdBT(s);
1791}
1792
1793
1794static bool atapiReadSS(ATADevState *s)
1795{
1796 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
1797 int rc = VINF_SUCCESS;
1798 uint32_t cbTransfer, cSectors;
1799
1800 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
1801 cbTransfer = RT_MIN(s->cbTotalTransfer, s->cbIOBuffer);
1802 cSectors = cbTransfer / s->cbATAPISector;
1803 Assert(cSectors * s->cbATAPISector <= cbTransfer);
1804 Log(("%s: %d sectors at LBA %d\n", __FUNCTION__, cSectors, s->iATAPILBA));
1805
1806 PDMCritSectLeave(&pCtl->lock);
1807
1808 STAM_PROFILE_ADV_START(&s->StatReads, r);
1809 s->Led.Asserted.s.fReading = s->Led.Actual.s.fReading = 1;
1810 switch (s->cbATAPISector)
1811 {
1812 case 2048:
1813 rc = s->pDrvBlock->pfnRead(s->pDrvBlock, (uint64_t)s->iATAPILBA * s->cbATAPISector, s->CTX_SUFF(pbIOBuffer), s->cbATAPISector * cSectors);
1814 break;
1815 case 2352:
1816 {
1817 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
1818
1819 for (uint32_t i = s->iATAPILBA; i < s->iATAPILBA + cSectors; i++)
1820 {
1821 /* Sync bytes, see 4.2.3.8 CD Main Channel Block Formats */
1822 *pbBuf++ = 0x00;
1823 memset(pbBuf, 0xff, 10);
1824 pbBuf += 10;
1825 *pbBuf++ = 0x00;
1826 /* MSF */
1827 ataLBA2MSF(pbBuf, i);
1828 pbBuf += 3;
1829 *pbBuf++ = 0x01; /* mode 1 data */
1830 /* data */
1831 rc = s->pDrvBlock->pfnRead(s->pDrvBlock, (uint64_t)i * 2048, pbBuf, 2048);
1832 if (RT_FAILURE(rc))
1833 break;
1834 pbBuf += 2048;
1835 /**
1836 * @todo: maybe compute ECC and parity, layout is:
1837 * 2072 4 EDC
1838 * 2076 172 P parity symbols
1839 * 2248 104 Q parity symbols
1840 */
1841 memset(pbBuf, 0, 280);
1842 pbBuf += 280;
1843 }
1844 }
1845 break;
1846 default:
1847 break;
1848 }
1849 STAM_PROFILE_ADV_STOP(&s->StatReads, r);
1850
1851 STAM_PROFILE_START(&pCtl->StatLockWait, a);
1852 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
1853 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
1854
1855 if (RT_SUCCESS(rc))
1856 {
1857 s->Led.Actual.s.fReading = 0;
1858 STAM_REL_COUNTER_ADD(&s->StatBytesRead, s->cbATAPISector * cSectors);
1859
1860 /* The initial buffer end value has been set up based on the total
1861 * transfer size. But the I/O buffer size limits what can actually be
1862 * done in one transfer, so set the actual value of the buffer end. */
1863 s->cbElementaryTransfer = cbTransfer;
1864 if (cbTransfer >= s->cbTotalTransfer)
1865 s->iSourceSink = ATAFN_SS_NULL;
1866 atapiCmdOK(s);
1867 s->iATAPILBA += cSectors;
1868 }
1869 else
1870 {
1871 if (s->cErrors++ < MAX_LOG_REL_ERRORS)
1872 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM read error, %d sectors at LBA %d\n", s->iLUN, cSectors, s->iATAPILBA));
1873
1874 /*
1875 * Check if we got interrupted. We don't need to set status variables
1876 * because the request was aborted.
1877 */
1878 if (rc != VERR_INTERRUPTED)
1879 atapiCmdErrorSimple(s, SCSI_SENSE_MEDIUM_ERROR, SCSI_ASC_READ_ERROR);
1880 }
1881 return false;
1882}
1883
1884
1885static bool atapiPassthroughSS(ATADevState *s)
1886{
1887 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
1888 int rc = VINF_SUCCESS;
1889 uint8_t abATAPISense[ATAPI_SENSE_SIZE];
1890 uint32_t cbTransfer;
1891 PSTAMPROFILEADV pProf = NULL;
1892
1893 cbTransfer = s->cbElementaryTransfer;
1894
1895 if (s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE)
1896 Log3(("ATAPI PT data write (%d): %.*Rhxs\n", cbTransfer, cbTransfer, s->CTX_SUFF(pbIOBuffer)));
1897
1898 /* Simple heuristics: if there is at least one sector of data
1899 * to transfer, it's worth updating the LEDs. */
1900 if (cbTransfer >= 2048)
1901 {
1902 if (s->uTxDir != PDMBLOCKTXDIR_TO_DEVICE)
1903 {
1904 s->Led.Asserted.s.fReading = s->Led.Actual.s.fReading = 1;
1905 pProf = &s->StatReads;
1906 }
1907 else
1908 {
1909 s->Led.Asserted.s.fWriting = s->Led.Actual.s.fWriting = 1;
1910 pProf = &s->StatWrites;
1911 }
1912 }
1913
1914 PDMCritSectLeave(&pCtl->lock);
1915
1916 if (pProf) { STAM_PROFILE_ADV_START(pProf, b); }
1917 if (cbTransfer > SCSI_MAX_BUFFER_SIZE)
1918 {
1919 /* Linux accepts commands with up to 100KB of data, but expects
1920 * us to handle commands with up to 128KB of data. The usual
1921 * imbalance of powers. */
1922 uint8_t aATAPICmd[ATAPI_PACKET_SIZE];
1923 uint32_t iATAPILBA, cSectors, cReqSectors, cbCurrTX;
1924 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
1925
1926 switch (s->aATAPICmd[0])
1927 {
1928 case SCSI_READ_10:
1929 case SCSI_WRITE_10:
1930 case SCSI_WRITE_AND_VERIFY_10:
1931 iATAPILBA = ataBE2H_U32(s->aATAPICmd + 2);
1932 cSectors = ataBE2H_U16(s->aATAPICmd + 7);
1933 break;
1934 case SCSI_READ_12:
1935 case SCSI_WRITE_12:
1936 iATAPILBA = ataBE2H_U32(s->aATAPICmd + 2);
1937 cSectors = ataBE2H_U32(s->aATAPICmd + 6);
1938 break;
1939 case SCSI_READ_CD:
1940 iATAPILBA = ataBE2H_U32(s->aATAPICmd + 2);
1941 cSectors = ataBE2H_U24(s->aATAPICmd + 6) / s->cbATAPISector;
1942 break;
1943 case SCSI_READ_CD_MSF:
1944 iATAPILBA = ataMSF2LBA(s->aATAPICmd + 3);
1945 cSectors = ataMSF2LBA(s->aATAPICmd + 6) - iATAPILBA;
1946 break;
1947 default:
1948 AssertMsgFailed(("Don't know how to split command %#04x\n", s->aATAPICmd[0]));
1949 if (s->cErrors++ < MAX_LOG_REL_ERRORS)
1950 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM passthrough split error\n", s->iLUN));
1951 atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
1952 {
1953 STAM_PROFILE_START(&pCtl->StatLockWait, a);
1954 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
1955 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
1956 }
1957 return false;
1958 }
1959 memcpy(aATAPICmd, s->aATAPICmd, ATAPI_PACKET_SIZE);
1960 cReqSectors = 0;
1961 for (uint32_t i = cSectors; i > 0; i -= cReqSectors)
1962 {
1963 if (i * s->cbATAPISector > SCSI_MAX_BUFFER_SIZE)
1964 cReqSectors = SCSI_MAX_BUFFER_SIZE / s->cbATAPISector;
1965 else
1966 cReqSectors = i;
1967 cbCurrTX = s->cbATAPISector * cReqSectors;
1968 switch (s->aATAPICmd[0])
1969 {
1970 case SCSI_READ_10:
1971 case SCSI_WRITE_10:
1972 case SCSI_WRITE_AND_VERIFY_10:
1973 ataH2BE_U32(aATAPICmd + 2, iATAPILBA);
1974 ataH2BE_U16(aATAPICmd + 7, cReqSectors);
1975 break;
1976 case SCSI_READ_12:
1977 case SCSI_WRITE_12:
1978 ataH2BE_U32(aATAPICmd + 2, iATAPILBA);
1979 ataH2BE_U32(aATAPICmd + 6, cReqSectors);
1980 break;
1981 case SCSI_READ_CD:
1982 ataH2BE_U32(s->aATAPICmd + 2, iATAPILBA);
1983 ataH2BE_U24(s->aATAPICmd + 6, cbCurrTX);
1984 break;
1985 case SCSI_READ_CD_MSF:
1986 ataLBA2MSF(aATAPICmd + 3, iATAPILBA);
1987 ataLBA2MSF(aATAPICmd + 6, iATAPILBA + cReqSectors);
1988 break;
1989 }
1990 rc = s->pDrvBlock->pfnSendCmd(s->pDrvBlock, aATAPICmd, (PDMBLOCKTXDIR)s->uTxDir, pbBuf, &cbCurrTX, abATAPISense, sizeof(abATAPISense), 30000 /**< @todo timeout */);
1991 if (rc != VINF_SUCCESS)
1992 break;
1993 iATAPILBA += cReqSectors;
1994 pbBuf += s->cbATAPISector * cReqSectors;
1995 }
1996 }
1997 else
1998 rc = s->pDrvBlock->pfnSendCmd(s->pDrvBlock, s->aATAPICmd, (PDMBLOCKTXDIR)s->uTxDir, s->CTX_SUFF(pbIOBuffer), &cbTransfer, abATAPISense, sizeof(abATAPISense), 30000 /**< @todo timeout */);
1999 if (pProf) { STAM_PROFILE_ADV_STOP(pProf, b); }
2000
2001 STAM_PROFILE_START(&pCtl->StatLockWait, a);
2002 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
2003 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
2004
2005 /* Update the LEDs and the read/write statistics. */
2006 if (cbTransfer >= 2048)
2007 {
2008 if (s->uTxDir != PDMBLOCKTXDIR_TO_DEVICE)
2009 {
2010 s->Led.Actual.s.fReading = 0;
2011 STAM_REL_COUNTER_ADD(&s->StatBytesRead, cbTransfer);
2012 }
2013 else
2014 {
2015 s->Led.Actual.s.fWriting = 0;
2016 STAM_REL_COUNTER_ADD(&s->StatBytesWritten, cbTransfer);
2017 }
2018 }
2019
2020 if (RT_SUCCESS(rc))
2021 {
2022 if (s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE)
2023 {
2024 Assert(cbTransfer <= s->cbTotalTransfer);
2025 /* Reply with the same amount of data as the real drive. */
2026 s->cbTotalTransfer = cbTransfer;
2027 /* The initial buffer end value has been set up based on the total
2028 * transfer size. But the I/O buffer size limits what can actually be
2029 * done in one transfer, so set the actual value of the buffer end. */
2030 s->cbElementaryTransfer = cbTransfer;
2031 if (s->aATAPICmd[0] == SCSI_INQUIRY)
2032 {
2033 /* Make sure that the real drive cannot be identified.
2034 * Motivation: changing the VM configuration should be as
2035 * invisible as possible to the guest. */
2036 Log3(("ATAPI PT inquiry data before (%d): %.*Rhxs\n", cbTransfer, cbTransfer, s->CTX_SUFF(pbIOBuffer)));
2037 ataSCSIPadStr(s->CTX_SUFF(pbIOBuffer) + 8, "VBOX", 8);
2038 ataSCSIPadStr(s->CTX_SUFF(pbIOBuffer) + 16, "CD-ROM", 16);
2039 ataSCSIPadStr(s->CTX_SUFF(pbIOBuffer) + 32, "1.0", 4);
2040 }
2041 if (cbTransfer)
2042 Log3(("ATAPI PT data read (%d): %.*Rhxs\n", cbTransfer, cbTransfer, s->CTX_SUFF(pbIOBuffer)));
2043 }
2044 s->iSourceSink = ATAFN_SS_NULL;
2045 atapiCmdOK(s);
2046 }
2047 else
2048 {
2049 if (s->cErrors < MAX_LOG_REL_ERRORS)
2050 {
2051 uint8_t u8Cmd = s->aATAPICmd[0];
2052 do
2053 {
2054 /* don't log superflous errors */
2055 if ( rc == VERR_DEV_IO_ERROR
2056 && ( u8Cmd == SCSI_TEST_UNIT_READY
2057 || u8Cmd == SCSI_READ_CAPACITY
2058 || u8Cmd == SCSI_READ_DVD_STRUCTURE
2059 || u8Cmd == SCSI_READ_TOC_PMA_ATIP))
2060 break;
2061 s->cErrors++;
2062 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM passthrough cmd=%#04x sense=%d ASC=%#02x ASCQ=%#02x %Rrc\n",
2063 s->iLUN, u8Cmd, abATAPISense[2] & 0x0f, abATAPISense[12], abATAPISense[13], rc));
2064 } while (0);
2065 }
2066 atapiCmdError(s, abATAPISense, sizeof(abATAPISense));
2067 }
2068 return false;
2069}
2070
2071/** @todo: Revise ASAP. */
2072static bool atapiReadDVDStructureSS(ATADevState *s)
2073{
2074 uint8_t *buf = s->CTX_SUFF(pbIOBuffer);
2075 int media = s->aATAPICmd[1];
2076 int format = s->aATAPICmd[7];
2077
2078 uint16_t max_len = ataBE2H_U16(&s->aATAPICmd[8]);
2079
2080 memset(buf, 0, max_len);
2081
2082 switch (format) {
2083 case 0x00:
2084 case 0x01:
2085 case 0x02:
2086 case 0x03:
2087 case 0x04:
2088 case 0x05:
2089 case 0x06:
2090 case 0x07:
2091 case 0x08:
2092 case 0x09:
2093 case 0x0a:
2094 case 0x0b:
2095 case 0x0c:
2096 case 0x0d:
2097 case 0x0e:
2098 case 0x0f:
2099 case 0x10:
2100 case 0x11:
2101 case 0x30:
2102 case 0x31:
2103 case 0xff:
2104 if (media == 0)
2105 {
2106 int uASC = SCSI_ASC_NONE;
2107
2108 switch (format)
2109 {
2110 case 0x0: /* Physical format information */
2111 {
2112 int layer = s->aATAPICmd[6];
2113 uint64_t total_sectors;
2114
2115 if (layer != 0)
2116 {
2117 uASC = -SCSI_ASC_INV_FIELD_IN_CMD_PACKET;
2118 break;
2119 }
2120
2121 total_sectors = s->cTotalSectors;
2122 total_sectors >>= 2;
2123 if (total_sectors == 0)
2124 {
2125 uASC = -SCSI_ASC_MEDIUM_NOT_PRESENT;
2126 break;
2127 }
2128
2129 buf[4] = 1; /* DVD-ROM, part version 1 */
2130 buf[5] = 0xf; /* 120mm disc, minimum rate unspecified */
2131 buf[6] = 1; /* one layer, read-only (per MMC-2 spec) */
2132 buf[7] = 0; /* default densities */
2133
2134 /* FIXME: 0x30000 per spec? */
2135 ataH2BE_U32(buf + 8, 0); /* start sector */
2136 ataH2BE_U32(buf + 12, total_sectors - 1); /* end sector */
2137 ataH2BE_U32(buf + 16, total_sectors - 1); /* l0 end sector */
2138
2139 /* Size of buffer, not including 2 byte size field */
2140 ataH2BE_U32(&buf[0], 2048 + 2);
2141
2142 /* 2k data + 4 byte header */
2143 uASC = (2048 + 4);
2144 }
2145 break;
2146 case 0x01: /* DVD copyright information */
2147 buf[4] = 0; /* no copyright data */
2148 buf[5] = 0; /* no region restrictions */
2149
2150 /* Size of buffer, not including 2 byte size field */
2151 ataH2BE_U16(buf, 4 + 2);
2152
2153 /* 4 byte header + 4 byte data */
2154 uASC = (4 + 4);
2155
2156 case 0x03: /* BCA information - invalid field for no BCA info */
2157 uASC = -SCSI_ASC_INV_FIELD_IN_CMD_PACKET;
2158 break;
2159
2160 case 0x04: /* DVD disc manufacturing information */
2161 /* Size of buffer, not including 2 byte size field */
2162 ataH2BE_U16(buf, 2048 + 2);
2163
2164 /* 2k data + 4 byte header */
2165 uASC = (2048 + 4);
2166 break;
2167 case 0xff:
2168 /*
2169 * This lists all the command capabilities above. Add new ones
2170 * in order and update the length and buffer return values.
2171 */
2172
2173 buf[4] = 0x00; /* Physical format */
2174 buf[5] = 0x40; /* Not writable, is readable */
2175 ataH2BE_U16((buf + 6), 2048 + 4);
2176
2177 buf[8] = 0x01; /* Copyright info */
2178 buf[9] = 0x40; /* Not writable, is readable */
2179 ataH2BE_U16((buf + 10), 4 + 4);
2180
2181 buf[12] = 0x03; /* BCA info */
2182 buf[13] = 0x40; /* Not writable, is readable */
2183 ataH2BE_U16((buf + 14), 188 + 4);
2184
2185 buf[16] = 0x04; /* Manufacturing info */
2186 buf[17] = 0x40; /* Not writable, is readable */
2187 ataH2BE_U16((buf + 18), 2048 + 4);
2188
2189 /* Size of buffer, not including 2 byte size field */
2190 ataH2BE_U16(buf, 16 + 2);
2191
2192 /* data written + 4 byte header */
2193 uASC = (16 + 4);
2194 break;
2195 default: /* TODO: formats beyond DVD-ROM requires */
2196 uASC = -SCSI_ASC_INV_FIELD_IN_CMD_PACKET;
2197 }
2198
2199 if (uASC < 0)
2200 {
2201 s->iSourceSink = ATAFN_SS_NULL;
2202 atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, -uASC);
2203 return false;
2204 }
2205 break;
2206 }
2207 /* TODO: BD support, fall through for now */
2208
2209 /* Generic disk structures */
2210 case 0x80: /* TODO: AACS volume identifier */
2211 case 0x81: /* TODO: AACS media serial number */
2212 case 0x82: /* TODO: AACS media identifier */
2213 case 0x83: /* TODO: AACS media key block */
2214 case 0x90: /* TODO: List of recognized format layers */
2215 case 0xc0: /* TODO: Write protection status */
2216 default:
2217 s->iSourceSink = ATAFN_SS_NULL;
2218 atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST,
2219 SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
2220 return false;
2221 }
2222
2223 s->iSourceSink = ATAFN_SS_NULL;
2224 atapiCmdOK(s);
2225 return false;
2226}
2227
2228static bool atapiReadSectors(ATADevState *s, uint32_t iATAPILBA, uint32_t cSectors, uint32_t cbSector)
2229{
2230 Assert(cSectors > 0);
2231 s->iATAPILBA = iATAPILBA;
2232 s->cbATAPISector = cbSector;
2233 ataStartTransfer(s, cSectors * cbSector, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ, true);
2234 return false;
2235}
2236
2237
2238static bool atapiReadCapacitySS(ATADevState *s)
2239{
2240 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
2241
2242 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
2243 Assert(s->cbElementaryTransfer <= 8);
2244 ataH2BE_U32(pbBuf, s->cTotalSectors - 1);
2245 ataH2BE_U32(pbBuf + 4, 2048);
2246 s->iSourceSink = ATAFN_SS_NULL;
2247 atapiCmdOK(s);
2248 return false;
2249}
2250
2251
2252static bool atapiReadDiscInformationSS(ATADevState *s)
2253{
2254 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
2255
2256 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
2257 Assert(s->cbElementaryTransfer <= 34);
2258 memset(pbBuf, '\0', 34);
2259 ataH2BE_U16(pbBuf, 32);
2260 pbBuf[2] = (0 << 4) | (3 << 2) | (2 << 0); /* not erasable, complete session, complete disc */
2261 pbBuf[3] = 1; /* number of first track */
2262 pbBuf[4] = 1; /* number of sessions (LSB) */
2263 pbBuf[5] = 1; /* first track number in last session (LSB) */
2264 pbBuf[6] = 1; /* last track number in last session (LSB) */
2265 pbBuf[7] = (0 << 7) | (0 << 6) | (1 << 5) | (0 << 2) | (0 << 0); /* disc id not valid, disc bar code not valid, unrestricted use, not dirty, not RW medium */
2266 pbBuf[8] = 0; /* disc type = CD-ROM */
2267 pbBuf[9] = 0; /* number of sessions (MSB) */
2268 pbBuf[10] = 0; /* number of sessions (MSB) */
2269 pbBuf[11] = 0; /* number of sessions (MSB) */
2270 ataH2BE_U32(pbBuf + 16, 0x00ffffff); /* last session lead-in start time is not available */
2271 ataH2BE_U32(pbBuf + 20, 0x00ffffff); /* last possible start time for lead-out is not available */
2272 s->iSourceSink = ATAFN_SS_NULL;
2273 atapiCmdOK(s);
2274 return false;
2275}
2276
2277
2278static bool atapiReadTrackInformationSS(ATADevState *s)
2279{
2280 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
2281
2282 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
2283 Assert(s->cbElementaryTransfer <= 36);
2284 /* Accept address/number type of 1 only, and only track 1 exists. */
2285 if ((s->aATAPICmd[1] & 0x03) != 1 || ataBE2H_U32(&s->aATAPICmd[2]) != 1)
2286 {
2287 atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
2288 return false;
2289 }
2290 memset(pbBuf, '\0', 36);
2291 ataH2BE_U16(pbBuf, 34);
2292 pbBuf[2] = 1; /* track number (LSB) */
2293 pbBuf[3] = 1; /* session number (LSB) */
2294 pbBuf[5] = (0 << 5) | (0 << 4) | (4 << 0); /* not damaged, primary copy, data track */
2295 pbBuf[6] = (0 << 7) | (0 << 6) | (0 << 5) | (0 << 6) | (1 << 0); /* not reserved track, not blank, not packet writing, not fixed packet, data mode 1 */
2296 pbBuf[7] = (0 << 1) | (0 << 0); /* last recorded address not valid, next recordable address not valid */
2297 ataH2BE_U32(pbBuf + 8, 0); /* track start address is 0 */
2298 ataH2BE_U32(pbBuf + 24, s->cTotalSectors); /* track size */
2299 pbBuf[32] = 0; /* track number (MSB) */
2300 pbBuf[33] = 0; /* session number (MSB) */
2301 s->iSourceSink = ATAFN_SS_NULL;
2302 atapiCmdOK(s);
2303 return false;
2304}
2305
2306
2307static bool atapiGetConfigurationSS(ATADevState *s)
2308{
2309 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
2310 uint16_t u16Sfn = ataBE2H_U16(&s->aATAPICmd[2]);
2311
2312 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
2313 Assert(s->cbElementaryTransfer <= 32);
2314 /* Accept valid request types only, and only starting feature 0. */
2315 if ((s->aATAPICmd[1] & 0x03) == 3 || u16Sfn != 0)
2316 {
2317 atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
2318 return false;
2319 }
2320 memset(pbBuf, '\0', 32);
2321 ataH2BE_U32(pbBuf, 16);
2322 /** @todo implement switching between CD-ROM and DVD-ROM profile (the only
2323 * way to differentiate them right now is based on the image size). Also
2324 * implement signalling "no current profile" if no medium is loaded. */
2325 ataH2BE_U16(pbBuf + 6, 0x08); /* current profile: read-only CD */
2326
2327 ataH2BE_U16(pbBuf + 8, 0); /* feature 0: list of profiles supported */
2328 pbBuf[10] = (0 << 2) | (1 << 1) | (1 || 0); /* version 0, persistent, current */
2329 pbBuf[11] = 8; /* additional bytes for profiles */
2330 /* The MMC-3 spec says that DVD-ROM read capability should be reported
2331 * before CD-ROM read capability. */
2332 ataH2BE_U16(pbBuf + 12, 0x10); /* profile: read-only DVD */
2333 pbBuf[14] = (0 << 0); /* NOT current profile */
2334 ataH2BE_U16(pbBuf + 16, 0x08); /* profile: read only CD */
2335 pbBuf[18] = (1 << 0); /* current profile */
2336 /* Other profiles we might want to add in the future: 0x40 (BD-ROM) and 0x50 (HDDVD-ROM) */
2337 s->iSourceSink = ATAFN_SS_NULL;
2338 atapiCmdOK(s);
2339 return false;
2340}
2341
2342
2343static bool atapiGetEventStatusNotificationSS(ATADevState *s)
2344{
2345 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
2346
2347 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
2348 Assert(s->cbElementaryTransfer <= 8);
2349
2350 if (!(s->aATAPICmd[1] & 1))
2351 {
2352 /* no asynchronous operation supported */
2353 atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
2354 return false;
2355 }
2356
2357 uint32_t OldStatus, NewStatus;
2358 do
2359 {
2360 OldStatus = ASMAtomicReadU32(&s->MediaEventStatus);
2361 NewStatus = ATA_EVENT_STATUS_UNCHANGED;
2362 switch (OldStatus)
2363 {
2364 case ATA_EVENT_STATUS_MEDIA_NEW:
2365 /* mount */
2366 ataH2BE_U16(pbBuf + 0, 6);
2367 pbBuf[2] = 0x04;
2368 pbBuf[3] = 0x5e;
2369 pbBuf[4] = 0x02;
2370 pbBuf[5] = 0x02;
2371 pbBuf[6] = 0x00;
2372 pbBuf[7] = 0x00;
2373 break;
2374
2375 case ATA_EVENT_STATUS_MEDIA_CHANGED:
2376 case ATA_EVENT_STATUS_MEDIA_REMOVED:
2377 /* umount */
2378 ataH2BE_U16(pbBuf + 0, 6);
2379 pbBuf[2] = 0x04;
2380 pbBuf[3] = 0x5e;
2381 pbBuf[4] = 0x03;
2382 pbBuf[5] = 0x00;
2383 pbBuf[6] = 0x00;
2384 pbBuf[7] = 0x00;
2385 if (OldStatus == ATA_EVENT_STATUS_MEDIA_CHANGED)
2386 NewStatus = ATA_EVENT_STATUS_MEDIA_NEW;
2387 break;
2388
2389 case ATA_EVENT_STATUS_UNCHANGED:
2390 default:
2391 ataH2BE_U16(pbBuf + 0, 6);
2392 pbBuf[2] = 0x01;
2393 pbBuf[3] = 0x5e;
2394 pbBuf[4] = 0x00;
2395 pbBuf[5] = 0x00;
2396 pbBuf[6] = 0x00;
2397 pbBuf[7] = 0x00;
2398 break;
2399 }
2400 } while (!ASMAtomicCmpXchgU32(&s->MediaEventStatus, NewStatus, OldStatus));
2401
2402 s->iSourceSink = ATAFN_SS_NULL;
2403 atapiCmdOK(s);
2404 return false;
2405}
2406
2407
2408static bool atapiInquirySS(ATADevState *s)
2409{
2410 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
2411
2412 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
2413 Assert(s->cbElementaryTransfer <= 36);
2414 pbBuf[0] = 0x05; /* CD-ROM */
2415 pbBuf[1] = 0x80; /* removable */
2416#if 1/*ndef VBOX*/ /** @todo implement MESN + AENC. (async notification on removal and stuff.) */
2417 pbBuf[2] = 0x00; /* ISO */
2418 pbBuf[3] = 0x21; /* ATAPI-2 (XXX: put ATAPI-4 ?) */
2419#else
2420 pbBuf[2] = 0x00; /* ISO */
2421 pbBuf[3] = 0x91; /* format 1, MESN=1, AENC=9 ??? */
2422#endif
2423 pbBuf[4] = 31; /* additional length */
2424 pbBuf[5] = 0; /* reserved */
2425 pbBuf[6] = 0; /* reserved */
2426 pbBuf[7] = 0; /* reserved */
2427 ataSCSIPadStr(pbBuf + 8, s->szInquiryVendorId, 8);
2428 ataSCSIPadStr(pbBuf + 16, s->szInquiryProductId, 16);
2429 ataSCSIPadStr(pbBuf + 32, s->szInquiryRevision, 4);
2430 s->iSourceSink = ATAFN_SS_NULL;
2431 atapiCmdOK(s);
2432 return false;
2433}
2434
2435
2436static bool atapiModeSenseErrorRecoverySS(ATADevState *s)
2437{
2438 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
2439
2440 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
2441 Assert(s->cbElementaryTransfer <= 16);
2442 ataH2BE_U16(&pbBuf[0], 16 + 6);
2443 pbBuf[2] = 0x70;
2444 pbBuf[3] = 0;
2445 pbBuf[4] = 0;
2446 pbBuf[5] = 0;
2447 pbBuf[6] = 0;
2448 pbBuf[7] = 0;
2449
2450 pbBuf[8] = 0x01;
2451 pbBuf[9] = 0x06;
2452 pbBuf[10] = 0x00;
2453 pbBuf[11] = 0x05;
2454 pbBuf[12] = 0x00;
2455 pbBuf[13] = 0x00;
2456 pbBuf[14] = 0x00;
2457 pbBuf[15] = 0x00;
2458 s->iSourceSink = ATAFN_SS_NULL;
2459 atapiCmdOK(s);
2460 return false;
2461}
2462
2463
2464static bool atapiModeSenseCDStatusSS(ATADevState *s)
2465{
2466 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
2467
2468 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
2469 Assert(s->cbElementaryTransfer <= 40);
2470 ataH2BE_U16(&pbBuf[0], 38);
2471 pbBuf[2] = 0x70;
2472 pbBuf[3] = 0;
2473 pbBuf[4] = 0;
2474 pbBuf[5] = 0;
2475 pbBuf[6] = 0;
2476 pbBuf[7] = 0;
2477
2478 pbBuf[8] = 0x2a;
2479 pbBuf[9] = 30; /* page length */
2480 pbBuf[10] = 0x08; /* DVD-ROM read support */
2481 pbBuf[11] = 0x00; /* no write support */
2482 /* The following claims we support audio play. This is obviously false,
2483 * but the Linux generic CDROM support makes many features depend on this
2484 * capability. If it's not set, this causes many things to be disabled. */
2485 pbBuf[12] = 0x71; /* multisession support, mode 2 form 1/2 support, audio play */
2486 pbBuf[13] = 0x00; /* no subchannel reads supported */
2487 pbBuf[14] = (1 << 0) | (1 << 3) | (1 << 5); /* lock supported, eject supported, tray type loading mechanism */
2488 if (s->pDrvMount->pfnIsLocked(s->pDrvMount))
2489 pbBuf[14] |= 1 << 1; /* report lock state */
2490 pbBuf[15] = 0; /* no subchannel reads supported, no separate audio volume control, no changer etc. */
2491 ataH2BE_U16(&pbBuf[16], 5632); /* (obsolete) claim 32x speed support */
2492 ataH2BE_U16(&pbBuf[18], 2); /* number of audio volume levels */
2493 ataH2BE_U16(&pbBuf[20], s->cbIOBuffer / _1K); /* buffer size supported in Kbyte */
2494 ataH2BE_U16(&pbBuf[22], 5632); /* (obsolete) current read speed 32x */
2495 pbBuf[24] = 0; /* reserved */
2496 pbBuf[25] = 0; /* reserved for digital audio (see idx 15) */
2497 ataH2BE_U16(&pbBuf[26], 0); /* (obsolete) maximum write speed */
2498 ataH2BE_U16(&pbBuf[28], 0); /* (obsolete) current write speed */
2499 ataH2BE_U16(&pbBuf[30], 0); /* copy management revision supported 0=no CSS */
2500 pbBuf[32] = 0; /* reserved */
2501 pbBuf[33] = 0; /* reserved */
2502 pbBuf[34] = 0; /* reserved */
2503 pbBuf[35] = 1; /* rotation control CAV */
2504 ataH2BE_U16(&pbBuf[36], 0); /* current write speed */
2505 ataH2BE_U16(&pbBuf[38], 0); /* number of write speed performance descriptors */
2506 s->iSourceSink = ATAFN_SS_NULL;
2507 atapiCmdOK(s);
2508 return false;
2509}
2510
2511
2512static bool atapiRequestSenseSS(ATADevState *s)
2513{
2514 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
2515
2516 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
2517 memset(pbBuf, '\0', s->cbElementaryTransfer);
2518 memcpy(pbBuf, s->abATAPISense, RT_MIN(s->cbElementaryTransfer, sizeof(s->abATAPISense)));
2519 s->iSourceSink = ATAFN_SS_NULL;
2520 atapiCmdOK(s);
2521 return false;
2522}
2523
2524
2525static bool atapiMechanismStatusSS(ATADevState *s)
2526{
2527 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
2528
2529 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
2530 Assert(s->cbElementaryTransfer <= 8);
2531 ataH2BE_U16(pbBuf, 0);
2532 /* no current LBA */
2533 pbBuf[2] = 0;
2534 pbBuf[3] = 0;
2535 pbBuf[4] = 0;
2536 pbBuf[5] = 1;
2537 ataH2BE_U16(pbBuf + 6, 0);
2538 s->iSourceSink = ATAFN_SS_NULL;
2539 atapiCmdOK(s);
2540 return false;
2541}
2542
2543
2544static bool atapiReadTOCNormalSS(ATADevState *s)
2545{
2546 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer), *q, iStartTrack;
2547 bool fMSF;
2548 uint32_t cbSize;
2549
2550 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
2551 fMSF = (s->aATAPICmd[1] >> 1) & 1;
2552 iStartTrack = s->aATAPICmd[6];
2553 if (iStartTrack > 1 && iStartTrack != 0xaa)
2554 {
2555 atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
2556 return false;
2557 }
2558 q = pbBuf + 2;
2559 *q++ = 1; /* first session */
2560 *q++ = 1; /* last session */
2561 if (iStartTrack <= 1)
2562 {
2563 *q++ = 0; /* reserved */
2564 *q++ = 0x14; /* ADR, control */
2565 *q++ = 1; /* track number */
2566 *q++ = 0; /* reserved */
2567 if (fMSF)
2568 {
2569 *q++ = 0; /* reserved */
2570 ataLBA2MSF(q, 0);
2571 q += 3;
2572 }
2573 else
2574 {
2575 /* sector 0 */
2576 ataH2BE_U32(q, 0);
2577 q += 4;
2578 }
2579 }
2580 /* lead out track */
2581 *q++ = 0; /* reserved */
2582 *q++ = 0x14; /* ADR, control */
2583 *q++ = 0xaa; /* track number */
2584 *q++ = 0; /* reserved */
2585 if (fMSF)
2586 {
2587 *q++ = 0; /* reserved */
2588 ataLBA2MSF(q, s->cTotalSectors);
2589 q += 3;
2590 }
2591 else
2592 {
2593 ataH2BE_U32(q, s->cTotalSectors);
2594 q += 4;
2595 }
2596 cbSize = q - pbBuf;
2597 ataH2BE_U16(pbBuf, cbSize - 2);
2598 if (cbSize < s->cbTotalTransfer)
2599 s->cbTotalTransfer = cbSize;
2600 s->iSourceSink = ATAFN_SS_NULL;
2601 atapiCmdOK(s);
2602 return false;
2603}
2604
2605
2606static bool atapiReadTOCMultiSS(ATADevState *s)
2607{
2608 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
2609 bool fMSF;
2610
2611 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
2612 Assert(s->cbElementaryTransfer <= 12);
2613 fMSF = (s->aATAPICmd[1] >> 1) & 1;
2614 /* multi session: only a single session defined */
2615/** @todo double-check this stuff against what a real drive says for a CD-ROM (not a CD-R) with only a single data session. Maybe solve the problem with "cdrdao read-toc" not being able to figure out whether numbers are in BCD or hex. */
2616 memset(pbBuf, 0, 12);
2617 pbBuf[1] = 0x0a;
2618 pbBuf[2] = 0x01;
2619 pbBuf[3] = 0x01;
2620 pbBuf[5] = 0x14; /* ADR, control */
2621 pbBuf[6] = 1; /* first track in last complete session */
2622 if (fMSF)
2623 {
2624 pbBuf[8] = 0; /* reserved */
2625 ataLBA2MSF(&pbBuf[9], 0);
2626 }
2627 else
2628 {
2629 /* sector 0 */
2630 ataH2BE_U32(pbBuf + 8, 0);
2631 }
2632 s->iSourceSink = ATAFN_SS_NULL;
2633 atapiCmdOK(s);
2634 return false;
2635}
2636
2637
2638static bool atapiReadTOCRawSS(ATADevState *s)
2639{
2640 uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer), *q, iStartTrack;
2641 bool fMSF;
2642 uint32_t cbSize;
2643
2644 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
2645 fMSF = (s->aATAPICmd[1] >> 1) & 1;
2646 iStartTrack = s->aATAPICmd[6];
2647
2648 q = pbBuf + 2;
2649 *q++ = 1; /* first session */
2650 *q++ = 1; /* last session */
2651
2652 *q++ = 1; /* session number */
2653 *q++ = 0x14; /* data track */
2654 *q++ = 0; /* track number */
2655 *q++ = 0xa0; /* first track in program area */
2656 *q++ = 0; /* min */
2657 *q++ = 0; /* sec */
2658 *q++ = 0; /* frame */
2659 *q++ = 0;
2660 *q++ = 1; /* first track */
2661 *q++ = 0x00; /* disk type CD-DA or CD data */
2662 *q++ = 0;
2663
2664 *q++ = 1; /* session number */
2665 *q++ = 0x14; /* data track */
2666 *q++ = 0; /* track number */
2667 *q++ = 0xa1; /* last track in program area */
2668 *q++ = 0; /* min */
2669 *q++ = 0; /* sec */
2670 *q++ = 0; /* frame */
2671 *q++ = 0;
2672 *q++ = 1; /* last track */
2673 *q++ = 0;
2674 *q++ = 0;
2675
2676 *q++ = 1; /* session number */
2677 *q++ = 0x14; /* data track */
2678 *q++ = 0; /* track number */
2679 *q++ = 0xa2; /* lead-out */
2680 *q++ = 0; /* min */
2681 *q++ = 0; /* sec */
2682 *q++ = 0; /* frame */
2683 if (fMSF)
2684 {
2685 *q++ = 0; /* reserved */
2686 ataLBA2MSF(q, s->cTotalSectors);
2687 q += 3;
2688 }
2689 else
2690 {
2691 ataH2BE_U32(q, s->cTotalSectors);
2692 q += 4;
2693 }
2694
2695 *q++ = 1; /* session number */
2696 *q++ = 0x14; /* ADR, control */
2697 *q++ = 0; /* track number */
2698 *q++ = 1; /* point */
2699 *q++ = 0; /* min */
2700 *q++ = 0; /* sec */
2701 *q++ = 0; /* frame */
2702 if (fMSF)
2703 {
2704 *q++ = 0; /* reserved */
2705 ataLBA2MSF(q, 0);
2706 q += 3;
2707 }
2708 else
2709 {
2710 /* sector 0 */
2711 ataH2BE_U32(q, 0);
2712 q += 4;
2713 }
2714
2715 cbSize = q - pbBuf;
2716 ataH2BE_U16(pbBuf, cbSize - 2);
2717 if (cbSize < s->cbTotalTransfer)
2718 s->cbTotalTransfer = cbSize;
2719 s->iSourceSink = ATAFN_SS_NULL;
2720 atapiCmdOK(s);
2721 return false;
2722}
2723
2724
2725static void atapiParseCmdVirtualATAPI(ATADevState *s)
2726{
2727 const uint8_t *pbPacket;
2728 uint8_t *pbBuf;
2729 uint32_t cbMax;
2730
2731 pbPacket = s->aATAPICmd;
2732 pbBuf = s->CTX_SUFF(pbIOBuffer);
2733 switch (pbPacket[0])
2734 {
2735 case SCSI_TEST_UNIT_READY:
2736 if (s->cNotifiedMediaChange > 0)
2737 {
2738 if (s->cNotifiedMediaChange-- > 2)
2739 atapiCmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
2740 else
2741 atapiCmdErrorSimple(s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
2742 }
2743 else if (s->pDrvMount->pfnIsMounted(s->pDrvMount))
2744 atapiCmdOK(s);
2745 else
2746 atapiCmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
2747 break;
2748 case SCSI_GET_EVENT_STATUS_NOTIFICATION:
2749 cbMax = ataBE2H_U16(pbPacket + 7);
2750 ataStartTransfer(s, RT_MIN(cbMax, 8), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_GET_EVENT_STATUS_NOTIFICATION, true);
2751 break;
2752 case SCSI_MODE_SENSE_10:
2753 {
2754 uint8_t uPageControl, uPageCode;
2755 cbMax = ataBE2H_U16(pbPacket + 7);
2756 uPageControl = pbPacket[2] >> 6;
2757 uPageCode = pbPacket[2] & 0x3f;
2758 switch (uPageControl)
2759 {
2760 case SCSI_PAGECONTROL_CURRENT:
2761 switch (uPageCode)
2762 {
2763 case SCSI_MODEPAGE_ERROR_RECOVERY:
2764 ataStartTransfer(s, RT_MIN(cbMax, 16), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_MODE_SENSE_ERROR_RECOVERY, true);
2765 break;
2766 case SCSI_MODEPAGE_CD_STATUS:
2767 ataStartTransfer(s, RT_MIN(cbMax, 40), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_MODE_SENSE_CD_STATUS, true);
2768 break;
2769 default:
2770 goto error_cmd;
2771 }
2772 break;
2773 case SCSI_PAGECONTROL_CHANGEABLE:
2774 goto error_cmd;
2775 case SCSI_PAGECONTROL_DEFAULT:
2776 goto error_cmd;
2777 default:
2778 case SCSI_PAGECONTROL_SAVED:
2779 atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_SAVING_PARAMETERS_NOT_SUPPORTED);
2780 break;
2781 }
2782 }
2783 break;
2784 case SCSI_REQUEST_SENSE:
2785 cbMax = pbPacket[4];
2786 ataStartTransfer(s, RT_MIN(cbMax, 18), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_REQUEST_SENSE, true);
2787 break;
2788 case SCSI_PREVENT_ALLOW_MEDIUM_REMOVAL:
2789 if (s->pDrvMount->pfnIsMounted(s->pDrvMount))
2790 {
2791 if (pbPacket[4] & 1)
2792 s->pDrvMount->pfnLock(s->pDrvMount);
2793 else
2794 s->pDrvMount->pfnUnlock(s->pDrvMount);
2795 atapiCmdOK(s);
2796 }
2797 else
2798 atapiCmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
2799 break;
2800 case SCSI_READ_10:
2801 case SCSI_READ_12:
2802 {
2803 uint32_t cSectors, iATAPILBA;
2804
2805 if (s->cNotifiedMediaChange > 0)
2806 {
2807 s->cNotifiedMediaChange-- ;
2808 atapiCmdErrorSimple(s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
2809 break;
2810 }
2811 else if (!s->pDrvMount->pfnIsMounted(s->pDrvMount))
2812 {
2813 atapiCmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
2814 break;
2815 }
2816 if (pbPacket[0] == SCSI_READ_10)
2817 cSectors = ataBE2H_U16(pbPacket + 7);
2818 else
2819 cSectors = ataBE2H_U32(pbPacket + 6);
2820 iATAPILBA = ataBE2H_U32(pbPacket + 2);
2821 if (cSectors == 0)
2822 {
2823 atapiCmdOK(s);
2824 break;
2825 }
2826 if ((uint64_t)iATAPILBA + cSectors > s->cTotalSectors)
2827 {
2828 /* Rate limited logging, one log line per second. For
2829 * guests that insist on reading from places outside the
2830 * valid area this often generates too many release log
2831 * entries otherwise. */
2832 static uint64_t uLastLogTS = 0;
2833 if (RTTimeMilliTS() >= uLastLogTS + 1000)
2834 {
2835 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM block number %Ld invalid (READ)\n", s->iLUN, (uint64_t)iATAPILBA + cSectors));
2836 uLastLogTS = RTTimeMilliTS();
2837 }
2838 atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR);
2839 break;
2840 }
2841 atapiReadSectors(s, iATAPILBA, cSectors, 2048);
2842 }
2843 break;
2844 case SCSI_READ_CD:
2845 {
2846 uint32_t cSectors, iATAPILBA;
2847
2848 if (s->cNotifiedMediaChange > 0)
2849 {
2850 s->cNotifiedMediaChange-- ;
2851 atapiCmdErrorSimple(s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
2852 break;
2853 }
2854 else if (!s->pDrvMount->pfnIsMounted(s->pDrvMount))
2855 {
2856 atapiCmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
2857 break;
2858 }
2859 cSectors = (pbPacket[6] << 16) | (pbPacket[7] << 8) | pbPacket[8];
2860 iATAPILBA = ataBE2H_U32(pbPacket + 2);
2861 if (cSectors == 0)
2862 {
2863 atapiCmdOK(s);
2864 break;
2865 }
2866 if ((uint64_t)iATAPILBA + cSectors > s->cTotalSectors)
2867 {
2868 /* Rate limited logging, one log line per second. For
2869 * guests that insist on reading from places outside the
2870 * valid area this often generates too many release log
2871 * entries otherwise. */
2872 static uint64_t uLastLogTS = 0;
2873 if (RTTimeMilliTS() >= uLastLogTS + 1000)
2874 {
2875 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM block number %Ld invalid (READ CD)\n", s->iLUN, (uint64_t)iATAPILBA + cSectors));
2876 uLastLogTS = RTTimeMilliTS();
2877 }
2878 atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR);
2879 break;
2880 }
2881 switch (pbPacket[9] & 0xf8)
2882 {
2883 case 0x00:
2884 /* nothing */
2885 atapiCmdOK(s);
2886 break;
2887 case 0x10:
2888 /* normal read */
2889 atapiReadSectors(s, iATAPILBA, cSectors, 2048);
2890 break;
2891 case 0xf8:
2892 /* read all data */
2893 atapiReadSectors(s, iATAPILBA, cSectors, 2352);
2894 break;
2895 default:
2896 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM sector format not supported (%#x)\n", s->iLUN, pbPacket[9] & 0xf8));
2897 atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
2898 break;
2899 }
2900 }
2901 break;
2902 case SCSI_SEEK_10:
2903 {
2904 uint32_t iATAPILBA;
2905 if (s->cNotifiedMediaChange > 0)
2906 {
2907 s->cNotifiedMediaChange-- ;
2908 atapiCmdErrorSimple(s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
2909 break;
2910 }
2911 else if (!s->pDrvMount->pfnIsMounted(s->pDrvMount))
2912 {
2913 atapiCmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
2914 break;
2915 }
2916 iATAPILBA = ataBE2H_U32(pbPacket + 2);
2917 if (iATAPILBA > s->cTotalSectors)
2918 {
2919 /* Rate limited logging, one log line per second. For
2920 * guests that insist on seeking to places outside the
2921 * valid area this often generates too many release log
2922 * entries otherwise. */
2923 static uint64_t uLastLogTS = 0;
2924 if (RTTimeMilliTS() >= uLastLogTS + 1000)
2925 {
2926 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM block number %Ld invalid (SEEK)\n", s->iLUN, (uint64_t)iATAPILBA));
2927 uLastLogTS = RTTimeMilliTS();
2928 }
2929 atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR);
2930 break;
2931 }
2932 atapiCmdOK(s);
2933 ataSetStatus(s, ATA_STAT_SEEK); /* Linux expects this. */
2934 }
2935 break;
2936 case SCSI_START_STOP_UNIT:
2937 {
2938 int rc = VINF_SUCCESS;
2939 switch (pbPacket[4] & 3)
2940 {
2941 case 0: /* 00 - Stop motor */
2942 case 1: /* 01 - Start motor */
2943 break;
2944 case 2: /* 10 - Eject media */
2945 /* This must be done from EMT. */
2946 {
2947 PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
2948 PPDMDEVINS pDevIns = ATADEVSTATE_2_DEVINS(s);
2949
2950 PDMCritSectLeave(&pCtl->lock);
2951 rc = VMR3ReqCallWait(PDMDevHlpGetVM(pDevIns), VMCPUID_ANY,
2952 (PFNRT)s->pDrvMount->pfnUnmount, 2, s->pDrvMount, false);
2953 Assert(RT_SUCCESS(rc) || (rc == VERR_PDM_MEDIA_LOCKED));
2954 {
2955 STAM_PROFILE_START(&pCtl->StatLockWait, a);
2956 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
2957 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
2958 }
2959 }
2960 break;
2961 case 3: /* 11 - Load media */
2962 /** @todo rc = s->pDrvMount->pfnLoadMedia(s->pDrvMount) */
2963 break;
2964 }
2965 if (RT_SUCCESS(rc))
2966 atapiCmdOK(s);
2967 else
2968 atapiCmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIA_LOAD_OR_EJECT_FAILED);
2969 }
2970 break;
2971 case SCSI_MECHANISM_STATUS:
2972 {
2973 cbMax = ataBE2H_U16(pbPacket + 8);
2974 ataStartTransfer(s, RT_MIN(cbMax, 8), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_MECHANISM_STATUS, true);
2975 }
2976 break;
2977 case SCSI_READ_TOC_PMA_ATIP:
2978 {
2979 uint8_t format;
2980
2981 if (s->cNotifiedMediaChange > 0)
2982 {
2983 s->cNotifiedMediaChange-- ;
2984 atapiCmdErrorSimple(s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
2985 break;
2986 }
2987 else if (!s->pDrvMount->pfnIsMounted(s->pDrvMount))
2988 {
2989 atapiCmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
2990 break;
2991 }
2992 cbMax = ataBE2H_U16(pbPacket + 7);
2993 /* SCSI MMC-3 spec says format is at offset 2 (lower 4 bits),
2994 * but Linux kernel uses offset 9 (topmost 2 bits). Hope that
2995 * the other field is clear... */
2996 format = (pbPacket[2] & 0xf) | (pbPacket[9] >> 6);
2997 switch (format)
2998 {
2999 case 0:
3000 ataStartTransfer(s, cbMax, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_TOC_NORMAL, true);
3001 break;
3002 case 1:
3003 ataStartTransfer(s, RT_MIN(cbMax, 12), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_TOC_MULTI, true);
3004 break;
3005 case 2:
3006 ataStartTransfer(s, cbMax, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_TOC_RAW, true);
3007 break;
3008 default:
3009 error_cmd:
3010 atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
3011 break;
3012 }
3013 }
3014 break;
3015 case SCSI_READ_CAPACITY:
3016 if (s->cNotifiedMediaChange > 0)
3017 {
3018 s->cNotifiedMediaChange-- ;
3019 atapiCmdErrorSimple(s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3020 break;
3021 }
3022 else if (!s->pDrvMount->pfnIsMounted(s->pDrvMount))
3023 {
3024 atapiCmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3025 break;
3026 }
3027 ataStartTransfer(s, 8, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_CAPACITY, true);
3028 break;
3029 case SCSI_READ_DISC_INFORMATION:
3030 if (s->cNotifiedMediaChange > 0)
3031 {
3032 s->cNotifiedMediaChange-- ;
3033 atapiCmdErrorSimple(s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3034 break;
3035 }
3036 else if (!s->pDrvMount->pfnIsMounted(s->pDrvMount))
3037 {
3038 atapiCmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3039 break;
3040 }
3041 cbMax = ataBE2H_U16(pbPacket + 7);
3042 ataStartTransfer(s, RT_MIN(cbMax, 34), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_DISC_INFORMATION, true);
3043 break;
3044 case SCSI_READ_TRACK_INFORMATION:
3045 if (s->cNotifiedMediaChange > 0)
3046 {
3047 s->cNotifiedMediaChange-- ;
3048 atapiCmdErrorSimple(s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
3049 break;
3050 }
3051 else if (!s->pDrvMount->pfnIsMounted(s->pDrvMount))
3052 {
3053 atapiCmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
3054 break;
3055 }
3056 cbMax = ataBE2H_U16(pbPacket + 7);
3057 ataStartTransfer(s, RT_MIN(cbMax, 36), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_TRACK_INFORMATION, true);
3058 break;
3059 case SCSI_GET_CONFIGURATION:
3060 /* No media change stuff here, it can confuse Linux guests. */
3061 cbMax = ataBE2H_U16(pbPacket + 7);
3062 ataStartTransfer(s, RT_MIN(cbMax, 32), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_GET_CONFIGURATION, true);
3063 break;
3064 case SCSI_INQUIRY:
3065 cbMax = ataBE2H_U16(pbPacket + 3);
3066 ataStartTransfer(s, RT_MIN(cbMax, 36), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_INQUIRY, true);
3067 break;
3068 case SCSI_READ_DVD_STRUCTURE:
3069 {
3070 cbMax = ataBE2H_U16(pbPacket + 8);
3071 ataStartTransfer(s, RT_MIN(cbMax, 4), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_DVD_STRUCTURE, true);
3072 break;
3073 }
3074 default:
3075 atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
3076 break;
3077 }
3078}
3079
3080
3081/*
3082 * Parse ATAPI commands, passing them directly to the CD/DVD drive.
3083 */
3084static void atapiParseCmdPassthrough(ATADevState *s)
3085{
3086 const uint8_t *pbPacket;
3087 uint8_t *pbBuf;
3088 uint32_t cSectors, iATAPILBA;
3089 uint32_t cbTransfer = 0;
3090 PDMBLOCKTXDIR uTxDir = PDMBLOCKTXDIR_NONE;
3091
3092 pbPacket = s->aATAPICmd;
3093 pbBuf = s->CTX_SUFF(pbIOBuffer);
3094 switch (pbPacket[0])
3095 {
3096 case SCSI_BLANK:
3097 goto sendcmd;
3098 case SCSI_CLOSE_TRACK_SESSION:
3099 goto sendcmd;
3100 case SCSI_ERASE_10:
3101 iATAPILBA = ataBE2H_U32(pbPacket + 2);
3102 cbTransfer = ataBE2H_U16(pbPacket + 7);
3103 Log2(("ATAPI PT: lba %d\n", iATAPILBA));
3104 uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3105 goto sendcmd;
3106 case SCSI_FORMAT_UNIT:
3107 cbTransfer = s->uATARegLCyl | (s->uATARegHCyl << 8); /* use ATAPI transfer length */
3108 uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3109 goto sendcmd;
3110 case SCSI_GET_CONFIGURATION:
3111 cbTransfer = ataBE2H_U16(pbPacket + 7);
3112 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3113 goto sendcmd;
3114 case SCSI_GET_EVENT_STATUS_NOTIFICATION:
3115 cbTransfer = ataBE2H_U16(pbPacket + 7);
3116 if (ASMAtomicReadU32(&s->MediaEventStatus) != ATA_EVENT_STATUS_UNCHANGED)
3117 {
3118 ataStartTransfer(s, RT_MIN(cbTransfer, 8), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_GET_EVENT_STATUS_NOTIFICATION, true);
3119 break;
3120 }
3121 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3122 goto sendcmd;
3123 case SCSI_GET_PERFORMANCE:
3124 cbTransfer = s->uATARegLCyl | (s->uATARegHCyl << 8); /* use ATAPI transfer length */
3125 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3126 goto sendcmd;
3127 case SCSI_INQUIRY:
3128 cbTransfer = ataBE2H_U16(pbPacket + 3);
3129 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3130 goto sendcmd;
3131 case SCSI_LOAD_UNLOAD_MEDIUM:
3132 goto sendcmd;
3133 case SCSI_MECHANISM_STATUS:
3134 cbTransfer = ataBE2H_U16(pbPacket + 8);
3135 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3136 goto sendcmd;
3137 case SCSI_MODE_SELECT_10:
3138 cbTransfer = ataBE2H_U16(pbPacket + 7);
3139 uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3140 goto sendcmd;
3141 case SCSI_MODE_SENSE_10:
3142 cbTransfer = ataBE2H_U16(pbPacket + 7);
3143 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3144 goto sendcmd;
3145 case SCSI_PAUSE_RESUME:
3146 goto sendcmd;
3147 case SCSI_PLAY_AUDIO_10:
3148 goto sendcmd;
3149 case SCSI_PLAY_AUDIO_12:
3150 goto sendcmd;
3151 case SCSI_PLAY_AUDIO_MSF:
3152 goto sendcmd;
3153 case SCSI_PREVENT_ALLOW_MEDIUM_REMOVAL:
3154 /** @todo do not forget to unlock when a VM is shut down */
3155 goto sendcmd;
3156 case SCSI_READ_10:
3157 iATAPILBA = ataBE2H_U32(pbPacket + 2);
3158 cSectors = ataBE2H_U16(pbPacket + 7);
3159 Log2(("ATAPI PT: lba %d sectors %d\n", iATAPILBA, cSectors));
3160 s->cbATAPISector = 2048; /**< @todo this size is not always correct */
3161 cbTransfer = cSectors * s->cbATAPISector;
3162 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3163 goto sendcmd;
3164 case SCSI_READ_12:
3165 iATAPILBA = ataBE2H_U32(pbPacket + 2);
3166 cSectors = ataBE2H_U32(pbPacket + 6);
3167 Log2(("ATAPI PT: lba %d sectors %d\n", iATAPILBA, cSectors));
3168 s->cbATAPISector = 2048; /**< @todo this size is not always correct */
3169 cbTransfer = cSectors * s->cbATAPISector;
3170 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3171 goto sendcmd;
3172 case SCSI_READ_BUFFER:
3173 cbTransfer = ataBE2H_U24(pbPacket + 6);
3174 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3175 goto sendcmd;
3176 case SCSI_READ_BUFFER_CAPACITY:
3177 cbTransfer = ataBE2H_U16(pbPacket + 7);
3178 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3179 goto sendcmd;
3180 case SCSI_READ_CAPACITY:
3181 cbTransfer = 8;
3182 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3183 goto sendcmd;
3184 case SCSI_READ_CD:
3185 s->cbATAPISector = 2048; /**< @todo this size is not always correct */
3186 cbTransfer = ataBE2H_U24(pbPacket + 6) / s->cbATAPISector * s->cbATAPISector;
3187 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3188 goto sendcmd;
3189 case SCSI_READ_CD_MSF:
3190 cSectors = ataMSF2LBA(pbPacket + 6) - ataMSF2LBA(pbPacket + 3);
3191 if (cSectors > 32)
3192 cSectors = 32; /* Limit transfer size to 64~74K. Safety first. In any case this can only harm software doing CDDA extraction. */
3193 s->cbATAPISector = 2048; /**< @todo this size is not always correct */
3194 cbTransfer = cSectors * s->cbATAPISector;
3195 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3196 goto sendcmd;
3197 case SCSI_READ_DISC_INFORMATION:
3198 cbTransfer = ataBE2H_U16(pbPacket + 7);
3199 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3200 goto sendcmd;
3201 case SCSI_READ_DVD_STRUCTURE:
3202 cbTransfer = ataBE2H_U16(pbPacket + 8);
3203 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3204 goto sendcmd;
3205 case SCSI_READ_FORMAT_CAPACITIES:
3206 cbTransfer = ataBE2H_U16(pbPacket + 7);
3207 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3208 goto sendcmd;
3209 case SCSI_READ_SUBCHANNEL:
3210 cbTransfer = ataBE2H_U16(pbPacket + 7);
3211 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3212 goto sendcmd;
3213 case SCSI_READ_TOC_PMA_ATIP:
3214 cbTransfer = ataBE2H_U16(pbPacket + 7);
3215 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3216 goto sendcmd;
3217 case SCSI_READ_TRACK_INFORMATION:
3218 cbTransfer = ataBE2H_U16(pbPacket + 7);
3219 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3220 goto sendcmd;
3221 case SCSI_REPAIR_TRACK:
3222 goto sendcmd;
3223 case SCSI_REPORT_KEY:
3224 cbTransfer = ataBE2H_U16(pbPacket + 8);
3225 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3226 goto sendcmd;
3227 case SCSI_REQUEST_SENSE:
3228 cbTransfer = pbPacket[4];
3229 if ((s->abATAPISense[2] & 0x0f) != SCSI_SENSE_NONE)
3230 {
3231 ataStartTransfer(s, RT_MIN(cbTransfer, 18), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_REQUEST_SENSE, true);
3232 break;
3233 }
3234 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3235 goto sendcmd;
3236 case SCSI_RESERVE_TRACK:
3237 goto sendcmd;
3238 case SCSI_SCAN:
3239 goto sendcmd;
3240 case SCSI_SEEK_10:
3241 goto sendcmd;
3242 case SCSI_SEND_CUE_SHEET:
3243 cbTransfer = ataBE2H_U24(pbPacket + 6);
3244 uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3245 goto sendcmd;
3246 case SCSI_SEND_DVD_STRUCTURE:
3247 cbTransfer = ataBE2H_U16(pbPacket + 8);
3248 uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3249 goto sendcmd;
3250 case SCSI_SEND_EVENT:
3251 cbTransfer = ataBE2H_U16(pbPacket + 8);
3252 uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3253 goto sendcmd;
3254 case SCSI_SEND_KEY:
3255 cbTransfer = ataBE2H_U16(pbPacket + 8);
3256 uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3257 goto sendcmd;
3258 case SCSI_SEND_OPC_INFORMATION:
3259 cbTransfer = ataBE2H_U16(pbPacket + 7);
3260 uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3261 goto sendcmd;
3262 case SCSI_SET_CD_SPEED:
3263 goto sendcmd;
3264 case SCSI_SET_READ_AHEAD:
3265 goto sendcmd;
3266 case SCSI_SET_STREAMING:
3267 cbTransfer = ataBE2H_U16(pbPacket + 9);
3268 uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3269 goto sendcmd;
3270 case SCSI_START_STOP_UNIT:
3271 goto sendcmd;
3272 case SCSI_STOP_PLAY_SCAN:
3273 goto sendcmd;
3274 case SCSI_SYNCHRONIZE_CACHE:
3275 goto sendcmd;
3276 case SCSI_TEST_UNIT_READY:
3277 goto sendcmd;
3278 case SCSI_VERIFY_10:
3279 goto sendcmd;
3280 case SCSI_WRITE_10:
3281 iATAPILBA = ataBE2H_U32(pbPacket + 2);
3282 cSectors = ataBE2H_U16(pbPacket + 7);
3283 Log2(("ATAPI PT: lba %d sectors %d\n", iATAPILBA, cSectors));
3284#if 0
3285 /* The sector size is determined by the async I/O thread. */
3286 s->cbATAPISector = 0;
3287 /* Preliminary, will be corrected once the sector size is known. */
3288 cbTransfer = cSectors;
3289#else
3290 s->cbATAPISector = 2048; /**< @todo this size is not always correct */
3291 cbTransfer = cSectors * s->cbATAPISector;
3292#endif
3293 uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3294 goto sendcmd;
3295 case SCSI_WRITE_12:
3296 iATAPILBA = ataBE2H_U32(pbPacket + 2);
3297 cSectors = ataBE2H_U32(pbPacket + 6);
3298 Log2(("ATAPI PT: lba %d sectors %d\n", iATAPILBA, cSectors));
3299#if 0
3300 /* The sector size is determined by the async I/O thread. */
3301 s->cbATAPISector = 0;
3302 /* Preliminary, will be corrected once the sector size is known. */
3303 cbTransfer = cSectors;
3304#else
3305 s->cbATAPISector = 2048; /**< @todo this size is not always correct */
3306 cbTransfer = cSectors * s->cbATAPISector;
3307#endif
3308 uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3309 goto sendcmd;
3310 case SCSI_WRITE_AND_VERIFY_10:
3311 iATAPILBA = ataBE2H_U32(pbPacket + 2);
3312 cSectors = ataBE2H_U16(pbPacket + 7);
3313 Log2(("ATAPI PT: lba %d sectors %d\n", iATAPILBA, cSectors));
3314 /* The sector size is determined by the async I/O thread. */
3315 s->cbATAPISector = 0;
3316 /* Preliminary, will be corrected once the sector size is known. */
3317 cbTransfer = cSectors;
3318 uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3319 goto sendcmd;
3320 case SCSI_WRITE_BUFFER:
3321 switch (pbPacket[1] & 0x1f)
3322 {
3323 case 0x04: /* download microcode */
3324 case 0x05: /* download microcode and save */
3325 case 0x06: /* download microcode with offsets */
3326 case 0x07: /* download microcode with offsets and save */
3327 case 0x0e: /* download microcode with offsets and defer activation */
3328 case 0x0f: /* activate deferred microcode */
3329 LogRel(("PIIX3 ATA: LUN#%d: CD-ROM passthrough command attempted to update firmware, blocked\n", s->iLUN));
3330 atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
3331 break;
3332 default:
3333 cbTransfer = ataBE2H_U16(pbPacket + 6);
3334 uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
3335 goto sendcmd;
3336 }
3337 break;
3338 case SCSI_REPORT_LUNS: /* Not part of MMC-3, but used by Windows. */
3339 cbTransfer = ataBE2H_U32(pbPacket + 6);
3340 uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
3341 goto sendcmd;
3342 case SCSI_REZERO_UNIT:
3343 /* Obsolete command used by cdrecord. What else would one expect?
3344 * This command is not sent to the drive, it is handled internally,
3345 * as the Linux kernel doesn't like it (message "scsi: unknown
3346 * opcode 0x01" in syslog) and replies with a sense code of 0,
3347 * which sends cdrecord to an endless loop. */
3348 atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
3349 break;
3350 default:
3351 LogRel(("PIIX3 ATA: LUN#%d: passthrough unimplemented for command %#x\n", s->iLUN, pbPacket[0]));
3352 atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
3353 break;
3354 sendcmd:
3355 /* Send a command to the drive, passing data in/out as required. */
3356 Log2(("ATAPI PT: max size %d\n", cbTransfer));
3357 Assert(cbTransfer <= s->cbIOBuffer);
3358 if (cbTransfer == 0)
3359 uTxDir = PDMBLOCKTXDIR_NONE;
3360 ataStartTransfer(s, cbTransfer, uTxDir, ATAFN_BT_ATAPI_PASSTHROUGH_CMD, ATAFN_SS_ATAPI_PASSTHROUGH, true);
3361 }
3362}
3363
3364
3365static void atapiParseCmd(ATADevState *s)
3366{
3367 const uint8_t *pbPacket;
3368
3369 pbPacket = s->aATAPICmd;
3370#ifdef DEBUG
3371 Log(("%s: LUN#%d DMA=%d CMD=%#04x \"%s\"\n", __FUNCTION__, s->iLUN, s->fDMA, pbPacket[0], SCSICmdText(pbPacket[0])));
3372#else /* !DEBUG */
3373 Log(("%s: LUN#%d DMA=%d CMD=%#04x\n", __FUNCTION__, s->iLUN, s->fDMA, pbPacket[0]));
3374#endif /* !DEBUG */
3375 Log2(("%s: limit=%#x packet: %.*Rhxs\n", __FUNCTION__, s->uATARegLCyl | (s->uATARegHCyl << 8), ATAPI_PACKET_SIZE, pbPacket));
3376
3377 if (s->fATAPIPassthrough)
3378 atapiParseCmdPassthrough(s);
3379 else
3380 atapiParseCmdVirtualATAPI(s);
3381}
3382
3383
3384static bool ataPacketSS(ATADevState *s)
3385{
3386 s->fDMA = !!(s->uATARegFeature & 1);
3387 memcpy(s->aATAPICmd, s->CTX_SUFF(pbIOBuffer), ATAPI_PACKET_SIZE);
3388 s->uTxDir = PDMBLOCKTXDIR_NONE;
3389 s->cbTotalTransfer = 0;
3390 s->cbElementaryTransfer = 0;
3391 atapiParseCmd(s);
3392 return false;
3393}
3394
3395
3396/**
3397 * SCSI_GET_EVENT_STATUS_NOTIFICATION should return "medium removed" event
3398 * from now on, regardless if there was a medium inserted or not.
3399 */
3400static void ataMediumRemoved(ATADevState *s)
3401{
3402 ASMAtomicWriteU32(&s->MediaEventStatus, ATA_EVENT_STATUS_MEDIA_REMOVED);
3403}
3404
3405
3406/**
3407 * SCSI_GET_EVENT_STATUS_NOTIFICATION should return "medium inserted". If
3408 * there was already a medium inserted, don't forget to send the "medium
3409 * removed" event first.
3410 */
3411static void ataMediumInserted(ATADevState *s)
3412{
3413 uint32_t OldStatus, NewStatus;
3414 do
3415 {
3416 OldStatus = ASMAtomicReadU32(&s->MediaEventStatus);
3417 switch (OldStatus)
3418 {
3419 case ATA_EVENT_STATUS_MEDIA_CHANGED:
3420 case ATA_EVENT_STATUS_MEDIA_REMOVED:
3421 /* no change, we will send "medium removed" + "medium inserted" */
3422 NewStatus = ATA_EVENT_STATUS_MEDIA_CHANGED;
3423 break;
3424 default:
3425 NewStatus = ATA_EVENT_STATUS_MEDIA_NEW;
3426 break;
3427 }
3428 } while (!ASMAtomicCmpXchgU32(&s->MediaEventStatus, NewStatus, OldStatus));
3429}
3430
3431
3432/**
3433 * Called when a media is mounted.
3434 *
3435 * @param pInterface Pointer to the interface structure containing the called function pointer.
3436 */
3437static DECLCALLBACK(void) ataMountNotify(PPDMIMOUNTNOTIFY pInterface)
3438{
3439 ATADevState *pIf = PDMIMOUNTNOTIFY_2_ATASTATE(pInterface);
3440 Log(("%s: changing LUN#%d\n", __FUNCTION__, pIf->iLUN));
3441
3442 /* Ignore the call if we're called while being attached. */
3443 if (!pIf->pDrvBlock)
3444 return;
3445
3446 if (pIf->fATAPI)
3447 pIf->cTotalSectors = pIf->pDrvBlock->pfnGetSize(pIf->pDrvBlock) / 2048;
3448 else
3449 pIf->cTotalSectors = pIf->pDrvBlock->pfnGetSize(pIf->pDrvBlock) / 512;
3450
3451 LogRel(("PIIX3 ATA: LUN#%d: CD/DVD, total number of sectors %Ld, passthrough unchanged\n", pIf->iLUN, pIf->cTotalSectors));
3452
3453 /* Report media changed in TEST UNIT and other (probably incorrect) places. */
3454 if (pIf->cNotifiedMediaChange < 2)
3455 pIf->cNotifiedMediaChange = 2;
3456 ataMediumInserted(pIf);
3457}
3458
3459/**
3460 * Called when a media is unmounted
3461 * @param pInterface Pointer to the interface structure containing the called function pointer.
3462 */
3463static DECLCALLBACK(void) ataUnmountNotify(PPDMIMOUNTNOTIFY pInterface)
3464{
3465 ATADevState *pIf = PDMIMOUNTNOTIFY_2_ATASTATE(pInterface);
3466 Log(("%s:\n", __FUNCTION__));
3467 pIf->cTotalSectors = 0;
3468
3469 /*
3470 * Whatever I do, XP will not use the GET MEDIA STATUS nor the EVENT stuff.
3471 * However, it will respond to TEST UNIT with a 0x6 0x28 (media changed) sense code.
3472 * So, we'll give it 4 TEST UNIT command to catch up, two which the media is not
3473 * present and 2 in which it is changed.
3474 */
3475 pIf->cNotifiedMediaChange = 4;
3476 ataMediumRemoved(pIf);
3477}
3478
3479static void ataPacketBT(ATADevState *s)
3480{
3481 s->cbElementaryTransfer = s->cbTotalTransfer;
3482 s->uATARegNSector = (s->uATARegNSector & ~7) | ATAPI_INT_REASON_CD;
3483 Log2(("%s: interrupt reason %#04x\n", __FUNCTION__, s->uATARegNSector));
3484 ataSetStatusValue(s, ATA_STAT_READY);
3485}
3486
3487
3488static void ataResetDevice(ATADevState *s)
3489{
3490 s->cMultSectors = ATA_MAX_MULT_SECTORS;
3491 s->cNotifiedMediaChange = 0;
3492 ASMAtomicWriteU32(&s->MediaEventStatus, ATA_EVENT_STATUS_UNCHANGED);
3493 ataUnsetIRQ(s);
3494
3495 s->uATARegSelect = 0x20;
3496 ataSetStatusValue(s, ATA_STAT_READY);
3497 ataSetSignature(s);
3498 s->cbTotalTransfer = 0;
3499 s->cbElementaryTransfer = 0;
3500 s->iIOBufferPIODataStart = 0;
3501 s->iIOBufferPIODataEnd = 0;
3502 s->iBeginTransfer = ATAFN_BT_NULL;
3503 s->iSourceSink = ATAFN_SS_NULL;
3504 s->fDMA = false;
3505 s->fATAPITransfer = false;
3506 s->uATATransferMode = ATA_MODE_UDMA | 2; /* PIIX3 supports only up to UDMA2 */
3507
3508 s->uATARegFeature = 0;
3509}
3510
3511
3512static bool ataExecuteDeviceDiagnosticSS(ATADevState *s)
3513{
3514 ataSetSignature(s);
3515 if (s->fATAPI)
3516 ataSetStatusValue(s, 0); /* NOTE: READY is _not_ set */
3517 else
3518 ataSetStatusValue(s, ATA_STAT_READY);
3519 s->uATARegError = 0x01;
3520 return false;
3521}
3522
3523
3524static void ataParseCmd(ATADevState *s, uint8_t cmd)
3525{
3526#ifdef DEBUG
3527 Log(("%s: LUN#%d CMD=%#04x \"%s\"\n", __FUNCTION__, s->iLUN, cmd, ATACmdText(cmd)));
3528#else /* !DEBUG */
3529 Log(("%s: LUN#%d CMD=%#04x\n", __FUNCTION__, s->iLUN, cmd));
3530#endif /* !DEBUG */
3531 s->fLBA48 = false;
3532 s->fDMA = false;
3533 if (cmd == ATA_IDLE_IMMEDIATE)
3534 {
3535 /* Detect Linux timeout recovery, first tries IDLE IMMEDIATE (which
3536 * would overwrite the failing command unfortunately), then RESET. */
3537 int32_t uCmdWait = -1;
3538 uint64_t uNow = RTTimeNanoTS();
3539 if (s->u64CmdTS)
3540 uCmdWait = (uNow - s->u64CmdTS) / 1000;
3541 LogRel(("PIIX3 ATA: LUN#%d: IDLE IMMEDIATE, CmdIf=%#04x (%d usec ago)\n",
3542 s->iLUN, s->uATARegCommand, uCmdWait));
3543 }
3544 s->uATARegCommand = cmd;
3545 switch (cmd)
3546 {
3547 case ATA_IDENTIFY_DEVICE:
3548 if (s->pDrvBlock && !s->fATAPI)
3549 ataStartTransfer(s, 512, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_NULL, ATAFN_SS_IDENTIFY, false);
3550 else
3551 {
3552 if (s->fATAPI)
3553 ataSetSignature(s);
3554 ataCmdError(s, ABRT_ERR);
3555 ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
3556 }
3557 break;
3558 case ATA_INITIALIZE_DEVICE_PARAMETERS:
3559 case ATA_RECALIBRATE:
3560 ataCmdOK(s, ATA_STAT_SEEK);
3561 ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
3562 break;
3563 case ATA_SET_MULTIPLE_MODE:
3564 if ( s->uATARegNSector != 0
3565 && ( s->uATARegNSector > ATA_MAX_MULT_SECTORS
3566 || (s->uATARegNSector & (s->uATARegNSector - 1)) != 0))
3567 {
3568 ataCmdError(s, ABRT_ERR);
3569 }
3570 else
3571 {
3572 Log2(("%s: set multi sector count to %d\n", __FUNCTION__, s->uATARegNSector));
3573 s->cMultSectors = s->uATARegNSector;
3574 ataCmdOK(s, 0);
3575 }
3576 ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
3577 break;
3578 case ATA_READ_VERIFY_SECTORS_EXT:
3579 s->fLBA48 = true;
3580 case ATA_READ_VERIFY_SECTORS:
3581 case ATA_READ_VERIFY_SECTORS_WITHOUT_RETRIES:
3582 /* do sector number check ? */
3583 ataCmdOK(s, 0);
3584 ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
3585 break;
3586 case ATA_READ_SECTORS_EXT:
3587 s->fLBA48 = true;
3588 case ATA_READ_SECTORS:
3589 case ATA_READ_SECTORS_WITHOUT_RETRIES:
3590 if (!s->pDrvBlock)
3591 goto abort_cmd;
3592 s->cSectorsPerIRQ = 1;
3593 ataStartTransfer(s, ataGetNSectors(s) * 512, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_READ_SECTORS, false);
3594 break;
3595 case ATA_WRITE_SECTORS_EXT:
3596 s->fLBA48 = true;
3597 case ATA_WRITE_SECTORS:
3598 case ATA_WRITE_SECTORS_WITHOUT_RETRIES:
3599 s->cSectorsPerIRQ = 1;
3600 ataStartTransfer(s, ataGetNSectors(s) * 512, PDMBLOCKTXDIR_TO_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_WRITE_SECTORS, false);
3601 break;
3602 case ATA_READ_MULTIPLE_EXT:
3603 s->fLBA48 = true;
3604 case ATA_READ_MULTIPLE:
3605 if (!s->cMultSectors)
3606 goto abort_cmd;
3607 s->cSectorsPerIRQ = s->cMultSectors;
3608 ataStartTransfer(s, ataGetNSectors(s) * 512, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_READ_SECTORS, false);
3609 break;
3610 case ATA_WRITE_MULTIPLE_EXT:
3611 s->fLBA48 = true;
3612 case ATA_WRITE_MULTIPLE:
3613 if (!s->cMultSectors)
3614 goto abort_cmd;
3615 s->cSectorsPerIRQ = s->cMultSectors;
3616 ataStartTransfer(s, ataGetNSectors(s) * 512, PDMBLOCKTXDIR_TO_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_WRITE_SECTORS, false);
3617 break;
3618 case ATA_READ_DMA_EXT:
3619 s->fLBA48 = true;
3620 case ATA_READ_DMA:
3621 case ATA_READ_DMA_WITHOUT_RETRIES:
3622 if (!s->pDrvBlock)
3623 goto abort_cmd;
3624 s->cSectorsPerIRQ = ATA_MAX_MULT_SECTORS;
3625 s->fDMA = true;
3626 ataStartTransfer(s, ataGetNSectors(s) * 512, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_READ_SECTORS, false);
3627 break;
3628 case ATA_WRITE_DMA_EXT:
3629 s->fLBA48 = true;
3630 case ATA_WRITE_DMA:
3631 case ATA_WRITE_DMA_WITHOUT_RETRIES:
3632 if (!s->pDrvBlock)
3633 goto abort_cmd;
3634 s->cSectorsPerIRQ = ATA_MAX_MULT_SECTORS;
3635 s->fDMA = true;
3636 ataStartTransfer(s, ataGetNSectors(s) * 512, PDMBLOCKTXDIR_TO_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_WRITE_SECTORS, false);
3637 break;
3638 case ATA_READ_NATIVE_MAX_ADDRESS_EXT:
3639 s->fLBA48 = true;
3640 ataSetSector(s, s->cTotalSectors - 1);
3641 ataCmdOK(s, 0);
3642 ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
3643 break;
3644 case ATA_SEEK: /* Used by the SCO OpenServer. Command is marked as obsolete */
3645 ataCmdOK(s, 0);
3646 ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
3647 break;
3648 case ATA_READ_NATIVE_MAX_ADDRESS:
3649 ataSetSector(s, RT_MIN(s->cTotalSectors, 1 << 28) - 1);
3650 ataCmdOK(s, 0);
3651 ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
3652 break;
3653 case ATA_CHECK_POWER_MODE:
3654 s->uATARegNSector = 0xff; /* drive active or idle */
3655 ataCmdOK(s, 0);
3656 ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
3657 break;
3658 case ATA_SET_FEATURES:
3659 Log2(("%s: feature=%#x\n", __FUNCTION__, s->uATARegFeature));
3660 if (!s->pDrvBlock)
3661 goto abort_cmd;
3662 switch (s->uATARegFeature)
3663 {
3664 case 0x02: /* write cache enable */
3665 Log2(("%s: write cache enable\n", __FUNCTION__));
3666 ataCmdOK(s, ATA_STAT_SEEK);
3667 ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
3668 break;
3669 case 0xaa: /* read look-ahead enable */
3670 Log2(("%s: read look-ahead enable\n", __FUNCTION__));
3671 ataCmdOK(s, ATA_STAT_SEEK);
3672 ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
3673 break;
3674 case 0x55: /* read look-ahead disable */
3675 Log2(("%s: read look-ahead disable\n", __FUNCTION__));
3676 ataCmdOK(s, ATA_STAT_SEEK);
3677 ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
3678 break;
3679 case 0xcc: /* reverting to power-on defaults enable */
3680 Log2(("%s: revert to power-on defaults enable\n", __FUNCTION__));
3681 ataCmdOK(s, ATA_STAT_SEEK);
3682 ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
3683 break;
3684 case 0x66: /* reverting to power-on defaults disable */
3685 Log2(("%s: revert to power-on defaults disable\n", __FUNCTION__));
3686 ataCmdOK(s, ATA_STAT_SEEK);
3687 ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
3688 break;
3689 case 0x82: /* write cache disable */
3690 Log2(("%s: write cache disable\n", __FUNCTION__));
3691 /* As per the ATA/ATAPI-6 specs, a write cache disable
3692 * command MUST flush the write buffers to disc. */
3693 ataStartTransfer(s, 0, PDMBLOCKTXDIR_NONE, ATAFN_BT_NULL, ATAFN_SS_FLUSH, false);
3694 break;
3695 case 0x03: { /* set transfer mode */
3696 Log2(("%s: transfer mode %#04x\n", __FUNCTION__, s->uATARegNSector));
3697 switch (s->uATARegNSector & 0xf8)
3698 {
3699 case 0x00: /* PIO default */
3700 case 0x08: /* PIO mode */
3701 break;
3702 case ATA_MODE_MDMA: /* MDMA mode */
3703 s->uATATransferMode = (s->uATARegNSector & 0xf8) | RT_MIN(s->uATARegNSector & 0x07, ATA_MDMA_MODE_MAX);
3704 break;
3705 case ATA_MODE_UDMA: /* UDMA mode */
3706 s->uATATransferMode = (s->uATARegNSector & 0xf8) | RT_MIN(s->uATARegNSector & 0x07, ATA_UDMA_MODE_MAX);
3707 break;
3708 default:
3709 goto abort_cmd;
3710 }
3711 ataCmdOK(s, ATA_STAT_SEEK);
3712 ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
3713 break;
3714 }
3715 default:
3716 goto abort_cmd;
3717 }
3718 /*
3719 * OS/2 workarond:
3720 * The OS/2 IDE driver from MCP2 appears to rely on the feature register being
3721 * reset here. According to the specification, this is a driver bug as the register
3722 * contents are undefined after the call. This means we can just as well reset it.
3723 */
3724 s->uATARegFeature = 0;
3725 break;
3726 case ATA_FLUSH_CACHE_EXT:
3727 case ATA_FLUSH_CACHE:
3728 if (!s->pDrvBlock || s->fATAPI)
3729 goto abort_cmd;
3730 ataStartTransfer(s, 0, PDMBLOCKTXDIR_NONE, ATAFN_BT_NULL, ATAFN_SS_FLUSH, false);
3731 break;
3732 case ATA_STANDBY_IMMEDIATE:
3733 ataCmdOK(s, 0);
3734 ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
3735 break;
3736 case ATA_IDLE_IMMEDIATE:
3737 LogRel(("PIIX3 ATA: LUN#%d: aborting current command\n", s->iLUN));
3738 ataAbortCurrentCommand(s, false);
3739 break;
3740 /* ATAPI commands */
3741 case ATA_IDENTIFY_PACKET_DEVICE:
3742 if (s->fATAPI)
3743 ataStartTransfer(s, 512, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_NULL, ATAFN_SS_ATAPI_IDENTIFY, false);
3744 else
3745 {
3746 ataCmdError(s, ABRT_ERR);
3747 ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
3748 }
3749 break;
3750 case ATA_EXECUTE_DEVICE_DIAGNOSTIC:
3751 ataStartTransfer(s, 0, PDMBLOCKTXDIR_NONE, ATAFN_BT_NULL, ATAFN_SS_EXECUTE_DEVICE_DIAGNOSTIC, false);
3752 break;
3753 case ATA_DEVICE_RESET:
3754 if (!s->fATAPI)
3755 goto abort_cmd;
3756 LogRel(("PIIX3 ATA: LUN#%d: performing device RESET\n", s->iLUN));
3757 ataAbortCurrentCommand(s, true);
3758 break;
3759 case ATA_PACKET:
3760 if (!s->fATAPI)
3761 goto abort_cmd;
3762 /* overlapping commands not supported */
3763 if (s->uATARegFeature & 0x02)
3764 goto abort_cmd;
3765 ataStartTransfer(s, ATAPI_PACKET_SIZE, PDMBLOCKTXDIR_TO_DEVICE, ATAFN_BT_PACKET, ATAFN_SS_PACKET, false);
3766 break;
3767 default:
3768 abort_cmd:
3769 ataCmdError(s, ABRT_ERR);
3770 ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
3771 break;
3772 }
3773}
3774
3775#endif /* IN_RING3 */
3776
3777static int ataIOPortWriteU8(PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
3778{
3779 Log2(("%s: write addr=%#x val=%#04x\n", __FUNCTION__, addr, val));
3780 addr &= 7;
3781 switch (addr)
3782 {
3783 case 0:
3784 break;
3785 case 1: /* feature register */
3786 /* NOTE: data is written to the two drives */
3787 pCtl->aIfs[0].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
3788 pCtl->aIfs[1].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
3789 pCtl->aIfs[0].uATARegFeatureHOB = pCtl->aIfs[0].uATARegFeature;
3790 pCtl->aIfs[1].uATARegFeatureHOB = pCtl->aIfs[1].uATARegFeature;
3791 pCtl->aIfs[0].uATARegFeature = val;
3792 pCtl->aIfs[1].uATARegFeature = val;
3793 break;
3794 case 2: /* sector count */
3795 pCtl->aIfs[0].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
3796 pCtl->aIfs[1].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
3797 pCtl->aIfs[0].uATARegNSectorHOB = pCtl->aIfs[0].uATARegNSector;
3798 pCtl->aIfs[1].uATARegNSectorHOB = pCtl->aIfs[1].uATARegNSector;
3799 pCtl->aIfs[0].uATARegNSector = val;
3800 pCtl->aIfs[1].uATARegNSector = val;
3801 break;
3802 case 3: /* sector number */
3803 pCtl->aIfs[0].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
3804 pCtl->aIfs[1].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
3805 pCtl->aIfs[0].uATARegSectorHOB = pCtl->aIfs[0].uATARegSector;
3806 pCtl->aIfs[1].uATARegSectorHOB = pCtl->aIfs[1].uATARegSector;
3807 pCtl->aIfs[0].uATARegSector = val;
3808 pCtl->aIfs[1].uATARegSector = val;
3809 break;
3810 case 4: /* cylinder low */
3811 pCtl->aIfs[0].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
3812 pCtl->aIfs[1].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
3813 pCtl->aIfs[0].uATARegLCylHOB = pCtl->aIfs[0].uATARegLCyl;
3814 pCtl->aIfs[1].uATARegLCylHOB = pCtl->aIfs[1].uATARegLCyl;
3815 pCtl->aIfs[0].uATARegLCyl = val;
3816 pCtl->aIfs[1].uATARegLCyl = val;
3817 break;
3818 case 5: /* cylinder high */
3819 pCtl->aIfs[0].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
3820 pCtl->aIfs[1].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
3821 pCtl->aIfs[0].uATARegHCylHOB = pCtl->aIfs[0].uATARegHCyl;
3822 pCtl->aIfs[1].uATARegHCylHOB = pCtl->aIfs[1].uATARegHCyl;
3823 pCtl->aIfs[0].uATARegHCyl = val;
3824 pCtl->aIfs[1].uATARegHCyl = val;
3825 break;
3826 case 6: /* drive/head */
3827 pCtl->aIfs[0].uATARegSelect = (val & ~0x10) | 0xa0;
3828 pCtl->aIfs[1].uATARegSelect = (val | 0x10) | 0xa0;
3829 if (((val >> 4) & 1) != pCtl->iSelectedIf)
3830 {
3831 PPDMDEVINS pDevIns = CONTROLLER_2_DEVINS(pCtl);
3832
3833 /* select another drive */
3834 pCtl->iSelectedIf = (val >> 4) & 1;
3835 /* The IRQ line is multiplexed between the two drives, so
3836 * update the state when switching to another drive. Only need
3837 * to update interrupt line if it is enabled and there is a
3838 * state change. */
3839 if ( !(pCtl->aIfs[pCtl->iSelectedIf].uATARegDevCtl & ATA_DEVCTL_DISABLE_IRQ)
3840 && ( pCtl->aIfs[pCtl->iSelectedIf].fIrqPending
3841 != pCtl->aIfs[pCtl->iSelectedIf ^ 1].fIrqPending))
3842 {
3843 if (pCtl->aIfs[pCtl->iSelectedIf].fIrqPending)
3844 {
3845 Log2(("%s: LUN#%d asserting IRQ (drive select change)\n", __FUNCTION__, pCtl->aIfs[pCtl->iSelectedIf].iLUN));
3846 /* The BMDMA unit unconditionally sets BM_STATUS_INT if
3847 * the interrupt line is asserted. It monitors the line
3848 * for a rising edge. */
3849 pCtl->BmDma.u8Status |= BM_STATUS_INT;
3850 if (pCtl->irq == 16)
3851 PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
3852 else
3853 PDMDevHlpISASetIrqNoWait(pDevIns, pCtl->irq, 1);
3854 }
3855 else
3856 {
3857 Log2(("%s: LUN#%d deasserting IRQ (drive select change)\n", __FUNCTION__, pCtl->aIfs[pCtl->iSelectedIf].iLUN));
3858 if (pCtl->irq == 16)
3859 PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
3860 else
3861 PDMDevHlpISASetIrqNoWait(pDevIns, pCtl->irq, 0);
3862 }
3863 }
3864 }
3865 break;
3866 default:
3867 case 7: /* command */
3868 /* ignore commands to non existant slave */
3869 if (pCtl->iSelectedIf && !pCtl->aIfs[pCtl->iSelectedIf].pDrvBlock)
3870 break;
3871#ifndef IN_RING3
3872 /* Don't do anything complicated in GC */
3873 return VINF_IOM_HC_IOPORT_WRITE;
3874#else /* IN_RING3 */
3875 ataParseCmd(&pCtl->aIfs[pCtl->iSelectedIf], val);
3876#endif /* !IN_RING3 */
3877 }
3878 return VINF_SUCCESS;
3879}
3880
3881
3882static int ataIOPortReadU8(PATACONTROLLER pCtl, uint32_t addr, uint32_t *pu32)
3883{
3884 ATADevState *s = &pCtl->aIfs[pCtl->iSelectedIf];
3885 uint32_t val;
3886 bool fHOB;
3887
3888 fHOB = !!(s->uATARegDevCtl & (1 << 7));
3889 switch (addr & 7)
3890 {
3891 case 0: /* data register */
3892 val = 0xff;
3893 break;
3894 case 1: /* error register */
3895 /* The ATA specification is very terse when it comes to specifying
3896 * the precise effects of reading back the error/feature register.
3897 * The error register (read-only) shares the register number with
3898 * the feature register (write-only), so it seems that it's not
3899 * necessary to support the usual HOB readback here. */
3900 if (!s->pDrvBlock)
3901 val = 0;
3902 else
3903 val = s->uATARegError;
3904 break;
3905 case 2: /* sector count */
3906 if (!s->pDrvBlock)
3907 val = 0;
3908 else if (fHOB)
3909 val = s->uATARegNSectorHOB;
3910 else
3911 val = s->uATARegNSector;
3912 break;
3913 case 3: /* sector number */
3914 if (!s->pDrvBlock)
3915 val = 0;
3916 else if (fHOB)
3917 val = s->uATARegSectorHOB;
3918 else
3919 val = s->uATARegSector;
3920 break;
3921 case 4: /* cylinder low */
3922 if (!s->pDrvBlock)
3923 val = 0;
3924 else if (fHOB)
3925 val = s->uATARegLCylHOB;
3926 else
3927 val = s->uATARegLCyl;
3928 break;
3929 case 5: /* cylinder high */
3930 if (!s->pDrvBlock)
3931 val = 0;
3932 else if (fHOB)
3933 val = s->uATARegHCylHOB;
3934 else
3935 val = s->uATARegHCyl;
3936 break;
3937 case 6: /* drive/head */
3938 /* This register must always work as long as there is at least
3939 * one drive attached to the controller. It is common between
3940 * both drives anyway (completely identical content). */
3941 if (!pCtl->aIfs[0].pDrvBlock && !pCtl->aIfs[1].pDrvBlock)
3942 val = 0;
3943 else
3944 val = s->uATARegSelect;
3945 break;
3946 default:
3947 case 7: /* primary status */
3948 {
3949 /* Counter for number of busy status seen in GC in a row. */
3950 static unsigned cBusy = 0;
3951
3952 if (!s->pDrvBlock)
3953 val = 0;
3954 else
3955 val = s->uATARegStatus;
3956
3957 /* Give the async I/O thread an opportunity to make progress,
3958 * don't let it starve by guests polling frequently. EMT has a
3959 * lower priority than the async I/O thread, but sometimes the
3960 * host OS doesn't care. With some guests we are only allowed to
3961 * be busy for about 5 milliseconds in some situations. Note that
3962 * this is no guarantee for any other VBox thread getting
3963 * scheduled, so this just lowers the CPU load a bit when drives
3964 * are busy. It cannot help with timing problems. */
3965 if (val & ATA_STAT_BUSY)
3966 {
3967#ifdef IN_RING3
3968 cBusy = 0;
3969 PDMCritSectLeave(&pCtl->lock);
3970
3971#ifndef RT_OS_WINDOWS
3972 /*
3973 * The thread might be stuck in an I/O operation
3974 * due to a high I/O load on the host. (see @bugref{3301})
3975 * To perform the reset successfully
3976 * we interrupt the operation by sending a signal to the thread
3977 * if the thread didn't responded in 10ms.
3978 * This works only on POSIX hosts (Windows has a CancelSynchronousIo function which
3979 * does the same but it was introduced with Vista) but so far
3980 * this hang was only observed on Linux and Mac OS X.
3981 *
3982 * This is a workaround and needs to be solved properly.
3983 */
3984 if (pCtl->fReset)
3985 {
3986 uint64_t u64ResetTimeStop = RTTimeMilliTS();
3987
3988 if ((u64ResetTimeStop - pCtl->u64ResetTime) >= 10)
3989 {
3990 LogRel(("PIIX3 ATA: Async I/O thread probably stuck in operation, interrupting\n"));
3991 pCtl->u64ResetTime = u64ResetTimeStop;
3992 RTThreadPoke(pCtl->AsyncIOThread);
3993 }
3994 }
3995#endif
3996
3997 RTThreadYield();
3998
3999 {
4000 STAM_PROFILE_START(&pCtl->StatLockWait, a);
4001 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
4002 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
4003 }
4004
4005 val = s->uATARegStatus;
4006#else /* !IN_RING3 */
4007 /* Cannot yield CPU in guest context. And switching to host
4008 * context for each and every busy status is too costly,
4009 * especially on SMP systems where we don't gain much by
4010 * yielding the CPU to someone else. */
4011 if (++cBusy >= 20)
4012 {
4013 cBusy = 0;
4014 return VINF_IOM_HC_IOPORT_READ;
4015 }
4016#endif /* !IN_RING3 */
4017 }
4018 else
4019 cBusy = 0;
4020 ataUnsetIRQ(s);
4021 break;
4022 }
4023 }
4024 Log2(("%s: addr=%#x val=%#04x\n", __FUNCTION__, addr, val));
4025 *pu32 = val;
4026 return VINF_SUCCESS;
4027}
4028
4029
4030static uint32_t ataStatusRead(PATACONTROLLER pCtl, uint32_t addr)
4031{
4032 ATADevState *s = &pCtl->aIfs[pCtl->iSelectedIf];
4033 uint32_t val;
4034
4035 if ((!pCtl->aIfs[0].pDrvBlock && !pCtl->aIfs[1].pDrvBlock) ||
4036 (pCtl->iSelectedIf == 1 && !s->pDrvBlock))
4037 val = 0;
4038 else
4039 val = s->uATARegStatus;
4040 Log2(("%s: addr=%#x val=%#04x\n", __FUNCTION__, addr, val));
4041 return val;
4042}
4043
4044static int ataControlWrite(PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
4045{
4046#ifndef IN_RING3
4047 if ((val ^ pCtl->aIfs[0].uATARegDevCtl) & ATA_DEVCTL_RESET)
4048 return VINF_IOM_HC_IOPORT_WRITE; /* The RESET stuff is too complicated for GC. */
4049#endif /* !IN_RING3 */
4050
4051 Log2(("%s: addr=%#x val=%#04x\n", __FUNCTION__, addr, val));
4052 /* RESET is common for both drives attached to a controller. */
4053 if (!(pCtl->aIfs[0].uATARegDevCtl & ATA_DEVCTL_RESET) &&
4054 (val & ATA_DEVCTL_RESET))
4055 {
4056#ifdef IN_RING3
4057 /* Software RESET low to high */
4058 int32_t uCmdWait0 = -1, uCmdWait1 = -1;
4059 uint64_t uNow = RTTimeNanoTS();
4060 if (pCtl->aIfs[0].u64CmdTS)
4061 uCmdWait0 = (uNow - pCtl->aIfs[0].u64CmdTS) / 1000;
4062 if (pCtl->aIfs[1].u64CmdTS)
4063 uCmdWait1 = (uNow - pCtl->aIfs[1].u64CmdTS) / 1000;
4064 LogRel(("PIIX3 ATA: Ctl#%d: RESET, DevSel=%d AIOIf=%d CmdIf0=%#04x (%d usec ago) CmdIf1=%#04x (%d usec ago)\n",
4065 ATACONTROLLER_IDX(pCtl), pCtl->iSelectedIf, pCtl->iAIOIf,
4066 pCtl->aIfs[0].uATARegCommand, uCmdWait0,
4067 pCtl->aIfs[1].uATARegCommand, uCmdWait1));
4068 pCtl->fReset = true;
4069 /* Everything must be done after the reset flag is set, otherwise
4070 * there are unavoidable races with the currently executing request
4071 * (which might just finish in the mean time). */
4072 pCtl->fChainedTransfer = false;
4073 for (uint32_t i = 0; i < RT_ELEMENTS(pCtl->aIfs); i++)
4074 {
4075 ataResetDevice(&pCtl->aIfs[i]);
4076 /* The following cannot be done using ataSetStatusValue() since the
4077 * reset flag is already set, which suppresses all status changes. */
4078 pCtl->aIfs[i].uATARegStatus = ATA_STAT_BUSY | ATA_STAT_SEEK;
4079 Log2(("%s: LUN#%d status %#04x\n", __FUNCTION__, pCtl->aIfs[i].iLUN, pCtl->aIfs[i].uATARegStatus));
4080 pCtl->aIfs[i].uATARegError = 0x01;
4081 }
4082 ataAsyncIOClearRequests(pCtl);
4083 Log2(("%s: Ctl#%d: message to async I/O thread, resetA\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
4084 if (val & ATA_DEVCTL_HOB)
4085 {
4086 val &= ~ATA_DEVCTL_HOB;
4087 Log2(("%s: ignored setting HOB\n", __FUNCTION__));
4088 }
4089
4090 /* Save the timestamp we started the reset. */
4091 pCtl->u64ResetTime = RTTimeMilliTS();
4092
4093 /* Issue the reset request now. */
4094 ataAsyncIOPutRequest(pCtl, &g_ataResetARequest);
4095#else /* !IN_RING3 */
4096 AssertMsgFailed(("RESET handling is too complicated for GC\n"));
4097#endif /* IN_RING3 */
4098 }
4099 else if ((pCtl->aIfs[0].uATARegDevCtl & ATA_DEVCTL_RESET) &&
4100 !(val & ATA_DEVCTL_RESET))
4101 {
4102#ifdef IN_RING3
4103 /* Software RESET high to low */
4104 Log(("%s: deasserting RESET\n", __FUNCTION__));
4105 Log2(("%s: Ctl#%d: message to async I/O thread, resetC\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
4106 if (val & ATA_DEVCTL_HOB)
4107 {
4108 val &= ~ATA_DEVCTL_HOB;
4109 Log2(("%s: ignored setting HOB\n", __FUNCTION__));
4110 }
4111 ataAsyncIOPutRequest(pCtl, &g_ataResetCRequest);
4112#else /* !IN_RING3 */
4113 AssertMsgFailed(("RESET handling is too complicated for GC\n"));
4114#endif /* IN_RING3 */
4115 }
4116
4117 /* Change of interrupt disable flag. Update interrupt line if interrupt
4118 * is pending on the current interface. */
4119 if ((val ^ pCtl->aIfs[0].uATARegDevCtl) & ATA_DEVCTL_DISABLE_IRQ
4120 && pCtl->aIfs[pCtl->iSelectedIf].fIrqPending)
4121 {
4122 if (!(val & ATA_DEVCTL_DISABLE_IRQ))
4123 {
4124 Log2(("%s: LUN#%d asserting IRQ (interrupt disable change)\n", __FUNCTION__, pCtl->aIfs[pCtl->iSelectedIf].iLUN));
4125 /* The BMDMA unit unconditionally sets BM_STATUS_INT if the
4126 * interrupt line is asserted. It monitors the line for a rising
4127 * edge. */
4128 pCtl->BmDma.u8Status |= BM_STATUS_INT;
4129 if (pCtl->irq == 16)
4130 PDMDevHlpPCISetIrqNoWait(CONTROLLER_2_DEVINS(pCtl), 0, 1);
4131 else
4132 PDMDevHlpISASetIrqNoWait(CONTROLLER_2_DEVINS(pCtl), pCtl->irq, 1);
4133 }
4134 else
4135 {
4136 Log2(("%s: LUN#%d deasserting IRQ (interrupt disable change)\n", __FUNCTION__, pCtl->aIfs[pCtl->iSelectedIf].iLUN));
4137 if (pCtl->irq == 16)
4138 PDMDevHlpPCISetIrqNoWait(CONTROLLER_2_DEVINS(pCtl), 0, 0);
4139 else
4140 PDMDevHlpISASetIrqNoWait(CONTROLLER_2_DEVINS(pCtl), pCtl->irq, 0);
4141 }
4142 }
4143
4144 if (val & ATA_DEVCTL_HOB)
4145 Log2(("%s: set HOB\n", __FUNCTION__));
4146
4147 pCtl->aIfs[0].uATARegDevCtl = val;
4148 pCtl->aIfs[1].uATARegDevCtl = val;
4149
4150 return VINF_SUCCESS;
4151}
4152
4153#ifdef IN_RING3
4154
4155static void ataPIOTransfer(PATACONTROLLER pCtl)
4156{
4157 ATADevState *s;
4158
4159 s = &pCtl->aIfs[pCtl->iAIOIf];
4160 Log3(("%s: if=%p\n", __FUNCTION__, s));
4161
4162 if (s->cbTotalTransfer && s->iIOBufferCur > s->iIOBufferEnd)
4163 {
4164 LogRel(("PIIX3 ATA: LUN#%d: %s data in the middle of a PIO transfer - VERY SLOW\n", s->iLUN, s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE ? "loading" : "storing"));
4165 /* Any guest OS that triggers this case has a pathetic ATA driver.
4166 * In a real system it would block the CPU via IORDY, here we do it
4167 * very similarly by not continuing with the current instruction
4168 * until the transfer to/from the storage medium is completed. */
4169 if (s->iSourceSink != ATAFN_SS_NULL)
4170 {
4171 bool fRedo;
4172 uint8_t status = s->uATARegStatus;
4173 ataSetStatusValue(s, ATA_STAT_BUSY);
4174 Log2(("%s: calling source/sink function\n", __FUNCTION__));
4175 fRedo = g_apfnSourceSinkFuncs[s->iSourceSink](s);
4176 pCtl->fRedo = fRedo;
4177 if (RT_UNLIKELY(fRedo))
4178 return;
4179 ataSetStatusValue(s, status);
4180 s->iIOBufferCur = 0;
4181 s->iIOBufferEnd = s->cbElementaryTransfer;
4182 }
4183 }
4184 if (s->cbTotalTransfer)
4185 {
4186 if (s->fATAPITransfer)
4187 ataPIOTransferLimitATAPI(s);
4188
4189 if (s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE && s->cbElementaryTransfer > s->cbTotalTransfer)
4190 s->cbElementaryTransfer = s->cbTotalTransfer;
4191
4192 Log2(("%s: %s tx_size=%d elem_tx_size=%d index=%d end=%d\n",
4193 __FUNCTION__, s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE ? "T2I" : "I2T",
4194 s->cbTotalTransfer, s->cbElementaryTransfer,
4195 s->iIOBufferCur, s->iIOBufferEnd));
4196 ataPIOTransferStart(s, s->iIOBufferCur, s->cbElementaryTransfer);
4197 s->cbTotalTransfer -= s->cbElementaryTransfer;
4198 s->iIOBufferCur += s->cbElementaryTransfer;
4199
4200 if (s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE && s->cbElementaryTransfer > s->cbTotalTransfer)
4201 s->cbElementaryTransfer = s->cbTotalTransfer;
4202 }
4203 else
4204 ataPIOTransferStop(s);
4205}
4206
4207
4208DECLINLINE(void) ataPIOTransferFinish(PATACONTROLLER pCtl, ATADevState *s)
4209{
4210 /* Do not interfere with RESET processing if the PIO transfer finishes
4211 * while the RESET line is asserted. */
4212 if (pCtl->fReset)
4213 {
4214 Log2(("%s: Ctl#%d: suppressed continuing PIO transfer as RESET is active\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
4215 return;
4216 }
4217
4218 if ( s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE
4219 || ( s->iSourceSink != ATAFN_SS_NULL
4220 && s->iIOBufferCur >= s->iIOBufferEnd))
4221 {
4222 /* Need to continue the transfer in the async I/O thread. This is
4223 * the case for write operations or generally for not yet finished
4224 * transfers (some data might need to be read). */
4225 ataUnsetStatus(s, ATA_STAT_READY | ATA_STAT_DRQ);
4226 ataSetStatus(s, ATA_STAT_BUSY);
4227
4228 Log2(("%s: Ctl#%d: message to async I/O thread, continuing PIO transfer\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
4229 ataAsyncIOPutRequest(pCtl, &g_ataPIORequest);
4230 }
4231 else
4232 {
4233 /* Either everything finished (though some data might still be pending)
4234 * or some data is pending before the next read is due. */
4235
4236 /* Continue a previously started transfer. */
4237 ataUnsetStatus(s, ATA_STAT_DRQ);
4238 ataSetStatus(s, ATA_STAT_READY);
4239
4240 if (s->cbTotalTransfer)
4241 {
4242 /* There is more to transfer, happens usually for large ATAPI
4243 * reads - the protocol limits the chunk size to 65534 bytes. */
4244 ataPIOTransfer(pCtl);
4245 ataSetIRQ(s);
4246 }
4247 else
4248 {
4249 Log2(("%s: Ctl#%d: skipping message to async I/O thread, ending PIO transfer\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
4250 /* Finish PIO transfer. */
4251 ataPIOTransfer(pCtl);
4252 Assert(!pCtl->fRedo);
4253 }
4254 }
4255}
4256
4257#endif /* IN_RING3 */
4258
4259static int ataDataWrite(PATACONTROLLER pCtl, uint32_t addr, uint32_t cbSize, const uint8_t *pbBuf)
4260{
4261 ATADevState *s = &pCtl->aIfs[pCtl->iSelectedIf];
4262 uint8_t *p;
4263
4264 if (s->iIOBufferPIODataStart < s->iIOBufferPIODataEnd)
4265 {
4266 Assert(s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE);
4267 p = s->CTX_SUFF(pbIOBuffer) + s->iIOBufferPIODataStart;
4268#ifndef IN_RING3
4269 /* All but the last transfer unit is simple enough for GC, but
4270 * sending a request to the async IO thread is too complicated. */
4271 if (s->iIOBufferPIODataStart + cbSize < s->iIOBufferPIODataEnd)
4272 {
4273 memcpy(p, pbBuf, cbSize);
4274 s->iIOBufferPIODataStart += cbSize;
4275 }
4276 else
4277 return VINF_IOM_HC_IOPORT_WRITE;
4278#else /* IN_RING3 */
4279 memcpy(p, pbBuf, cbSize);
4280 s->iIOBufferPIODataStart += cbSize;
4281 if (s->iIOBufferPIODataStart >= s->iIOBufferPIODataEnd)
4282 ataPIOTransferFinish(pCtl, s);
4283#endif /* !IN_RING3 */
4284 }
4285 else
4286 Log2(("%s: DUMMY data\n", __FUNCTION__));
4287 Log3(("%s: addr=%#x val=%.*Rhxs\n", __FUNCTION__, addr, cbSize, pbBuf));
4288 return VINF_SUCCESS;
4289}
4290
4291static int ataDataRead(PATACONTROLLER pCtl, uint32_t addr, uint32_t cbSize, uint8_t *pbBuf)
4292{
4293 ATADevState *s = &pCtl->aIfs[pCtl->iSelectedIf];
4294 uint8_t *p;
4295
4296 if (s->iIOBufferPIODataStart < s->iIOBufferPIODataEnd)
4297 {
4298 Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
4299 p = s->CTX_SUFF(pbIOBuffer) + s->iIOBufferPIODataStart;
4300#ifndef IN_RING3
4301 /* All but the last transfer unit is simple enough for GC, but
4302 * sending a request to the async IO thread is too complicated. */
4303 if (s->iIOBufferPIODataStart + cbSize < s->iIOBufferPIODataEnd)
4304 {
4305 memcpy(pbBuf, p, cbSize);
4306 s->iIOBufferPIODataStart += cbSize;
4307 }
4308 else
4309 return VINF_IOM_HC_IOPORT_READ;
4310#else /* IN_RING3 */
4311 memcpy(pbBuf, p, cbSize);
4312 s->iIOBufferPIODataStart += cbSize;
4313 if (s->iIOBufferPIODataStart >= s->iIOBufferPIODataEnd)
4314 ataPIOTransferFinish(pCtl, s);
4315#endif /* !IN_RING3 */
4316 }
4317 else
4318 {
4319 Log2(("%s: DUMMY data\n", __FUNCTION__));
4320 memset(pbBuf, '\xff', cbSize);
4321 }
4322 Log3(("%s: addr=%#x val=%.*Rhxs\n", __FUNCTION__, addr, cbSize, pbBuf));
4323 return VINF_SUCCESS;
4324}
4325
4326#ifdef IN_RING3
4327
4328static void ataDMATransferStop(ATADevState *s)
4329{
4330 s->cbTotalTransfer = 0;
4331 s->cbElementaryTransfer = 0;
4332 s->iBeginTransfer = ATAFN_BT_NULL;
4333 s->iSourceSink = ATAFN_SS_NULL;
4334}
4335
4336
4337/**
4338 * Perform the entire DMA transfer in one go (unless a source/sink operation
4339 * has to be redone or a RESET comes in between). Unlike the PIO counterpart
4340 * this function cannot handle empty transfers.
4341 *
4342 * @param pCtl Controller for which to perform the transfer.
4343 */
4344static void ataDMATransfer(PATACONTROLLER pCtl)
4345{
4346 PPDMDEVINS pDevIns = CONTROLLER_2_DEVINS(pCtl);
4347 ATADevState *s = &pCtl->aIfs[pCtl->iAIOIf];
4348 bool fRedo;
4349 RTGCPHYS32 pDesc;
4350 uint32_t cbTotalTransfer, cbElementaryTransfer;
4351 uint32_t iIOBufferCur, iIOBufferEnd;
4352 uint32_t dmalen;
4353 PDMBLOCKTXDIR uTxDir;
4354 bool fLastDesc = false;
4355
4356 Assert(sizeof(BMDMADesc) == 8);
4357
4358 fRedo = pCtl->fRedo;
4359 if (RT_LIKELY(!fRedo))
4360 Assert(s->cbTotalTransfer);
4361 uTxDir = (PDMBLOCKTXDIR)s->uTxDir;
4362 cbTotalTransfer = s->cbTotalTransfer;
4363 cbElementaryTransfer = s->cbElementaryTransfer;
4364 iIOBufferCur = s->iIOBufferCur;
4365 iIOBufferEnd = s->iIOBufferEnd;
4366
4367 /* The DMA loop is designed to hold the lock only when absolutely
4368 * necessary. This avoids long freezes should the guest access the
4369 * ATA registers etc. for some reason. */
4370 PDMCritSectLeave(&pCtl->lock);
4371
4372 Log2(("%s: %s tx_size=%d elem_tx_size=%d index=%d end=%d\n",
4373 __FUNCTION__, uTxDir == PDMBLOCKTXDIR_FROM_DEVICE ? "T2I" : "I2T",
4374 cbTotalTransfer, cbElementaryTransfer,
4375 iIOBufferCur, iIOBufferEnd));
4376 for (pDesc = pCtl->pFirstDMADesc; pDesc <= pCtl->pLastDMADesc; pDesc += sizeof(BMDMADesc))
4377 {
4378 BMDMADesc DMADesc;
4379 RTGCPHYS32 pBuffer;
4380 uint32_t cbBuffer;
4381
4382 if (RT_UNLIKELY(fRedo))
4383 {
4384 pBuffer = pCtl->pRedoDMABuffer;
4385 cbBuffer = pCtl->cbRedoDMABuffer;
4386 fLastDesc = pCtl->fRedoDMALastDesc;
4387 }
4388 else
4389 {
4390 PDMDevHlpPhysRead(pDevIns, pDesc, &DMADesc, sizeof(BMDMADesc));
4391 pBuffer = RT_LE2H_U32(DMADesc.pBuffer);
4392 cbBuffer = RT_LE2H_U32(DMADesc.cbBuffer);
4393 fLastDesc = !!(cbBuffer & 0x80000000);
4394 cbBuffer &= 0xfffe;
4395 if (cbBuffer == 0)
4396 cbBuffer = 0x10000;
4397 if (cbBuffer > cbTotalTransfer)
4398 cbBuffer = cbTotalTransfer;
4399 }
4400
4401 while (RT_UNLIKELY(fRedo) || (cbBuffer && cbTotalTransfer))
4402 {
4403 if (RT_LIKELY(!fRedo))
4404 {
4405 dmalen = RT_MIN(cbBuffer, iIOBufferEnd - iIOBufferCur);
4406 Log2(("%s: DMA desc %#010x: addr=%#010x size=%#010x\n", __FUNCTION__,
4407 (int)pDesc, pBuffer, cbBuffer));
4408 if (uTxDir == PDMBLOCKTXDIR_FROM_DEVICE)
4409 PDMDevHlpPhysWrite(pDevIns, pBuffer, s->CTX_SUFF(pbIOBuffer) + iIOBufferCur, dmalen);
4410 else
4411 PDMDevHlpPhysRead(pDevIns, pBuffer, s->CTX_SUFF(pbIOBuffer) + iIOBufferCur, dmalen);
4412 iIOBufferCur += dmalen;
4413 cbTotalTransfer -= dmalen;
4414 cbBuffer -= dmalen;
4415 pBuffer += dmalen;
4416 }
4417 if ( iIOBufferCur == iIOBufferEnd
4418 && (uTxDir == PDMBLOCKTXDIR_TO_DEVICE || cbTotalTransfer))
4419 {
4420 if (uTxDir == PDMBLOCKTXDIR_FROM_DEVICE && cbElementaryTransfer > cbTotalTransfer)
4421 cbElementaryTransfer = cbTotalTransfer;
4422
4423 {
4424 STAM_PROFILE_START(&pCtl->StatLockWait, a);
4425 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
4426 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
4427 }
4428
4429 /* The RESET handler could have cleared the DMA transfer
4430 * state (since we didn't hold the lock until just now
4431 * the guest can continue in parallel). If so, the state
4432 * is already set up so the loop is exited immediately. */
4433 if (s->iSourceSink != ATAFN_SS_NULL)
4434 {
4435 s->iIOBufferCur = iIOBufferCur;
4436 s->iIOBufferEnd = iIOBufferEnd;
4437 s->cbElementaryTransfer = cbElementaryTransfer;
4438 s->cbTotalTransfer = cbTotalTransfer;
4439 Log2(("%s: calling source/sink function\n", __FUNCTION__));
4440 fRedo = g_apfnSourceSinkFuncs[s->iSourceSink](s);
4441 if (RT_UNLIKELY(fRedo))
4442 {
4443 pCtl->pFirstDMADesc = pDesc;
4444 pCtl->pRedoDMABuffer = pBuffer;
4445 pCtl->cbRedoDMABuffer = cbBuffer;
4446 pCtl->fRedoDMALastDesc = fLastDesc;
4447 }
4448 else
4449 {
4450 cbTotalTransfer = s->cbTotalTransfer;
4451 cbElementaryTransfer = s->cbElementaryTransfer;
4452
4453 if (uTxDir == PDMBLOCKTXDIR_TO_DEVICE && cbElementaryTransfer > cbTotalTransfer)
4454 cbElementaryTransfer = cbTotalTransfer;
4455 iIOBufferCur = 0;
4456 iIOBufferEnd = cbElementaryTransfer;
4457 }
4458 pCtl->fRedo = fRedo;
4459 }
4460 else
4461 {
4462 /* This forces the loop to exit immediately. */
4463 pDesc = pCtl->pLastDMADesc + 1;
4464 }
4465
4466 PDMCritSectLeave(&pCtl->lock);
4467 if (RT_UNLIKELY(fRedo))
4468 break;
4469 }
4470 }
4471
4472 if (RT_UNLIKELY(fRedo))
4473 break;
4474
4475 /* end of transfer */
4476 if (!cbTotalTransfer || fLastDesc)
4477 break;
4478
4479 {
4480 STAM_PROFILE_START(&pCtl->StatLockWait, a);
4481 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
4482 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
4483 }
4484
4485 if (!(pCtl->BmDma.u8Cmd & BM_CMD_START) || pCtl->fReset)
4486 {
4487 LogRel(("PIIX3 ATA: Ctl#%d: ABORT DMA%s\n", ATACONTROLLER_IDX(pCtl), pCtl->fReset ? " due to RESET" : ""));
4488 if (!pCtl->fReset)
4489 ataDMATransferStop(s);
4490 /* This forces the loop to exit immediately. */
4491 pDesc = pCtl->pLastDMADesc + 1;
4492 }
4493
4494 PDMCritSectLeave(&pCtl->lock);
4495 }
4496
4497 {
4498 STAM_PROFILE_START(&pCtl->StatLockWait, a);
4499 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
4500 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
4501 }
4502
4503 if (RT_UNLIKELY(fRedo))
4504 return;
4505
4506 if (fLastDesc)
4507 pCtl->BmDma.u8Status &= ~BM_STATUS_DMAING;
4508 s->cbTotalTransfer = cbTotalTransfer;
4509 s->cbElementaryTransfer = cbElementaryTransfer;
4510 s->iIOBufferCur = iIOBufferCur;
4511 s->iIOBufferEnd = iIOBufferEnd;
4512}
4513
4514/**
4515 * Signal PDM that we're idle (if we actually are).
4516 *
4517 * @param pCtl The controller.
4518 */
4519static void ataR3AsyncSignalIdle(PATACONTROLLER pCtl)
4520{
4521 /*
4522 * Take the mutex here and recheck the idle indicator to avoid
4523 * unnecessary work and racing ataR3WaitForAsyncIOIsIdle.
4524 */
4525 int rc = RTSemMutexRequest(pCtl->AsyncIORequestMutex, RT_INDEFINITE_WAIT); AssertRC(rc);
4526
4527 if ( pCtl->fSignalIdle
4528 && ataAsyncIOIsIdle(pCtl, false /*fStrict*/))
4529 {
4530 PDMDevHlpAsyncNotificationCompleted(pCtl->pDevInsR3);
4531 RTThreadUserSignal(pCtl->AsyncIOThread); /* for ataR3Construct/ataR3ResetCommon. */
4532 }
4533
4534 rc = RTSemMutexRelease(pCtl->AsyncIORequestMutex); AssertRC(rc);
4535}
4536
4537/** Asynch I/O thread for an interface. Once upon a time this was readable
4538 * code with several loops and a different semaphore for each purpose. But
4539 * then came the "how can one save the state in the middle of a PIO transfer"
4540 * question. The solution was to use an ASM, which is what's there now. */
4541static DECLCALLBACK(int) ataAsyncIOLoop(RTTHREAD ThreadSelf, void *pvUser)
4542{
4543 const ATARequest *pReq;
4544 uint64_t u64TS = 0; /* shut up gcc */
4545 uint64_t uWait;
4546 int rc = VINF_SUCCESS;
4547 PATACONTROLLER pCtl = (PATACONTROLLER)pvUser;
4548 ATADevState *s;
4549
4550 pReq = NULL;
4551 pCtl->fChainedTransfer = false;
4552 while (!pCtl->fShutdown)
4553 {
4554 /* Keep this thread from doing anything as long as EMT is suspended. */
4555 while (pCtl->fRedoIdle)
4556 {
4557 if (pCtl->fSignalIdle)
4558 ataR3AsyncSignalIdle(pCtl);
4559 rc = RTSemEventWait(pCtl->SuspendIOSem, RT_INDEFINITE_WAIT);
4560 /* Continue if we got a signal by RTThreadPoke().
4561 * We will get notified if there is a request to process.
4562 */
4563 if (RT_UNLIKELY(rc == VERR_INTERRUPTED))
4564 continue;
4565 if (RT_FAILURE(rc) || pCtl->fShutdown)
4566 break;
4567
4568 pCtl->fRedoIdle = false;
4569 }
4570
4571 /* Wait for work. */
4572 while (pReq == NULL)
4573 {
4574 if (pCtl->fSignalIdle)
4575 ataR3AsyncSignalIdle(pCtl);
4576 rc = RTSemEventWait(pCtl->AsyncIOSem, RT_INDEFINITE_WAIT);
4577 /* Continue if we got a signal by RTThreadPoke().
4578 * We will get notified if there is a request to process.
4579 */
4580 if (RT_UNLIKELY(rc == VERR_INTERRUPTED))
4581 continue;
4582 if (RT_FAILURE(rc) || RT_UNLIKELY(pCtl->fShutdown))
4583 break;
4584
4585 pReq = ataAsyncIOGetCurrentRequest(pCtl);
4586 }
4587
4588 if (RT_FAILURE(rc) || pCtl->fShutdown)
4589 break;
4590
4591 if (pReq == NULL)
4592 continue;
4593
4594 ATAAIO ReqType = pReq->ReqType;
4595
4596 Log2(("%s: Ctl#%d: state=%d, req=%d\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl), pCtl->uAsyncIOState, ReqType));
4597 if (pCtl->uAsyncIOState != ReqType)
4598 {
4599 /* The new state is not the state that was expected by the normal
4600 * state changes. This is either a RESET/ABORT or there's something
4601 * really strange going on. */
4602 if ( (pCtl->uAsyncIOState == ATA_AIO_PIO || pCtl->uAsyncIOState == ATA_AIO_DMA)
4603 && (ReqType == ATA_AIO_PIO || ReqType == ATA_AIO_DMA))
4604 {
4605 /* Incorrect sequence of PIO/DMA states. Dump request queue. */
4606 ataAsyncIODumpRequests(pCtl);
4607 }
4608 AssertReleaseMsg(ReqType == ATA_AIO_RESET_ASSERTED || ReqType == ATA_AIO_RESET_CLEARED || ReqType == ATA_AIO_ABORT || pCtl->uAsyncIOState == ReqType, ("I/O state inconsistent: state=%d request=%d\n", pCtl->uAsyncIOState, ReqType));
4609 }
4610
4611 /* Do our work. */
4612 {
4613 STAM_PROFILE_START(&pCtl->StatLockWait, a);
4614 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
4615 STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
4616 }
4617
4618 if (pCtl->uAsyncIOState == ATA_AIO_NEW && !pCtl->fChainedTransfer)
4619 {
4620 u64TS = RTTimeNanoTS();
4621#if defined(DEBUG) || defined(VBOX_WITH_STATISTICS)
4622 STAM_PROFILE_ADV_START(&pCtl->StatAsyncTime, a);
4623#endif /* DEBUG || VBOX_WITH_STATISTICS */
4624 }
4625
4626 switch (ReqType)
4627 {
4628 case ATA_AIO_NEW:
4629
4630 pCtl->iAIOIf = pReq->u.t.iIf;
4631 s = &pCtl->aIfs[pCtl->iAIOIf];
4632 s->cbTotalTransfer = pReq->u.t.cbTotalTransfer;
4633 s->uTxDir = pReq->u.t.uTxDir;
4634 s->iBeginTransfer = pReq->u.t.iBeginTransfer;
4635 s->iSourceSink = pReq->u.t.iSourceSink;
4636 s->iIOBufferEnd = 0;
4637 s->u64CmdTS = u64TS;
4638
4639 if (s->fATAPI)
4640 {
4641 if (pCtl->fChainedTransfer)
4642 {
4643 /* Only count the actual transfers, not the PIO
4644 * transfer of the ATAPI command bytes. */
4645 if (s->fDMA)
4646 STAM_REL_COUNTER_INC(&s->StatATAPIDMA);
4647 else
4648 STAM_REL_COUNTER_INC(&s->StatATAPIPIO);
4649 }
4650 }
4651 else
4652 {
4653 if (s->fDMA)
4654 STAM_REL_COUNTER_INC(&s->StatATADMA);
4655 else
4656 STAM_REL_COUNTER_INC(&s->StatATAPIO);
4657 }
4658
4659 pCtl->fChainedTransfer = false;
4660
4661 if (s->iBeginTransfer != ATAFN_BT_NULL)
4662 {
4663 Log2(("%s: Ctl#%d: calling begin transfer function\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
4664 g_apfnBeginTransFuncs[s->iBeginTransfer](s);
4665 s->iBeginTransfer = ATAFN_BT_NULL;
4666 if (s->uTxDir != PDMBLOCKTXDIR_FROM_DEVICE)
4667 s->iIOBufferEnd = s->cbElementaryTransfer;
4668 }
4669 else
4670 {
4671 s->cbElementaryTransfer = s->cbTotalTransfer;
4672 s->iIOBufferEnd = s->cbTotalTransfer;
4673 }
4674 s->iIOBufferCur = 0;
4675
4676 if (s->uTxDir != PDMBLOCKTXDIR_TO_DEVICE)
4677 {
4678 if (s->iSourceSink != ATAFN_SS_NULL)
4679 {
4680 bool fRedo;
4681 Log2(("%s: Ctl#%d: calling source/sink function\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
4682 fRedo = g_apfnSourceSinkFuncs[s->iSourceSink](s);
4683 pCtl->fRedo = fRedo;
4684 if (RT_UNLIKELY(fRedo && !pCtl->fReset))
4685 {
4686 /* Operation failed at the initial transfer, restart
4687 * everything from scratch by resending the current
4688 * request. Occurs very rarely, not worth optimizing. */
4689 LogRel(("%s: Ctl#%d: redo entire operation\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
4690 ataAsyncIOPutRequest(pCtl, pReq);
4691 break;
4692 }
4693 }
4694 else
4695 ataCmdOK(s, 0);
4696 s->iIOBufferEnd = s->cbElementaryTransfer;
4697
4698 }
4699
4700 /* Do not go into the transfer phase if RESET is asserted.
4701 * The CritSect is released while waiting for the host OS
4702 * to finish the I/O, thus RESET is possible here. Most
4703 * important: do not change uAsyncIOState. */
4704 if (pCtl->fReset)
4705 break;
4706
4707 if (s->fDMA)
4708 {
4709 if (s->cbTotalTransfer)
4710 {
4711 ataSetStatus(s, ATA_STAT_DRQ);
4712
4713 pCtl->uAsyncIOState = ATA_AIO_DMA;
4714 /* If BMDMA is already started, do the transfer now. */
4715 if (pCtl->BmDma.u8Cmd & BM_CMD_START)
4716 {
4717 Log2(("%s: Ctl#%d: message to async I/O thread, continuing DMA transfer immediately\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
4718 ataAsyncIOPutRequest(pCtl, &g_ataDMARequest);
4719 }
4720 }
4721 else
4722 {
4723 Assert(s->uTxDir == PDMBLOCKTXDIR_NONE); /* Any transfer which has an initial transfer size of 0 must be marked as such. */
4724 /* Finish DMA transfer. */
4725 ataDMATransferStop(s);
4726 ataSetIRQ(s);
4727 pCtl->uAsyncIOState = ATA_AIO_NEW;
4728 }
4729 }
4730 else
4731 {
4732 if (s->cbTotalTransfer)
4733 {
4734 ataPIOTransfer(pCtl);
4735 Assert(!pCtl->fRedo);
4736 if (s->fATAPITransfer || s->uTxDir != PDMBLOCKTXDIR_TO_DEVICE)
4737 ataSetIRQ(s);
4738
4739 if (s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE || s->iSourceSink != ATAFN_SS_NULL)
4740 {
4741 /* Write operations and not yet finished transfers
4742 * must be completed in the async I/O thread. */
4743 pCtl->uAsyncIOState = ATA_AIO_PIO;
4744 }
4745 else
4746 {
4747 /* Finished read operation can be handled inline
4748 * in the end of PIO transfer handling code. Linux
4749 * depends on this, as it waits only briefly for
4750 * devices to become ready after incoming data
4751 * transfer. Cannot find anything in the ATA spec
4752 * that backs this assumption, but as all kernels
4753 * are affected (though most of the time it does
4754 * not cause any harm) this must work. */
4755 pCtl->uAsyncIOState = ATA_AIO_NEW;
4756 }
4757 }
4758 else
4759 {
4760 Assert(s->uTxDir == PDMBLOCKTXDIR_NONE); /* Any transfer which has an initial transfer size of 0 must be marked as such. */
4761 /* Finish PIO transfer. */
4762 ataPIOTransfer(pCtl);
4763 Assert(!pCtl->fRedo);
4764 if (!s->fATAPITransfer)
4765 ataSetIRQ(s);
4766 pCtl->uAsyncIOState = ATA_AIO_NEW;
4767 }
4768 }
4769 break;
4770
4771 case ATA_AIO_DMA:
4772 {
4773 BMDMAState *bm = &pCtl->BmDma;
4774 s = &pCtl->aIfs[pCtl->iAIOIf]; /* Do not remove or there's an instant crash after loading the saved state */
4775 ATAFNSS iOriginalSourceSink = (ATAFNSS)s->iSourceSink; /* Used by the hack below, but gets reset by then. */
4776
4777 if (s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE)
4778 AssertRelease(bm->u8Cmd & BM_CMD_WRITE);
4779 else
4780 AssertRelease(!(bm->u8Cmd & BM_CMD_WRITE));
4781
4782 if (RT_LIKELY(!pCtl->fRedo))
4783 {
4784 /* The specs say that the descriptor table must not cross a
4785 * 4K boundary. */
4786 pCtl->pFirstDMADesc = bm->pvAddr;
4787 pCtl->pLastDMADesc = RT_ALIGN_32(bm->pvAddr + 1, _4K) - sizeof(BMDMADesc);
4788 }
4789 ataDMATransfer(pCtl);
4790
4791 if (RT_UNLIKELY(pCtl->fRedo && !pCtl->fReset))
4792 {
4793 LogRel(("PIIX3 ATA: Ctl#%d: redo DMA operation\n", ATACONTROLLER_IDX(pCtl)));
4794 ataAsyncIOPutRequest(pCtl, &g_ataDMARequest);
4795 break;
4796 }
4797
4798 /* The infamous delay IRQ hack. */
4799 if ( iOriginalSourceSink == ATAFN_SS_WRITE_SECTORS
4800 && s->cbTotalTransfer == 0
4801 && pCtl->DelayIRQMillies)
4802 {
4803 /* Delay IRQ for writing. Required to get the Win2K
4804 * installation work reliably (otherwise it crashes,
4805 * usually during component install). So far no better
4806 * solution has been found. */
4807 Log(("%s: delay IRQ hack\n", __FUNCTION__));
4808 PDMCritSectLeave(&pCtl->lock);
4809 RTThreadSleep(pCtl->DelayIRQMillies);
4810 PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
4811 }
4812
4813 ataUnsetStatus(s, ATA_STAT_DRQ);
4814 Assert(!pCtl->fChainedTransfer);
4815 Assert(s->iSourceSink == ATAFN_SS_NULL);
4816 if (s->fATAPITransfer)
4817 {
4818 s->uATARegNSector = (s->uATARegNSector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
4819 Log2(("%s: Ctl#%d: interrupt reason %#04x\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl), s->uATARegNSector));
4820 s->fATAPITransfer = false;
4821 }
4822 ataSetIRQ(s);
4823 pCtl->uAsyncIOState = ATA_AIO_NEW;
4824 break;
4825 }
4826
4827 case ATA_AIO_PIO:
4828 s = &pCtl->aIfs[pCtl->iAIOIf]; /* Do not remove or there's an instant crash after loading the saved state */
4829
4830 if (s->iSourceSink != ATAFN_SS_NULL)
4831 {
4832 bool fRedo;
4833 Log2(("%s: Ctl#%d: calling source/sink function\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
4834 fRedo = g_apfnSourceSinkFuncs[s->iSourceSink](s);
4835 pCtl->fRedo = fRedo;
4836 if (RT_UNLIKELY(fRedo && !pCtl->fReset))
4837 {
4838 LogRel(("PIIX3 ATA: Ctl#%d: redo PIO operation\n", ATACONTROLLER_IDX(pCtl)));
4839 ataAsyncIOPutRequest(pCtl, &g_ataPIORequest);
4840 ataSuspendRedo(pCtl);
4841 break;
4842 }
4843 s->iIOBufferCur = 0;
4844 s->iIOBufferEnd = s->cbElementaryTransfer;
4845 }
4846 else
4847 {
4848 /* Continue a previously started transfer. */
4849 ataUnsetStatus(s, ATA_STAT_BUSY);
4850 ataSetStatus(s, ATA_STAT_READY);
4851 }
4852
4853 /* It is possible that the drives on this controller get RESET
4854 * during the above call to the source/sink function. If that's
4855 * the case, don't restart the transfer and don't finish it the
4856 * usual way. RESET handling took care of all that already.
4857 * Most important: do not change uAsyncIOState. */
4858 if (pCtl->fReset)
4859 break;
4860
4861 if (s->cbTotalTransfer)
4862 {
4863 ataPIOTransfer(pCtl);
4864 ataSetIRQ(s);
4865
4866 if (s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE || s->iSourceSink != ATAFN_SS_NULL)
4867 {
4868 /* Write operations and not yet finished transfers
4869 * must be completed in the async I/O thread. */
4870 pCtl->uAsyncIOState = ATA_AIO_PIO;
4871 }
4872 else
4873 {
4874 /* Finished read operation can be handled inline
4875 * in the end of PIO transfer handling code. Linux
4876 * depends on this, as it waits only briefly for
4877 * devices to become ready after incoming data
4878 * transfer. Cannot find anything in the ATA spec
4879 * that backs this assumption, but as all kernels
4880 * are affected (though most of the time it does
4881 * not cause any harm) this must work. */
4882 pCtl->uAsyncIOState = ATA_AIO_NEW;
4883 }
4884 }
4885 else
4886 {
4887 /* Finish PIO transfer. */
4888 ataPIOTransfer(pCtl);
4889 if ( !pCtl->fChainedTransfer
4890 && !s->fATAPITransfer
4891 && s->uTxDir != PDMBLOCKTXDIR_FROM_DEVICE)
4892 {
4893 ataSetIRQ(s);
4894 }
4895 pCtl->uAsyncIOState = ATA_AIO_NEW;
4896 }
4897 break;
4898
4899 case ATA_AIO_RESET_ASSERTED:
4900 pCtl->uAsyncIOState = ATA_AIO_RESET_CLEARED;
4901 ataPIOTransferStop(&pCtl->aIfs[0]);
4902 ataPIOTransferStop(&pCtl->aIfs[1]);
4903 /* Do not change the DMA registers, they are not affected by the
4904 * ATA controller reset logic. It should be sufficient to issue a
4905 * new command, which is now possible as the state is cleared. */
4906 break;
4907
4908 case ATA_AIO_RESET_CLEARED:
4909 pCtl->uAsyncIOState = ATA_AIO_NEW;
4910 pCtl->fReset = false;
4911 /* Ensure that half-completed transfers are not redone. A reset
4912 * cancels the entire transfer, so continuing is wrong. */
4913 pCtl->fRedo = false;
4914 pCtl->fRedoDMALastDesc = false;
4915 LogRel(("PIIX3 ATA: Ctl#%d: finished processing RESET\n",
4916 ATACONTROLLER_IDX(pCtl)));
4917 for (uint32_t i = 0; i < RT_ELEMENTS(pCtl->aIfs); i++)
4918 {
4919 if (pCtl->aIfs[i].fATAPI)
4920 ataSetStatusValue(&pCtl->aIfs[i], 0); /* NOTE: READY is _not_ set */
4921 else
4922 ataSetStatusValue(&pCtl->aIfs[i], ATA_STAT_READY | ATA_STAT_SEEK);
4923 ataSetSignature(&pCtl->aIfs[i]);
4924 }
4925 break;
4926
4927 case ATA_AIO_ABORT:
4928 /* Abort the current command only if it operates on the same interface. */
4929 if (pCtl->iAIOIf == pReq->u.a.iIf)
4930 {
4931 s = &pCtl->aIfs[pCtl->iAIOIf];
4932
4933 pCtl->uAsyncIOState = ATA_AIO_NEW;
4934 /* Do not change the DMA registers, they are not affected by the
4935 * ATA controller reset logic. It should be sufficient to issue a
4936 * new command, which is now possible as the state is cleared. */
4937 if (pReq->u.a.fResetDrive)
4938 {
4939 ataResetDevice(s);
4940 ataExecuteDeviceDiagnosticSS(s);
4941 }
4942 else
4943 {
4944 /* Stop any pending DMA transfer. */
4945 s->fDMA = false;
4946 ataPIOTransferStop(s);
4947 ataUnsetStatus(s, ATA_STAT_BUSY | ATA_STAT_DRQ | ATA_STAT_SEEK | ATA_STAT_ERR);
4948 ataSetStatus(s, ATA_STAT_READY);
4949 ataSetIRQ(s);
4950 }
4951 }
4952 break;
4953
4954 default:
4955 AssertMsgFailed(("Undefined async I/O state %d\n", pCtl->uAsyncIOState));
4956 }
4957
4958 ataAsyncIORemoveCurrentRequest(pCtl, ReqType);
4959 pReq = ataAsyncIOGetCurrentRequest(pCtl);
4960
4961 if (pCtl->uAsyncIOState == ATA_AIO_NEW && !pCtl->fChainedTransfer)
4962 {
4963#if defined(DEBUG) || defined(VBOX_WITH_STATISTICS)
4964 STAM_PROFILE_ADV_STOP(&pCtl->StatAsyncTime, a);
4965#endif /* DEBUG || VBOX_WITH_STATISTICS */
4966
4967 u64TS = RTTimeNanoTS() - u64TS;
4968 uWait = u64TS / 1000;
4969 Log(("%s: Ctl#%d: LUN#%d finished I/O transaction in %d microseconds\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl), pCtl->aIfs[pCtl->iAIOIf].iLUN, (uint32_t)(uWait)));
4970 /* Mark command as finished. */
4971 pCtl->aIfs[pCtl->iAIOIf].u64CmdTS = 0;
4972
4973 /*
4974 * Release logging of command execution times depends on the
4975 * command type. ATAPI commands often take longer (due to CD/DVD
4976 * spin up time etc.) so the threshold is different.
4977 */
4978 if (pCtl->aIfs[pCtl->iAIOIf].uATARegCommand != ATA_PACKET)
4979 {
4980 if (uWait > 8 * 1000 * 1000)
4981 {
4982 /*
4983 * Command took longer than 8 seconds. This is close
4984 * enough or over the guest's command timeout, so place
4985 * an entry in the release log to allow tracking such
4986 * timing errors (which are often caused by the host).
4987 */
4988 LogRel(("PIIX3 ATA: execution time for ATA command %#04x was %d seconds\n", pCtl->aIfs[pCtl->iAIOIf].uATARegCommand, uWait / (1000 * 1000)));
4989 }
4990 }
4991 else
4992 {
4993 if (uWait > 20 * 1000 * 1000)
4994 {
4995 /*
4996 * Command took longer than 20 seconds. This is close
4997 * enough or over the guest's command timeout, so place
4998 * an entry in the release log to allow tracking such
4999 * timing errors (which are often caused by the host).
5000 */
5001 LogRel(("PIIX3 ATA: execution time for ATAPI command %#04x was %d seconds\n", pCtl->aIfs[pCtl->iAIOIf].aATAPICmd[0], uWait / (1000 * 1000)));
5002 }
5003 }
5004
5005#if defined(DEBUG) || defined(VBOX_WITH_STATISTICS)
5006 if (uWait < pCtl->StatAsyncMinWait || !pCtl->StatAsyncMinWait)
5007 pCtl->StatAsyncMinWait = uWait;
5008 if (uWait > pCtl->StatAsyncMaxWait)
5009 pCtl->StatAsyncMaxWait = uWait;
5010
5011 STAM_COUNTER_ADD(&pCtl->StatAsyncTimeUS, uWait);
5012 STAM_COUNTER_INC(&pCtl->StatAsyncOps);
5013#endif /* DEBUG || VBOX_WITH_STATISTICS */
5014 }
5015
5016 PDMCritSectLeave(&pCtl->lock);
5017 }
5018
5019 /* Signal the ultimate idleness. */
5020 RTThreadUserSignal(pCtl->AsyncIOThread);
5021 if (pCtl->fSignalIdle)
5022 PDMDevHlpAsyncNotificationCompleted(pCtl->pDevInsR3);
5023
5024 /* Cleanup the state. */
5025 /* Do not destroy request mutex yet, still needed for proper shutdown. */
5026 pCtl->fShutdown = false;
5027
5028 Log2(("%s: Ctl#%d: return %Rrc\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl), rc));
5029 return rc;
5030}
5031
5032#endif /* IN_RING3 */
5033
5034static uint32_t ataBMDMACmdReadB(PATACONTROLLER pCtl, uint32_t addr)
5035{
5036 uint32_t val = pCtl->BmDma.u8Cmd;
5037 Log2(("%s: addr=%#06x val=%#04x\n", __FUNCTION__, addr, val));
5038 return val;
5039}
5040
5041
5042static void ataBMDMACmdWriteB(PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
5043{
5044 Log2(("%s: addr=%#06x val=%#04x\n", __FUNCTION__, addr, val));
5045 if (!(val & BM_CMD_START))
5046 {
5047 pCtl->BmDma.u8Status &= ~BM_STATUS_DMAING;
5048 pCtl->BmDma.u8Cmd = val & (BM_CMD_START | BM_CMD_WRITE);
5049 }
5050 else
5051 {
5052#ifdef IN_RING3
5053 /* Check whether the guest OS wants to change DMA direction in
5054 * mid-flight. Not allowed, according to the PIIX3 specs. */
5055 Assert(!(pCtl->BmDma.u8Status & BM_STATUS_DMAING) || !((val ^ pCtl->BmDma.u8Cmd) & 0x04));
5056 pCtl->BmDma.u8Status |= BM_STATUS_DMAING;
5057 pCtl->BmDma.u8Cmd = val & (BM_CMD_START | BM_CMD_WRITE);
5058
5059 /* Do not continue DMA transfers while the RESET line is asserted. */
5060 if (pCtl->fReset)
5061 {
5062 Log2(("%s: Ctl#%d: suppressed continuing DMA transfer as RESET is active\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
5063 return;
5064 }
5065
5066 /* Do not start DMA transfers if there's a PIO transfer going on. */
5067 if (!pCtl->aIfs[pCtl->iSelectedIf].fDMA)
5068 return;
5069
5070 if (pCtl->aIfs[pCtl->iAIOIf].uATARegStatus & ATA_STAT_DRQ)
5071 {
5072 Log2(("%s: Ctl#%d: message to async I/O thread, continuing DMA transfer\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
5073 ataAsyncIOPutRequest(pCtl, &g_ataDMARequest);
5074 }
5075#else /* !IN_RING3 */
5076 AssertMsgFailed(("DMA START handling is too complicated for GC\n"));
5077#endif /* IN_RING3 */
5078 }
5079}
5080
5081static uint32_t ataBMDMAStatusReadB(PATACONTROLLER pCtl, uint32_t addr)
5082{
5083 uint32_t val = pCtl->BmDma.u8Status;
5084 Log2(("%s: addr=%#06x val=%#04x\n", __FUNCTION__, addr, val));
5085 return val;
5086}
5087
5088static void ataBMDMAStatusWriteB(PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
5089{
5090 Log2(("%s: addr=%#06x val=%#04x\n", __FUNCTION__, addr, val));
5091 pCtl->BmDma.u8Status = (val & (BM_STATUS_D0DMA | BM_STATUS_D1DMA))
5092 | (pCtl->BmDma.u8Status & BM_STATUS_DMAING)
5093 | (pCtl->BmDma.u8Status & ~val & (BM_STATUS_ERROR | BM_STATUS_INT));
5094}
5095
5096static uint32_t ataBMDMAAddrReadL(PATACONTROLLER pCtl, uint32_t addr)
5097{
5098 uint32_t val = (uint32_t)pCtl->BmDma.pvAddr;
5099 Log2(("%s: addr=%#06x val=%#010x\n", __FUNCTION__, addr, val));
5100 return val;
5101}
5102
5103static void ataBMDMAAddrWriteL(PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
5104{
5105 Log2(("%s: addr=%#06x val=%#010x\n", __FUNCTION__, addr, val));
5106 pCtl->BmDma.pvAddr = val & ~3;
5107}
5108
5109static void ataBMDMAAddrWriteLowWord(PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
5110{
5111 Log2(("%s: addr=%#06x val=%#010x\n", __FUNCTION__, addr, val));
5112 pCtl->BmDma.pvAddr = (pCtl->BmDma.pvAddr & 0xFFFF0000) | RT_LOWORD(val & ~3);
5113
5114}
5115
5116static void ataBMDMAAddrWriteHighWord(PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
5117{
5118 Log2(("%s: addr=%#06x val=%#010x\n", __FUNCTION__, addr, val));
5119 pCtl->BmDma.pvAddr = (RT_LOWORD(val) << 16) | RT_LOWORD(pCtl->BmDma.pvAddr);
5120}
5121
5122#define VAL(port, size) ( ((port) & 7) | ((size) << 3) )
5123
5124/**
5125 * Port I/O Handler for bus master DMA IN operations.
5126 * @see FNIOMIOPORTIN for details.
5127 */
5128PDMBOTHCBDECL(int) ataBMDMAIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
5129{
5130 uint32_t i = (uint32_t)(uintptr_t)pvUser;
5131 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
5132 PATACONTROLLER pCtl = &pThis->aCts[i];
5133 int rc;
5134
5135 rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_HC_IOPORT_READ);
5136 if (rc != VINF_SUCCESS)
5137 return rc;
5138 switch (VAL(Port, cb))
5139 {
5140 case VAL(0, 1): *pu32 = ataBMDMACmdReadB(pCtl, Port); break;
5141 case VAL(0, 2): *pu32 = ataBMDMACmdReadB(pCtl, Port); break;
5142 case VAL(2, 1): *pu32 = ataBMDMAStatusReadB(pCtl, Port); break;
5143 case VAL(2, 2): *pu32 = ataBMDMAStatusReadB(pCtl, Port); break;
5144 case VAL(4, 4): *pu32 = ataBMDMAAddrReadL(pCtl, Port); break;
5145 case VAL(0, 4):
5146 /* The SCO OpenServer tries to read 4 bytes starting from offset 0. */
5147 *pu32 = ataBMDMACmdReadB(pCtl, Port) | (ataBMDMAStatusReadB(pCtl, Port) << 16);
5148 break;
5149 default:
5150 AssertMsgFailed(("%s: Unsupported read from port %x size=%d\n", __FUNCTION__, Port, cb));
5151 PDMCritSectLeave(&pCtl->lock);
5152 return VERR_IOM_IOPORT_UNUSED;
5153 }
5154 PDMCritSectLeave(&pCtl->lock);
5155 return rc;
5156}
5157
5158/**
5159 * Port I/O Handler for bus master DMA OUT operations.
5160 * @see FNIOMIOPORTOUT for details.
5161 */
5162PDMBOTHCBDECL(int) ataBMDMAIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
5163{
5164 uint32_t i = (uint32_t)(uintptr_t)pvUser;
5165 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
5166 PATACONTROLLER pCtl = &pThis->aCts[i];
5167 int rc;
5168
5169 rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_HC_IOPORT_WRITE);
5170 if (rc != VINF_SUCCESS)
5171 return rc;
5172 switch (VAL(Port, cb))
5173 {
5174 case VAL(0, 1):
5175#ifndef IN_RING3
5176 if (u32 & BM_CMD_START)
5177 {
5178 rc = VINF_IOM_HC_IOPORT_WRITE;
5179 break;
5180 }
5181#endif /* !IN_RING3 */
5182 ataBMDMACmdWriteB(pCtl, Port, u32);
5183 break;
5184 case VAL(2, 1): ataBMDMAStatusWriteB(pCtl, Port, u32); break;
5185 case VAL(4, 4): ataBMDMAAddrWriteL(pCtl, Port, u32); break;
5186 case VAL(4, 2): ataBMDMAAddrWriteLowWord(pCtl, Port, u32); break;
5187 case VAL(6, 2): ataBMDMAAddrWriteHighWord(pCtl, Port, u32); break;
5188 default: AssertMsgFailed(("%s: Unsupported write to port %x size=%d val=%x\n", __FUNCTION__, Port, cb, u32)); break;
5189 }
5190 PDMCritSectLeave(&pCtl->lock);
5191 return rc;
5192}
5193
5194#undef VAL
5195
5196#ifdef IN_RING3
5197
5198/**
5199 * Callback function for mapping an PCI I/O region.
5200 *
5201 * @return VBox status code.
5202 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
5203 * @param iRegion The region number.
5204 * @param GCPhysAddress Physical address of the region. If iType is PCI_ADDRESS_SPACE_IO, this is an
5205 * I/O port, else it's a physical address.
5206 * This address is *NOT* relative to pci_mem_base like earlier!
5207 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
5208 */
5209static DECLCALLBACK(int) ataBMDMAIORangeMap(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
5210{
5211 PCIATAState *pThis = PCIDEV_2_PCIATASTATE(pPciDev);
5212 int rc = VINF_SUCCESS;
5213 Assert(enmType == PCI_ADDRESS_SPACE_IO);
5214 Assert(iRegion == 4);
5215 AssertMsg(RT_ALIGN(GCPhysAddress, 8) == GCPhysAddress, ("Expected 8 byte alignment. GCPhysAddress=%#x\n", GCPhysAddress));
5216
5217 /* Register the port range. */
5218 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
5219 {
5220 int rc2 = PDMDevHlpIOPortRegister(pPciDev->pDevIns, (RTIOPORT)GCPhysAddress + i * 8, 8,
5221 (RTHCPTR)i, ataBMDMAIOPortWrite, ataBMDMAIOPortRead, NULL, NULL, "ATA Bus Master DMA");
5222 AssertRC(rc2);
5223 if (rc2 < rc)
5224 rc = rc2;
5225
5226 if (pThis->fGCEnabled)
5227 {
5228 rc2 = PDMDevHlpIOPortRegisterGC(pPciDev->pDevIns, (RTIOPORT)GCPhysAddress + i * 8, 8,
5229 (RTGCPTR)i, "ataBMDMAIOPortWrite", "ataBMDMAIOPortRead", NULL, NULL, "ATA Bus Master DMA");
5230 AssertRC(rc2);
5231 if (rc2 < rc)
5232 rc = rc2;
5233 }
5234 if (pThis->fR0Enabled)
5235 {
5236 rc2 = PDMDevHlpIOPortRegisterR0(pPciDev->pDevIns, (RTIOPORT)GCPhysAddress + i * 8, 8,
5237 (RTR0PTR)i, "ataBMDMAIOPortWrite", "ataBMDMAIOPortRead", NULL, NULL, "ATA Bus Master DMA");
5238 AssertRC(rc2);
5239 if (rc2 < rc)
5240 rc = rc2;
5241 }
5242 }
5243 return rc;
5244}
5245
5246
5247/* -=-=-=-=-=- PCIATAState::IBase -=-=-=-=-=- */
5248
5249/**
5250 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
5251 */
5252static DECLCALLBACK(void *) ataStatus_QueryInterface(PPDMIBASE pInterface, const char *pszIID)
5253{
5254 PCIATAState *pThis = PDMIBASE_2_PCIATASTATE(pInterface);
5255 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
5256 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
5257 return NULL;
5258}
5259
5260
5261/* -=-=-=-=-=- PCIATAState::ILeds -=-=-=-=-=- */
5262
5263/**
5264 * Gets the pointer to the status LED of a unit.
5265 *
5266 * @returns VBox status code.
5267 * @param pInterface Pointer to the interface structure containing the called function pointer.
5268 * @param iLUN The unit which status LED we desire.
5269 * @param ppLed Where to store the LED pointer.
5270 */
5271static DECLCALLBACK(int) ataStatus_QueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
5272{
5273 PCIATAState *pThis = PDMILEDPORTS_2_PCIATASTATE(pInterface);
5274 if (iLUN < 4)
5275 {
5276 switch (iLUN)
5277 {
5278 case 0: *ppLed = &pThis->aCts[0].aIfs[0].Led; break;
5279 case 1: *ppLed = &pThis->aCts[0].aIfs[1].Led; break;
5280 case 2: *ppLed = &pThis->aCts[1].aIfs[0].Led; break;
5281 case 3: *ppLed = &pThis->aCts[1].aIfs[1].Led; break;
5282 }
5283 Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
5284 return VINF_SUCCESS;
5285 }
5286 return VERR_PDM_LUN_NOT_FOUND;
5287}
5288
5289
5290/* -=-=-=-=-=- ATADevState::IBase -=-=-=-=-=- */
5291
5292/**
5293 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
5294 */
5295static DECLCALLBACK(void *) ataQueryInterface(PPDMIBASE pInterface, const char *pszIID)
5296{
5297 ATADevState *pIf = PDMIBASE_2_ATASTATE(pInterface);
5298 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pIf->IBase);
5299 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBLOCKPORT, &pIf->IPort);
5300 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIMOUNTNOTIFY, &pIf->IMountNotify);
5301 return NULL;
5302}
5303
5304#endif /* IN_RING3 */
5305
5306
5307/* -=-=-=-=-=- Wrappers -=-=-=-=-=- */
5308
5309/**
5310 * Port I/O Handler for primary port range OUT operations.
5311 * @see FNIOMIOPORTOUT for details.
5312 */
5313PDMBOTHCBDECL(int) ataIOPortWrite1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
5314{
5315 uint32_t i = (uint32_t)(uintptr_t)pvUser;
5316 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
5317 PATACONTROLLER pCtl = &pThis->aCts[i];
5318 int rc = VINF_SUCCESS;
5319
5320 Assert(i < 2);
5321
5322 rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_HC_IOPORT_WRITE);
5323 if (rc != VINF_SUCCESS)
5324 return rc;
5325 if (cb == 1)
5326 rc = ataIOPortWriteU8(pCtl, Port, u32);
5327 else if (Port == pCtl->IOPortBase1)
5328 {
5329 Assert(cb == 2 || cb == 4);
5330 rc = ataDataWrite(pCtl, Port, cb, (const uint8_t *)&u32);
5331 }
5332 else
5333 AssertMsgFailed(("ataIOPortWrite1: unsupported write to port %x val=%x size=%d\n", Port, u32, cb));
5334 PDMCritSectLeave(&pCtl->lock);
5335 return rc;
5336}
5337
5338
5339/**
5340 * Port I/O Handler for primary port range IN operations.
5341 * @see FNIOMIOPORTIN for details.
5342 */
5343PDMBOTHCBDECL(int) ataIOPortRead1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
5344{
5345 uint32_t i = (uint32_t)(uintptr_t)pvUser;
5346 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
5347 PATACONTROLLER pCtl = &pThis->aCts[i];
5348 int rc = VINF_SUCCESS;
5349
5350 Assert(i < 2);
5351
5352 rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_HC_IOPORT_READ);
5353 if (rc != VINF_SUCCESS)
5354 return rc;
5355 if (cb == 1)
5356 {
5357 rc = ataIOPortReadU8(pCtl, Port, pu32);
5358 }
5359 else if (Port == pCtl->IOPortBase1)
5360 {
5361 Assert(cb == 2 || cb == 4);
5362 rc = ataDataRead(pCtl, Port, cb, (uint8_t *)pu32);
5363 if (cb == 2)
5364 *pu32 &= 0xffff;
5365 }
5366 else
5367 {
5368 AssertMsgFailed(("ataIOPortRead1: unsupported read from port %x size=%d\n", Port, cb));
5369 rc = VERR_IOM_IOPORT_UNUSED;
5370 }
5371 PDMCritSectLeave(&pCtl->lock);
5372 return rc;
5373}
5374
5375#ifndef IN_RING0 /** @todo do this in ring-0 as well. */
5376/**
5377 * Port I/O Handler for primary port range IN string operations.
5378 * @see FNIOMIOPORTINSTRING for details.
5379 */
5380PDMBOTHCBDECL(int) ataIOPortReadStr1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrDst, PRTGCUINTREG pcTransfer, unsigned cb)
5381{
5382 uint32_t i = (uint32_t)(uintptr_t)pvUser;
5383 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
5384 PATACONTROLLER pCtl = &pThis->aCts[i];
5385 int rc = VINF_SUCCESS;
5386
5387 Assert(i < 2);
5388
5389 rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_HC_IOPORT_READ);
5390 if (rc != VINF_SUCCESS)
5391 return rc;
5392 if (Port == pCtl->IOPortBase1)
5393 {
5394 uint32_t cTransAvailable, cTransfer = *pcTransfer, cbTransfer;
5395 RTGCPTR GCDst = *pGCPtrDst;
5396 ATADevState *s = &pCtl->aIfs[pCtl->iSelectedIf];
5397 Assert(cb == 2 || cb == 4);
5398
5399 cTransAvailable = (s->iIOBufferPIODataEnd - s->iIOBufferPIODataStart) / cb;
5400#ifndef IN_RING3
5401 /* Deal with the unlikely case where no data (or not enough for the read length operation) is available; go back to ring 3. */
5402 if (!cTransAvailable)
5403 {
5404 PDMCritSectLeave(&pCtl->lock);
5405 return VINF_IOM_HC_IOPORT_READ;
5406 }
5407 /* The last transfer unit cannot be handled in GC, as it involves thread communication. */
5408 cTransAvailable--;
5409#endif /* !IN_RING3 */
5410 /* Do not handle the dummy transfer stuff here, leave it to the single-word transfers.
5411 * They are not performance-critical and generally shouldn't occur at all. */
5412 if (cTransAvailable > cTransfer)
5413 cTransAvailable = cTransfer;
5414 cbTransfer = cTransAvailable * cb;
5415
5416 rc = PGMPhysSimpleDirtyWriteGCPtr(PDMDevHlpGetVMCPU(pDevIns), GCDst, s->CTX_SUFF(pbIOBuffer) + s->iIOBufferPIODataStart, cbTransfer);
5417 Assert(rc == VINF_SUCCESS);
5418
5419 if (cbTransfer)
5420 Log3(("%s: addr=%#x val=%.*Rhxs\n", __FUNCTION__, Port, cbTransfer, s->CTX_SUFF(pbIOBuffer) + s->iIOBufferPIODataStart));
5421 s->iIOBufferPIODataStart += cbTransfer;
5422 *pGCPtrDst = (RTGCPTR)((RTGCUINTPTR)GCDst + cbTransfer);
5423 *pcTransfer = cTransfer - cTransAvailable;
5424#ifdef IN_RING3
5425 if (s->iIOBufferPIODataStart >= s->iIOBufferPIODataEnd)
5426 ataPIOTransferFinish(pCtl, s);
5427#endif /* IN_RING3 */
5428 }
5429 PDMCritSectLeave(&pCtl->lock);
5430 return rc;
5431}
5432
5433
5434/**
5435 * Port I/O Handler for primary port range OUT string operations.
5436 * @see FNIOMIOPORTOUTSTRING for details.
5437 */
5438PDMBOTHCBDECL(int) ataIOPortWriteStr1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrSrc, PRTGCUINTREG pcTransfer, unsigned cb)
5439{
5440 uint32_t i = (uint32_t)(uintptr_t)pvUser;
5441 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
5442 PATACONTROLLER pCtl = &pThis->aCts[i];
5443 int rc;
5444
5445 Assert(i < 2);
5446
5447 rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_HC_IOPORT_WRITE);
5448 if (rc != VINF_SUCCESS)
5449 return rc;
5450 if (Port == pCtl->IOPortBase1)
5451 {
5452 uint32_t cTransAvailable, cTransfer = *pcTransfer, cbTransfer;
5453 RTGCPTR GCSrc = *pGCPtrSrc;
5454 ATADevState *s = &pCtl->aIfs[pCtl->iSelectedIf];
5455 Assert(cb == 2 || cb == 4);
5456
5457 cTransAvailable = (s->iIOBufferPIODataEnd - s->iIOBufferPIODataStart) / cb;
5458#ifndef IN_RING3
5459 /* Deal with the unlikely case where no data (or not enough for the read length operation) is available; go back to ring 3. */
5460 if (!cTransAvailable)
5461 {
5462 PDMCritSectLeave(&pCtl->lock);
5463 return VINF_IOM_HC_IOPORT_WRITE;
5464 }
5465 /* The last transfer unit cannot be handled in GC, as it involves thread communication. */
5466 cTransAvailable--;
5467#endif /* !IN_RING3 */
5468 /* Do not handle the dummy transfer stuff here, leave it to the single-word transfers.
5469 * They are not performance-critical and generally shouldn't occur at all. */
5470 if (cTransAvailable > cTransfer)
5471 cTransAvailable = cTransfer;
5472 cbTransfer = cTransAvailable * cb;
5473
5474 rc = PGMPhysSimpleReadGCPtr(PDMDevHlpGetVMCPU(pDevIns), s->CTX_SUFF(pbIOBuffer) + s->iIOBufferPIODataStart, GCSrc, cbTransfer);
5475 Assert(rc == VINF_SUCCESS);
5476
5477 if (cbTransfer)
5478 Log3(("%s: addr=%#x val=%.*Rhxs\n", __FUNCTION__, Port, cbTransfer, s->CTX_SUFF(pbIOBuffer) + s->iIOBufferPIODataStart));
5479 s->iIOBufferPIODataStart += cbTransfer;
5480 *pGCPtrSrc = (RTGCPTR)((RTGCUINTPTR)GCSrc + cbTransfer);
5481 *pcTransfer = cTransfer - cTransAvailable;
5482#ifdef IN_RING3
5483 if (s->iIOBufferPIODataStart >= s->iIOBufferPIODataEnd)
5484 ataPIOTransferFinish(pCtl, s);
5485#endif /* IN_RING3 */
5486 }
5487 PDMCritSectLeave(&pCtl->lock);
5488 return rc;
5489}
5490#endif /* !IN_RING0 */
5491
5492/**
5493 * Port I/O Handler for secondary port range OUT operations.
5494 * @see FNIOMIOPORTOUT for details.
5495 */
5496PDMBOTHCBDECL(int) ataIOPortWrite2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
5497{
5498 uint32_t i = (uint32_t)(uintptr_t)pvUser;
5499 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
5500 PATACONTROLLER pCtl = &pThis->aCts[i];
5501 int rc;
5502
5503 Assert(i < 2);
5504
5505 if (cb != 1)
5506 return VINF_SUCCESS;
5507 rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_HC_IOPORT_WRITE);
5508 if (rc != VINF_SUCCESS)
5509 return rc;
5510 rc = ataControlWrite(pCtl, Port, u32);
5511 PDMCritSectLeave(&pCtl->lock);
5512 return rc;
5513}
5514
5515
5516/**
5517 * Port I/O Handler for secondary port range IN operations.
5518 * @see FNIOMIOPORTIN for details.
5519 */
5520PDMBOTHCBDECL(int) ataIOPortRead2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
5521{
5522 uint32_t i = (uint32_t)(uintptr_t)pvUser;
5523 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
5524 PATACONTROLLER pCtl = &pThis->aCts[i];
5525 int rc;
5526
5527 Assert(i < 2);
5528
5529 if (cb != 1)
5530 return VERR_IOM_IOPORT_UNUSED;
5531
5532 rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_HC_IOPORT_READ);
5533 if (rc != VINF_SUCCESS)
5534 return rc;
5535 *pu32 = ataStatusRead(pCtl, Port);
5536 PDMCritSectLeave(&pCtl->lock);
5537 return VINF_SUCCESS;
5538}
5539
5540#ifdef IN_RING3
5541
5542
5543DECLINLINE(void) ataRelocBuffer(PPDMDEVINS pDevIns, ATADevState *s)
5544{
5545 if (s->pbIOBufferR3)
5546 s->pbIOBufferRC = MMHyperR3ToRC(PDMDevHlpGetVM(pDevIns), s->pbIOBufferR3);
5547}
5548
5549
5550/**
5551 * @copydoc FNPDMDEVRELOCATE
5552 */
5553static DECLCALLBACK(void) ataR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
5554{
5555 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
5556
5557 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
5558 {
5559 pThis->aCts[i].pDevInsRC += offDelta;
5560 pThis->aCts[i].aIfs[0].pDevInsRC += offDelta;
5561 pThis->aCts[i].aIfs[0].pControllerRC += offDelta;
5562 ataRelocBuffer(pDevIns, &pThis->aCts[i].aIfs[0]);
5563 pThis->aCts[i].aIfs[1].pDevInsRC += offDelta;
5564 pThis->aCts[i].aIfs[1].pControllerRC += offDelta;
5565 ataRelocBuffer(pDevIns, &pThis->aCts[i].aIfs[1]);
5566 }
5567}
5568
5569
5570/**
5571 * Destroy a driver instance.
5572 *
5573 * Most VM resources are freed by the VM. This callback is provided so that any non-VM
5574 * resources can be freed correctly.
5575 *
5576 * @param pDevIns The device instance data.
5577 */
5578static DECLCALLBACK(int) ataR3Destruct(PPDMDEVINS pDevIns)
5579{
5580 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
5581 int rc;
5582
5583 Log(("ataR3Destruct\n"));
5584
5585 /*
5586 * Tell the async I/O threads to terminate.
5587 */
5588 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
5589 {
5590 if (pThis->aCts[i].AsyncIOThread != NIL_RTTHREAD)
5591 {
5592 ASMAtomicWriteU32(&pThis->aCts[i].fShutdown, true);
5593 rc = RTSemEventSignal(pThis->aCts[i].AsyncIOSem);
5594 AssertRC(rc);
5595 }
5596 }
5597
5598 /*
5599 * Wait for the threads to terminate before destroying their resources.
5600 */
5601 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
5602 {
5603 if (pThis->aCts[i].AsyncIOThread != NIL_RTTHREAD)
5604 {
5605 rc = RTThreadWait(pThis->aCts[i].AsyncIOThread, 30000 /* 30 s*/, NULL);
5606 if (RT_SUCCESS(rc))
5607 pThis->aCts[i].AsyncIOThread = NIL_RTTHREAD;
5608 else
5609 LogRel(("PIIX3 ATA Dtor: Ctl#%u is still executing, DevSel=%d AIOIf=%d CmdIf0=%#04x CmdIf1=%#04x rc=%Rrc\n",
5610 i, pThis->aCts[i].iSelectedIf, pThis->aCts[i].iAIOIf,
5611 pThis->aCts[i].aIfs[0].uATARegCommand, pThis->aCts[i].aIfs[1].uATARegCommand, rc));
5612 }
5613 }
5614
5615 /*
5616 * Free resources.
5617 */
5618 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
5619 {
5620 if (pThis->aCts[i].AsyncIORequestMutex != NIL_RTSEMMUTEX)
5621 {
5622 RTSemMutexDestroy(pThis->aCts[i].AsyncIORequestMutex);
5623 pThis->aCts[i].AsyncIORequestMutex = NIL_RTSEMMUTEX;
5624 }
5625 if (pThis->aCts[i].AsyncIOSem != NIL_RTSEMEVENT)
5626 {
5627 RTSemEventDestroy(pThis->aCts[i].AsyncIOSem);
5628 pThis->aCts[i].AsyncIOSem = NIL_RTSEMEVENT;
5629 }
5630 if (pThis->aCts[i].SuspendIOSem != NIL_RTSEMEVENT)
5631 {
5632 RTSemEventDestroy(pThis->aCts[i].SuspendIOSem);
5633 pThis->aCts[i].SuspendIOSem = NIL_RTSEMEVENT;
5634 }
5635
5636 /* try one final time */
5637 if (pThis->aCts[i].AsyncIOThread != NIL_RTTHREAD)
5638 {
5639 rc = RTThreadWait(pThis->aCts[i].AsyncIOThread, 1 /*ms*/, NULL);
5640 if (RT_SUCCESS(rc))
5641 {
5642 pThis->aCts[i].AsyncIOThread = NIL_RTTHREAD;
5643 LogRel(("PIIX3 ATA Dtor: Ctl#%u actually completed.\n", i));
5644 }
5645 }
5646 }
5647
5648 return VINF_SUCCESS;
5649}
5650
5651
5652/**
5653 * Detach notification.
5654 *
5655 * The DVD drive has been unplugged.
5656 *
5657 * @param pDevIns The device instance.
5658 * @param iLUN The logical unit which is being detached.
5659 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5660 */
5661static DECLCALLBACK(void) ataR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
5662{
5663 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
5664 PATACONTROLLER pCtl;
5665 ATADevState *pIf;
5666 unsigned iController;
5667 unsigned iInterface;
5668
5669 AssertMsg(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
5670 ("PIIX3IDE: Device does not support hotplugging\n"));
5671
5672 /*
5673 * Locate the controller and stuff.
5674 */
5675 iController = iLUN / RT_ELEMENTS(pThis->aCts[0].aIfs);
5676 AssertReleaseMsg(iController < RT_ELEMENTS(pThis->aCts), ("iController=%d iLUN=%d\n", iController, iLUN));
5677 pCtl = &pThis->aCts[iController];
5678
5679 iInterface = iLUN % RT_ELEMENTS(pThis->aCts[0].aIfs);
5680 pIf = &pCtl->aIfs[iInterface];
5681
5682 /*
5683 * Zero some important members.
5684 */
5685 pIf->pDrvBase = NULL;
5686 pIf->pDrvBlock = NULL;
5687 pIf->pDrvBlockBios = NULL;
5688 pIf->pDrvMount = NULL;
5689
5690 /*
5691 * In case there was a medium inserted.
5692 */
5693 ataMediumRemoved(pIf);
5694}
5695
5696
5697/**
5698 * Configure a LUN.
5699 *
5700 * @returns VBox status code.
5701 * @param pDevIns The device instance.
5702 * @param pIf The ATA unit state.
5703 */
5704static int ataConfigLun(PPDMDEVINS pDevIns, ATADevState *pIf)
5705{
5706 int rc = VINF_SUCCESS;
5707 PDMBLOCKTYPE enmType;
5708
5709 /*
5710 * Query Block, Bios and Mount interfaces.
5711 */
5712 pIf->pDrvBlock = PDMIBASE_QUERY_INTERFACE(pIf->pDrvBase, PDMIBLOCK);
5713 if (!pIf->pDrvBlock)
5714 {
5715 AssertMsgFailed(("Configuration error: LUN#%d hasn't a block interface!\n", pIf->iLUN));
5716 return VERR_PDM_MISSING_INTERFACE;
5717 }
5718
5719 /** @todo implement the BIOS invisible code path. */
5720 pIf->pDrvBlockBios = PDMIBASE_QUERY_INTERFACE(pIf->pDrvBase, PDMIBLOCKBIOS);
5721 if (!pIf->pDrvBlockBios)
5722 {
5723 AssertMsgFailed(("Configuration error: LUN#%d hasn't a block BIOS interface!\n", pIf->iLUN));
5724 return VERR_PDM_MISSING_INTERFACE;
5725 }
5726 pIf->pDrvMount = PDMIBASE_QUERY_INTERFACE(pIf->pDrvBase, PDMIMOUNT);
5727
5728 /*
5729 * Validate type.
5730 */
5731 enmType = pIf->pDrvBlock->pfnGetType(pIf->pDrvBlock);
5732 if ( enmType != PDMBLOCKTYPE_CDROM
5733 && enmType != PDMBLOCKTYPE_DVD
5734 && enmType != PDMBLOCKTYPE_HARD_DISK)
5735 {
5736 AssertMsgFailed(("Configuration error: LUN#%d isn't a disk or cd/dvd-rom. enmType=%d\n", pIf->iLUN, enmType));
5737 return VERR_PDM_UNSUPPORTED_BLOCK_TYPE;
5738 }
5739 if ( ( enmType == PDMBLOCKTYPE_DVD
5740 || enmType == PDMBLOCKTYPE_CDROM)
5741 && !pIf->pDrvMount)
5742 {
5743 AssertMsgFailed(("Internal error: cdrom without a mountable interface, WTF???!\n"));
5744 return VERR_INTERNAL_ERROR;
5745 }
5746 pIf->fATAPI = enmType == PDMBLOCKTYPE_DVD || enmType == PDMBLOCKTYPE_CDROM;
5747 pIf->fATAPIPassthrough = pIf->fATAPI ? (pIf->pDrvBlock->pfnSendCmd != NULL) : false;
5748
5749 /*
5750 * Allocate I/O buffer.
5751 */
5752 PVM pVM = PDMDevHlpGetVM(pDevIns);
5753 if (pIf->cbIOBuffer)
5754 {
5755 /* Buffer is (probably) already allocated. Validate the fields,
5756 * because memory corruption can also overwrite pIf->cbIOBuffer. */
5757 if (pIf->fATAPI)
5758 AssertRelease(pIf->cbIOBuffer == _128K);
5759 else
5760 AssertRelease(pIf->cbIOBuffer == ATA_MAX_MULT_SECTORS * 512);
5761 Assert(pIf->pbIOBufferR3);
5762 Assert(pIf->pbIOBufferR0 == MMHyperR3ToR0(pVM, pIf->pbIOBufferR3));
5763 Assert(pIf->pbIOBufferRC == MMHyperR3ToRC(pVM, pIf->pbIOBufferR3));
5764 }
5765 else
5766 {
5767 if (pIf->fATAPI)
5768 pIf->cbIOBuffer = _128K;
5769 else
5770 pIf->cbIOBuffer = ATA_MAX_MULT_SECTORS * 512;
5771 Assert(!pIf->pbIOBufferR3);
5772 rc = MMR3HyperAllocOnceNoRel(pVM, pIf->cbIOBuffer, 0, MM_TAG_PDM_DEVICE_USER, (void **)&pIf->pbIOBufferR3);
5773 if (RT_FAILURE(rc))
5774 return VERR_NO_MEMORY;
5775 pIf->pbIOBufferR0 = MMHyperR3ToR0(pVM, pIf->pbIOBufferR3);
5776 pIf->pbIOBufferRC = MMHyperR3ToRC(pVM, pIf->pbIOBufferR3);
5777 }
5778
5779 /*
5780 * Init geometry (only for non-CD/DVD media).
5781 */
5782 if (pIf->fATAPI)
5783 {
5784 pIf->cTotalSectors = pIf->pDrvBlock->pfnGetSize(pIf->pDrvBlock) / 2048;
5785 pIf->PCHSGeometry.cCylinders = 0; /* dummy */
5786 pIf->PCHSGeometry.cHeads = 0; /* dummy */
5787 pIf->PCHSGeometry.cSectors = 0; /* dummy */
5788 LogRel(("PIIX3 ATA: LUN#%d: CD/DVD, total number of sectors %Ld, passthrough %s\n", pIf->iLUN, pIf->cTotalSectors, (pIf->fATAPIPassthrough ? "enabled" : "disabled")));
5789 }
5790 else
5791 {
5792 pIf->cTotalSectors = pIf->pDrvBlock->pfnGetSize(pIf->pDrvBlock) / 512;
5793 rc = pIf->pDrvBlockBios->pfnGetPCHSGeometry(pIf->pDrvBlockBios,
5794 &pIf->PCHSGeometry);
5795 if (rc == VERR_PDM_MEDIA_NOT_MOUNTED)
5796 {
5797 pIf->PCHSGeometry.cCylinders = 0;
5798 pIf->PCHSGeometry.cHeads = 16; /*??*/
5799 pIf->PCHSGeometry.cSectors = 63; /*??*/
5800 }
5801 else if (rc == VERR_PDM_GEOMETRY_NOT_SET)
5802 {
5803 pIf->PCHSGeometry.cCylinders = 0; /* autodetect marker */
5804 rc = VINF_SUCCESS;
5805 }
5806 AssertRC(rc);
5807
5808 if ( pIf->PCHSGeometry.cCylinders == 0
5809 || pIf->PCHSGeometry.cHeads == 0
5810 || pIf->PCHSGeometry.cSectors == 0
5811 )
5812 {
5813 uint64_t cCylinders = pIf->cTotalSectors / (16 * 63);
5814 pIf->PCHSGeometry.cCylinders = RT_MAX(RT_MIN(cCylinders, 16383), 1);
5815 pIf->PCHSGeometry.cHeads = 16;
5816 pIf->PCHSGeometry.cSectors = 63;
5817 /* Set the disk geometry information. Ignore errors. */
5818 pIf->pDrvBlockBios->pfnSetPCHSGeometry(pIf->pDrvBlockBios,
5819 &pIf->PCHSGeometry);
5820 rc = VINF_SUCCESS;
5821 }
5822 LogRel(("PIIX3 ATA: LUN#%d: disk, PCHS=%u/%u/%u, total number of sectors %Ld\n", pIf->iLUN, pIf->PCHSGeometry.cCylinders, pIf->PCHSGeometry.cHeads, pIf->PCHSGeometry.cSectors, pIf->cTotalSectors));
5823 }
5824 return rc;
5825}
5826
5827
5828/**
5829 * Attach command.
5830 *
5831 * This is called when we change block driver for the DVD drive.
5832 *
5833 * @returns VBox status code.
5834 * @param pDevIns The device instance.
5835 * @param iLUN The logical unit which is being detached.
5836 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5837 */
5838static DECLCALLBACK(int) ataR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
5839{
5840 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
5841 PATACONTROLLER pCtl;
5842 ATADevState *pIf;
5843 int rc;
5844 unsigned iController;
5845 unsigned iInterface;
5846
5847 AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
5848 ("PIIX3IDE: Device does not support hotplugging\n"),
5849 VERR_INVALID_PARAMETER);
5850
5851 /*
5852 * Locate the controller and stuff.
5853 */
5854 iController = iLUN / RT_ELEMENTS(pThis->aCts[0].aIfs);
5855 AssertReleaseMsg(iController < RT_ELEMENTS(pThis->aCts), ("iController=%d iLUN=%d\n", iController, iLUN));
5856 pCtl = &pThis->aCts[iController];
5857
5858 iInterface = iLUN % RT_ELEMENTS(pThis->aCts[0].aIfs);
5859 pIf = &pCtl->aIfs[iInterface];
5860
5861 /* the usual paranoia */
5862 AssertRelease(!pIf->pDrvBase);
5863 AssertRelease(!pIf->pDrvBlock);
5864 Assert(ATADEVSTATE_2_CONTROLLER(pIf) == pCtl);
5865 Assert(pIf->iLUN == iLUN);
5866
5867 /*
5868 * Try attach the block device and get the interfaces,
5869 * required as well as optional.
5870 */
5871 rc = PDMDevHlpDriverAttach(pDevIns, pIf->iLUN, &pIf->IBase, &pIf->pDrvBase, NULL);
5872 if (RT_SUCCESS(rc))
5873 {
5874 rc = ataConfigLun(pDevIns, pIf);
5875 /*
5876 * In case there is a medium inserted.
5877 */
5878 ataMediumInserted(pIf);
5879 }
5880 else
5881 AssertMsgFailed(("Failed to attach LUN#%d. rc=%Rrc\n", pIf->iLUN, rc));
5882
5883 if (RT_FAILURE(rc))
5884 {
5885 pIf->pDrvBase = NULL;
5886 pIf->pDrvBlock = NULL;
5887 }
5888 return rc;
5889}
5890
5891
5892/**
5893 * Resume notification.
5894 *
5895 * @returns VBox status.
5896 * @param pDevIns The device instance data.
5897 */
5898static DECLCALLBACK(void) ataR3Resume(PPDMDEVINS pDevIns)
5899{
5900 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
5901 int rc;
5902
5903 Log(("%s:\n", __FUNCTION__));
5904 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
5905 {
5906 if (pThis->aCts[i].fRedo && pThis->aCts[i].fRedoIdle)
5907 {
5908 rc = RTSemEventSignal(pThis->aCts[i].SuspendIOSem);
5909 AssertRC(rc);
5910 }
5911 }
5912 return;
5913}
5914
5915
5916/**
5917 * Checks if all (both) the async I/O threads have quiesced.
5918 *
5919 * @returns true on success.
5920 * @returns false when one or more threads is still processing.
5921 * @param pThis Pointer to the instance data.
5922 */
5923static bool ataR3AllAsyncIOIsIdle(PPDMDEVINS pDevIns)
5924{
5925 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
5926
5927 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
5928 if (pThis->aCts[i].AsyncIOThread != NIL_RTTHREAD)
5929 {
5930 bool fRc = ataAsyncIOIsIdle(&pThis->aCts[i], false /*fStrict*/);
5931 if (!fRc)
5932 {
5933 /* Make it signal PDM & itself when its done */
5934 RTSemMutexRequest(pThis->aCts[i].AsyncIORequestMutex, RT_INDEFINITE_WAIT);
5935 ASMAtomicWriteBool(&pThis->aCts[i].fSignalIdle, true);
5936 RTSemMutexRelease(pThis->aCts[i].AsyncIORequestMutex);
5937 fRc = ataAsyncIOIsIdle(&pThis->aCts[i], false /*fStrict*/);
5938 if (!fRc)
5939 {
5940#if 0 /** @todo Need to do some time tracking here... */
5941 LogRel(("PIIX3 ATA: Ctl#%u is still executing, DevSel=%d AIOIf=%d CmdIf0=%#04x CmdIf1=%#04x\n",
5942 i, pThis->aCts[i].iSelectedIf, pThis->aCts[i].iAIOIf,
5943 pThis->aCts[i].aIfs[0].uATARegCommand, pThis->aCts[i].aIfs[1].uATARegCommand));
5944#endif
5945 return false;
5946 }
5947 }
5948 ASMAtomicWriteBool(&pThis->aCts[i].fSignalIdle, false);
5949 }
5950 return true;
5951}
5952
5953
5954/**
5955 * Callback employed by ataSuspend and ataR3PowerOff.
5956 *
5957 * @returns true if we've quiesced, false if we're still working.
5958 * @param pDevIns The device instance.
5959 */
5960static DECLCALLBACK(bool) ataR3IsAsyncSuspendOrPowerOffDone(PPDMDEVINS pDevIns)
5961{
5962 return ataR3AllAsyncIOIsIdle(pDevIns);
5963}
5964
5965
5966/**
5967 * Common worker for ataSuspend and ataR3PowerOff.
5968 */
5969static void ataR3SuspendOrPowerOff(PPDMDEVINS pDevIns)
5970{
5971 if (!ataR3AllAsyncIOIsIdle(pDevIns))
5972 PDMDevHlpSetAsyncNotification(pDevIns, ataR3IsAsyncSuspendOrPowerOffDone);
5973}
5974
5975
5976/**
5977 * Power Off notification.
5978 *
5979 * @returns VBox status.
5980 * @param pDevIns The device instance data.
5981 */
5982static DECLCALLBACK(void) ataR3PowerOff(PPDMDEVINS pDevIns)
5983{
5984 Log(("%s:\n", __FUNCTION__));
5985 ataR3SuspendOrPowerOff(pDevIns);
5986}
5987
5988
5989/**
5990 * Suspend notification.
5991 *
5992 * @returns VBox status.
5993 * @param pDevIns The device instance data.
5994 */
5995static DECLCALLBACK(void) ataR3Suspend(PPDMDEVINS pDevIns)
5996{
5997 Log(("%s:\n", __FUNCTION__));
5998 ataR3SuspendOrPowerOff(pDevIns);
5999}
6000
6001
6002/**
6003 * Callback employed by ataR3Reset.
6004 *
6005 * @returns true if we've quiesced, false if we're still working.
6006 * @param pDevIns The device instance.
6007 */
6008static DECLCALLBACK(bool) ataR3IsAsyncResetDone(PPDMDEVINS pDevIns)
6009{
6010 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
6011
6012 if (!ataR3AllAsyncIOIsIdle(pDevIns))
6013 return false;
6014
6015 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
6016 {
6017 PDMCritSectEnter(&pThis->aCts[i].lock, VERR_INTERNAL_ERROR);
6018 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
6019 ataResetDevice(&pThis->aCts[i].aIfs[j]);
6020 PDMCritSectLeave(&pThis->aCts[i].lock);
6021 }
6022 return true;
6023}
6024
6025
6026/**
6027 * Common reset worker for ataR3Reset and ataR3Construct.
6028 *
6029 * @returns VBox status.
6030 * @param pDevIns The device instance data.
6031 * @param fConstruct Indicates who is calling.
6032 */
6033static int ataR3ResetCommon(PPDMDEVINS pDevIns, bool fConstruct)
6034{
6035 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
6036
6037 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
6038 {
6039 PDMCritSectEnter(&pThis->aCts[i].lock, VERR_INTERNAL_ERROR);
6040
6041 pThis->aCts[i].iSelectedIf = 0;
6042 pThis->aCts[i].iAIOIf = 0;
6043 pThis->aCts[i].BmDma.u8Cmd = 0;
6044 /* Report that both drives present on the bus are in DMA mode. This
6045 * pretends that there is a BIOS that has set it up. Normal reset
6046 * default is 0x00. */
6047 pThis->aCts[i].BmDma.u8Status = (pThis->aCts[i].aIfs[0].pDrvBase != NULL ? BM_STATUS_D0DMA : 0)
6048 | (pThis->aCts[i].aIfs[1].pDrvBase != NULL ? BM_STATUS_D1DMA : 0);
6049 pThis->aCts[i].BmDma.pvAddr = 0;
6050
6051 pThis->aCts[i].fReset = true;
6052 pThis->aCts[i].fRedo = false;
6053 pThis->aCts[i].fRedoIdle = false;
6054 ataAsyncIOClearRequests(&pThis->aCts[i]);
6055 Log2(("%s: Ctl#%d: message to async I/O thread, reset controller\n", __FUNCTION__, i));
6056 ataAsyncIOPutRequest(&pThis->aCts[i], &g_ataResetARequest);
6057 ataAsyncIOPutRequest(&pThis->aCts[i], &g_ataResetCRequest);
6058
6059 PDMCritSectLeave(&pThis->aCts[i].lock);
6060 }
6061
6062 int rcRet = VINF_SUCCESS;
6063 if (!fConstruct)
6064 {
6065 /*
6066 * Setup asynchronous notification compmletion if the requests haven't
6067 * completed yet.
6068 */
6069 if (!ataR3IsAsyncResetDone(pDevIns))
6070 PDMDevHlpSetAsyncNotification(pDevIns, ataR3IsAsyncResetDone);
6071 }
6072 else
6073 {
6074 /*
6075 * Wait for the requests for complete.
6076 *
6077 * Would be real nice if we could do it all from EMT(0) and not
6078 * involve the worker threads, then we could dispense with all the
6079 * waiting and semaphore ping-pong here...
6080 */
6081 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
6082 {
6083 if (pThis->aCts[i].AsyncIOThread != NIL_RTTHREAD)
6084 {
6085 int rc = RTSemMutexRequest(pThis->aCts[i].AsyncIORequestMutex, RT_INDEFINITE_WAIT);
6086 AssertRC(rc);
6087
6088 ASMAtomicWriteBool(&pThis->aCts[i].fSignalIdle, true);
6089 rc = RTThreadUserReset(pThis->aCts[i].AsyncIOThread);
6090 AssertRC(rc);
6091
6092 rc = RTSemMutexRelease(pThis->aCts[i].AsyncIORequestMutex);
6093 AssertRC(rc);
6094
6095 if (!ataAsyncIOIsIdle(&pThis->aCts[i], false /*fStrict*/))
6096 {
6097 rc = RTThreadUserWait(pThis->aCts[i].AsyncIOThread, 30*1000 /*ms*/);
6098 if (RT_FAILURE(rc))
6099 rc = RTThreadUserWait(pThis->aCts[i].AsyncIOThread, 1000 /*ms*/);
6100 if (RT_FAILURE(rc))
6101 {
6102 AssertRC(rc);
6103 rcRet = rc;
6104 }
6105 }
6106 }
6107 ASMAtomicWriteBool(&pThis->aCts[i].fSignalIdle, false);
6108 }
6109 if (RT_SUCCESS(rcRet))
6110 {
6111 rcRet = ataR3IsAsyncResetDone(pDevIns) ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
6112 AssertRC(rcRet);
6113 }
6114 }
6115 return rcRet;
6116}
6117
6118
6119/**
6120 * Reset notification.
6121 *
6122 * @param pDevIns The device instance data.
6123 */
6124static DECLCALLBACK(void) ataR3Reset(PPDMDEVINS pDevIns)
6125{
6126 ataR3ResetCommon(pDevIns, false /*fConstruct*/);
6127}
6128
6129
6130/**
6131 * Prepare state save and load operation.
6132 *
6133 * @returns VBox status code.
6134 * @param pDevIns Device instance of the device which registered the data unit.
6135 * @param pSSM SSM operation handle.
6136 */
6137static DECLCALLBACK(int) ataSaveLoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6138{
6139 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
6140
6141 /* sanity - the suspend notification will wait on the async stuff. */
6142 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
6143 AssertLogRelMsgReturn(ataAsyncIOIsIdle(&pThis->aCts[i], false /*fStrict*/),
6144 ("i=%u\n", i),
6145 VERR_SSM_IDE_ASYNC_TIMEOUT);
6146 return VINF_SUCCESS;
6147}
6148
6149/**
6150 * @copydoc FNSSMDEVLIVEEXEC
6151 */
6152static DECLCALLBACK(int) ataLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
6153{
6154 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
6155
6156 SSMR3PutU8(pSSM, pThis->u8Type);
6157 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
6158 {
6159 SSMR3PutBool(pSSM, true); /* For controller enabled / disabled. */
6160 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
6161 {
6162 SSMR3PutBool(pSSM, pThis->aCts[i].aIfs[j].pDrvBase != NULL);
6163 SSMR3PutStrZ(pSSM, pThis->aCts[i].aIfs[j].szSerialNumber);
6164 SSMR3PutStrZ(pSSM, pThis->aCts[i].aIfs[j].szFirmwareRevision);
6165 SSMR3PutStrZ(pSSM, pThis->aCts[i].aIfs[j].szModelNumber);
6166 }
6167 }
6168
6169 return VINF_SSM_DONT_CALL_AGAIN;
6170}
6171
6172
6173/**
6174 * @copydoc FNSSMDEVSAVEEXEC
6175 */
6176static DECLCALLBACK(int) ataSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6177{
6178 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
6179
6180 ataLiveExec(pDevIns, pSSM, SSM_PASS_FINAL);
6181
6182 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
6183 {
6184 SSMR3PutU8(pSSM, pThis->aCts[i].iSelectedIf);
6185 SSMR3PutU8(pSSM, pThis->aCts[i].iAIOIf);
6186 SSMR3PutU8(pSSM, pThis->aCts[i].uAsyncIOState);
6187 SSMR3PutBool(pSSM, pThis->aCts[i].fChainedTransfer);
6188 SSMR3PutBool(pSSM, pThis->aCts[i].fReset);
6189 SSMR3PutBool(pSSM, pThis->aCts[i].fRedo);
6190 SSMR3PutBool(pSSM, pThis->aCts[i].fRedoIdle);
6191 SSMR3PutBool(pSSM, pThis->aCts[i].fRedoDMALastDesc);
6192 SSMR3PutMem(pSSM, &pThis->aCts[i].BmDma, sizeof(pThis->aCts[i].BmDma));
6193 SSMR3PutGCPhys32(pSSM, pThis->aCts[i].pFirstDMADesc);
6194 SSMR3PutGCPhys32(pSSM, pThis->aCts[i].pLastDMADesc);
6195 SSMR3PutGCPhys32(pSSM, pThis->aCts[i].pRedoDMABuffer);
6196 SSMR3PutU32(pSSM, pThis->aCts[i].cbRedoDMABuffer);
6197
6198 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
6199 {
6200 SSMR3PutBool(pSSM, pThis->aCts[i].aIfs[j].fLBA48);
6201 SSMR3PutBool(pSSM, pThis->aCts[i].aIfs[j].fATAPI);
6202 SSMR3PutBool(pSSM, pThis->aCts[i].aIfs[j].fIrqPending);
6203 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].cMultSectors);
6204 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].PCHSGeometry.cCylinders);
6205 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].PCHSGeometry.cHeads);
6206 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].PCHSGeometry.cSectors);
6207 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].cSectorsPerIRQ);
6208 SSMR3PutU64(pSSM, pThis->aCts[i].aIfs[j].cTotalSectors);
6209 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegFeature);
6210 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegFeatureHOB);
6211 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegError);
6212 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegNSector);
6213 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegNSectorHOB);
6214 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegSector);
6215 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegSectorHOB);
6216 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegLCyl);
6217 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegLCylHOB);
6218 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegHCyl);
6219 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegHCylHOB);
6220 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegSelect);
6221 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegStatus);
6222 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegCommand);
6223 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATARegDevCtl);
6224 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uATATransferMode);
6225 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].uTxDir);
6226 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].iBeginTransfer);
6227 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].iSourceSink);
6228 SSMR3PutBool(pSSM, pThis->aCts[i].aIfs[j].fDMA);
6229 SSMR3PutBool(pSSM, pThis->aCts[i].aIfs[j].fATAPITransfer);
6230 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].cbTotalTransfer);
6231 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].cbElementaryTransfer);
6232 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].iIOBufferCur);
6233 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].iIOBufferEnd);
6234 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].iIOBufferPIODataStart);
6235 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].iIOBufferPIODataEnd);
6236 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].iATAPILBA);
6237 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].cbATAPISector);
6238 SSMR3PutMem(pSSM, &pThis->aCts[i].aIfs[j].aATAPICmd, sizeof(pThis->aCts[i].aIfs[j].aATAPICmd));
6239 SSMR3PutMem(pSSM, &pThis->aCts[i].aIfs[j].abATAPISense, sizeof(pThis->aCts[i].aIfs[j].abATAPISense));
6240 SSMR3PutU8(pSSM, pThis->aCts[i].aIfs[j].cNotifiedMediaChange);
6241 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].MediaEventStatus);
6242 SSMR3PutMem(pSSM, &pThis->aCts[i].aIfs[j].Led, sizeof(pThis->aCts[i].aIfs[j].Led));
6243 SSMR3PutU32(pSSM, pThis->aCts[i].aIfs[j].cbIOBuffer);
6244 if (pThis->aCts[i].aIfs[j].cbIOBuffer)
6245 SSMR3PutMem(pSSM, pThis->aCts[i].aIfs[j].CTX_SUFF(pbIOBuffer), pThis->aCts[i].aIfs[j].cbIOBuffer);
6246 else
6247 Assert(pThis->aCts[i].aIfs[j].CTX_SUFF(pbIOBuffer) == NULL);
6248 }
6249 }
6250
6251 return SSMR3PutU32(pSSM, ~0); /* sanity/terminator */
6252}
6253
6254/**
6255 * Converts the LUN number into a message string.
6256 */
6257static const char *ataStringifyLun(unsigned iLun)
6258{
6259 switch (iLun)
6260 {
6261 case 0: return "primary master";
6262 case 1: return "primary slave";
6263 case 2: return "secondary master";
6264 case 3: return "secondary slave";
6265 default: AssertFailedReturn("unknown lun");
6266 }
6267}
6268
6269/**
6270 * FNSSMDEVLOADEXEC
6271 */
6272static DECLCALLBACK(int) ataLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
6273{
6274 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
6275 int rc;
6276 uint32_t u32;
6277
6278 if ( uVersion != ATA_SAVED_STATE_VERSION
6279 && uVersion != ATA_SAVED_STATE_VERSION_VBOX_30
6280 && uVersion != ATA_SAVED_STATE_VERSION_WITHOUT_FULL_SENSE
6281 && uVersion != ATA_SAVED_STATE_VERSION_WITHOUT_EVENT_STATUS
6282 && uVersion != ATA_SAVED_STATE_VERSION_WITH_BOOL_TYPE)
6283 {
6284 AssertMsgFailed(("uVersion=%d\n", uVersion));
6285 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
6286 }
6287
6288 /*
6289 * Verify the configuration.
6290 */
6291 if (uVersion > ATA_SAVED_STATE_VERSION_VBOX_30)
6292 {
6293 uint8_t u8Type;
6294 rc = SSMR3GetU8(pSSM, &u8Type);
6295 AssertRCReturn(rc, rc);
6296 if (u8Type != pThis->u8Type)
6297 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: u8Type - saved=%u config=%u"), u8Type, pThis->u8Type);
6298
6299 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
6300 {
6301 bool fEnabled;
6302 rc = SSMR3GetBool(pSSM, &fEnabled);
6303 AssertRCReturn(rc, rc);
6304 if (!fEnabled)
6305 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Ctr#%u onfig mismatch: fEnabled != true"), i);
6306
6307 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
6308 {
6309 ATADevState const *pIf = &pThis->aCts[i].aIfs[j];
6310
6311 bool fInUse;
6312 rc = SSMR3GetBool(pSSM, &fInUse);
6313 AssertRCReturn(rc, rc);
6314 if (fInUse != (pIf->pDrvBase != NULL))
6315 return SSMR3SetCfgError(pSSM, RT_SRC_POS,
6316 N_("The %s VM is missing a %s device. Please make sure the source and target VMs have compatible storage configurations"),
6317 fInUse ? "target" : "source", ataStringifyLun(pIf->iLUN) );
6318
6319 char szSerialNumber[ATA_SERIAL_NUMBER_LENGTH+1];
6320 rc = SSMR3GetStrZ(pSSM, szSerialNumber, sizeof(szSerialNumber));
6321 AssertRCReturn(rc, rc);
6322 if (strcmp(szSerialNumber, pIf->szSerialNumber))
6323 LogRel(("PIIX3 ATA: LUN#%u config mismatch: Serial number - saved='%s' config='%s'\n",
6324 pIf->iLUN, szSerialNumber, pIf->szSerialNumber));
6325
6326 char szFirmwareRevision[ATA_FIRMWARE_REVISION_LENGTH+1];
6327 rc = SSMR3GetStrZ(pSSM, szFirmwareRevision, sizeof(szFirmwareRevision));
6328 AssertRCReturn(rc, rc);
6329 if (strcmp(szFirmwareRevision, pIf->szFirmwareRevision))
6330 LogRel(("PIIX3 ATA: LUN#%u config mismatch: Firmware revision - saved='%s' config='%s'\n",
6331 pIf->iLUN, szFirmwareRevision, pIf->szFirmwareRevision));
6332
6333 char szModelNumber[ATA_MODEL_NUMBER_LENGTH+1];
6334 rc = SSMR3GetStrZ(pSSM, szModelNumber, sizeof(szModelNumber));
6335 AssertRCReturn(rc, rc);
6336 if (strcmp(szModelNumber, pIf->szModelNumber))
6337 LogRel(("PIIX3 ATA: LUN#%u config mismatch: Model number - saved='%s' config='%s'\n",
6338 pIf->iLUN, szModelNumber, pIf->szModelNumber));
6339 }
6340 }
6341 }
6342 if (uPass != SSM_PASS_FINAL)
6343 return VINF_SUCCESS;
6344
6345 /*
6346 * Restore valid parts of the PCIATAState structure
6347 */
6348 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
6349 {
6350 /* integrity check */
6351 if (!ataAsyncIOIsIdle(&pThis->aCts[i], false))
6352 {
6353 AssertMsgFailed(("Async I/O for controller %d is active\n", i));
6354 return VERR_INTERNAL_ERROR_4;
6355 }
6356
6357 SSMR3GetU8(pSSM, &pThis->aCts[i].iSelectedIf);
6358 SSMR3GetU8(pSSM, &pThis->aCts[i].iAIOIf);
6359 SSMR3GetU8(pSSM, &pThis->aCts[i].uAsyncIOState);
6360 SSMR3GetBool(pSSM, &pThis->aCts[i].fChainedTransfer);
6361 SSMR3GetBool(pSSM, (bool *)&pThis->aCts[i].fReset);
6362 SSMR3GetBool(pSSM, (bool *)&pThis->aCts[i].fRedo);
6363 SSMR3GetBool(pSSM, (bool *)&pThis->aCts[i].fRedoIdle);
6364 SSMR3GetBool(pSSM, (bool *)&pThis->aCts[i].fRedoDMALastDesc);
6365 SSMR3GetMem(pSSM, &pThis->aCts[i].BmDma, sizeof(pThis->aCts[i].BmDma));
6366 SSMR3GetGCPhys32(pSSM, &pThis->aCts[i].pFirstDMADesc);
6367 SSMR3GetGCPhys32(pSSM, &pThis->aCts[i].pLastDMADesc);
6368 SSMR3GetGCPhys32(pSSM, &pThis->aCts[i].pRedoDMABuffer);
6369 SSMR3GetU32(pSSM, &pThis->aCts[i].cbRedoDMABuffer);
6370
6371 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
6372 {
6373 SSMR3GetBool(pSSM, &pThis->aCts[i].aIfs[j].fLBA48);
6374 SSMR3GetBool(pSSM, &pThis->aCts[i].aIfs[j].fATAPI);
6375 SSMR3GetBool(pSSM, &pThis->aCts[i].aIfs[j].fIrqPending);
6376 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].cMultSectors);
6377 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].PCHSGeometry.cCylinders);
6378 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].PCHSGeometry.cHeads);
6379 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].PCHSGeometry.cSectors);
6380 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].cSectorsPerIRQ);
6381 SSMR3GetU64(pSSM, &pThis->aCts[i].aIfs[j].cTotalSectors);
6382 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegFeature);
6383 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegFeatureHOB);
6384 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegError);
6385 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegNSector);
6386 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegNSectorHOB);
6387 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegSector);
6388 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegSectorHOB);
6389 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegLCyl);
6390 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegLCylHOB);
6391 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegHCyl);
6392 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegHCylHOB);
6393 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegSelect);
6394 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegStatus);
6395 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegCommand);
6396 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATARegDevCtl);
6397 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uATATransferMode);
6398 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].uTxDir);
6399 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].iBeginTransfer);
6400 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].iSourceSink);
6401 SSMR3GetBool(pSSM, &pThis->aCts[i].aIfs[j].fDMA);
6402 SSMR3GetBool(pSSM, &pThis->aCts[i].aIfs[j].fATAPITransfer);
6403 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].cbTotalTransfer);
6404 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].cbElementaryTransfer);
6405 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].iIOBufferCur);
6406 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].iIOBufferEnd);
6407 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].iIOBufferPIODataStart);
6408 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].iIOBufferPIODataEnd);
6409 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].iATAPILBA);
6410 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].cbATAPISector);
6411 SSMR3GetMem(pSSM, &pThis->aCts[i].aIfs[j].aATAPICmd, sizeof(pThis->aCts[i].aIfs[j].aATAPICmd));
6412 if (uVersion > ATA_SAVED_STATE_VERSION_WITHOUT_FULL_SENSE)
6413 {
6414 SSMR3GetMem(pSSM, pThis->aCts[i].aIfs[j].abATAPISense, sizeof(pThis->aCts[i].aIfs[j].abATAPISense));
6415 }
6416 else
6417 {
6418 uint8_t uATAPISenseKey, uATAPIASC;
6419 memset(pThis->aCts[i].aIfs[j].abATAPISense, '\0', sizeof(pThis->aCts[i].aIfs[j].abATAPISense));
6420 pThis->aCts[i].aIfs[j].abATAPISense[0] = 0x70 | (1 << 7);
6421 pThis->aCts[i].aIfs[j].abATAPISense[7] = 10;
6422 SSMR3GetU8(pSSM, &uATAPISenseKey);
6423 SSMR3GetU8(pSSM, &uATAPIASC);
6424 pThis->aCts[i].aIfs[j].abATAPISense[2] = uATAPISenseKey & 0x0f;
6425 pThis->aCts[i].aIfs[j].abATAPISense[12] = uATAPIASC;
6426 }
6427 /** @todo triple-check this hack after passthrough is working */
6428 SSMR3GetU8(pSSM, &pThis->aCts[i].aIfs[j].cNotifiedMediaChange);
6429 if (uVersion > ATA_SAVED_STATE_VERSION_WITHOUT_EVENT_STATUS)
6430 SSMR3GetU32(pSSM, (uint32_t*)&pThis->aCts[i].aIfs[j].MediaEventStatus);
6431 else
6432 pThis->aCts[i].aIfs[j].MediaEventStatus = ATA_EVENT_STATUS_UNCHANGED;
6433 SSMR3GetMem(pSSM, &pThis->aCts[i].aIfs[j].Led, sizeof(pThis->aCts[i].aIfs[j].Led));
6434 SSMR3GetU32(pSSM, &pThis->aCts[i].aIfs[j].cbIOBuffer);
6435 if (pThis->aCts[i].aIfs[j].cbIOBuffer)
6436 {
6437 if (pThis->aCts[i].aIfs[j].CTX_SUFF(pbIOBuffer))
6438 SSMR3GetMem(pSSM, pThis->aCts[i].aIfs[j].CTX_SUFF(pbIOBuffer), pThis->aCts[i].aIfs[j].cbIOBuffer);
6439 else
6440 {
6441 LogRel(("ATA: No buffer for %d/%d\n", i, j));
6442 if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
6443 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("No buffer for %d/%d"), i, j);
6444
6445 /* skip the buffer if we're loading for the debugger / animator. */
6446 uint8_t u8Ignored;
6447 size_t cbLeft = pThis->aCts[i].aIfs[j].cbIOBuffer;
6448 while (cbLeft-- > 0)
6449 SSMR3GetU8(pSSM, &u8Ignored);
6450 }
6451 }
6452 else
6453 Assert(pThis->aCts[i].aIfs[j].CTX_SUFF(pbIOBuffer) == NULL);
6454 }
6455 }
6456 if (uVersion <= ATA_SAVED_STATE_VERSION_VBOX_30)
6457 SSMR3GetU8(pSSM, &pThis->u8Type);
6458
6459 rc = SSMR3GetU32(pSSM, &u32);
6460 if (RT_FAILURE(rc))
6461 return rc;
6462 if (u32 != ~0U)
6463 {
6464 AssertMsgFailed(("u32=%#x expected ~0\n", u32));
6465 rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
6466 return rc;
6467 }
6468
6469 return VINF_SUCCESS;
6470}
6471
6472/**
6473 * Convert config value to DEVPCBIOSBOOT.
6474 *
6475 * @returns VBox status code.
6476 * @param pDevIns The device instance data.
6477 * @param pCfgHandle Configuration handle.
6478 * @param penmChipset Where to store the chipset type.
6479 */
6480static int ataControllerFromCfg(PPDMDEVINS pDevIns, PCFGMNODE pCfgHandle, CHIPSET *penmChipset)
6481{
6482 char szType[20];
6483
6484 int rc = CFGMR3QueryStringDef(pCfgHandle, "Type", &szType[0], sizeof(szType), "PIIX4");
6485 if (RT_FAILURE(rc))
6486 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
6487 N_("Configuration error: Querying \"Type\" as a string failed"));
6488 if (!strcmp(szType, "PIIX3"))
6489 *penmChipset = CHIPSET_PIIX3;
6490 else if (!strcmp(szType, "PIIX4"))
6491 *penmChipset = CHIPSET_PIIX4;
6492 else if (!strcmp(szType, "ICH6"))
6493 *penmChipset = CHIPSET_ICH6;
6494 else
6495 {
6496 PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
6497 N_("Configuration error: The \"Type\" value \"%s\" is unknown"),
6498 szType);
6499 rc = VERR_INTERNAL_ERROR;
6500 }
6501 return rc;
6502}
6503
6504
6505/**
6506 * Construct a device instance for a VM.
6507 *
6508 * @returns VBox status.
6509 * @param pDevIns The device instance data.
6510 * If the registration structure is needed, pDevIns->pDevReg points to it.
6511 * @param iInstance Instance number. Use this to figure out which registers and such to use.
6512 * The device number is also found in pDevIns->iInstance, but since it's
6513 * likely to be freqently used PDM passes it as parameter.
6514 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
6515 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
6516 * iInstance it's expected to be used a bit in this function.
6517 */
6518static DECLCALLBACK(int) ataR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
6519{
6520 PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
6521 PPDMIBASE pBase;
6522 int rc;
6523 bool fGCEnabled;
6524 bool fR0Enabled;
6525 uint32_t DelayIRQMillies;
6526
6527 Assert(iInstance == 0);
6528
6529 /*
6530 * Initialize NIL handle values (for the destructor).
6531 */
6532 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
6533 {
6534 pThis->aCts[i].AsyncIOSem = NIL_RTSEMEVENT;
6535 pThis->aCts[i].SuspendIOSem = NIL_RTSEMEVENT;
6536 pThis->aCts[i].AsyncIORequestMutex = NIL_RTSEMMUTEX;
6537 pThis->aCts[i].AsyncIOThread = NIL_RTTHREAD;
6538 }
6539
6540 /*
6541 * Validate and read configuration.
6542 */
6543 if (!CFGMR3AreValuesValid(pCfgHandle,
6544 "GCEnabled\0"
6545 "R0Enabled\0"
6546 "IRQDelay\0"
6547 "Type\0")
6548 /** @todo || invalid keys */)
6549 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
6550 N_("PIIX3 configuration error: unknown option specified"));
6551
6552 rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
6553 if (RT_FAILURE(rc))
6554 return PDMDEV_SET_ERROR(pDevIns, rc,
6555 N_("PIIX3 configuration error: failed to read GCEnabled as boolean"));
6556 Log(("%s: fGCEnabled=%d\n", __FUNCTION__, fGCEnabled));
6557
6558 rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
6559 if (RT_FAILURE(rc))
6560 return PDMDEV_SET_ERROR(pDevIns, rc,
6561 N_("PIIX3 configuration error: failed to read R0Enabled as boolean"));
6562 Log(("%s: fR0Enabled=%d\n", __FUNCTION__, fR0Enabled));
6563
6564 rc = CFGMR3QueryU32Def(pCfgHandle, "IRQDelay", &DelayIRQMillies, 0);
6565 if (RT_FAILURE(rc))
6566 return PDMDEV_SET_ERROR(pDevIns, rc,
6567 N_("PIIX3 configuration error: failed to read IRQDelay as integer"));
6568 Log(("%s: DelayIRQMillies=%d\n", __FUNCTION__, DelayIRQMillies));
6569 Assert(DelayIRQMillies < 50);
6570
6571 CHIPSET enmChipset = CHIPSET_PIIX3;
6572 rc = ataControllerFromCfg(pDevIns, pCfgHandle, &enmChipset);
6573 if (RT_FAILURE(rc))
6574 return rc;
6575 pThis->u8Type = (uint8_t)enmChipset;
6576
6577 /*
6578 * Initialize data (most of it anyway).
6579 */
6580 /* Status LUN. */
6581 pThis->IBase.pfnQueryInterface = ataStatus_QueryInterface;
6582 pThis->ILeds.pfnQueryStatusLed = ataStatus_QueryStatusLed;
6583
6584 /* PCI configuration space. */
6585 PCIDevSetVendorId(&pThis->dev, 0x8086); /* Intel */
6586
6587 /*
6588 * When adding more IDE chipsets, don't forget to update pci_bios_init_device()
6589 * as it explicitly checks for PCI id for IDE controllers.
6590 */
6591 switch (pThis->u8Type)
6592 {
6593 case CHIPSET_ICH6:
6594 PCIDevSetDeviceId(&pThis->dev, 0x269e); /* ICH6 IDE */
6595 /** @todo: do we need it? Do we need anything else? */
6596 pThis->dev.config[0x48] = 0x00; /* UDMACTL */
6597 pThis->dev.config[0x4A] = 0x00; /* UDMATIM */
6598 pThis->dev.config[0x4B] = 0x00;
6599 {
6600 /*
6601 * See www.intel.com/Assets/PDF/manual/298600.pdf p. 30
6602 * Report
6603 * WR_Ping-Pong_EN: must be set
6604 * PCR0, PCR1: 80-pin primary cable reporting for both disks
6605 * SCR0, SCR1: 80-pin secondary cable reporting for both disks
6606 */
6607 uint16_t u16Config = (1<<10) | (1<<7) | (1<<6) | (1<<5) | (1<<4) ;
6608 pThis->dev.config[0x54] = u16Config & 0xff;
6609 pThis->dev.config[0x55] = u16Config >> 8;
6610 }
6611 break;
6612 case CHIPSET_PIIX4:
6613 PCIDevSetDeviceId(&pThis->dev, 0x7111); /* PIIX4 IDE */
6614 PCIDevSetRevisionId(&pThis->dev, 0x01); /* PIIX4E */
6615 pThis->dev.config[0x48] = 0x00; /* UDMACTL */
6616 pThis->dev.config[0x4A] = 0x00; /* UDMATIM */
6617 pThis->dev.config[0x4B] = 0x00;
6618 break;
6619 case CHIPSET_PIIX3:
6620 PCIDevSetDeviceId(&pThis->dev, 0x7010); /* PIIX3 IDE */
6621 break;
6622 default:
6623 AssertMsgFailed(("Unsupported IDE chipset type: %d\n", pThis->u8Type));
6624 }
6625
6626 PCIDevSetCommand( &pThis->dev, PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS | PCI_COMMAND_BUSMASTER);
6627 PCIDevSetClassProg( &pThis->dev, 0x8a); /* programming interface = PCI_IDE bus master is supported */
6628 PCIDevSetClassSub( &pThis->dev, 0x01); /* class_sub = PCI_IDE */
6629 PCIDevSetClassBase( &pThis->dev, 0x01); /* class_base = PCI_mass_storage */
6630 PCIDevSetHeaderType(&pThis->dev, 0x00);
6631
6632 pThis->pDevIns = pDevIns;
6633 pThis->fGCEnabled = fGCEnabled;
6634 pThis->fR0Enabled = fR0Enabled;
6635 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
6636 {
6637 pThis->aCts[i].pDevInsR3 = pDevIns;
6638 pThis->aCts[i].pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
6639 pThis->aCts[i].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
6640 pThis->aCts[i].DelayIRQMillies = (uint32_t)DelayIRQMillies;
6641 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
6642 {
6643 ATADevState *pIf = &pThis->aCts[i].aIfs[j];
6644
6645 pIf->iLUN = i * RT_ELEMENTS(pThis->aCts) + j;
6646 pIf->pDevInsR3 = pDevIns;
6647 pIf->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
6648 pIf->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
6649 pIf->pControllerR3 = &pThis->aCts[i];
6650 pIf->pControllerR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pDevIns), &pThis->aCts[i]);
6651 pIf->pControllerRC = MMHyperR3ToRC(PDMDevHlpGetVM(pDevIns), &pThis->aCts[i]);
6652 pIf->IBase.pfnQueryInterface = ataQueryInterface;
6653 pIf->IMountNotify.pfnMountNotify = ataMountNotify;
6654 pIf->IMountNotify.pfnUnmountNotify = ataUnmountNotify;
6655 pIf->Led.u32Magic = PDMLED_MAGIC;
6656 }
6657 }
6658
6659 Assert(RT_ELEMENTS(pThis->aCts) == 2);
6660 pThis->aCts[0].irq = 14;
6661 pThis->aCts[0].IOPortBase1 = 0x1f0;
6662 pThis->aCts[0].IOPortBase2 = 0x3f6;
6663 pThis->aCts[1].irq = 15;
6664 pThis->aCts[1].IOPortBase1 = 0x170;
6665 pThis->aCts[1].IOPortBase2 = 0x376;
6666
6667 /*
6668 * Register the PCI device.
6669 * N.B. There's a hack in the PIIX3 PCI bridge device to assign this
6670 * device the slot next to itself.
6671 */
6672 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->dev);
6673 if (RT_FAILURE(rc))
6674 return PDMDEV_SET_ERROR(pDevIns, rc,
6675 N_("PIIX3 cannot register PCI device"));
6676 AssertMsg(pThis->dev.devfn == 9 || iInstance != 0, ("pThis->dev.devfn=%d\n", pThis->dev.devfn));
6677 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 4, 0x10, PCI_ADDRESS_SPACE_IO, ataBMDMAIORangeMap);
6678 if (RT_FAILURE(rc))
6679 return PDMDEV_SET_ERROR(pDevIns, rc,
6680 N_("PIIX3 cannot register PCI I/O region for BMDMA"));
6681
6682 /*
6683 * Register the I/O ports.
6684 * The ports are all hardcoded and enforced by the PIIX3 host bridge controller.
6685 */
6686 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
6687 {
6688 rc = PDMDevHlpIOPortRegister(pDevIns, pThis->aCts[i].IOPortBase1, 8, (RTHCPTR)i,
6689 ataIOPortWrite1, ataIOPortRead1, ataIOPortWriteStr1, ataIOPortReadStr1, "ATA I/O Base 1");
6690 if (RT_FAILURE(rc))
6691 return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot register I/O handlers"));
6692
6693 if (fGCEnabled)
6694 {
6695 rc = PDMDevHlpIOPortRegisterGC(pDevIns, pThis->aCts[i].IOPortBase1, 8, (RTGCPTR)i,
6696 "ataIOPortWrite1", "ataIOPortRead1", "ataIOPortWriteStr1", "ataIOPortReadStr1", "ATA I/O Base 1");
6697 if (RT_FAILURE(rc))
6698 return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot register I/O handlers (GC)"));
6699 }
6700
6701 if (fR0Enabled)
6702 {
6703#if 1
6704 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->aCts[i].IOPortBase1, 8, (RTR0PTR)i,
6705 "ataIOPortWrite1", "ataIOPortRead1", NULL, NULL, "ATA I/O Base 1");
6706#else
6707 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->aCts[i].IOPortBase1, 8, (RTR0PTR)i,
6708 "ataIOPortWrite1", "ataIOPortRead1", "ataIOPortWriteStr1", "ataIOPortReadStr1", "ATA I/O Base 1");
6709#endif
6710 if (RT_FAILURE(rc))
6711 return PDMDEV_SET_ERROR(pDevIns, rc, "PIIX3 cannot register I/O handlers (R0).");
6712 }
6713
6714 rc = PDMDevHlpIOPortRegister(pDevIns, pThis->aCts[i].IOPortBase2, 1, (RTHCPTR)i,
6715 ataIOPortWrite2, ataIOPortRead2, NULL, NULL, "ATA I/O Base 2");
6716 if (RT_FAILURE(rc))
6717 return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot register base2 I/O handlers"));
6718
6719 if (fGCEnabled)
6720 {
6721 rc = PDMDevHlpIOPortRegisterGC(pDevIns, pThis->aCts[i].IOPortBase2, 1, (RTGCPTR)i,
6722 "ataIOPortWrite2", "ataIOPortRead2", NULL, NULL, "ATA I/O Base 2");
6723 if (RT_FAILURE(rc))
6724 return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot register base2 I/O handlers (GC)"));
6725 }
6726 if (fR0Enabled)
6727 {
6728 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->aCts[i].IOPortBase2, 1, (RTR0PTR)i,
6729 "ataIOPortWrite2", "ataIOPortRead2", NULL, NULL, "ATA I/O Base 2");
6730 if (RT_FAILURE(rc))
6731 return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot register base2 I/O handlers (R0)"));
6732 }
6733
6734 for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
6735 {
6736 ATADevState *pIf = &pThis->aCts[i].aIfs[j];
6737 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatATADMA, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
6738 "Number of ATA DMA transfers.", "/Devices/IDE%d/ATA%d/Unit%d/DMA", iInstance, i, j);
6739 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatATAPIO, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
6740 "Number of ATA PIO transfers.", "/Devices/IDE%d/ATA%d/Unit%d/PIO", iInstance, i, j);
6741 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatATAPIDMA, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
6742 "Number of ATAPI DMA transfers.", "/Devices/IDE%d/ATA%d/Unit%d/AtapiDMA", iInstance, i, j);
6743 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatATAPIPIO, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
6744 "Number of ATAPI PIO transfers.", "/Devices/IDE%d/ATA%d/Unit%d/AtapiPIO", iInstance, i, j);
6745#ifdef VBOX_WITH_STATISTICS /** @todo release too. */
6746 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatReads, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
6747 "Profiling of the read operations.", "/Devices/IDE%d/ATA%d/Unit%d/Reads", iInstance, i, j);
6748#endif
6749 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatBytesRead, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
6750 "Amount of data read.", "/Devices/IDE%d/ATA%d/Unit%d/ReadBytes", iInstance, i, j);
6751#ifdef VBOX_INSTRUMENT_DMA_WRITES
6752 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatInstrVDWrites,STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
6753 "Profiling of the VD DMA write operations.", "/Devices/IDE%d/ATA%d/Unit%d/InstrVDWrites", iInstance, i, j);
6754#endif
6755#ifdef VBOX_WITH_STATISTICS
6756 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatWrites, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
6757 "Profiling of the write operations.", "/Devices/IDE%d/ATA%d/Unit%d/Writes", iInstance, i, j);
6758#endif
6759 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatBytesWritten, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
6760 "Amount of data written.", "/Devices/IDE%d/ATA%d/Unit%d/WrittenBytes", iInstance, i, j);
6761#ifdef VBOX_WITH_STATISTICS
6762 PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatFlushes, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
6763 "Profiling of the flush operations.", "/Devices/IDE%d/ATA%d/Unit%d/Flushes", iInstance, i, j);
6764#endif
6765 }
6766#ifdef VBOX_WITH_STATISTICS /** @todo release too. */
6767 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aCts[i].StatAsyncOps, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
6768 "The number of async operations.", "/Devices/IDE%d/ATA%d/Async/Operations", iInstance, i);
6769 /** @todo STAMUNIT_MICROSECS */
6770 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aCts[i].StatAsyncMinWait, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
6771 "Minimum wait in microseconds.", "/Devices/IDE%d/ATA%d/Async/MinWait", iInstance, i);
6772 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aCts[i].StatAsyncMaxWait, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
6773 "Maximum wait in microseconds.", "/Devices/IDE%d/ATA%d/Async/MaxWait", iInstance, i);
6774 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aCts[i].StatAsyncTimeUS, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
6775 "Total time spent in microseconds.", "/Devices/IDE%d/ATA%d/Async/TotalTimeUS", iInstance, i);
6776 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aCts[i].StatAsyncTime, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
6777 "Profiling of async operations.", "/Devices/IDE%d/ATA%d/Async/Time", iInstance, i);
6778 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aCts[i].StatLockWait, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
6779 "Profiling of locks.", "/Devices/IDE%d/ATA%d/Async/LockWait", iInstance, i);
6780#endif /* VBOX_WITH_STATISTICS */
6781
6782 /* Initialize per-controller critical section */
6783 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->aCts[i].lock, RT_SRC_POS, "ATA%u", i);
6784 if (RT_FAILURE(rc))
6785 return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot initialize critical section"));
6786 }
6787
6788 /*
6789 * Attach status driver (optional).
6790 */
6791 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThis->IBase, &pBase, "Status Port");
6792 if (RT_SUCCESS(rc))
6793 pThis->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
6794 else if (rc != VERR_PDM_NO_ATTACHED_DRIVER)
6795 {
6796 AssertMsgFailed(("Failed to attach to status driver. rc=%Rrc\n", rc));
6797 return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot attach to status driver"));
6798 }
6799
6800 /*
6801 * Attach the units.
6802 */
6803 uint32_t cbTotalBuffer = 0;
6804 for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
6805 {
6806 PATACONTROLLER pCtl = &pThis->aCts[i];
6807
6808 /*
6809 * Start the worker thread.
6810 */
6811 pCtl->uAsyncIOState = ATA_AIO_NEW;
6812 rc = RTSemEventCreate(&pCtl->AsyncIOSem);
6813 AssertLogRelRCReturn(rc, rc);
6814 rc = RTSemEventCreate(&pCtl->SuspendIOSem);
6815 AssertLogRelRCReturn(rc, rc);
6816 rc = RTSemMutexCreate(&pCtl->AsyncIORequestMutex);
6817 AssertLogRelRCReturn(rc, rc);
6818 ataAsyncIOClearRequests(pCtl);
6819 rc = RTThreadCreateF(&pCtl->AsyncIOThread, ataAsyncIOLoop, (void *)pCtl, 128*1024 /*cbStack*/,
6820 RTTHREADTYPE_IO, RTTHREADFLAGS_WAITABLE, "ATA-%u", i);
6821 AssertLogRelRCReturn(rc, rc);
6822 Assert(pCtl->AsyncIOThread != NIL_RTTHREAD && pCtl->AsyncIOSem != NIL_RTSEMEVENT && pCtl->SuspendIOSem != NIL_RTSEMEVENT && pCtl->AsyncIORequestMutex != NIL_RTSEMMUTEX);
6823 Log(("%s: controller %d AIO thread id %#x; sem %p susp_sem %p mutex %p\n", __FUNCTION__, i, pCtl->AsyncIOThread, pCtl->AsyncIOSem, pCtl->SuspendIOSem, pCtl->AsyncIORequestMutex));
6824
6825 for (uint32_t j = 0; j < RT_ELEMENTS(pCtl->aIfs); j++)
6826 {
6827 static const char *s_apszDescs[RT_ELEMENTS(pThis->aCts)][RT_ELEMENTS(pCtl->aIfs)] =
6828 {
6829 { "Primary Master", "Primary Slave" },
6830 { "Secondary Master", "Secondary Slave" }
6831 };
6832
6833 /*
6834 * Try attach the block device and get the interfaces,
6835 * required as well as optional.
6836 */
6837 ATADevState *pIf = &pCtl->aIfs[j];
6838
6839 rc = PDMDevHlpDriverAttach(pDevIns, pIf->iLUN, &pIf->IBase, &pIf->pDrvBase, s_apszDescs[i][j]);
6840 if (RT_SUCCESS(rc))
6841 {
6842 rc = ataConfigLun(pDevIns, pIf);
6843 if (RT_SUCCESS(rc))
6844 {
6845 /*
6846 * Init vendor product data.
6847 */
6848 static const char *s_apszCFGMKeys[RT_ELEMENTS(pThis->aCts)][RT_ELEMENTS(pCtl->aIfs)] =
6849 {
6850 { "PrimaryMaster", "PrimarySlave" },
6851 { "SecondaryMaster", "SecondarySlave" }
6852 };
6853
6854 /* Generate a default serial number. */
6855 char szSerial[ATA_SERIAL_NUMBER_LENGTH+1];
6856 RTUUID Uuid;
6857 if (pIf->pDrvBlock)
6858 rc = pIf->pDrvBlock->pfnGetUuid(pIf->pDrvBlock, &Uuid);
6859 else
6860 RTUuidClear(&Uuid);
6861
6862 if (RT_FAILURE(rc) || RTUuidIsNull(&Uuid))
6863 {
6864 /* Generate a predictable serial for drives which don't have a UUID. */
6865 RTStrPrintf(szSerial, sizeof(szSerial), "VB%x-%04x%04x",
6866 pIf->iLUN + pDevIns->iInstance * 32,
6867 pThis->aCts[i].IOPortBase1, pThis->aCts[i].IOPortBase2);
6868 }
6869 else
6870 RTStrPrintf(szSerial, sizeof(szSerial), "VB%08x-%08x", Uuid.au32[0], Uuid.au32[3]);
6871
6872 /* Get user config if present using defaults otherwise. */
6873 PCFGMNODE pCfgNode = CFGMR3GetChild(pCfgHandle, s_apszCFGMKeys[i][j]);
6874 rc = CFGMR3QueryStringDef(pCfgNode, "SerialNumber", pIf->szSerialNumber, sizeof(pIf->szSerialNumber),
6875 szSerial);
6876 if (RT_FAILURE(rc))
6877 {
6878 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
6879 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
6880 N_("PIIX3 configuration error: \"SerialNumber\" is longer than 20 bytes"));
6881 return PDMDEV_SET_ERROR(pDevIns, rc,
6882 N_("PIIX3 configuration error: failed to read \"SerialNumber\" as string"));
6883 }
6884
6885 rc = CFGMR3QueryStringDef(pCfgNode, "FirmwareRevision", pIf->szFirmwareRevision, sizeof(pIf->szFirmwareRevision),
6886 "1.0");
6887 if (RT_FAILURE(rc))
6888 {
6889 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
6890 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
6891 N_("PIIX3 configuration error: \"FirmwareRevision\" is longer than 8 bytes"));
6892 return PDMDEV_SET_ERROR(pDevIns, rc,
6893 N_("PIIX3 configuration error: failed to read \"FirmwareRevision\" as string"));
6894 }
6895
6896 rc = CFGMR3QueryStringDef(pCfgNode, "ModelNumber", pIf->szModelNumber, sizeof(pIf->szModelNumber),
6897 pIf->fATAPI ? "VBOX CD-ROM" : "VBOX HARDDISK");
6898 if (RT_FAILURE(rc))
6899 {
6900 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
6901 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
6902 N_("PIIX3 configuration error: \"ModelNumber\" is longer than 40 bytes"));
6903 return PDMDEV_SET_ERROR(pDevIns, rc,
6904 N_("PIIX3 configuration error: failed to read \"ModelNumber\" as string"));
6905 }
6906
6907 /* There are three other identification strings for CD drives used for INQUIRY */
6908 if (pIf->fATAPI)
6909 {
6910 rc = CFGMR3QueryStringDef(pCfgNode, "ATAPIVendorId", pIf->szInquiryVendorId, sizeof(pIf->szInquiryVendorId),
6911 "VBOX");
6912 if (RT_FAILURE(rc))
6913 {
6914 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
6915 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
6916 N_("PIIX3 configuration error: \"ATAPIVendorId\" is longer than 16 bytes"));
6917 return PDMDEV_SET_ERROR(pDevIns, rc,
6918 N_("PIIX3 configuration error: failed to read \"ATAPIVendorId\" as string"));
6919 }
6920
6921 rc = CFGMR3QueryStringDef(pCfgNode, "ATAPIProductId", pIf->szInquiryProductId, sizeof(pIf->szInquiryProductId),
6922 "CD-ROM");
6923 if (RT_FAILURE(rc))
6924 {
6925 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
6926 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
6927 N_("PIIX3 configuration error: \"ATAPIProductId\" is longer than 16 bytes"));
6928 return PDMDEV_SET_ERROR(pDevIns, rc,
6929 N_("PIIX3 configuration error: failed to read \"ATAPIProductId\" as string"));
6930 }
6931
6932 rc = CFGMR3QueryStringDef(pCfgNode, "ATAPIRevision", pIf->szInquiryRevision, sizeof(pIf->szInquiryRevision),
6933 "1.0");
6934 if (RT_FAILURE(rc))
6935 {
6936 if (rc == VERR_CFGM_NOT_ENOUGH_SPACE)
6937 return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
6938 N_("PIIX3 configuration error: \"ATAPIRevision\" is longer than 4 bytes"));
6939 return PDMDEV_SET_ERROR(pDevIns, rc,
6940 N_("PIIX3 configuration error: failed to read \"ATAPIRevision\" as string"));
6941 }
6942 }
6943 }
6944
6945 }
6946 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
6947 {
6948 pIf->pDrvBase = NULL;
6949 pIf->pDrvBlock = NULL;
6950 pIf->cbIOBuffer = 0;
6951 pIf->pbIOBufferR3 = NULL;
6952 pIf->pbIOBufferR0 = NIL_RTR0PTR;
6953 pIf->pbIOBufferRC = NIL_RTGCPTR;
6954 LogRel(("PIIX3 ATA: LUN#%d: no unit\n", pIf->iLUN));
6955 }
6956 else
6957 {
6958 switch (rc)
6959 {
6960 case VERR_ACCESS_DENIED:
6961 /* Error already catched by DrvHostBase */
6962 return rc;
6963 default:
6964 return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
6965 N_("PIIX3 cannot attach drive to the %s"),
6966 s_apszDescs[i][j]);
6967 }
6968 }
6969 cbTotalBuffer += pIf->cbIOBuffer;
6970 }
6971 }
6972
6973 rc = PDMDevHlpSSMRegisterEx(pDevIns, ATA_SAVED_STATE_VERSION, sizeof(*pThis) + cbTotalBuffer, NULL,
6974 NULL, ataLiveExec, NULL,
6975 ataSaveLoadPrep, ataSaveExec, NULL,
6976 ataSaveLoadPrep, ataLoadExec, NULL);
6977 if (RT_FAILURE(rc))
6978 return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot register save state handlers"));
6979
6980 /*
6981 * Initialize the device state.
6982 */
6983 return ataR3ResetCommon(pDevIns, true /*fConstruct*/);
6984}
6985
6986
6987/**
6988 * The device registration structure.
6989 */
6990const PDMDEVREG g_DevicePIIX3IDE =
6991{
6992 /* u32Version */
6993 PDM_DEVREG_VERSION,
6994 /* szDeviceName */
6995 "piix3ide",
6996 /* szRCMod */
6997 "VBoxDDGC.gc",
6998 /* szR0Mod */
6999 "VBoxDDR0.r0",
7000 /* pszDescription */
7001 "Intel PIIX3 ATA controller.\n"
7002 " LUN #0 is primary master.\n"
7003 " LUN #1 is primary slave.\n"
7004 " LUN #2 is secondary master.\n"
7005 " LUN #3 is secondary slave.\n"
7006 " LUN #999 is the LED/Status connector.",
7007 /* fFlags */
7008 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0 |
7009 PDM_DEVREG_FLAGS_FIRST_SUSPEND_NOTIFICATION | PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION,
7010 /* fClass */
7011 PDM_DEVREG_CLASS_STORAGE,
7012 /* cMaxInstances */
7013 1,
7014 /* cbInstance */
7015 sizeof(PCIATAState),
7016 /* pfnConstruct */
7017 ataR3Construct,
7018 /* pfnDestruct */
7019 ataR3Destruct,
7020 /* pfnRelocate */
7021 ataR3Relocate,
7022 /* pfnIOCtl */
7023 NULL,
7024 /* pfnPowerOn */
7025 NULL,
7026 /* pfnReset */
7027 ataR3Reset,
7028 /* pfnSuspend */
7029 ataR3Suspend,
7030 /* pfnResume */
7031 ataR3Resume,
7032 /* pfnAttach */
7033 ataR3Attach,
7034 /* pfnDetach */
7035 ataR3Detach,
7036 /* pfnQueryInterface. */
7037 NULL,
7038 /* pfnInitComplete */
7039 NULL,
7040 /* pfnPowerOff */
7041 ataR3PowerOff,
7042 /* pfnSoftReset */
7043 NULL,
7044 /* u32VersionEnd */
7045 PDM_DEVREG_VERSION
7046};
7047#endif /* IN_RING3 */
7048#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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