UartCore.cpp@ 73299

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1	/* $Id: UartCore.cpp 73299 2018-07-22 14:07:59Z vboxsync $ */
2	/** @file
3	* UartCore - UART (16550A up to 16950) emulation.
4	*
5	* The documentation for this device was taken from the PC16550D spec from TI.
6	*/
7
8	/*
9	* Copyright (C) 2018 Oracle Corporation
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.215389.xyz. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*/
19
20
21	/*********************************************************************************************************************************
22	* Header Files *
23	*********************************************************************************************************************************/
24	#define LOG_GROUP LOG_GROUP_DEV_SERIAL
25	#include <VBox/vmm/tm.h>
26	#include <iprt/log.h>
27	#include <iprt/uuid.h>
28	#include <iprt/assert.h>
29
30	#include "VBoxDD.h"
31	#include "UartCore.h"
32
33
34	/*********************************************************************************************************************************
35	* Defined Constants And Macros *
36	*********************************************************************************************************************************/
37
38	/** The RBR/DLL register index (from the base of the port range). */
39	#define UART_REG_RBR_DLL_INDEX 0
40
41	/** The THR/DLL register index (from the base of the port range). */
42	#define UART_REG_THR_DLL_INDEX 0
43
44	/** The IER/DLM register index (from the base of the port range). */
45	#define UART_REG_IER_DLM_INDEX 1
46	/** Enable received data available interrupt */
47	# define UART_REG_IER_ERBFI RT_BIT(0)
48	/** Enable transmitter holding register empty interrupt */
49	# define UART_REG_IER_ETBEI RT_BIT(1)
50	/** Enable receiver line status interrupt */
51	# define UART_REG_IER_ELSI RT_BIT(2)
52	/** Enable modem status interrupt. */
53	# define UART_REG_IER_EDSSI RT_BIT(3)
54	/** Sleep mode enable. */
55	# define UART_REG_IER_SLEEP_MODE_EN RT_BIT(4)
56	/** Low power mode enable. */
57	# define UART_REG_IER_LP_MODE_EN RT_BIT(5)
58	/** Mask of writeable bits. */
59	# define UART_REG_IER_MASK_WR 0x0f
60	/** Mask of writeable bits for 16750+. */
61	# define UART_REG_IER_MASK_WR_16750 0x3f
62
63	/** The IIR register index (from the base of the port range). */
64	#define UART_REG_IIR_INDEX 2
65	/** Interrupt Pending - high means no interrupt pending. */
66	# define UART_REG_IIR_IP_NO_INT RT_BIT(0)
67	/** Interrupt identification mask. */
68	# define UART_REG_IIR_ID_MASK 0x0e
69	/** Sets the interrupt identification to the given value. */
70	# define UART_REG_IIR_ID_SET(a_Val) (((a_Val) << 1) & UART_REG_IIR_ID_MASK)
71	/** Receiver Line Status interrupt. */
72	# define UART_REG_IIR_ID_RCL 0x3
73	/** Received Data Available interrupt. */
74	# define UART_REG_IIR_ID_RDA 0x2
75	/** Character Timeou Indicator interrupt. */
76	# define UART_REG_IIR_ID_CTI 0x6
77	/** Transmitter Holding Register Empty interrupt. */
78	# define UART_REG_IIR_ID_THRE 0x1
79	/** Modem Status interrupt. */
80	# define UART_REG_IIR_ID_MS 0x0
81	/** 64 byte FIFOs enabled (15750+ only). */
82	# define UART_REG_IIR_64BYTE_FIFOS_EN RT_BIT(5)
83	/** FIFOs enabled. */
84	# define UART_REG_IIR_FIFOS_EN 0xc0
85	/** Bits relevant for checking whether the interrupt status has changed. */
86	# define UART_REG_IIR_CHANGED_MASK 0x0f
87
88	/** The FCR register index (from the base of the port range). */
89	#define UART_REG_FCR_INDEX 2
90	/** Enable the TX/RX FIFOs. */
91	# define UART_REG_FCR_FIFO_EN RT_BIT(0)
92	/** Reset the receive FIFO. */
93	# define UART_REG_FCR_RCV_FIFO_RST RT_BIT(1)
94	/** Reset the transmit FIFO. */
95	# define UART_REG_FCR_XMIT_FIFO_RST RT_BIT(2)
96	/** DMA Mode Select. */
97	# define UART_REG_FCR_DMA_MODE_SEL RT_BIT(3)
98	/** 64 Byte FIFO enable (15750+ only). */
99	# define UART_REG_FCR_64BYTE_FIFO_EN RT_BIT(5)
100	/** Receiver level interrupt trigger. */
101	# define UART_REG_FCR_RCV_LVL_IRQ_MASK 0xc0
102	/** Returns the receive level trigger value from the given FCR register. */
103	# define UART_REG_FCR_RCV_LVL_IRQ_GET(a_Fcr) (((a_Fcr) & UART_REG_FCR_RCV_LVL_IRQ_MASK) >> 6)
104	/** RCV Interrupt trigger level - 1 byte. */
105	# define UART_REG_FCR_RCV_LVL_IRQ_1 0x0
106	/** RCV Interrupt trigger level - 4 bytes. */
107	# define UART_REG_FCR_RCV_LVL_IRQ_4 0x1
108	/** RCV Interrupt trigger level - 8 bytes. */
109	# define UART_REG_FCR_RCV_LVL_IRQ_8 0x2
110	/** RCV Interrupt trigger level - 14 bytes. */
111	# define UART_REG_FCR_RCV_LVL_IRQ_14 0x3
112	/** Mask of writeable bits. */
113	# define UART_REG_FCR_MASK_WR 0xcf
114	/** Mask of sticky bits. */
115	# define UART_REG_FCR_MASK_STICKY 0xe9
116
117	/** The LCR register index (from the base of the port range). */
118	#define UART_REG_LCR_INDEX 3
119	/** Word Length Select Mask. */
120	# define UART_REG_LCR_WLS_MASK 0x3
121	/** Returns the WLS value form the given LCR register value. */
122	# define UART_REG_LCR_WLS_GET(a_Lcr) ((a_Lcr) & UART_REG_LCR_WLS_MASK)
123	/** Number of stop bits. */
124	# define UART_REG_LCR_STB RT_BIT(2)
125	/** Parity Enable. */
126	# define UART_REG_LCR_PEN RT_BIT(3)
127	/** Even Parity. */
128	# define UART_REG_LCR_EPS RT_BIT(4)
129	/** Stick parity. */
130	# define UART_REG_LCR_PAR_STICK RT_BIT(5)
131	/** Set Break. */
132	# define UART_REG_LCR_BRK_SET RT_BIT(6)
133	/** Divisor Latch Access Bit. */
134	# define UART_REG_LCR_DLAB RT_BIT(7)
135
136	/** The MCR register index (from the base of the port range). */
137	#define UART_REG_MCR_INDEX 4
138	/** Data Terminal Ready. */
139	# define UART_REG_MCR_DTR RT_BIT(0)
140	/** Request To Send. */
141	# define UART_REG_MCR_RTS RT_BIT(1)
142	/** Out1. */
143	# define UART_REG_MCR_OUT1 RT_BIT(2)
144	/** Out2. */
145	# define UART_REG_MCR_OUT2 RT_BIT(3)
146	/** Loopback connection. */
147	# define UART_REG_MCR_LOOP RT_BIT(4)
148	/** Flow Control Enable (15750+ only). */
149	# define UART_REG_MCR_AFE RT_BIT(5)
150	/** Mask of writeable bits (15450 and 15550A). */
151	# define UART_REG_MCR_MASK_WR 0x1f
152	/** Mask of writeable bits (15750+). */
153	# define UART_REG_MCR_MASK_WR_15750 0x3f
154
155	/** The LSR register index (from the base of the port range). */
156	#define UART_REG_LSR_INDEX 5
157	/** Data Ready. */
158	# define UART_REG_LSR_DR RT_BIT(0)
159	/** Overrun Error. */
160	# define UART_REG_LSR_OE RT_BIT(1)
161	/** Parity Error. */
162	# define UART_REG_LSR_PE RT_BIT(2)
163	/** Framing Error. */
164	# define UART_REG_LSR_FE RT_BIT(3)
165	/** Break Interrupt. */
166	# define UART_REG_LSR_BI RT_BIT(4)
167	/** Transmitter Holding Register. */
168	# define UART_REG_LSR_THRE RT_BIT(5)
169	/** Transmitter Empty. */
170	# define UART_REG_LSR_TEMT RT_BIT(6)
171	/** Error in receiver FIFO. */
172	# define UART_REG_LSR_RCV_FIFO_ERR RT_BIT(7)
173	/** The bits to check in this register when checking for the RCL interrupt. */
174	# define UART_REG_LSR_BITS_IIR_RCL 0x1e
175
176	/** The MSR register index (from the base of the port range). */
177	#define UART_REG_MSR_INDEX 6
178	/** Delta Clear to Send. */
179	# define UART_REG_MSR_DCTS RT_BIT(0)
180	/** Delta Data Set Ready. */
181	# define UART_REG_MSR_DDSR RT_BIT(1)
182	/** Trailing Edge Ring Indicator. */
183	# define UART_REG_MSR_TERI RT_BIT(2)
184	/** Delta Data Carrier Detect. */
185	# define UART_REG_MSR_DDCD RT_BIT(3)
186	/** Clear to Send. */
187	# define UART_REG_MSR_CTS RT_BIT(4)
188	/** Data Set Ready. */
189	# define UART_REG_MSR_DSR RT_BIT(5)
190	/** Ring Indicator. */
191	# define UART_REG_MSR_RI RT_BIT(6)
192	/** Data Carrier Detect. */
193	# define UART_REG_MSR_DCD RT_BIT(7)
194	/** The bits to check in this register when checking for the MS interrupt. */
195	# define UART_REG_MSR_BITS_IIR_MS 0x0f
196
197	/** The SCR register index (from the base of the port range). */
198	#define UART_REG_SCR_INDEX 7
199
200	/** Set the specified bits in the given register. */
201	#define UART_REG_SET(a_Reg, a_Set) ((a_Reg) \|= (a_Set))
202	/** Clear the specified bits in the given register. */
203	#define UART_REG_CLR(a_Reg, a_Clr) ((a_Reg) &= ~(a_Clr))
204
205
206	/*********************************************************************************************************************************
207	* Structures and Typedefs *
208	*********************************************************************************************************************************/
209
210	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
211
212
213	/*********************************************************************************************************************************
214	* Global Variables *
215	*********************************************************************************************************************************/
216
217	#ifdef IN_RING3
218	/**
219	* FIFO ITL levels.
220	*/
221	static struct
222	{
223	/** ITL level for a 16byte FIFO. */
224	uint8_t cbItl16;
225	/** ITL level for a 64byte FIFO. */
226	uint8_t cbItl64;
227	} s_aFifoItl[] =
228	{
229	/* cbItl16 cbItl64 */
230	{ 1, 1 },
231	{ 4, 16 },
232	{ 8, 32 },
233	{ 14, 56 }
234	};
235
236
237	/**
238	* String versions of the parity enum.
239	*/
240	static const char *s_aszParity[] =
241	{
242	"INVALID",
243	"NONE",
244	"EVEN",
245	"ODD",
246	"MARK",
247	"SPACE",
248	"INVALID"
249	};
250
251
252	/**
253	* String versions of the stop bits enum.
254	*/
255	static const char *s_aszStopBits[] =
256	{
257	"INVALID",
258	"1",
259	"1.5",
260	"2",
261	"INVALID"
262	};
263	#endif
264
265
266	/*********************************************************************************************************************************
267	* Internal Functions *
268	*********************************************************************************************************************************/
269
270
271	/**
272	* Updates the IRQ state based on the current device state.
273	*
274	* @returns nothing.
275	* @param pThis The UART core instance.
276	*/
277	static void uartIrqUpdate(PUARTCORE pThis)
278	{
279	LogFlowFunc(("pThis=%#p\n", pThis));
280
281	/*
282	* The interrupt uses a priority scheme, only the interrupt with the
283	* highest priority is indicated in the interrupt identification register.
284	*
285	* The priorities are as follows (high to low):
286	* * Receiver line status
287	* * Received data available
288	* * Character timeout indication (only in FIFO mode).
289	* * Transmitter holding register empty
290	* * Modem status change.
291	*/
292	uint8_t uRegIirNew = UART_REG_IIR_IP_NO_INT;
293	if ( (pThis->uRegLsr & UART_REG_LSR_BITS_IIR_RCL)
294	&& (pThis->uRegIer & UART_REG_IER_ELSI))
295	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_RCL);
296	else if ( (pThis->uRegIer & UART_REG_IER_ERBFI)
297	&& pThis->fIrqCtiPending)
298	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_CTI);
299	else if ( (pThis->uRegLsr & UART_REG_LSR_DR)
300	&& (pThis->uRegIer & UART_REG_IER_ERBFI)
301	&& ( !(pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
302	\|\| pThis->FifoRecv.cbUsed >= pThis->FifoRecv.cbItl))
303	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_RDA);
304	else if ( (pThis->uRegLsr & UART_REG_LSR_THRE)
305	&& (pThis->uRegIer & UART_REG_IER_ETBEI))
306	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_THRE);
307	else if ( (pThis->uRegMsr & UART_REG_MSR_BITS_IIR_MS)
308	&& (pThis->uRegIer & UART_REG_IER_EDSSI))
309	uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_MS);
310
311	LogFlowFunc((" uRegIirNew=%#x uRegIir=%#x\n", uRegIirNew, pThis->uRegIir));
312
313	/* Change interrupt only if the interrupt status really changed from the previous value. */
314	if (uRegIirNew != (pThis->uRegIir & UART_REG_IIR_CHANGED_MASK))
315	{
316	LogFlow((" Interrupt source changed from %#x -> %#x (IRQ %d -> %d)\n",
317	pThis->uRegIir, uRegIirNew,
318	pThis->uRegIir == UART_REG_IIR_IP_NO_INT ? 0 : 1,
319	uRegIirNew == UART_REG_IIR_IP_NO_INT ? 0 : 1));
320	if (uRegIirNew == UART_REG_IIR_IP_NO_INT)
321	pThis->CTX_SUFF(pfnUartIrqReq)(pThis->CTX_SUFF(pDevIns), pThis, pThis->iLUN, 0);
322	else
323	pThis->CTX_SUFF(pfnUartIrqReq)(pThis->CTX_SUFF(pDevIns), pThis, pThis->iLUN, 1);
324	}
325	else
326	LogFlow((" No change in interrupt source\n"));
327
328	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
329	uRegIirNew \|= UART_REG_IIR_FIFOS_EN;
330	if (pThis->uRegFcr & UART_REG_FCR_64BYTE_FIFO_EN)
331	uRegIirNew \|= UART_REG_IIR_64BYTE_FIFOS_EN;
332
333	pThis->uRegIir = uRegIirNew;
334	}
335
336
337	/**
338	* Clears the given FIFO.
339	*
340	* @returns nothing.
341	* @param pFifo The FIFO to clear.
342	*/
343	DECLINLINE(void) uartFifoClear(PUARTFIFO pFifo)
344	{
345	memset(&pFifo->abBuf[0], 0, sizeof(pFifo->abBuf));
346	pFifo->cbUsed = 0;
347	pFifo->offWrite = 0;
348	pFifo->offRead = 0;
349	}
350
351
352	/**
353	* Returns the amount of free bytes in the given FIFO.
354	*
355	* @returns The amount of bytes free in the given FIFO.
356	* @param pFifo The FIFO.
357	*/
358	DECLINLINE(size_t) uartFifoFreeGet(PUARTFIFO pFifo)
359	{
360	return pFifo->cbMax - pFifo->cbUsed;
361	}
362
363
364	/**
365	* Puts a new character into the given FIFO.
366	*
367	* @returns Flag whether the FIFO overflowed.
368	* @param pFifo The FIFO to put the data into.
369	* @param fOvrWr Flag whether to overwrite data if the FIFO is full.
370	* @param bData The data to add.
371	*/
372	DECLINLINE(bool) uartFifoPut(PUARTFIFO pFifo, bool fOvrWr, uint8_t bData)
373	{
374	if (fOvrWr \|\| pFifo->cbUsed < pFifo->cbMax)
375	{
376	pFifo->abBuf[pFifo->offWrite] = bData;
377	pFifo->offWrite = (pFifo->offWrite + 1) % pFifo->cbMax;
378	}
379
380	bool fOverFlow = false;
381	if (pFifo->cbUsed < pFifo->cbMax)
382	pFifo->cbUsed++;
383	else
384	{
385	fOverFlow = true;
386	if (fOvrWr) /* Advance the read position to account for the lost character. */
387	pFifo->offRead = (pFifo->offRead + 1) % pFifo->cbMax;
388	}
389
390	return fOverFlow;
391	}
392
393
394	/**
395	* Returns the next character in the FIFO.
396	*
397	* @return Next byte in the FIFO.
398	* @param pFifo The FIFO to get data from.
399	*/
400	DECLINLINE(uint8_t) uartFifoGet(PUARTFIFO pFifo)
401	{
402	uint8_t bRet = 0;
403
404	if (pFifo->cbUsed)
405	{
406	bRet = pFifo->abBuf[pFifo->offRead];
407	pFifo->offRead = (pFifo->offRead + 1) % pFifo->cbMax;
408	pFifo->cbUsed--;
409	}
410
411	return bRet;
412	}
413
414
415	/**
416	* Tries to copy the requested amount of data from the given FIFO into the provided buffer.
417	*
418	* @returns Amount of bytes actually copied.
419	* @param pFifo The FIFO to copy data from.
420	* @param pvDst Where to copy the data to.
421	* @param cbCopy How much to copy.
422	*/
423	DECLINLINE(size_t) uartFifoCopyTo(PUARTFIFO pFifo, void *pvDst, size_t cbCopy)
424	{
425	size_t cbCopied = 0;
426	uint8_t pbDst = (uint8_t )pvDst;
427
428	cbCopy = RT_MIN(cbCopy, pFifo->cbUsed);
429	while (cbCopy)
430	{
431	size_t cbThisCopy = RT_MIN(cbCopy, (uint8_t)(pFifo->cbMax - pFifo->offRead));
432	memcpy(pbDst, &pFifo->abBuf[pFifo->offRead], cbThisCopy);
433
434	pFifo->offRead = (pFifo->offRead + cbThisCopy) % pFifo->cbMax;
435	pFifo->cbUsed -= cbThisCopy;
436	pbDst += cbThisCopy;
437	cbCopied += cbThisCopy;
438	cbCopy -= cbThisCopy;
439	}
440
441	return cbCopied;
442	}
443
444
445	/**
446	* Tries to copy the requested amount of data from the provided buffer into the given FIFO.
447	*
448	* @returns Amount of bytes actually copied.
449	* @param pFifo The FIFO to copy data to.
450	* @param pvSrc Where to copy the data from.
451	* @param cbCopy How much to copy.
452	*/
453	DECLINLINE(size_t) uartFifoCopyFrom(PUARTFIFO pFifo, void *pvSrc, size_t cbCopy)
454	{
455	size_t cbCopied = 0;
456	uint8_t pbSrc = (uint8_t )pvSrc;
457
458	cbCopy = RT_MIN(cbCopy, uartFifoFreeGet(pFifo));
459	while (cbCopy)
460	{
461	size_t cbThisCopy = RT_MIN(cbCopy, (uint8_t)(pFifo->cbMax - pFifo->offWrite));
462	memcpy(&pFifo->abBuf[pFifo->offWrite], pbSrc, cbThisCopy);
463
464	pFifo->offWrite = (pFifo->offWrite + cbThisCopy) % pFifo->cbMax;
465	pFifo->cbUsed += cbThisCopy;
466	pbSrc += cbThisCopy;
467	cbCopied += cbThisCopy;
468	cbCopy -= cbThisCopy;
469	}
470
471	return cbCopied;
472	}
473
474
475	#ifdef IN_RING3
476	/**
477	* Updates the delta bits for the given MSR register value which has the status line
478	* bits set.
479	*
480	* @returns nothing.
481	* @param pThis The serial port instance.
482	* @param uMsrSts MSR value with the appropriate status bits set.
483	*/
484	static void uartR3MsrUpdate(PUARTCORE pThis, uint8_t uMsrSts)
485	{
486	/* Compare current and new states and set remaining bits accordingly. */
487	if ((uMsrSts & UART_REG_MSR_CTS) != (pThis->uRegMsr & UART_REG_MSR_CTS))
488	uMsrSts \|= UART_REG_MSR_DCTS;
489	if ((uMsrSts & UART_REG_MSR_DSR) != (pThis->uRegMsr & UART_REG_MSR_DSR))
490	uMsrSts \|= UART_REG_MSR_DDSR;
491	if ((uMsrSts & UART_REG_MSR_RI) != 0 && (pThis->uRegMsr & UART_REG_MSR_RI) == 0)
492	uMsrSts \|= UART_REG_MSR_TERI;
493	if ((uMsrSts & UART_REG_MSR_DCD) != (pThis->uRegMsr & UART_REG_MSR_DCD))
494	uMsrSts \|= UART_REG_MSR_DDCD;
495
496	pThis->uRegMsr = uMsrSts;
497
498	uartIrqUpdate(pThis);
499	}
500
501
502	/**
503	* Updates the serial port parameters of the attached driver with the current configuration.
504	*
505	* @returns nothing.
506	* @param pThis The serial port instance.
507	*/
508	static void uartR3ParamsUpdate(PUARTCORE pThis)
509	{
510	if ( pThis->uRegDivisor != 0
511	&& pThis->pDrvSerial)
512	{
513	uint32_t uBps = 115200 / pThis->uRegDivisor; /* This is for PC compatible serial port with a 1.8432 MHz crystal. */
514	unsigned cDataBits = UART_REG_LCR_WLS_GET(pThis->uRegLcr) + 5;
515	uint32_t cFrameBits = cDataBits;
516	PDMSERIALSTOPBITS enmStopBits = PDMSERIALSTOPBITS_ONE;
517	PDMSERIALPARITY enmParity = PDMSERIALPARITY_NONE;
518
519	if (pThis->uRegLcr & UART_REG_LCR_STB)
520	{
521	enmStopBits = cDataBits == 5 ? PDMSERIALSTOPBITS_ONEPOINTFIVE : PDMSERIALSTOPBITS_TWO;
522	cFrameBits += 2;
523	}
524	else
525	cFrameBits++;
526
527	if (pThis->uRegLcr & UART_REG_LCR_PEN)
528	{
529	/* Select the correct parity mode based on the even and stick parity bits. */
530	switch (pThis->uRegLcr & (UART_REG_LCR_EPS \| UART_REG_LCR_PAR_STICK))
531	{
532	case 0:
533	enmParity = PDMSERIALPARITY_ODD;
534	break;
535	case UART_REG_LCR_EPS:
536	enmParity = PDMSERIALPARITY_EVEN;
537	break;
538	case UART_REG_LCR_EPS \| UART_REG_LCR_PAR_STICK:
539	enmParity = PDMSERIALPARITY_SPACE;
540	break;
541	case UART_REG_LCR_PAR_STICK:
542	enmParity = PDMSERIALPARITY_MARK;
543	break;
544	default:
545	/* We should never get here as all cases where caught earlier. */
546	AssertMsgFailed(("This shouldn't happen at all: %#x\n",
547	pThis->uRegLcr & (UART_REG_LCR_EPS \| UART_REG_LCR_PAR_STICK)));
548	}
549
550	cFrameBits++;
551	}
552
553	uint64_t uTimerFreq = TMTimerGetFreq(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
554	pThis->cSymbolXferTicks = (uTimerFreq / uBps) * cFrameBits;
555
556	LogFlowFunc(("Changing parameters to: %u,%s,%u,%s\n",
557	uBps, s_aszParity[enmParity], cDataBits, s_aszStopBits[enmStopBits]));
558
559	int rc = pThis->pDrvSerial->pfnChgParams(pThis->pDrvSerial, uBps, enmParity, cDataBits, enmStopBits);
560	if (RT_FAILURE(rc))
561	LogRelMax(10, ("Serial#%d: Failed to change parameters to %u,%s,%u,%s -> %Rrc\n",
562	pThis->pDevInsR3->iInstance, uBps, s_aszParity[enmParity], cDataBits, s_aszStopBits[enmStopBits], rc));
563
564	/* Changed parameters will flush all receive queues, so there won't be any data to read even if indicated. */
565	ASMAtomicWriteU32(&pThis->cbAvailRdr, 0);
566	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
567	}
568	}
569
570
571	/**
572	* Updates the internal device state with the given PDM status line states.
573	*
574	* @returns nothing.
575	* @param pThis The serial port instance.
576	* @param fStsLines The PDM status line states.
577	*/
578	static void uartR3StsLinesUpdate(PUARTCORE pThis, uint32_t fStsLines)
579	{
580	uint8_t uRegMsrNew = 0; /* The new MSR value. */
581
582	if (fStsLines & PDMISERIALPORT_STS_LINE_DCD)
583	uRegMsrNew \|= UART_REG_MSR_DCD;
584	if (fStsLines & PDMISERIALPORT_STS_LINE_RI)
585	uRegMsrNew \|= UART_REG_MSR_RI;
586	if (fStsLines & PDMISERIALPORT_STS_LINE_DSR)
587	uRegMsrNew \|= UART_REG_MSR_DSR;
588	if (fStsLines & PDMISERIALPORT_STS_LINE_CTS)
589	uRegMsrNew \|= UART_REG_MSR_CTS;
590
591	uartR3MsrUpdate(pThis, uRegMsrNew);
592	}
593
594
595	/**
596	* Fills up the receive FIFO with as much data as possible.
597	*
598	* @returns nothing.
599	* @param pThis The serial port instance.
600	*/
601	static void uartR3RecvFifoFill(PUARTCORE pThis)
602	{
603	LogFlowFunc(("pThis=%#p\n", pThis));
604
605	PUARTFIFO pFifo = &pThis->FifoRecv;
606	size_t cbFill = RT_MIN(uartFifoFreeGet(pFifo),
607	ASMAtomicReadU32(&pThis->cbAvailRdr));
608	size_t cbFilled = 0;
609
610	while (cbFilled < cbFill)
611	{
612	size_t cbThisRead = RT_MIN(cbFill - cbFilled, (uint8_t)(pFifo->cbMax - pFifo->offWrite));
613	size_t cbRead = 0;
614	int rc = pThis->pDrvSerial->pfnReadRdr(pThis->pDrvSerial, &pFifo->abBuf[pFifo->offWrite], cbThisRead, &cbRead);
615	/Assert(RT_SUCCESS(rc) && cbRead == cbThisRead);/ RT_NOREF(rc);
616
617	pFifo->offWrite = (pFifo->offWrite + cbRead) % pFifo->cbMax;
618	pFifo->cbUsed += cbRead;
619	cbFilled += cbRead;
620
621	if (cbRead < cbThisRead)
622	break;
623	}
624
625	if (cbFilled)
626	{
627	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
628	uartIrqUpdate(pThis);
629	}
630
631	Assert(cbFilled <= pThis->cbAvailRdr);
632	ASMAtomicSubU32(&pThis->cbAvailRdr, cbFilled);
633	}
634
635
636	/**
637	* Fetches a single byte and writes it to RBR.
638	*
639	* @returns nothing.
640	* @param pThis The serial port instance.
641	*/
642	static void uartR3ByteFetch(PUARTCORE pThis)
643	{
644	if (ASMAtomicReadU32(&pThis->cbAvailRdr))
645	{
646	AssertPtr(pThis->pDrvSerial);
647	size_t cbRead = 0;
648	int rc2 = pThis->pDrvSerial->pfnReadRdr(pThis->pDrvSerial, &pThis->uRegRbr, 1, &cbRead);
649	AssertMsg(RT_SUCCESS(rc2) && cbRead == 1, ("This shouldn't fail and always return one byte!\n")); RT_NOREF(rc2);
650	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
651	uartIrqUpdate(pThis);
652	}
653	}
654
655
656	/**
657	* Fetches a ready data based on the FIFO setting.
658	*
659	* @returns nothing.
660	* @param pThis The serial port instance.
661	*/
662	static void uartR3DataFetch(PUARTCORE pThis)
663	{
664	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
665	uartR3RecvFifoFill(pThis);
666	else
667	uartR3ByteFetch(pThis);
668	}
669	#endif
670
671
672	/**
673	* Write handler for the THR/DLL register (depending on the DLAB bit in LCR).
674	*
675	* @returns VBox status code.
676	* @param pThis The serial port instance.
677	* @param uVal The value to write.
678	*/
679	DECLINLINE(int) uartRegThrDllWrite(PUARTCORE pThis, uint8_t uVal)
680	{
681	int rc = VINF_SUCCESS;
682
683	/* A set DLAB causes a write to the lower 8bits of the divisor latch. */
684	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
685	{
686	if (uVal != (pThis->uRegDivisor & 0xff))
687	{
688	#ifndef IN_RING3
689	rc = VINF_IOM_R3_IOPORT_WRITE;
690	#else
691	pThis->uRegDivisor = (pThis->uRegDivisor & 0xff00) \| uVal;
692	uartR3ParamsUpdate(pThis);
693	#endif
694	}
695	}
696	else
697	{
698	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
699	{
700	#ifndef IN_RING3
701	rc = VINF_IOM_R3_IOPORT_WRITE;
702	#else
703	uartFifoPut(&pThis->FifoXmit, true /fOvrWr/, uVal);
704	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE \| UART_REG_LSR_TEMT);
705	uartIrqUpdate(pThis);
706	if (pThis->pDrvSerial)
707	{
708	int rc2 = pThis->pDrvSerial->pfnDataAvailWrNotify(pThis->pDrvSerial, 1);
709	if (RT_FAILURE(rc2))
710	LogRelMax(10, ("Serial#%d: Failed to send data with %Rrc\n", rc2));
711	}
712	#endif
713	}
714	else
715	{
716	/* Notify the lower driver about available data only if the register was empty before. */
717	if (pThis->uRegLsr & UART_REG_LSR_THRE)
718	{
719	#ifndef IN_RING3
720	rc = VINF_IOM_R3_IOPORT_WRITE;
721	#else
722	pThis->uRegThr = uVal;
723	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE \| UART_REG_LSR_TEMT);
724	uartIrqUpdate(pThis);
725	if (pThis->pDrvSerial)
726	{
727	int rc2 = pThis->pDrvSerial->pfnDataAvailWrNotify(pThis->pDrvSerial, 1);
728	if (RT_FAILURE(rc2))
729	LogRelMax(10, ("Serial#%d: Failed to send data with %Rrc\n", rc2));
730	}
731	#endif
732	}
733	else
734	pThis->uRegThr = uVal;
735	}
736	}
737
738	return rc;
739	}
740
741
742	/**
743	* Write handler for the IER/DLM register (depending on the DLAB bit in LCR).
744	*
745	* @returns VBox status code.
746	* @param pThis The serial port instance.
747	* @param uVal The value to write.
748	*/
749	DECLINLINE(int) uartRegIerDlmWrite(PUARTCORE pThis, uint8_t uVal)
750	{
751	int rc = VINF_SUCCESS;
752
753	/* A set DLAB causes a write to the higher 8bits of the divisor latch. */
754	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
755	{
756	if (uVal != (pThis->uRegDivisor & 0xff00) >> 8)
757	{
758	#ifndef IN_RING3
759	rc = VINF_IOM_R3_IOPORT_WRITE;
760	#else
761	pThis->uRegDivisor = (pThis->uRegDivisor & 0xff) \| (uVal << 8);
762	uartR3ParamsUpdate(pThis);
763	#endif
764	}
765	}
766	else
767	{
768	if (pThis->enmType < UARTTYPE_16750)
769	pThis->uRegIer = uVal & UART_REG_IER_MASK_WR;
770	else
771	pThis->uRegIer = uVal & UART_REG_IER_MASK_WR_16750;
772	uartIrqUpdate(pThis);
773	}
774
775	return rc;
776	}
777
778
779	/**
780	* Write handler for the FCR register.
781	*
782	* @returns VBox status code.
783	* @param pThis The serial port instance.
784	* @param uVal The value to write.
785	*/
786	DECLINLINE(int) uartRegFcrWrite(PUARTCORE pThis, uint8_t uVal)
787	{
788	#ifndef IN_RING3
789	RT_NOREF(pThis, uVal);
790	return VINF_IOM_R3_IOPORT_WRITE;
791	#else
792	int rc = VINF_SUCCESS;
793	if ( pThis->enmType >= UARTTYPE_16550A
794	&& uVal != pThis->uRegFcr)
795	{
796	/* A change in the FIFO enable bit clears both FIFOs automatically. */
797	if ((uVal ^ pThis->uRegFcr) & UART_REG_FCR_FIFO_EN)
798	{
799	uartFifoClear(&pThis->FifoXmit);
800	uartFifoClear(&pThis->FifoRecv);
801
802	/*
803	* If the FIFO is about to be enabled and the DR bit is ready we have an unacknowledged
804	* byte in the RBR register which will be lost so we have to adjust the available bytes.
805	*/
806	if ( ASMAtomicReadU32(&pThis->cbAvailRdr) > 0
807	&& (pThis->uRegFcr & UART_REG_FCR_FIFO_EN))
808	ASMAtomicDecU32(&pThis->cbAvailRdr);
809
810	/* Clear the DR bit too. */
811	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
812	}
813
814	if (rc == VINF_SUCCESS)
815	{
816	if (uVal & UART_REG_FCR_RCV_FIFO_RST)
817	{
818	TMTimerStop(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
819	pThis->fIrqCtiPending = false;
820	uartFifoClear(&pThis->FifoRecv);
821	}
822	if (uVal & UART_REG_FCR_XMIT_FIFO_RST)
823	uartFifoClear(&pThis->FifoXmit);
824
825	/*
826	* The 64byte FIFO enable bit is only changeable for 16750
827	* and if the DLAB bit in LCR is set.
828	*/
829	if ( pThis->enmType < UARTTYPE_16750
830	\|\| !(pThis->uRegLcr & UART_REG_LCR_DLAB))
831	uVal &= ~UART_REG_FCR_64BYTE_FIFO_EN;
832	else /* Use previous value. */
833	uVal \|= pThis->uRegFcr & UART_REG_FCR_64BYTE_FIFO_EN;
834
835	if (uVal & UART_REG_FCR_64BYTE_FIFO_EN)
836	{
837	pThis->FifoRecv.cbMax = 64;
838	pThis->FifoXmit.cbMax = 64;
839	}
840	else
841	{
842	pThis->FifoRecv.cbMax = 16;
843	pThis->FifoXmit.cbMax = 16;
844	}
845
846	if (uVal & UART_REG_FCR_FIFO_EN)
847	{
848	uint8_t idxItl = UART_REG_FCR_RCV_LVL_IRQ_GET(uVal);
849	if (uVal & UART_REG_FCR_64BYTE_FIFO_EN)
850	pThis->FifoRecv.cbItl = s_aFifoItl[idxItl].cbItl64;
851	else
852	pThis->FifoRecv.cbItl = s_aFifoItl[idxItl].cbItl16;
853	}
854
855	/* The FIFO reset bits are self clearing. */
856	pThis->uRegFcr = uVal & UART_REG_FCR_MASK_STICKY;
857	uartIrqUpdate(pThis);
858	}
859
860	/* Fill in the next data. */
861	if (ASMAtomicReadU32(&pThis->cbAvailRdr))
862	uartR3DataFetch(pThis);
863	}
864
865	return rc;
866	#endif
867	}
868
869
870	/**
871	* Write handler for the LCR register.
872	*
873	* @returns VBox status code.
874	* @param pThis The serial port instance.
875	* @param uVal The value to write.
876	*/
877	DECLINLINE(int) uartRegLcrWrite(PUARTCORE pThis, uint8_t uVal)
878	{
879	int rc = VINF_SUCCESS;
880
881	/* Any change except the DLAB bit causes a switch to R3. */
882	if ((pThis->uRegLcr & ~UART_REG_LCR_DLAB) != (uVal & ~UART_REG_LCR_DLAB))
883	{
884	#ifndef IN_RING3
885	rc = VINF_IOM_R3_IOPORT_WRITE;
886	#else
887	/* Check whether the BREAK bit changed before updating the LCR value. */
888	bool fBrkEn = RT_BOOL(uVal & UART_REG_LCR_BRK_SET);
889	bool fBrkChg = fBrkEn != RT_BOOL(pThis->uRegLcr & UART_REG_LCR_BRK_SET);
890	pThis->uRegLcr = uVal;
891	uartR3ParamsUpdate(pThis);
892
893	if ( fBrkChg
894	&& pThis->pDrvSerial)
895	pThis->pDrvSerial->pfnChgBrk(pThis->pDrvSerial, fBrkEn);
896	#endif
897	}
898	else
899	pThis->uRegLcr = uVal;
900
901	return rc;
902	}
903
904
905	/**
906	* Write handler for the MCR register.
907	*
908	* @returns VBox status code.
909	* @param pThis The serial port instance.
910	* @param uVal The value to write.
911	*/
912	DECLINLINE(int) uartRegMcrWrite(PUARTCORE pThis, uint8_t uVal)
913	{
914	int rc = VINF_SUCCESS;
915
916	if (pThis->enmType < UARTTYPE_16750)
917	uVal &= UART_REG_MCR_MASK_WR;
918	else
919	uVal &= UART_REG_MCR_MASK_WR_15750;
920	if (pThis->uRegMcr != uVal)
921	{
922	#ifndef IN_RING3
923	rc = VINF_IOM_R3_IOPORT_WRITE;
924	#else
925	/*
926	* When loopback mode is activated the RTS, DTR, OUT1 and OUT2 lines are
927	* disconnected and looped back to MSR.
928	*/
929	if ( (uVal & UART_REG_MCR_LOOP)
930	&& !(pThis->uRegMcr & UART_REG_MCR_LOOP)
931	&& pThis->pDrvSerial)
932	pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial, false /fRts/, false /fDtr/);
933
934	pThis->uRegMcr = uVal;
935	if (uVal & UART_REG_MCR_LOOP)
936	{
937	uint8_t uRegMsrSts = 0;
938
939	if (uVal & UART_REG_MCR_RTS)
940	uRegMsrSts \|= UART_REG_MSR_CTS;
941	if (uVal & UART_REG_MCR_DTR)
942	uRegMsrSts \|= UART_REG_MSR_DSR;
943	if (uVal & UART_REG_MCR_OUT1)
944	uRegMsrSts \|= UART_REG_MSR_RI;
945	if (uVal & UART_REG_MCR_OUT2)
946	uRegMsrSts \|= UART_REG_MSR_DCD;
947	uartR3MsrUpdate(pThis, uRegMsrSts);
948	}
949	else if (pThis->pDrvSerial)
950	pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial,
951	RT_BOOL(uVal & UART_REG_MCR_RTS),
952	RT_BOOL(uVal & UART_REG_MCR_DTR));
953	#endif
954	}
955
956	return rc;
957	}
958
959
960	/**
961	* Read handler for the RBR/DLL register (depending on the DLAB bit in LCR).
962	*
963	* @returns VBox status code.
964	* @param pThis The serial port instance.
965	* @param puVal Where to store the read value on success.
966	*/
967	DECLINLINE(int) uartRegRbrDllRead(PUARTCORE pThis, uint32_t *puVal)
968	{
969	int rc = VINF_SUCCESS;
970
971	/* A set DLAB causes a read from the lower 8bits of the divisor latch. */
972	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
973	*puVal = pThis->uRegDivisor & 0xff;
974	else
975	{
976	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
977	{
978	/*
979	* Only go back to R3 if there is new data available for the FIFO
980	* and we would clear the interrupt to fill it up again.
981	*/
982	if ( pThis->FifoRecv.cbUsed <= pThis->FifoRecv.cbItl
983	&& ASMAtomicReadU32(&pThis->cbAvailRdr) > 0)
984	{
985	#ifndef IN_RING3
986	rc = VINF_IOM_R3_IOPORT_READ;
987	#else
988	uartR3RecvFifoFill(pThis);
989	#endif
990	}
991
992	if (rc == VINF_SUCCESS)
993	{
994	*puVal = uartFifoGet(&pThis->FifoRecv);
995	pThis->fIrqCtiPending = false;
996	if (!pThis->FifoRecv.cbUsed)
997	{
998	TMTimerStop(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
999	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
1000	}
1001	else
1002	{
1003	uint64_t tsCtiFire = TMTimerGet(pThis->CTX_SUFF(pTimerRcvFifoTimeout)) + pThis->cSymbolXferTicks * 4;
1004	TMTimerSet(pThis->CTX_SUFF(pTimerRcvFifoTimeout), tsCtiFire);
1005	}
1006	uartIrqUpdate(pThis);
1007	}
1008	}
1009	else
1010	{
1011	*puVal = pThis->uRegRbr;
1012
1013	if (pThis->uRegLsr & UART_REG_LSR_DR)
1014	{
1015	Assert(pThis->cbAvailRdr);
1016	uint32_t cbAvail = ASMAtomicDecU32(&pThis->cbAvailRdr);
1017	if (!cbAvail)
1018	{
1019	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
1020	uartIrqUpdate(pThis);
1021	}
1022	else
1023	{
1024	#ifndef IN_RING3
1025	/* Restore state and go back to R3. */
1026	ASMAtomicIncU32(&pThis->cbAvailRdr);
1027	rc = VINF_IOM_R3_IOPORT_READ;
1028	#else
1029	/* Fetch new data and keep the DR bit set. */
1030	uartR3DataFetch(pThis);
1031	#endif
1032	}
1033	}
1034	}
1035	}
1036
1037	return rc;
1038	}
1039
1040
1041	/**
1042	* Read handler for the IER/DLM register (depending on the DLAB bit in LCR).
1043	*
1044	* @returns VBox status code.
1045	* @param pThis The serial port instance.
1046	* @param puVal Where to store the read value on success.
1047	*/
1048	DECLINLINE(int) uartRegIerDlmRead(PUARTCORE pThis, uint32_t *puVal)
1049	{
1050	int rc = VINF_SUCCESS;
1051
1052	/* A set DLAB causes a read from the upper 8bits of the divisor latch. */
1053	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1054	*puVal = (pThis->uRegDivisor & 0xff00) >> 8;
1055	else
1056	*puVal = pThis->uRegIer;
1057
1058	return rc;
1059	}
1060
1061
1062	/**
1063	* Read handler for the IIR register.
1064	*
1065	* @returns VBox status code.
1066	* @param pThis The serial port instance.
1067	* @param puVal Where to store the read value on success.
1068	*/
1069	DECLINLINE(int) uartRegIirRead(PUARTCORE pThis, uint32_t *puVal)
1070	{
1071	*puVal = pThis->uRegIir;
1072	return VINF_SUCCESS;
1073	}
1074
1075
1076	/**
1077	* Read handler for the LSR register.
1078	*
1079	* @returns VBox status code.
1080	* @param pThis The serial port instance.
1081	* @param puVal Where to store the read value on success.
1082	*/
1083	DECLINLINE(int) uartRegLsrRead(PUARTCORE pThis, uint32_t *puVal)
1084	{
1085	int rc = VINF_SUCCESS;
1086
1087	/* Yield if configured and there is no data available. */
1088	if ( !(pThis->uRegLsr & UART_REG_LSR_DR)
1089	&& (pThis->fFlags & UART_CORE_YIELD_ON_LSR_READ))
1090	{
1091	#ifndef IN_RING3
1092	return VINF_IOM_R3_IOPORT_READ;
1093	#else
1094	RTThreadYield();
1095	#endif
1096	}
1097
1098	*puVal = pThis->uRegLsr;
1099	/*
1100	* Reading this register clears the Overrun (OE), Parity (PE) and Framing (FE) error
1101	* as well as the Break Interrupt (BI).
1102	*/
1103	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_BITS_IIR_RCL);
1104	uartIrqUpdate(pThis);
1105
1106	return rc;
1107	}
1108
1109
1110	/**
1111	* Read handler for the MSR register.
1112	*
1113	* @returns VBox status code.
1114	* @param pThis The serial port instance.
1115	* @param puVal Where to store the read value on success.
1116	*/
1117	DECLINLINE(int) uartRegMsrRead(PUARTCORE pThis, uint32_t *puVal)
1118	{
1119	*puVal = pThis->uRegMsr;
1120
1121	/* Clear any of the delta bits. */
1122	UART_REG_CLR(pThis->uRegMsr, UART_REG_MSR_BITS_IIR_MS);
1123	uartIrqUpdate(pThis);
1124	return VINF_SUCCESS;
1125	}
1126
1127
1128	#ifdef LOG_ENABLED
1129	/**
1130	* Converts the register index into a sensible memnonic.
1131	*
1132	* @returns Register memnonic.
1133	* @param pThis The serial port instance.
1134	* @param idxReg Register index.
1135	* @param fWrite Flag whether the register gets written.
1136	*/
1137	DECLINLINE(const char *) uartRegIdx2Str(PUARTCORE pThis, uint8_t idxReg, bool fWrite)
1138	{
1139	const char *psz = "INV";
1140
1141	switch (idxReg)
1142	{
1143	/case UART_REG_THR_DLL_INDEX:/
1144	case UART_REG_RBR_DLL_INDEX:
1145	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1146	psz = "DLL";
1147	else if (fWrite)
1148	psz = "THR";
1149	else
1150	psz = "RBR";
1151	break;
1152	case UART_REG_IER_DLM_INDEX:
1153	if (pThis->uRegLcr & UART_REG_LCR_DLAB)
1154	psz = "DLM";
1155	else
1156	psz = "IER";
1157	break;
1158	/case UART_REG_IIR_INDEX:/
1159	case UART_REG_FCR_INDEX:
1160	if (fWrite)
1161	psz = "FCR";
1162	else
1163	psz = "IIR";
1164	break;
1165	case UART_REG_LCR_INDEX:
1166	psz = "LCR";
1167	break;
1168	case UART_REG_MCR_INDEX:
1169	psz = "MCR";
1170	break;
1171	case UART_REG_LSR_INDEX:
1172	psz = "LSR";
1173	break;
1174	case UART_REG_MSR_INDEX:
1175	psz = "MSR";
1176	break;
1177	case UART_REG_SCR_INDEX:
1178	psz = "SCR";
1179	break;
1180	}
1181
1182	return psz;
1183	}
1184	#endif
1185
1186
1187	DECLHIDDEN(int) uartRegWrite(PUARTCORE pThis, uint32_t uReg, uint32_t u32, size_t cb)
1188	{
1189	AssertMsgReturn(cb == 1, ("uReg=%#x cb=%d u32=%#x\n", uReg, cb, u32), VINF_SUCCESS);
1190
1191	int rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_R3_IOPORT_WRITE);
1192	if (rc != VINF_SUCCESS)
1193	return rc;
1194
1195	uint8_t idxReg = uReg & 0x7;
1196	LogFlowFunc(("pThis=%#p uReg=%u{%s} u32=%#x cb=%u\n",
1197	pThis, uReg, uartRegIdx2Str(pThis, idxReg, true /fWrite/), u32, cb));
1198
1199	uint8_t uVal = (uint8_t)u32;
1200	switch (idxReg)
1201	{
1202	case UART_REG_THR_DLL_INDEX:
1203	rc = uartRegThrDllWrite(pThis, uVal);
1204	break;
1205	case UART_REG_IER_DLM_INDEX:
1206	rc = uartRegIerDlmWrite(pThis, uVal);
1207	break;
1208	case UART_REG_FCR_INDEX:
1209	rc = uartRegFcrWrite(pThis, uVal);
1210	break;
1211	case UART_REG_LCR_INDEX:
1212	rc = uartRegLcrWrite(pThis, uVal);
1213	break;
1214	case UART_REG_MCR_INDEX:
1215	rc = uartRegMcrWrite(pThis, uVal);
1216	break;
1217	case UART_REG_SCR_INDEX:
1218	pThis->uRegScr = u32;
1219	break;
1220	default:
1221	break;
1222	}
1223
1224	PDMCritSectLeave(&pThis->CritSect);
1225	LogFlowFunc(("-> %Rrc\n", rc));
1226	return rc;
1227	}
1228
1229
1230	DECLHIDDEN(int) uartRegRead(PUARTCORE pThis, uint32_t uReg, uint32_t *pu32, size_t cb)
1231	{
1232	if (cb != 1)
1233	return VERR_IOM_IOPORT_UNUSED;
1234
1235	int rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_R3_IOPORT_READ);
1236	if (rc != VINF_SUCCESS)
1237	return rc;
1238
1239	uint8_t idxReg = uReg & 0x7;
1240	switch (idxReg)
1241	{
1242	case UART_REG_RBR_DLL_INDEX:
1243	rc = uartRegRbrDllRead(pThis, pu32);
1244	break;
1245	case UART_REG_IER_DLM_INDEX:
1246	rc = uartRegIerDlmRead(pThis, pu32);
1247	break;
1248	case UART_REG_IIR_INDEX:
1249	rc = uartRegIirRead(pThis, pu32);
1250	break;
1251	case UART_REG_LCR_INDEX:
1252	*pu32 = pThis->uRegLcr;
1253	break;
1254	case UART_REG_MCR_INDEX:
1255	*pu32 = pThis->uRegMcr;
1256	break;
1257	case UART_REG_LSR_INDEX:
1258	rc = uartRegLsrRead(pThis, pu32);
1259	break;
1260	case UART_REG_MSR_INDEX:
1261	rc = uartRegMsrRead(pThis, pu32);
1262	break;
1263	case UART_REG_SCR_INDEX:
1264	*pu32 = pThis->uRegScr;
1265	break;
1266	default:
1267	rc = VERR_IOM_IOPORT_UNUSED;
1268	}
1269
1270	PDMCritSectLeave(&pThis->CritSect);
1271	LogFlowFunc(("pThis=%#p uReg=%u{%s} u32=%#x cb=%u -> %Rrc\n",
1272	pThis, uReg, uartRegIdx2Str(pThis, idxReg, false /fWrite/), *pu32, cb, rc));
1273	return rc;
1274	}
1275
1276
1277	#ifdef IN_RING3
1278
1279	/* -=-=-=-=-=-=-=-=- Timer callbacks -=-=-=-=-=-=-=-=- */
1280
1281	/**
1282	* @callback_method_impl{FNTMTIMERDEV, Fifo timer function.}
1283	*/
1284	static DECLCALLBACK(void) uartR3RcvFifoTimeoutTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1285	{
1286	RT_NOREF(pDevIns, pTimer);
1287	PUARTCORE pThis = (PUARTCORE)pvUser;
1288	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1289	if (pThis->FifoRecv.cbUsed)
1290	{
1291	pThis->fIrqCtiPending = true;
1292	uartIrqUpdate(pThis);
1293	}
1294	PDMCritSectLeave(&pThis->CritSect);
1295	}
1296
1297
1298	/* -=-=-=-=-=-=-=-=- PDMISERIALPORT on LUN#0 -=-=-=-=-=-=-=-=- */
1299
1300
1301	/**
1302	* @interface_method_impl{PDMISERIALPORT,pfnDataAvailRdrNotify}
1303	*/
1304	static DECLCALLBACK(int) uartR3DataAvailRdrNotify(PPDMISERIALPORT pInterface, size_t cbAvail)
1305	{
1306	LogFlowFunc(("pInterface=%#p cbAvail=%zu\n", pInterface, cbAvail));
1307	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1308
1309	AssertMsg((uint32_t)cbAvail == cbAvail, ("Too much data available\n"));
1310
1311	uint32_t cbAvailOld = ASMAtomicAddU32(&pThis->cbAvailRdr, (uint32_t)cbAvail);
1312	LogFlow((" cbAvailRdr=%zu -> cbAvailRdr=%zu\n", cbAvailOld, cbAvail + cbAvailOld));
1313	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1314	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
1315	uartR3RecvFifoFill(pThis);
1316	else if (!cbAvailOld)
1317	{
1318	size_t cbRead = 0;
1319	int rc = pThis->pDrvSerial->pfnReadRdr(pThis->pDrvSerial, &pThis->uRegRbr, 1, &cbRead);
1320	AssertMsg(RT_SUCCESS(rc) && cbRead == 1, ("This shouldn't fail and always return one byte!\n")); RT_NOREF(rc);
1321	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_DR);
1322	uartIrqUpdate(pThis);
1323	}
1324	PDMCritSectLeave(&pThis->CritSect);
1325
1326	return VINF_SUCCESS;
1327	}
1328
1329
1330	/**
1331	* @interface_method_impl{PDMISERIALPORT,pfnDataSentNotify}
1332	*/
1333	static DECLCALLBACK(int) uartR3DataSentNotify(PPDMISERIALPORT pInterface)
1334	{
1335	LogFlowFunc(("pInterface=%#p\n", pInterface));
1336	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1337
1338	/* Set the transmitter empty bit because everything was sent. */
1339	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1340	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_TEMT);
1341	uartIrqUpdate(pThis);
1342	PDMCritSectLeave(&pThis->CritSect);
1343	return VINF_SUCCESS;
1344	}
1345
1346
1347	/**
1348	* @interface_method_impl{PDMISERIALPORT,pfnReadWr}
1349	*/
1350	static DECLCALLBACK(int) uartR3ReadWr(PPDMISERIALPORT pInterface, void pvBuf, size_t cbRead, size_t pcbRead)
1351	{
1352	LogFlowFunc(("pInterface=%#p pvBuf=%#p cbRead=%zu pcbRead=%#p\n", pInterface, pvBuf, cbRead, pcbRead));
1353	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1354
1355	AssertReturn(cbRead > 0, VERR_INVALID_PARAMETER);
1356
1357	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1358	if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
1359	{
1360	*pcbRead = uartFifoCopyTo(&pThis->FifoXmit, pvBuf, cbRead);
1361	if (!pThis->FifoXmit.cbUsed)
1362	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_THRE);
1363	if (*pcbRead)
1364	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_TEMT);
1365	uartIrqUpdate(pThis);
1366	}
1367	else if (!(pThis->uRegLsr & UART_REG_LSR_THRE))
1368	{
1369	(uint8_t )pvBuf = pThis->uRegThr;
1370	*pcbRead = 1;
1371	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_THRE);
1372	UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_TEMT);
1373	uartIrqUpdate(pThis);
1374	}
1375	else
1376	{
1377	/*
1378	* This can happen if there was data in the FIFO when the connection was closed,
1379	* idicate this condition to the lower driver by returning 0 bytes.
1380	*/
1381	*pcbRead = 0;
1382	}
1383	PDMCritSectLeave(&pThis->CritSect);
1384
1385	LogFlowFunc(("-> VINF_SUCCESS{pcbRead=%zu}\n", pcbRead));
1386	return VINF_SUCCESS;
1387	}
1388
1389
1390	/**
1391	* @interface_method_impl{PDMISERIALPORT,pfnNotifyStsLinesChanged}
1392	*/
1393	static DECLCALLBACK(int) uartR3NotifyStsLinesChanged(PPDMISERIALPORT pInterface, uint32_t fNewStatusLines)
1394	{
1395	LogFlowFunc(("pInterface=%#p fNewStatusLines=%#x\n", pInterface, fNewStatusLines));
1396	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1397
1398	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1399	uartR3StsLinesUpdate(pThis, fNewStatusLines);
1400	PDMCritSectLeave(&pThis->CritSect);
1401	return VINF_SUCCESS;
1402	}
1403
1404
1405	/**
1406	* @interface_method_impl{PDMISERIALPORT,pfnNotifyBrk}
1407	*/
1408	static DECLCALLBACK(int) uartR3NotifyBrk(PPDMISERIALPORT pInterface)
1409	{
1410	LogFlowFunc(("pInterface=%#p\n", pInterface));
1411	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, ISerialPort);
1412
1413	PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
1414	UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_BI);
1415	uartIrqUpdate(pThis);
1416	PDMCritSectLeave(&pThis->CritSect);
1417	return VINF_SUCCESS;
1418	}
1419
1420
1421	/* -=-=-=-=-=-=-=-=- PDMIBASE -=-=-=-=-=-=-=-=- */
1422
1423	/**
1424	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
1425	*/
1426	static DECLCALLBACK(void ) uartR3QueryInterface(PPDMIBASE pInterface, const char pszIID)
1427	{
1428	PUARTCORE pThis = RT_FROM_MEMBER(pInterface, UARTCORE, IBase);
1429	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
1430	PDMIBASE_RETURN_INTERFACE(pszIID, PDMISERIALPORT, &pThis->ISerialPort);
1431	return NULL;
1432	}
1433
1434
1435	DECLHIDDEN(int) uartR3SaveExec(PUARTCORE pThis, PSSMHANDLE pSSM)
1436	{
1437	SSMR3PutU16(pSSM, pThis->uRegDivisor);
1438	SSMR3PutU8(pSSM, pThis->uRegRbr);
1439	SSMR3PutU8(pSSM, pThis->uRegThr);
1440	SSMR3PutU8(pSSM, pThis->uRegIer);
1441	SSMR3PutU8(pSSM, pThis->uRegIir);
1442	SSMR3PutU8(pSSM, pThis->uRegFcr);
1443	SSMR3PutU8(pSSM, pThis->uRegLcr);
1444	SSMR3PutU8(pSSM, pThis->uRegMcr);
1445	SSMR3PutU8(pSSM, pThis->uRegLsr);
1446	SSMR3PutU8(pSSM, pThis->uRegMsr);
1447	SSMR3PutU8(pSSM, pThis->uRegScr);
1448	SSMR3PutBool(pSSM, pThis->fIrqCtiPending);
1449	SSMR3PutU8(pSSM, pThis->FifoXmit.cbMax);
1450	SSMR3PutU8(pSSM, pThis->FifoXmit.cbItl);
1451	SSMR3PutU8(pSSM, pThis->FifoRecv.cbMax);
1452	SSMR3PutU8(pSSM, pThis->FifoRecv.cbItl);
1453
1454	return TMR3TimerSave(pThis->pTimerRcvFifoTimeoutR3, pSSM);
1455	}
1456
1457
1458	DECLHIDDEN(int) uartR3LoadExec(PUARTCORE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass,
1459	uint8_t puIrq, RTIOPORT pPortBase)
1460	{
1461	RT_NOREF(uPass);
1462	int rc = VINF_SUCCESS;
1463
1464	if (uVersion > UART_SAVED_STATE_VERSION_LEGACY_CODE)
1465	{
1466	SSMR3GetU16(pSSM, &pThis->uRegDivisor);
1467	SSMR3GetU8(pSSM, &pThis->uRegRbr);
1468	SSMR3GetU8(pSSM, &pThis->uRegThr);
1469	SSMR3GetU8(pSSM, &pThis->uRegIer);
1470	SSMR3GetU8(pSSM, &pThis->uRegIir);
1471	SSMR3GetU8(pSSM, &pThis->uRegFcr);
1472	SSMR3GetU8(pSSM, &pThis->uRegLcr);
1473	SSMR3GetU8(pSSM, &pThis->uRegMcr);
1474	SSMR3GetU8(pSSM, &pThis->uRegLsr);
1475	SSMR3GetU8(pSSM, &pThis->uRegMsr);
1476	SSMR3GetU8(pSSM, &pThis->uRegScr);
1477	SSMR3GetBool(pSSM, &pThis->fIrqCtiPending);
1478	SSMR3GetU8(pSSM, &pThis->FifoXmit.cbMax);
1479	SSMR3GetU8(pSSM, &pThis->FifoXmit.cbItl);
1480	SSMR3GetU8(pSSM, &pThis->FifoRecv.cbMax);
1481	SSMR3GetU8(pSSM, &pThis->FifoRecv.cbItl);
1482
1483	TMR3TimerLoad(pThis->pTimerRcvFifoTimeoutR3, pSSM);
1484	}
1485	else
1486	{
1487	if (uVersion == UART_SAVED_STATE_VERSION_16450)
1488	{
1489	pThis->enmType = UARTTYPE_16450;
1490	LogRel(("Serial#%d: falling back to 16450 mode from load state\n", pThis->pDevInsR3->iInstance));
1491	}
1492
1493	int uIrq;
1494	uint32_t PortBase;
1495
1496	SSMR3GetU16(pSSM, &pThis->uRegDivisor);
1497	SSMR3GetU8(pSSM, &pThis->uRegRbr);
1498	SSMR3GetU8(pSSM, &pThis->uRegIer);
1499	SSMR3GetU8(pSSM, &pThis->uRegLcr);
1500	SSMR3GetU8(pSSM, &pThis->uRegMcr);
1501	SSMR3GetU8(pSSM, &pThis->uRegLsr);
1502	SSMR3GetU8(pSSM, &pThis->uRegMsr);
1503	SSMR3GetU8(pSSM, &pThis->uRegScr);
1504	if (uVersion > UART_SAVED_STATE_VERSION_16450)
1505	SSMR3GetU8(pSSM, &pThis->uRegFcr);
1506	SSMR3Skip(pSSM, sizeof(int32_t));
1507	SSMR3GetS32(pSSM, &uIrq);
1508	SSMR3Skip(pSSM, sizeof(int32_t));
1509	SSMR3GetU32(pSSM, &PortBase);
1510	rc = SSMR3Skip(pSSM, sizeof(int32_t));
1511
1512	if ( RT_SUCCESS(rc)
1513	&& uVersion > UART_SAVED_STATE_VERSION_MISSING_BITS)
1514	{
1515	SSMR3GetU8(pSSM, &pThis->uRegThr);
1516	SSMR3Skip(pSSM, sizeof(uint8_t)); /* The old transmit shift register, not used anymore. */
1517	SSMR3GetU8(pSSM, &pThis->uRegIir);
1518
1519	int iTimeoutPending = 0;
1520	SSMR3GetS32(pSSM, &iTimeoutPending);
1521	pThis->fIrqCtiPending = RT_BOOL(iTimeoutPending);
1522
1523	TMR3TimerLoad(pThis->pTimerRcvFifoTimeoutR3, pSSM);
1524	TMR3TimerSkip(pSSM, NULL);
1525	SSMR3GetU8(pSSM, &pThis->FifoRecv.cbItl);
1526	rc = SSMR3GetU8(pSSM, &pThis->FifoRecv.cbItl);
1527	}
1528
1529	if (RT_SUCCESS(rc))
1530	{
1531	AssertPtr(puIrq);
1532	AssertPtr(pPortBase);
1533	*puIrq = (uint8_t)uIrq;
1534	*pPortBase = (RTIOPORT)PortBase;
1535	}
1536	}
1537
1538	return rc;
1539	}
1540
1541
1542	DECLHIDDEN(int) uartR3LoadDone(PUARTCORE pThis, PSSMHANDLE pSSM)
1543	{
1544	RT_NOREF(pSSM);
1545
1546	uartR3ParamsUpdate(pThis);
1547	uartIrqUpdate(pThis);
1548
1549	if (pThis->pDrvSerial)
1550	{
1551	/* Set the modem lines to reflect the current state. */
1552	int rc = pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial,
1553	RT_BOOL(pThis->uRegMcr & UART_REG_MCR_RTS),
1554	RT_BOOL(pThis->uRegMcr & UART_REG_MCR_DTR));
1555	if (RT_FAILURE(rc))
1556	LogRel(("Serial#%d: Failed to set modem lines with %Rrc during saved state load\n",
1557	pThis->pDevInsR3->iInstance, rc));
1558
1559	uint32_t fStsLines = 0;
1560	rc = pThis->pDrvSerial->pfnQueryStsLines(pThis->pDrvSerial, &fStsLines);
1561	if (RT_SUCCESS(rc))
1562	uartR3StsLinesUpdate(pThis, fStsLines);
1563	else
1564	LogRel(("Serial#%d: Failed to query status line status with %Rrc during reset\n",
1565	pThis->pDevInsR3->iInstance, rc));
1566	}
1567
1568	return VINF_SUCCESS;
1569	}
1570
1571
1572	DECLHIDDEN(void) uartR3Relocate(PUARTCORE pThis, RTGCINTPTR offDelta)
1573	{
1574	RT_NOREF(offDelta);
1575	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pThis->pDevInsR3);
1576	pThis->pTimerRcvFifoTimeoutRC = TMTimerRCPtr(pThis->pTimerRcvFifoTimeoutR3);
1577	}
1578
1579
1580	DECLHIDDEN(void) uartR3Reset(PUARTCORE pThis)
1581	{
1582	pThis->uRegDivisor = 0x0c; /* Default to 9600 Baud. */
1583	pThis->uRegRbr = 0;
1584	pThis->uRegThr = 0;
1585	pThis->uRegIer = 0;
1586	pThis->uRegIir = UART_REG_IIR_IP_NO_INT;
1587	pThis->uRegFcr = 0;
1588	pThis->uRegLcr = 0; /* 5 data bits, no parity, 1 stop bit. */
1589	pThis->uRegMcr = 0;
1590	pThis->uRegLsr = UART_REG_LSR_THRE \| UART_REG_LSR_TEMT;
1591	pThis->uRegMsr = 0; /* Updated below. */
1592	pThis->uRegScr = 0;
1593	pThis->fIrqCtiPending = false;
1594
1595	/* Standard FIFO size for 15550A. */
1596	pThis->FifoXmit.cbMax = 16;
1597	pThis->FifoRecv.cbMax = 16;
1598	uartFifoClear(&pThis->FifoXmit);
1599	uartFifoClear(&pThis->FifoRecv);
1600	pThis->FifoRecv.cbItl = 1;
1601
1602	uartR3ParamsUpdate(pThis);
1603	uartIrqUpdate(pThis);
1604
1605	if (pThis->pDrvSerial)
1606	{
1607	/* Set the modem lines to reflect the current state. */
1608	int rc = pThis->pDrvSerial->pfnChgModemLines(pThis->pDrvSerial, false /fRts/, false /fDtr/);
1609	if (RT_FAILURE(rc))
1610	LogRel(("Serial#%d: Failed to set modem lines with %Rrc during reset\n",
1611	pThis->pDevInsR3->iInstance, rc));
1612
1613	uint32_t fStsLines = 0;
1614	rc = pThis->pDrvSerial->pfnQueryStsLines(pThis->pDrvSerial, &fStsLines);
1615	if (RT_SUCCESS(rc))
1616	uartR3StsLinesUpdate(pThis, fStsLines);
1617	else
1618	LogRel(("Serial#%d: Failed to query status line status with %Rrc during reset\n",
1619	pThis->pDevInsR3->iInstance, rc));
1620	}
1621	}
1622
1623
1624	DECLHIDDEN(int) uartR3Attach(PUARTCORE pThis, unsigned iLUN)
1625	{
1626	int rc = PDMDevHlpDriverAttach(pThis->pDevInsR3, iLUN, &pThis->IBase, &pThis->pDrvBase, "Serial Char");
1627	if (RT_SUCCESS(rc))
1628	{
1629	pThis->pDrvSerial = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMISERIALCONNECTOR);
1630	if (!pThis->pDrvSerial)
1631	{
1632	AssertLogRelMsgFailed(("Configuration error: instance %d has no serial interface!\n", pThis->pDevInsR3->iInstance));
1633	return VERR_PDM_MISSING_INTERFACE;
1634	}
1635	}
1636	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1637	{
1638	pThis->pDrvBase = NULL;
1639	pThis->pDrvSerial = NULL;
1640	rc = VINF_SUCCESS;
1641	LogRel(("Serial#%d: no unit\n", pThis->pDevInsR3->iInstance));
1642	}
1643	else /* Don't call VMSetError here as we assume that the driver already set an appropriate error */
1644	LogRel(("Serial#%d: Failed to attach to serial driver. rc=%Rrc\n", pThis->pDevInsR3->iInstance, rc));
1645
1646	return rc;
1647	}
1648
1649
1650	DECLHIDDEN(void) uartR3Detach(PUARTCORE pThis)
1651	{
1652	/* Zero out important members. */
1653	pThis->pDrvBase = NULL;
1654	pThis->pDrvSerial = NULL;
1655	}
1656
1657
1658	DECLHIDDEN(void) uartR3Destruct(PUARTCORE pThis)
1659	{
1660	PDMR3CritSectDelete(&pThis->CritSect);
1661	}
1662
1663
1664	DECLHIDDEN(int) uartR3Init(PUARTCORE pThis, PPDMDEVINS pDevInsR3, UARTTYPE enmType, unsigned iLUN, uint32_t fFlags,
1665	R3PTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqR3, R0PTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqR0,
1666	RCPTRTYPE(PFNUARTCOREIRQREQ) pfnUartIrqReqRC)
1667	{
1668	int rc = VINF_SUCCESS;
1669
1670	/*
1671	* Initialize the instance data.
1672	* (Do this early or the destructor might choke on something!)
1673	*/
1674	pThis->pDevInsR3 = pDevInsR3;
1675	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevInsR3);
1676	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevInsR3);
1677	pThis->iLUN = iLUN;
1678	pThis->enmType = enmType;
1679	pThis->fFlags = fFlags;
1680	pThis->pfnUartIrqReqR3 = pfnUartIrqReqR3;
1681	pThis->pfnUartIrqReqR0 = pfnUartIrqReqR0;
1682	pThis->pfnUartIrqReqRC = pfnUartIrqReqRC;
1683
1684	/* IBase */
1685	pThis->IBase.pfnQueryInterface = uartR3QueryInterface;
1686
1687	/* ISerialPort */
1688	pThis->ISerialPort.pfnDataAvailRdrNotify = uartR3DataAvailRdrNotify;
1689	pThis->ISerialPort.pfnDataSentNotify = uartR3DataSentNotify;
1690	pThis->ISerialPort.pfnReadWr = uartR3ReadWr;
1691	pThis->ISerialPort.pfnNotifyStsLinesChanged = uartR3NotifyStsLinesChanged;
1692	pThis->ISerialPort.pfnNotifyBrk = uartR3NotifyBrk;
1693
1694	rc = PDMDevHlpCritSectInit(pDevInsR3, &pThis->CritSect, RT_SRC_POS, "Uart{%s#%d}#%d",
1695	pDevInsR3->pReg->szName, pDevInsR3->iInstance, iLUN);
1696	AssertRCReturn(rc, rc);
1697
1698	/*
1699	* Attach the char driver and get the interfaces.
1700	*/
1701	rc = PDMDevHlpDriverAttach(pDevInsR3, iLUN, &pThis->IBase, &pThis->pDrvBase, "UART");
1702	if (RT_SUCCESS(rc))
1703	{
1704	pThis->pDrvSerial = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMISERIALCONNECTOR);
1705	if (!pThis->pDrvSerial)
1706	{
1707	AssertLogRelMsgFailed(("Configuration error: instance %d has no serial interface!\n", iLUN));
1708	return VERR_PDM_MISSING_INTERFACE;
1709	}
1710	}
1711	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1712	{
1713	pThis->pDrvBase = NULL;
1714	pThis->pDrvSerial = NULL;
1715	LogRel(("Serial#%d: no unit\n", iLUN));
1716	}
1717	else
1718	{
1719	AssertLogRelMsgFailed(("Serial#%d: Failed to attach to char driver. rc=%Rrc\n", iLUN, rc));
1720	/* Don't call VMSetError here as we assume that the driver already set an appropriate error */
1721	return rc;
1722	}
1723
1724	/*
1725	* Create the receive FIFO character timeout indicator timer.
1726	*/
1727	rc = PDMDevHlpTMTimerCreate(pDevInsR3, TMCLOCK_VIRTUAL, uartR3RcvFifoTimeoutTimer, pThis,
1728	TMTIMER_FLAGS_NO_CRIT_SECT, "UART Rcv FIFO Timer",
1729	&pThis->pTimerRcvFifoTimeoutR3);
1730	AssertRCReturn(rc, rc);
1731
1732	rc = TMR3TimerSetCritSect(pThis->pTimerRcvFifoTimeoutR3, &pThis->CritSect);
1733	AssertRCReturn(rc, rc);
1734
1735	pThis->pTimerRcvFifoTimeoutR0 = TMTimerR0Ptr(pThis->pTimerRcvFifoTimeoutR3);
1736	pThis->pTimerRcvFifoTimeoutRC = TMTimerRCPtr(pThis->pTimerRcvFifoTimeoutR3);
1737
1738	uartR3Reset(pThis);
1739	return VINF_SUCCESS;
1740	}
1741
1742	#endif /* IN_RING3 */
1743
1744	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */

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source: vbox/trunk/src/VBox/Devices/Serial/UartCore.cpp@ 73299

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