DevVGA-SVGA.cpp@ 86864

Last change on this file since 86864 was 86864, checked in by vboxsync, 5 years ago
Devices/Graphics: vmsvga3dQueryCaps for DX backend. bugref:9830
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1	/* $Id: DevVGA-SVGA.cpp 86864 2020-11-12 06:05:51Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	* - LogRel for the usual important stuff.
13	* - LogRel2 for cursor.
14	* - LogRel3 for 3D performance data.
15	* - LogRel4 for HW accelerated graphics output.
16	*/
17
18	/*
19	* Copyright (C) 2013-2020 Oracle Corporation
20	*
21	* This file is part of VirtualBox Open Source Edition (OSE), as
22	* available from http://www.215389.xyz. This file is free software;
23	* you can redistribute it and/or modify it under the terms of the GNU
24	* General Public License (GPL) as published by the Free Software
25	* Foundation, in version 2 as it comes in the "COPYING" file of the
26	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
27	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
28	*/
29
30
31	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
32	*
33	* This device emulation was contributed by trivirt AG. It offers an
34	* alternative to our Bochs based VGA graphics and 3d emulations. This is
35	* valuable for Xorg based guests, as there is driver support shipping with Xorg
36	* since it forked from XFree86.
37	*
38	*
39	* @section sec_dev_vmsvga_sdk The VMware SDK
40	*
41	* This is officially deprecated now, however it's still quite useful,
42	* especially for getting the old features working:
43	* http://vmware-svga.sourceforge.net/
44	*
45	* They currently point developers at the following resources.
46	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
47	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
48	* - http://cgit.freedesktop.org/mesa/vmwgfx/
49	*
50	* @subsection subsec_dev_vmsvga_sdk_results Test results
51	*
52	* Test results:
53	* - 2dmark.img:
54	* + todo
55	* - backdoor-tclo.img:
56	* + todo
57	* - blit-cube.img:
58	* + todo
59	* - bunnies.img:
60	* + todo
61	* - cube.img:
62	* + todo
63	* - cubemark.img:
64	* + todo
65	* - dynamic-vertex-stress.img:
66	* + todo
67	* - dynamic-vertex.img:
68	* + todo
69	* - fence-stress.img:
70	* + todo
71	* - gmr-test.img:
72	* + todo
73	* - half-float-test.img:
74	* + todo
75	* - noscreen-cursor.img:
76	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
77	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
78	* visible though.)
79	* - Cursor animation via the palette doesn't work.
80	* - During debugging, it turns out that the framebuffer content seems to
81	* be halfways ignore or something (memset(fb, 0xcc, lots)).
82	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
83	* grow it 0x10 fold (128KB -> 2MB like in WS10).
84	* - null.img:
85	* + todo
86	* - pong.img:
87	* + todo
88	* - presentReadback.img:
89	* + todo
90	* - resolution-set.img:
91	* + todo
92	* - rt-gamma-test.img:
93	* + todo
94	* - screen-annotation.img:
95	* + todo
96	* - screen-cursor.img:
97	* + todo
98	* - screen-dma-coalesce.img:
99	* + todo
100	* - screen-gmr-discontig.img:
101	* + todo
102	* - screen-gmr-remap.img:
103	* + todo
104	* - screen-multimon.img:
105	* + todo
106	* - screen-present-clip.img:
107	* + todo
108	* - screen-render-test.img:
109	* + todo
110	* - screen-simple.img:
111	* + todo
112	* - screen-text.img:
113	* + todo
114	* - simple-shaders.img:
115	* + todo
116	* - simple_blit.img:
117	* + todo
118	* - tiny-2d-updates.img:
119	* + todo
120	* - video-formats.img:
121	* + todo
122	* - video-sync.img:
123	* + todo
124	*
125	*/
126
127
128	/*********************************************************************************************************************************
129	* Header Files *
130	*********************************************************************************************************************************/
131	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
132	#include <VBox/vmm/pdmdev.h>
133	#include <VBox/version.h>
134	#include <VBox/err.h>
135	#include <VBox/log.h>
136	#include <VBox/vmm/pgm.h>
137	#include <VBox/sup.h>
138
139	#include <iprt/assert.h>
140	#include <iprt/semaphore.h>
141	#include <iprt/uuid.h>
142	#ifdef IN_RING3
143	# include <iprt/ctype.h>
144	# include <iprt/mem.h>
145	# ifdef VBOX_STRICT
146	# include <iprt/time.h>
147	# endif
148	#endif
149
150	#include <VBox/AssertGuest.h>
151	#include <VBox/VMMDev.h>
152	#include <VBoxVideo.h>
153	#include <VBox/bioslogo.h>
154
155	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
156	#include "DevVGA.h"
157
158	#ifdef IN_RING3
159	/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
160	#include "DevVGA-SVGA-internal.h"
161	#endif
162	#ifdef VBOX_WITH_VMSVGA3D
163	# include "DevVGA-SVGA3d.h"
164	# ifdef RT_OS_DARWIN
165	# include "DevVGA-SVGA3d-cocoa.h"
166	# endif
167	# ifdef RT_OS_LINUX
168	# ifdef IN_RING3
169	# include "DevVGA-SVGA3d-glLdr.h"
170	# endif
171	# endif
172	#endif
173
174
175	/*********************************************************************************************************************************
176	* Defined Constants And Macros *
177	*********************************************************************************************************************************/
178	/**
179	* Macro for checking if a fixed FIFO register is valid according to the
180	* current FIFO configuration.
181	*
182	* @returns true / false.
183	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
184	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
185	*/
186	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
187
188
189	/*********************************************************************************************************************************
190	* Structures and Typedefs *
191	*********************************************************************************************************************************/
192
193
194	/*********************************************************************************************************************************
195	* Internal Functions *
196	*********************************************************************************************************************************/
197	#ifdef IN_RING3
198	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
199	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
200	# endif
201	# ifdef DEBUG_GMR_ACCESS
202	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
203	# endif
204	#endif
205
206
207	/*********************************************************************************************************************************
208	* Global Variables *
209	*********************************************************************************************************************************/
210	#ifdef IN_RING3
211
212	/**
213	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
214	*/
215	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
216	{
217	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
218	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
219	SSMFIELD_ENTRY_TERM()
220	};
221
222	/**
223	* SSM descriptor table for the GMR structure.
224	*/
225	static SSMFIELD const g_aGMRFields[] =
226	{
227	SSMFIELD_ENTRY( GMR, cMaxPages),
228	SSMFIELD_ENTRY( GMR, cbTotal),
229	SSMFIELD_ENTRY( GMR, numDescriptors),
230	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
231	SSMFIELD_ENTRY_TERM()
232	};
233
234	/**
235	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
236	*/
237	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
238	{
239	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
240	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
241	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
242	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
243	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
244	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
245	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
246	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
247	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
248	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
249	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
250	SSMFIELD_ENTRY_VER( VMSVGASCREENOBJECT, cDpi, VGA_SAVEDSTATE_VERSION_VMSVGA_MIPLEVELS),
251	SSMFIELD_ENTRY_TERM()
252	};
253
254	/**
255	* SSM descriptor table for the VMSVGAR3STATE structure.
256	*/
257	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
258	{
259	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
260	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
261	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
262	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
263	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
264	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
265	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
266	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
267	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
268	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
269	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
270	#ifdef VMSVGA_USE_EMT_HALT_CODE
271	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
272	#else
273	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
274	#endif
275	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
276	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
277	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
278	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
279	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
280	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
281	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
282	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
283	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
284	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
285	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
286	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
287	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
288	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
289	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
290	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
291	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdMoveCursor),
292	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDisplayCursor),
293	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectFill),
294	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectCopy),
295	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectRopCopy),
296	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
297	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
298	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
299	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
300	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
301	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
302	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
303	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
304	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
305	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
306	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
307	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
308	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
309	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
310	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
311	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
312	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
313	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
314	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
315	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
316	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
317	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
318	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
319	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
320	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
321	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
322	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
323	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
324	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
325	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
326	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
327	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
328	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
329	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
330	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
331	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
332	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
333	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
334	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
335	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
336	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
337	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
338
339	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
340	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
341	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
342	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
343
344	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
345	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
346	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
347	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
348	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
349	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
350	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
351	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
352	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
353	# endif
354	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
355	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
356	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
357	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
358
359	SSMFIELD_ENTRY_TERM()
360	};
361
362	/**
363	* SSM descriptor table for the VGAState.svga structure.
364	*/
365	static SSMFIELD const g_aVGAStateSVGAFields[] =
366	{
367	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
368	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
369	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
370	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
371	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
372	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
373	SSMFIELD_ENTRY( VMSVGAState, fBusy),
374	SSMFIELD_ENTRY( VMSVGAState, fTraces),
375	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
376	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
377	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
378	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
379	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
380	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
381	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
382	SSMFIELD_ENTRY( VMSVGAState, u32DeviceCaps),
383	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
384	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
385	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
386	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
387	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
388	SSMFIELD_ENTRY( VMSVGAState, uWidth),
389	SSMFIELD_ENTRY( VMSVGAState, uHeight),
390	SSMFIELD_ENTRY( VMSVGAState, uBpp),
391	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
392	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
393	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorX, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
394	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorY, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
395	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorID, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
396	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorOn, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
397	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
398	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
399	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
400	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
401	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
402	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
403	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
404	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
405	SSMFIELD_ENTRY_TERM()
406	};
407	#endif /* IN_RING3 */
408
409
410	/*********************************************************************************************************************************
411	* Internal Functions *
412	*********************************************************************************************************************************/
413	#ifdef IN_RING3
414	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
415	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
416	uint32_t uVersion, uint32_t uPass);
417	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
418	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx);
419	#endif /* IN_RING3 */
420
421
422	#define SVGA_CASE_ID2STR(idx) case idx: return #idx
423	#if defined(LOG_ENABLED)
424	/**
425	* Index register string name lookup
426	*
427	* @returns Index register string or "UNKNOWN"
428	* @param pThis The shared VGA/VMSVGA state.
429	* @param idxReg The index register.
430	*/
431	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
432	{
433	switch (idxReg)
434	{
435	SVGA_CASE_ID2STR(SVGA_REG_ID);
436	SVGA_CASE_ID2STR(SVGA_REG_ENABLE);
437	SVGA_CASE_ID2STR(SVGA_REG_WIDTH);
438	SVGA_CASE_ID2STR(SVGA_REG_HEIGHT);
439	SVGA_CASE_ID2STR(SVGA_REG_MAX_WIDTH);
440	SVGA_CASE_ID2STR(SVGA_REG_MAX_HEIGHT);
441	SVGA_CASE_ID2STR(SVGA_REG_DEPTH);
442	SVGA_CASE_ID2STR(SVGA_REG_BITS_PER_PIXEL); /* Current bpp in the guest */
443	SVGA_CASE_ID2STR(SVGA_REG_PSEUDOCOLOR);
444	SVGA_CASE_ID2STR(SVGA_REG_RED_MASK);
445	SVGA_CASE_ID2STR(SVGA_REG_GREEN_MASK);
446	SVGA_CASE_ID2STR(SVGA_REG_BLUE_MASK);
447	SVGA_CASE_ID2STR(SVGA_REG_BYTES_PER_LINE);
448	SVGA_CASE_ID2STR(SVGA_REG_FB_START); /* (Deprecated) */
449	SVGA_CASE_ID2STR(SVGA_REG_FB_OFFSET);
450	SVGA_CASE_ID2STR(SVGA_REG_VRAM_SIZE);
451	SVGA_CASE_ID2STR(SVGA_REG_FB_SIZE);
452
453	/* ID 0 implementation only had the above registers, then the palette */
454	SVGA_CASE_ID2STR(SVGA_REG_CAPABILITIES);
455	SVGA_CASE_ID2STR(SVGA_REG_MEM_START); /* (Deprecated) */
456	SVGA_CASE_ID2STR(SVGA_REG_MEM_SIZE);
457	SVGA_CASE_ID2STR(SVGA_REG_CONFIG_DONE); /* Set when memory area configured */
458	SVGA_CASE_ID2STR(SVGA_REG_SYNC); /* See "FIFO Synchronization Registers" */
459	SVGA_CASE_ID2STR(SVGA_REG_BUSY); /* See "FIFO Synchronization Registers" */
460	SVGA_CASE_ID2STR(SVGA_REG_GUEST_ID); /* Set guest OS identifier */
461	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_ID); /* (Deprecated) */
462	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_X); /* (Deprecated) */
463	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_Y); /* (Deprecated) */
464	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_ON); /* (Deprecated) */
465	SVGA_CASE_ID2STR(SVGA_REG_HOST_BITS_PER_PIXEL); /* (Deprecated) */
466	SVGA_CASE_ID2STR(SVGA_REG_SCRATCH_SIZE); /* Number of scratch registers */
467	SVGA_CASE_ID2STR(SVGA_REG_MEM_REGS); /* Number of FIFO registers */
468	SVGA_CASE_ID2STR(SVGA_REG_NUM_DISPLAYS); /* (Deprecated) */
469	SVGA_CASE_ID2STR(SVGA_REG_PITCHLOCK); /* Fixed pitch for all modes */
470	SVGA_CASE_ID2STR(SVGA_REG_IRQMASK); /* Interrupt mask */
471
472	/* Legacy multi-monitor support */
473	SVGA_CASE_ID2STR(SVGA_REG_NUM_GUEST_DISPLAYS); /* Number of guest displays in X/Y direction */
474	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_ID); /* Display ID for the following display attributes */
475	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_IS_PRIMARY); /* Whether this is a primary display */
476	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_X); /* The display position x */
477	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_Y); /* The display position y */
478	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_WIDTH); /* The display's width */
479	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_HEIGHT); /* The display's height */
480
481	SVGA_CASE_ID2STR(SVGA_REG_GMR_ID);
482	SVGA_CASE_ID2STR(SVGA_REG_GMR_DESCRIPTOR);
483	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_IDS);
484	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
485
486	SVGA_CASE_ID2STR(SVGA_REG_TRACES); /* Enable trace-based updates even when FIFO is on */
487	SVGA_CASE_ID2STR(SVGA_REG_GMRS_MAX_PAGES); /* Maximum number of 4KB pages for all GMRs */
488	SVGA_CASE_ID2STR(SVGA_REG_MEMORY_SIZE); /* Total dedicated device memory excluding FIFO */
489	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_LOW); /* Lower 32 bits and submits commands */
490	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_HIGH); /* Upper 32 bits of command buffer PA */
491	SVGA_CASE_ID2STR(SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); /* Max primary memory */
492	SVGA_CASE_ID2STR(SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); /* Suggested limit on mob mem */
493	SVGA_CASE_ID2STR(SVGA_REG_DEV_CAP); /* Write dev cap index, read value */
494	SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_LOW);
495	SVGA_CASE_ID2STR(SVGA_REG_iCMD_PREPEND_HIGH);
496	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_WIDTH);
497	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_HEIGHT);
498	SVGA_CASE_ID2STR(SVGA_REG_MOB_MAX_SIZE);
499	SVGA_CASE_ID2STR(SVGA_REG_TOP); /* Must be 1 more than the last register */
500
501	default:
502	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
503	return "SVGA_SCRATCH_BASE reg";
504	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
505	return "SVGA_PALETTE_BASE reg";
506	return "UNKNOWN";
507	}
508	}
509	#endif /* LOG_ENABLED */
510
511	#if defined(LOG_ENABLED) \|\| (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D))
512	static const char *vmsvgaDevCapIndexToString(SVGA3dDevCapIndex idxDevCap)
513	{
514	switch (idxDevCap)
515	{
516	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_INVALID);
517	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_3D);
518	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LIGHTS);
519	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURES);
520	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CLIP_PLANES);
521	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER_VERSION);
522	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER);
523	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION);
524	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER);
525	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_RENDER_TARGETS);
526	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S23E8_TEXTURES);
527	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S10E5_TEXTURES);
528	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND);
529	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D16_BUFFER_FORMAT);
530	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT);
531	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT);
532	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_QUERY_TYPES);
533	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING);
534	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_POINT_SIZE);
535	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SHADER_TEXTURES);
536	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
537	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
538	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VOLUME_EXTENT);
539	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT);
540	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO);
541	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY);
542	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT);
543	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_INDEX);
544	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS);
545	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS);
546	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS);
547	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS);
548	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_OPS);
549	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8);
550	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8);
551	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10);
552	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5);
553	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5);
554	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4);
555	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R5G6B5);
556	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16);
557	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8);
558	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ALPHA8);
559	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8);
560	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D16);
561	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8);
562	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8);
563	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT1);
564	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT2);
565	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT3);
566	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT4);
567	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT5);
568	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8);
569	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10);
570	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8);
571	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8);
572	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_CxV8U8);
573	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S10E5);
574	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S23E8);
575	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5);
576	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8);
577	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5);
578	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8);
579	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MISSING62);
580	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES);
581	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS);
582	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_V16U16);
583	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_G16R16);
584	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16);
585	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_UYVY);
586	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YUY2);
587	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES);
588	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES);
589	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_ALPHATOCOVERAGE);
590	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SUPERSAMPLE);
591	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_AUTOGENMIPMAPS);
592	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_NV12);
593	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_AYUV);
594	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CONTEXT_IDS);
595	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SURFACE_IDS);
596	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF16);
597	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF24);
598	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT);
599	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI1);
600	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI2);
601	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD1);
602	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VIDEO_DECODE);
603	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VIDEO_PROCESS);
604	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_AA);
605	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_STIPPLE);
606	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LINE_WIDTH);
607	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH);
608	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YV12);
609	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGICOPS);
610	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TS_COLOR_KEY);
611	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD2);
612	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX);
613	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE);
614	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS);
615	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS);
616	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_PROVOKING_VERTEX);
617	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8R8G8B8);
618	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8R8G8B8);
619	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R5G6B5);
620	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X1R5G5B5);
621	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A1R5G5B5);
622	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A4R4G4B4);
623	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D32);
624	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D16);
625	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8);
626	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D15S1);
627	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8);
628	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4);
629	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE16);
630	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8);
631	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT1);
632	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT2);
633	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT3);
634	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT4);
635	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT5);
636	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPU8V8);
637	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5);
638	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8);
639	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1);
640	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S10E5);
641	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S23E8);
642	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2R10G10B10);
643	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V8U8);
644	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Q8W8V8U8);
645	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_CxV8U8);
646	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8L8V8U8);
647	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2W10V10U10);
648	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ALPHA8);
649	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S10E5);
650	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S23E8);
651	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S10E5);
652	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S23E8);
653	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUFFER);
654	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24X8);
655	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V16U16);
656	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G16R16);
657	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A16B16G16R16);
658	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_UYVY);
659	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YUY2);
660	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_NV12);
661	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_AYUV);
662	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS);
663	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT);
664	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT);
665	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS);
666	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT);
667	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT);
668	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT);
669	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS);
670	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT);
671	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM);
672	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT);
673	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS);
674	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_UINT);
675	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_SINT);
676	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS);
677	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT);
678	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24_TYPELESS);
679	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X32_TYPELESS_G8X24_UINT);
680	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS);
681	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT);
682	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT);
683	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS);
684	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM);
685	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB);
686	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT);
687	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT);
688	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS);
689	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UINT);
690	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SINT);
691	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_TYPELESS);
692	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT);
693	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_UINT);
694	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_SINT);
695	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS);
696	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT);
697	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8_TYPELESS);
698	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X24_TYPELESS_G8_UINT);
699	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS);
700	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UNORM);
701	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UINT);
702	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SINT);
703	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_TYPELESS);
704	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UNORM);
705	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UINT);
706	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SNORM);
707	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SINT);
708	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_TYPELESS);
709	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UNORM);
710	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UINT);
711	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SNORM);
712	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SINT);
713	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_P8);
714	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP);
715	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM);
716	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM);
717	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS);
718	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB);
719	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS);
720	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB);
721	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS);
722	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB);
723	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS);
724	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI1);
725	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_SNORM);
726	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS);
727	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI2);
728	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_SNORM);
729	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM);
730	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS);
731	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB);
732	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS);
733	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB);
734	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF16);
735	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF24);
736	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT);
737	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YV12);
738	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT);
739	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT);
740	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM);
741	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT);
742	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM);
743	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM);
744	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT);
745	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UNORM);
746	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SNORM);
747	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT);
748	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SNORM);
749	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_FLOAT);
750	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D16_UNORM);
751	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8_UNORM);
752	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM);
753	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM);
754	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM);
755	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM);
756	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM);
757	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM);
758	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM);
759	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_UNORM);
760	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_UNORM);
761
762	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX);
763
764	default:
765	break;
766	}
767	return "UNKNOWN";
768	}
769	#endif /* defined(LOG_ENABLED) \|\| (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D)) */
770	#undef SVGA_CASE_ID2STR
771
772
773	#ifdef IN_RING3
774
775	/**
776	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
777	*/
778	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
779	{
780	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
781	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
782
783	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
784	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
785
786	/** @todo Test how it interacts with multiple screen objects. */
787	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
788	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
789	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
790
791	if (x < uWidth)
792	{
793	pThis->svga.viewport.x = x;
794	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
795	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
796	}
797	else
798	{
799	pThis->svga.viewport.x = uWidth;
800	pThis->svga.viewport.cx = 0;
801	pThis->svga.viewport.xRight = uWidth;
802	}
803	if (y < uHeight)
804	{
805	pThis->svga.viewport.y = y;
806	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
807	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
808	pThis->svga.viewport.yHighWC = uHeight - y;
809	}
810	else
811	{
812	pThis->svga.viewport.y = uHeight;
813	pThis->svga.viewport.cy = 0;
814	pThis->svga.viewport.yLowWC = 0;
815	pThis->svga.viewport.yHighWC = 0;
816	}
817
818	# ifdef VBOX_WITH_VMSVGA3D
819	/*
820	* Now inform the 3D backend.
821	*/
822	if (pThis->svga.f3DEnabled)
823	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
824	# else
825	RT_NOREF(OldViewport);
826	# endif
827	}
828
829
830	/**
831	* Updating screen information in API
832	*
833	* @param pThis The The shared VGA/VMSVGA instance data.
834	* @param pThisCC The VGA/VMSVGA state for ring-3.
835	*/
836	void vmsvgaR3VBVAResize(PVGASTATE pThis, PVGASTATECC pThisCC)
837	{
838	int rc;
839
840	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
841
842	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
843	{
844	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
845	if (!pScreen->fModified)
846	continue;
847
848	pScreen->fModified = false;
849
850	VBVAINFOVIEW view;
851	RT_ZERO(view);
852	view.u32ViewIndex = pScreen->idScreen;
853	// view.u32ViewOffset = 0;
854	view.u32ViewSize = pThis->vram_size;
855	view.u32MaxScreenSize = pThis->vram_size;
856
857	VBVAINFOSCREEN screen;
858	RT_ZERO(screen);
859	screen.u32ViewIndex = pScreen->idScreen;
860
861	if (pScreen->fDefined)
862	{
863	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
864	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
865	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
866	{
867	Assert(pThis->svga.fGFBRegisters);
868	continue;
869	}
870
871	screen.i32OriginX = pScreen->xOrigin;
872	screen.i32OriginY = pScreen->yOrigin;
873	screen.u32StartOffset = pScreen->offVRAM;
874	screen.u32LineSize = pScreen->cbPitch;
875	screen.u32Width = pScreen->cWidth;
876	screen.u32Height = pScreen->cHeight;
877	screen.u16BitsPerPixel = pScreen->cBpp;
878	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
879	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
880	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
881	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
882	}
883	else
884	{
885	/* Screen is destroyed. */
886	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
887	}
888
889	void *pvVRAM = pScreen->pvScreenBitmap ? pScreen->pvScreenBitmap : pThisCC->pbVRam;
890	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pvVRAM, /fResetInputMapping=/ true);
891	AssertRC(rc);
892	}
893	}
894
895
896	/**
897	* @interface_method_impl{PDMIDISPLAYPORT,pfnReportMonitorPositions}
898	*
899	* Used to update screen offsets (positions) since appearently vmwgfx fails to
900	* pass correct offsets thru FIFO.
901	*/
902	DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PCRTPOINT paPositions)
903	{
904	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
905	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
906	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
907
908	AssertReturnVoid(pSVGAState);
909
910	/* We assume cPositions is the # of outputs Xserver reports and paPositions is (-1, -1) for disabled monitors. */
911	cPositions = RT_MIN(cPositions, RT_ELEMENTS(pSVGAState->aScreens));
912	for (uint32_t i = 0; i < cPositions; ++i)
913	{
914	if ( pSVGAState->aScreens[i].xOrigin == paPositions[i].x
915	&& pSVGAState->aScreens[i].yOrigin == paPositions[i].y)
916	continue;
917
918	if (pSVGAState->aScreens[i].xOrigin == -1)
919	continue;
920	if (pSVGAState->aScreens[i].yOrigin == -1)
921	continue;
922
923	pSVGAState->aScreens[i].xOrigin = paPositions[i].x;
924	pSVGAState->aScreens[i].yOrigin = paPositions[i].y;
925	pSVGAState->aScreens[i].fModified = true;
926	}
927
928	vmsvgaR3VBVAResize(pThis, pThisCC);
929	}
930
931	#endif /* IN_RING3 */
932
933	/**
934	* Read port register
935	*
936	* @returns VBox status code.
937	* @param pDevIns The device instance.
938	* @param pThis The shared VGA/VMSVGA state.
939	* @param pu32 Where to store the read value
940	*/
941	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
942	{
943	#ifdef IN_RING3
944	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
945	#endif
946	int rc = VINF_SUCCESS;
947	*pu32 = 0;
948
949	/* Rough index register validation. */
950	uint32_t idxReg = pThis->svga.u32IndexReg;
951	#if !defined(IN_RING3) && defined(VBOX_STRICT)
952	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
953	VINF_IOM_R3_IOPORT_READ);
954	#else
955	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
956	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
957	VINF_SUCCESS);
958	#endif
959	RT_UNTRUSTED_VALIDATED_FENCE();
960
961	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
962	if ( idxReg >= SVGA_REG_ID_0_TOP
963	&& pThis->svga.u32SVGAId == SVGA_ID_0)
964	{
965	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
966	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
967	}
968
969	switch (idxReg)
970	{
971	case SVGA_REG_ID:
972	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
973	*pu32 = pThis->svga.u32SVGAId;
974	break;
975
976	case SVGA_REG_ENABLE:
977	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
978	*pu32 = pThis->svga.fEnabled;
979	break;
980
981	case SVGA_REG_WIDTH:
982	{
983	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
984	if ( pThis->svga.fEnabled
985	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
986	*pu32 = pThis->svga.uWidth;
987	else
988	{
989	#ifndef IN_RING3
990	rc = VINF_IOM_R3_IOPORT_READ;
991	#else
992	*pu32 = pThisCC->pDrv->cx;
993	#endif
994	}
995	break;
996	}
997
998	case SVGA_REG_HEIGHT:
999	{
1000	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
1001	if ( pThis->svga.fEnabled
1002	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1003	*pu32 = pThis->svga.uHeight;
1004	else
1005	{
1006	#ifndef IN_RING3
1007	rc = VINF_IOM_R3_IOPORT_READ;
1008	#else
1009	*pu32 = pThisCC->pDrv->cy;
1010	#endif
1011	}
1012	break;
1013	}
1014
1015	case SVGA_REG_MAX_WIDTH:
1016	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
1017	*pu32 = pThis->svga.u32MaxWidth;
1018	break;
1019
1020	case SVGA_REG_MAX_HEIGHT:
1021	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
1022	*pu32 = pThis->svga.u32MaxHeight;
1023	break;
1024
1025	case SVGA_REG_DEPTH:
1026	/* This returns the color depth of the current mode. */
1027	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
1028	switch (pThis->svga.uBpp)
1029	{
1030	case 15:
1031	case 16:
1032	case 24:
1033	*pu32 = pThis->svga.uBpp;
1034	break;
1035
1036	default:
1037	case 32:
1038	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
1039	break;
1040	}
1041	break;
1042
1043	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
1044	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
1045	*pu32 = pThis->svga.uHostBpp;
1046	break;
1047
1048	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1049	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
1050	*pu32 = pThis->svga.uBpp;
1051	break;
1052
1053	case SVGA_REG_PSEUDOCOLOR:
1054	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
1055	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
1056	break;
1057
1058	case SVGA_REG_RED_MASK:
1059	case SVGA_REG_GREEN_MASK:
1060	case SVGA_REG_BLUE_MASK:
1061	{
1062	uint32_t uBpp;
1063
1064	if (pThis->svga.fEnabled)
1065	uBpp = pThis->svga.uBpp;
1066	else
1067	uBpp = pThis->svga.uHostBpp;
1068
1069	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
1070	switch (uBpp)
1071	{
1072	case 8:
1073	u32RedMask = 0x07;
1074	u32GreenMask = 0x38;
1075	u32BlueMask = 0xc0;
1076	break;
1077
1078	case 15:
1079	u32RedMask = 0x0000001f;
1080	u32GreenMask = 0x000003e0;
1081	u32BlueMask = 0x00007c00;
1082	break;
1083
1084	case 16:
1085	u32RedMask = 0x0000001f;
1086	u32GreenMask = 0x000007e0;
1087	u32BlueMask = 0x0000f800;
1088	break;
1089
1090	case 24:
1091	case 32:
1092	default:
1093	u32RedMask = 0x00ff0000;
1094	u32GreenMask = 0x0000ff00;
1095	u32BlueMask = 0x000000ff;
1096	break;
1097	}
1098	switch (idxReg)
1099	{
1100	case SVGA_REG_RED_MASK:
1101	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
1102	*pu32 = u32RedMask;
1103	break;
1104
1105	case SVGA_REG_GREEN_MASK:
1106	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
1107	*pu32 = u32GreenMask;
1108	break;
1109
1110	case SVGA_REG_BLUE_MASK:
1111	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
1112	*pu32 = u32BlueMask;
1113	break;
1114	}
1115	break;
1116	}
1117
1118	case SVGA_REG_BYTES_PER_LINE:
1119	{
1120	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
1121	if ( pThis->svga.fEnabled
1122	&& pThis->svga.cbScanline)
1123	*pu32 = pThis->svga.cbScanline;
1124	else
1125	{
1126	#ifndef IN_RING3
1127	rc = VINF_IOM_R3_IOPORT_READ;
1128	#else
1129	*pu32 = pThisCC->pDrv->cbScanline;
1130	#endif
1131	}
1132	break;
1133	}
1134
1135	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1136	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1137	*pu32 = pThis->vram_size;
1138	break;
1139
1140	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1141	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1142	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1143	*pu32 = pThis->GCPhysVRAM;
1144	break;
1145
1146	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1147	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1148	/* Always zero in our case. */
1149	*pu32 = 0;
1150	break;
1151
1152	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1153	{
1154	#ifndef IN_RING3
1155	rc = VINF_IOM_R3_IOPORT_READ;
1156	#else
1157	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1158
1159	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1160	if ( pThis->svga.fEnabled
1161	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1162	{
1163	/* Hardware enabled; return real framebuffer size .*/
1164	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1165	}
1166	else
1167	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1168
1169	pu32 = RT_MIN(pThis->vram_size, pu32);
1170	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1171	#endif
1172	break;
1173	}
1174
1175	case SVGA_REG_CAPABILITIES:
1176	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1177	*pu32 = pThis->svga.u32DeviceCaps;
1178	break;
1179
1180	case SVGA_REG_MEM_START: /* FIFO start */
1181	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1182	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1183	*pu32 = pThis->svga.GCPhysFIFO;
1184	break;
1185
1186	case SVGA_REG_MEM_SIZE: /* FIFO size */
1187	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1188	*pu32 = pThis->svga.cbFIFO;
1189	break;
1190
1191	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1192	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1193	*pu32 = pThis->svga.fConfigured;
1194	break;
1195
1196	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1197	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1198	*pu32 = 0;
1199	break;
1200
1201	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1202	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1203	if (pThis->svga.fBusy)
1204	{
1205	#ifndef IN_RING3
1206	/* Go to ring-3 and halt the CPU. */
1207	rc = VINF_IOM_R3_IOPORT_READ;
1208	RT_NOREF(pDevIns);
1209	break;
1210	#else
1211	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1212	/* The guest is basically doing a HLT via the device here, but with
1213	a special wake up condition on FIFO completion. */
1214	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1215	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1216	PVM pVM = PDMDevHlpGetVM(pDevIns);
1217	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1218	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1219	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1220	if (pThis->svga.fBusy)
1221	{
1222	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1223	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1224	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1225	}
1226	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1227	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1228	# else
1229
1230	/* Delay the EMT a bit so the FIFO and others can get some work done.
1231	This used to be a crude 50 ms sleep. The current code tries to be
1232	more efficient, but the consept is still very crude. */
1233	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1234	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1235	RTThreadYield();
1236	if (pThis->svga.fBusy)
1237	{
1238	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1239
1240	if (pThis->svga.fBusy && cRefs == 1)
1241	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1242	if (pThis->svga.fBusy)
1243	{
1244	/** @todo If this code is going to stay, we need to call into the halt/wait
1245	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1246	* suffer when the guest is polling on a busy FIFO. */
1247	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns));
1248	if (cNsMaxWait >= RT_NS_100US)
1249	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1250	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1251	RT_MIN(cNsMaxWait, RT_NS_10MS));
1252	}
1253
1254	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1255	}
1256	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1257	# endif
1258	*pu32 = pThis->svga.fBusy != 0;
1259	#endif
1260	}
1261	else
1262	*pu32 = false;
1263	break;
1264
1265	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1266	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1267	*pu32 = pThis->svga.u32GuestId;
1268	break;
1269
1270	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1271	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1272	*pu32 = pThis->svga.cScratchRegion;
1273	break;
1274
1275	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1276	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1277	*pu32 = SVGA_FIFO_NUM_REGS;
1278	break;
1279
1280	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1281	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1282	*pu32 = pThis->svga.u32PitchLock;
1283	break;
1284
1285	case SVGA_REG_IRQMASK: /* Interrupt mask */
1286	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1287	*pu32 = pThis->svga.u32IrqMask;
1288	break;
1289
1290	/* See "Guest memory regions" below. */
1291	case SVGA_REG_GMR_ID:
1292	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1293	*pu32 = pThis->svga.u32CurrentGMRId;
1294	break;
1295
1296	case SVGA_REG_GMR_DESCRIPTOR:
1297	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1298	/* Write only */
1299	*pu32 = 0;
1300	break;
1301
1302	case SVGA_REG_GMR_MAX_IDS:
1303	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1304	*pu32 = pThis->svga.cGMR;
1305	break;
1306
1307	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1308	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1309	*pu32 = VMSVGA_MAX_GMR_PAGES;
1310	break;
1311
1312	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1313	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1314	*pu32 = pThis->svga.fTraces;
1315	break;
1316
1317	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1318	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1319	*pu32 = VMSVGA_MAX_GMR_PAGES;
1320	break;
1321
1322	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1323	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1324	*pu32 = VMSVGA_SURFACE_SIZE;
1325	break;
1326
1327	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1328	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1329	break;
1330
1331	/* Mouse cursor support. */
1332	case SVGA_REG_CURSOR_ID:
1333	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdRd);
1334	*pu32 = pThis->svga.uCursorID;
1335	break;
1336
1337	case SVGA_REG_CURSOR_X:
1338	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXRd);
1339	*pu32 = pThis->svga.uCursorX;
1340	break;
1341
1342	case SVGA_REG_CURSOR_Y:
1343	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYRd);
1344	*pu32 = pThis->svga.uCursorY;
1345	break;
1346
1347	case SVGA_REG_CURSOR_ON:
1348	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnRd);
1349	*pu32 = pThis->svga.uCursorOn;
1350	break;
1351
1352	/* Legacy multi-monitor support */
1353	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1354	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1355	*pu32 = 1;
1356	break;
1357
1358	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1359	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1360	*pu32 = 0;
1361	break;
1362
1363	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1364	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1365	*pu32 = 0;
1366	break;
1367
1368	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1369	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1370	*pu32 = 0;
1371	break;
1372
1373	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1374	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1375	*pu32 = 0;
1376	break;
1377
1378	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1379	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1380	*pu32 = pThis->svga.uWidth;
1381	break;
1382
1383	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1384	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1385	*pu32 = pThis->svga.uHeight;
1386	break;
1387
1388	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1389	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1390	/* We must return something sensible here otherwise the Linux driver
1391	will take a legacy code path without 3d support. This number also
1392	limits how many screens Linux guests will allow. */
1393	*pu32 = pThis->cMonitors;
1394	break;
1395
1396	/*
1397	* SVGA_CAP_GBOBJECTS+ registers.
1398	*/
1399	case SVGA_REG_COMMAND_LOW:
1400	/* Lower 32 bits of command buffer physical address. */
1401	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowRd);
1402	*pu32 = pThis->svga.u32RegCommandLow;
1403	break;
1404
1405	case SVGA_REG_COMMAND_HIGH:
1406	/* Upper 32 bits of command buffer PA. */
1407	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighRd);
1408	*pu32 = pThis->svga.u32RegCommandHigh;
1409	break;
1410
1411	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
1412	/* Max primary (screen) memory. */
1413	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxPrimBBMemRd);
1414	pu32 = pThis->vram_size; /* @todo Maybe half VRAM? */
1415	break;
1416
1417	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
1418	/* Suggested limit on mob mem (i.e. size of the guest mapped VRAM in KB) */
1419	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGBMemSizeRd);
1420	*pu32 = pThis->vram_size / 1024;
1421	break;
1422
1423	case SVGA_REG_DEV_CAP:
1424	/* Write dev cap index, read value */
1425	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapRd);
1426	if (pThis->svga.u32DevCapIndex < RT_ELEMENTS(pThis->svga.au32DevCaps))
1427	{
1428	RT_UNTRUSTED_VALIDATED_FENCE();
1429	*pu32 = pThis->svga.au32DevCaps[pThis->svga.u32DevCapIndex];
1430	}
1431	else
1432	*pu32 = 0;
1433	break;
1434
1435	case SVGA_REG_CMD_PREPEND_LOW:
1436	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowRd);
1437	pu32 = 0; / Not supported. */
1438	break;
1439
1440	case SVGA_REG_iCMD_PREPEND_HIGH:
1441	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighRd);
1442	pu32 = 0; / Not supported. */
1443	break;
1444
1445	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
1446	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxWidthRd);
1447	*pu32 = pThis->svga.u32MaxWidth;
1448	break;
1449
1450	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
1451	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxHeightRd);
1452	*pu32 = pThis->svga.u32MaxHeight;
1453	break;
1454
1455	case SVGA_REG_MOB_MAX_SIZE:
1456	/* Essentially the max texture size */
1457	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMobMaxSizeRd);
1458	pu32 = _128M; /* @todo Some actual value. Probably the mapped VRAM size. */
1459	break;
1460
1461	default:
1462	{
1463	uint32_t offReg;
1464	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1465	{
1466	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1467	RT_UNTRUSTED_VALIDATED_FENCE();
1468	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1469	}
1470	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1471	{
1472	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1473	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1474	RT_UNTRUSTED_VALIDATED_FENCE();
1475	uint32_t u32 = pThis->last_palette[offReg / 3];
1476	switch (offReg % 3)
1477	{
1478	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1479	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1480	case 2: pu32 = u32 & 0xff; break; / blue */
1481	}
1482	}
1483	else
1484	{
1485	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1486	rc = VINF_IOM_R3_IOPORT_READ;
1487	#else
1488	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1489
1490	/* Do not assert. The guest might be reading all registers. */
1491	LogFunc(("Unknown reg=%#x\n", idxReg));
1492	#endif
1493	}
1494	break;
1495	}
1496	}
1497	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1498	return rc;
1499	}
1500
1501	#ifdef IN_RING3
1502	/**
1503	* Apply the current resolution settings to change the video mode.
1504	*
1505	* @returns VBox status code.
1506	* @param pThis The shared VGA state.
1507	* @param pThisCC The ring-3 VGA state.
1508	*/
1509	int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1510	{
1511	/* Always do changemode on FIFO thread. */
1512	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1513
1514	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1515
1516	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1517
1518	if (pThis->svga.fGFBRegisters)
1519	{
1520	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1521	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1522	* deletes all screens other than screen #0, and redefines screen
1523	* #0 according to the specified mode. Drivers that use
1524	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1525	*/
1526
1527	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1528	pScreen->fDefined = true;
1529	pScreen->fModified = true;
1530	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1531	pScreen->idScreen = 0;
1532	pScreen->xOrigin = 0;
1533	pScreen->yOrigin = 0;
1534	pScreen->offVRAM = 0;
1535	pScreen->cbPitch = pThis->svga.cbScanline;
1536	pScreen->cWidth = pThis->svga.uWidth;
1537	pScreen->cHeight = pThis->svga.uHeight;
1538	pScreen->cBpp = pThis->svga.uBpp;
1539
1540	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1541	{
1542	/* Delete screen. */
1543	pScreen = &pSVGAState->aScreens[iScreen];
1544	if (pScreen->fDefined)
1545	{
1546	pScreen->fModified = true;
1547	pScreen->fDefined = false;
1548	}
1549	}
1550	}
1551	else
1552	{
1553	/* "If Screen Objects are supported, they can be used to fully
1554	* replace the functionality provided by the framebuffer registers
1555	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1556	*/
1557	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1558	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1559	pThis->svga.uBpp = pThis->svga.uHostBpp;
1560	}
1561
1562	vmsvgaR3VBVAResize(pThis, pThisCC);
1563
1564	/* Last stuff. For the VGA device screenshot. */
1565	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1566	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1567	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1568	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1569	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1570
1571	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1572	if ( pThis->svga.viewport.cx == 0
1573	&& pThis->svga.viewport.cy == 0)
1574	{
1575	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1576	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1577	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1578	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1579	pThis->svga.viewport.yLowWC = 0;
1580	}
1581
1582	return VINF_SUCCESS;
1583	}
1584
1585	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1586	{
1587	VBVACMDHDR cmd;
1588	cmd.x = (int16_t)(pScreen->xOrigin + x);
1589	cmd.y = (int16_t)(pScreen->yOrigin + y);
1590	cmd.w = (uint16_t)w;
1591	cmd.h = (uint16_t)h;
1592
1593	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1594	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1595	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1596	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1597
1598	return VINF_SUCCESS;
1599	}
1600
1601	#endif /* IN_RING3 */
1602	#if defined(IN_RING0) \|\| defined(IN_RING3)
1603
1604	/**
1605	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1606	*
1607	* @param pThis The shared VGA/VMSVGA instance data.
1608	* @param pThisCC The VGA/VMSVGA state for the current context.
1609	* @param fState The busy state.
1610	*/
1611	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1612	{
1613	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1614
1615	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1616	{
1617	/* Race / unfortunately scheduling. Highly unlikly. */
1618	uint32_t cLoops = 64;
1619	do
1620	{
1621	ASMNopPause();
1622	fState = (pThis->svga.fBusy != 0);
1623	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1624	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1625	}
1626	}
1627
1628
1629	/**
1630	* Update the scanline pitch in response to the guest changing mode
1631	* width/bpp.
1632	*
1633	* @param pThis The shared VGA/VMSVGA state.
1634	* @param pThisCC The VGA/VMSVGA state for the current context.
1635	*/
1636	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1637	{
1638	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1639	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1640	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1641	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1642
1643	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1644	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1645	* location but it has a different meaning.
1646	*/
1647	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1648	uFifoPitchLock = 0;
1649
1650	/* Sanitize values. */
1651	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1652	uFifoPitchLock = 0;
1653	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1654	uRegPitchLock = 0;
1655
1656	/* Prefer the register value to the FIFO value.*/
1657	if (uRegPitchLock)
1658	pThis->svga.cbScanline = uRegPitchLock;
1659	else if (uFifoPitchLock)
1660	pThis->svga.cbScanline = uFifoPitchLock;
1661	else
1662	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1663
1664	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1665	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1666	}
1667
1668	#endif /* IN_RING0 \|\| IN_RING3 */
1669
1670	#ifdef IN_RING3
1671
1672	/**
1673	* Sends cursor position and visibility information from legacy
1674	* SVGA registers to the front-end.
1675	*/
1676	static void vmsvgaR3RegUpdateCursor(PVGASTATECC pThisCC, PVGASTATE pThis, uint32_t uCursorOn)
1677	{
1678	/*
1679	* Writing the X/Y/ID registers does not trigger changes; only writing the
1680	* SVGA_REG_CURSOR_ON register does. That minimizes the overhead.
1681	* We boldly assume that guests aren't stupid and aren't writing the CURSOR_ON
1682	* register if they don't have to.
1683	*/
1684	uint32_t x, y, idScreen;
1685	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
1686
1687	x = pThis->svga.uCursorX;
1688	y = pThis->svga.uCursorY;
1689	idScreen = SVGA_ID_INVALID; /* The old register interface is single screen only. */
1690
1691	/* The original values for SVGA_REG_CURSOR_ON were off (0) and on (1); later, the values
1692	* were extended as follows:
1693	*
1694	* SVGA_CURSOR_ON_HIDE 0
1695	* SVGA_CURSOR_ON_SHOW 1
1696	* SVGA_CURSOR_ON_REMOVE_FROM_FB 2 - cursor on but not in the framebuffer
1697	* SVGA_CURSOR_ON_RESTORE_TO_FB 3 - cursor on, possibly in the framebuffer
1698	*
1699	* Since we never draw the cursor into the guest's framebuffer, we do not need to
1700	* distinguish between the non-zero values but still remember them.
1701	*/
1702	if (RT_BOOL(pThis->svga.uCursorOn) != RT_BOOL(uCursorOn))
1703	{
1704	LogRel2(("vmsvgaR3RegUpdateCursor: uCursorOn %d prev CursorOn %d (%d,%d)\n", uCursorOn, pThis->svga.uCursorOn, x, y));
1705	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(uCursorOn), false, 0, 0, 0, 0, NULL);
1706	}
1707	pThis->svga.uCursorOn = uCursorOn;
1708	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
1709	}
1710
1711	#endif /* IN_RING3 */
1712
1713
1714	/**
1715	* Write port register
1716	*
1717	* @returns Strict VBox status code.
1718	* @param pDevIns The device instance.
1719	* @param pThis The shared VGA/VMSVGA state.
1720	* @param pThisCC The VGA/VMSVGA state for the current context.
1721	* @param u32 Value to write
1722	*/
1723	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1724	{
1725	#ifdef IN_RING3
1726	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1727	#endif
1728	VBOXSTRICTRC rc = VINF_SUCCESS;
1729	RT_NOREF(pThisCC);
1730
1731	/* Rough index register validation. */
1732	uint32_t idxReg = pThis->svga.u32IndexReg;
1733	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1734	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1735	VINF_IOM_R3_IOPORT_WRITE);
1736	#else
1737	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1738	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1739	VINF_SUCCESS);
1740	#endif
1741	RT_UNTRUSTED_VALIDATED_FENCE();
1742
1743	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1744	if ( idxReg >= SVGA_REG_ID_0_TOP
1745	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1746	{
1747	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1748	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1749	}
1750	#ifdef LOG_ENABLED
1751	if (idxReg != SVGA_REG_DEV_CAP)
1752	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1753	else
1754	Log(("vmsvgaWritePort index=%s (%d) val=%s (%d)\n", vmsvgaIndexToString(pThis, idxReg), idxReg, vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)u32), u32));
1755	#endif
1756	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1757	switch (idxReg)
1758	{
1759	case SVGA_REG_WIDTH:
1760	case SVGA_REG_HEIGHT:
1761	case SVGA_REG_PITCHLOCK:
1762	case SVGA_REG_BITS_PER_PIXEL:
1763	pThis->svga.fGFBRegisters = true;
1764	break;
1765	default:
1766	break;
1767	}
1768
1769	switch (idxReg)
1770	{
1771	case SVGA_REG_ID:
1772	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1773	if ( u32 == SVGA_ID_0
1774	\|\| u32 == SVGA_ID_1
1775	\|\| u32 == SVGA_ID_2)
1776	pThis->svga.u32SVGAId = u32;
1777	else
1778	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1779	break;
1780
1781	case SVGA_REG_ENABLE:
1782	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1783	#ifdef IN_RING3
1784	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1785	&& pThis->svga.fEnabled == false)
1786	{
1787	/* Make a backup copy of the first 512kb in order to save font data etc. */
1788	/** @todo should probably swap here, rather than copy + zero */
1789	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1790	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1791	}
1792
1793	pThis->svga.fEnabled = u32;
1794	if (pThis->svga.fEnabled)
1795	{
1796	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1797	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED)
1798	{
1799	/* Keep the current mode. */
1800	pThis->svga.uWidth = pThisCC->pDrv->cx;
1801	pThis->svga.uHeight = pThisCC->pDrv->cy;
1802	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1803	}
1804
1805	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1806	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1807	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1808	# ifdef LOG_ENABLED
1809	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1810	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1811	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1812	# endif
1813
1814	/* Disable or enable dirty page tracking according to the current fTraces value. */
1815	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1816
1817	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1818	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1819	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
1820
1821	/* Make the cursor visible again as needed. */
1822	if (pSVGAState->Cursor.fActive)
1823	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, false, 0, 0, 0, 0, NULL);
1824	}
1825	else
1826	{
1827	/* Make sure the cursor is off. */
1828	if (pSVGAState->Cursor.fActive)
1829	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, false /fVisible/, false, 0, 0, 0, 0, NULL);
1830
1831	/* Restore the text mode backup. */
1832	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1833
1834	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1835
1836	/* Enable dirty page tracking again when going into legacy mode. */
1837	vmsvgaR3SetTraces(pDevIns, pThis, true);
1838
1839	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1840	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1841	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1842
1843	/* Clear the pitch lock. */
1844	pThis->svga.u32PitchLock = 0;
1845	}
1846	#else /* !IN_RING3 */
1847	rc = VINF_IOM_R3_IOPORT_WRITE;
1848	#endif /* !IN_RING3 */
1849	break;
1850
1851	case SVGA_REG_WIDTH:
1852	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1853	if (pThis->svga.uWidth != u32)
1854	{
1855	#if defined(IN_RING3) \|\| defined(IN_RING0)
1856	pThis->svga.uWidth = u32;
1857	vmsvgaHCUpdatePitch(pThis, pThisCC);
1858	if (pThis->svga.fEnabled)
1859	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1860	#else
1861	rc = VINF_IOM_R3_IOPORT_WRITE;
1862	#endif
1863	}
1864	/* else: nop */
1865	break;
1866
1867	case SVGA_REG_HEIGHT:
1868	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1869	if (pThis->svga.uHeight != u32)
1870	{
1871	pThis->svga.uHeight = u32;
1872	if (pThis->svga.fEnabled)
1873	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1874	}
1875	/* else: nop */
1876	break;
1877
1878	case SVGA_REG_DEPTH:
1879	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1880	/** @todo read-only?? */
1881	break;
1882
1883	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1884	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1885	if (pThis->svga.uBpp != u32)
1886	{
1887	#if defined(IN_RING3) \|\| defined(IN_RING0)
1888	pThis->svga.uBpp = u32;
1889	vmsvgaHCUpdatePitch(pThis, pThisCC);
1890	if (pThis->svga.fEnabled)
1891	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1892	#else
1893	rc = VINF_IOM_R3_IOPORT_WRITE;
1894	#endif
1895	}
1896	/* else: nop */
1897	break;
1898
1899	case SVGA_REG_PSEUDOCOLOR:
1900	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1901	break;
1902
1903	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1904	#ifdef IN_RING3
1905	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1906	pThis->svga.fConfigured = u32;
1907	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1908	if (!pThis->svga.fConfigured)
1909	pThis->svga.fTraces = true;
1910	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1911	#else
1912	rc = VINF_IOM_R3_IOPORT_WRITE;
1913	#endif
1914	break;
1915
1916	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1917	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1918	if ( pThis->svga.fEnabled
1919	&& pThis->svga.fConfigured)
1920	{
1921	#if defined(IN_RING3) \|\| defined(IN_RING0)
1922	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
1923	/*
1924	* The VMSVGA_BUSY_F_EMT_FORCE flag makes sure we will check if the FIFO is empty
1925	* at least once; VMSVGA_BUSY_F_FIFO alone does not ensure that.
1926	*/
1927	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1928	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
1929	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
1930
1931	/* Kick the FIFO thread to start processing commands again. */
1932	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
1933	#else
1934	rc = VINF_IOM_R3_IOPORT_WRITE;
1935	#endif
1936	}
1937	/* else nothing to do. */
1938	else
1939	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1940
1941	break;
1942
1943	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1944	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1945	break;
1946
1947	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1948	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1949	pThis->svga.u32GuestId = u32;
1950	break;
1951
1952	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1953	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1954	pThis->svga.u32PitchLock = u32;
1955	/* Should this also update the FIFO pitch lock? Unclear. */
1956	break;
1957
1958	case SVGA_REG_IRQMASK: /* Interrupt mask */
1959	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1960	pThis->svga.u32IrqMask = u32;
1961
1962	/* Irq pending after the above change? */
1963	if (pThis->svga.u32IrqStatus & u32)
1964	{
1965	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1966	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
1967	}
1968	else
1969	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1970	break;
1971
1972	/* Mouse cursor support */
1973	case SVGA_REG_CURSOR_ID:
1974	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdWr);
1975	pThis->svga.uCursorID = u32;
1976	break;
1977
1978	case SVGA_REG_CURSOR_X:
1979	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXWr);
1980	pThis->svga.uCursorX = u32;
1981	break;
1982
1983	case SVGA_REG_CURSOR_Y:
1984	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYWr);
1985	pThis->svga.uCursorY = u32;
1986	break;
1987
1988	case SVGA_REG_CURSOR_ON:
1989	#ifdef IN_RING3
1990	/* The cursor is only updated when SVGA_REG_CURSOR_ON is written. */
1991	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnWr);
1992	vmsvgaR3RegUpdateCursor(pThisCC, pThis, u32);
1993	#else
1994	rc = VINF_IOM_R3_IOPORT_WRITE;
1995	#endif
1996	break;
1997
1998	/* Legacy multi-monitor support */
1999	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
2000	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
2001	break;
2002	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
2003	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
2004	break;
2005	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
2006	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
2007	break;
2008	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
2009	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
2010	break;
2011	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
2012	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
2013	break;
2014	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
2015	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
2016	break;
2017	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
2018	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
2019	break;
2020	#ifdef VBOX_WITH_VMSVGA3D
2021	/* See "Guest memory regions" below. */
2022	case SVGA_REG_GMR_ID:
2023	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
2024	pThis->svga.u32CurrentGMRId = u32;
2025	break;
2026
2027	case SVGA_REG_GMR_DESCRIPTOR:
2028	# ifndef IN_RING3
2029	rc = VINF_IOM_R3_IOPORT_WRITE;
2030	break;
2031	# else /* IN_RING3 */
2032	{
2033	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
2034
2035	/* Validate current GMR id. */
2036	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
2037	AssertBreak(idGMR < pThis->svga.cGMR);
2038	RT_UNTRUSTED_VALIDATED_FENCE();
2039
2040	/* Free the old GMR if present. */
2041	vmsvgaR3GmrFree(pThisCC, idGMR);
2042
2043	/* Just undefine the GMR? */
2044	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
2045	if (GCPhys == 0)
2046	{
2047	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
2048	break;
2049	}
2050
2051
2052	/* Never cross a page boundary automatically. */
2053	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
2054	uint32_t cPagesTotal = 0;
2055	uint32_t iDesc = 0;
2056	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
2057	uint32_t cLoops = 0;
2058	RTGCPHYS GCPhysBase = GCPhys;
2059	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
2060	{
2061	/* Read descriptor. */
2062	SVGAGuestMemDescriptor desc;
2063	rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
2064	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
2065
2066	if (desc.numPages != 0)
2067	{
2068	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2069	cPagesTotal += desc.numPages;
2070	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2071
2072	if ((iDesc & 15) == 0)
2073	{
2074	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
2075	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
2076	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
2077	}
2078
2079	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2080	paDescs[iDesc++].numPages = desc.numPages;
2081
2082	/* Continue with the next descriptor. */
2083	GCPhys += sizeof(desc);
2084	}
2085	else if (desc.ppn == 0)
2086	break; /* terminator */
2087	else /* Pointer to the next physical page of descriptors. */
2088	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2089
2090	cLoops++;
2091	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
2092	}
2093
2094	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
2095	if (RT_SUCCESS(rc))
2096	{
2097	/* Commit the GMR. */
2098	pSVGAState->paGMR[idGMR].paDesc = paDescs;
2099	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
2100	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
2101	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
2102	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
2103	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
2104	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
2105	}
2106	else
2107	{
2108	RTMemFree(paDescs);
2109	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
2110	}
2111	break;
2112	}
2113	# endif /* IN_RING3 */
2114	#endif // VBOX_WITH_VMSVGA3D
2115
2116	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
2117	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
2118	if (pThis->svga.fTraces == u32)
2119	break; /* nothing to do */
2120
2121	#ifdef IN_RING3
2122	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
2123	#else
2124	rc = VINF_IOM_R3_IOPORT_WRITE;
2125	#endif
2126	break;
2127
2128	case SVGA_REG_TOP: /* Must be 1 more than the last register */
2129	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
2130	break;
2131
2132	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
2133	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
2134	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
2135	break;
2136
2137	/*
2138	* SVGA_CAP_GBOBJECTS+ registers.
2139	*/
2140	case SVGA_REG_COMMAND_LOW:
2141	{
2142	/* Lower 32 bits of command buffer physical address and submit the command buffer. */
2143	#ifdef IN_RING3
2144	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowWr);
2145	pThis->svga.u32RegCommandLow = u32;
2146
2147	/* "lower 6 bits are used for the SVGACBContext" */
2148	RTGCPHYS GCPhysCB = pThis->svga.u32RegCommandHigh;
2149	GCPhysCB <<= 32;
2150	GCPhysCB \|= pThis->svga.u32RegCommandLow & ~SVGA_CB_CONTEXT_MASK;
2151	SVGACBContext const CBCtx = (SVGACBContext)(pThis->svga.u32RegCommandLow & SVGA_CB_CONTEXT_MASK);
2152	vmsvgaR3CmdBufSubmit(pDevIns, pThis, pThisCC, GCPhysCB, CBCtx);
2153	#else
2154	rc = VINF_IOM_R3_IOPORT_WRITE;
2155	#endif
2156	break;
2157	}
2158
2159	case SVGA_REG_COMMAND_HIGH:
2160	/* Upper 32 bits of command buffer PA. */
2161	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighWr);
2162	pThis->svga.u32RegCommandHigh = u32;
2163	break;
2164
2165	case SVGA_REG_DEV_CAP:
2166	/* Write dev cap index, read value */
2167	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapWr);
2168	pThis->svga.u32DevCapIndex = u32;
2169	break;
2170
2171	case SVGA_REG_CMD_PREPEND_LOW:
2172	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowWr);
2173	/* Not supported. */
2174	break;
2175
2176	case SVGA_REG_iCMD_PREPEND_HIGH:
2177	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighWr);
2178	/* Not supported. */
2179	break;
2180
2181	case SVGA_REG_FB_START:
2182	case SVGA_REG_MEM_START:
2183	case SVGA_REG_HOST_BITS_PER_PIXEL:
2184	case SVGA_REG_MAX_WIDTH:
2185	case SVGA_REG_MAX_HEIGHT:
2186	case SVGA_REG_VRAM_SIZE:
2187	case SVGA_REG_FB_SIZE:
2188	case SVGA_REG_CAPABILITIES:
2189	case SVGA_REG_MEM_SIZE:
2190	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
2191	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
2192	case SVGA_REG_BYTES_PER_LINE:
2193	case SVGA_REG_FB_OFFSET:
2194	case SVGA_REG_RED_MASK:
2195	case SVGA_REG_GREEN_MASK:
2196	case SVGA_REG_BLUE_MASK:
2197	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
2198	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
2199	case SVGA_REG_GMR_MAX_IDS:
2200	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
2201	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
2202	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
2203	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
2204	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
2205	case SVGA_REG_MOB_MAX_SIZE:
2206	/* Read only - ignore. */
2207	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
2208	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
2209	break;
2210
2211	default:
2212	{
2213	uint32_t offReg;
2214	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
2215	{
2216	RT_UNTRUSTED_VALIDATED_FENCE();
2217	pThis->svga.au32ScratchRegion[offReg] = u32;
2218	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
2219	}
2220	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
2221	{
2222	/* Note! Using last_palette rather than palette here to preserve the VGA one.
2223	Btw, see rgb_to_pixel32. */
2224	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
2225	u32 &= 0xff;
2226	RT_UNTRUSTED_VALIDATED_FENCE();
2227	uint32_t uRgb = pThis->last_palette[offReg / 3];
2228	switch (offReg % 3)
2229	{
2230	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
2231	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
2232	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
2233	}
2234	pThis->last_palette[offReg / 3] = uRgb;
2235	}
2236	else
2237	{
2238	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2239	rc = VINF_IOM_R3_IOPORT_WRITE;
2240	#else
2241	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
2242	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
2243	#endif
2244	}
2245	break;
2246	}
2247	}
2248	return rc;
2249	}
2250
2251	/**
2252	* @callback_method_impl{FNIOMIOPORTNEWIN}
2253	*/
2254	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2255	{
2256	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2257	RT_NOREF_PV(pvUser);
2258
2259	/* Only dword accesses. */
2260	if (cb == 4)
2261	{
2262	switch (offPort)
2263	{
2264	case SVGA_INDEX_PORT:
2265	*pu32 = pThis->svga.u32IndexReg;
2266	break;
2267
2268	case SVGA_VALUE_PORT:
2269	return vmsvgaReadPort(pDevIns, pThis, pu32);
2270
2271	case SVGA_BIOS_PORT:
2272	Log(("Ignoring BIOS port read\n"));
2273	*pu32 = 0;
2274	break;
2275
2276	case SVGA_IRQSTATUS_PORT:
2277	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2278	*pu32 = pThis->svga.u32IrqStatus;
2279	break;
2280
2281	default:
2282	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
2283	*pu32 = UINT32_MAX;
2284	break;
2285	}
2286	}
2287	else
2288	{
2289	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2290	*pu32 = UINT32_MAX;
2291	}
2292	return VINF_SUCCESS;
2293	}
2294
2295	/**
2296	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2297	*/
2298	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2299	{
2300	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2301	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2302	RT_NOREF_PV(pvUser);
2303
2304	/* Only dword accesses. */
2305	if (cb == 4)
2306	switch (offPort)
2307	{
2308	case SVGA_INDEX_PORT:
2309	pThis->svga.u32IndexReg = u32;
2310	break;
2311
2312	case SVGA_VALUE_PORT:
2313	return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2314
2315	case SVGA_BIOS_PORT:
2316	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2317	break;
2318
2319	case SVGA_IRQSTATUS_PORT:
2320	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2321	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2322	/* Clear the irq in case all events have been cleared. */
2323	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2324	{
2325	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2326	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2327	}
2328	break;
2329
2330	default:
2331	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2332	break;
2333	}
2334	else
2335	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2336
2337	return VINF_SUCCESS;
2338	}
2339
2340	#ifdef IN_RING3
2341
2342	# ifdef DEBUG_FIFO_ACCESS
2343	/**
2344	* Handle FIFO memory access.
2345	* @returns VBox status code.
2346	* @param pVM VM handle.
2347	* @param pThis The shared VGA/VMSVGA instance data.
2348	* @param GCPhys The access physical address.
2349	* @param fWriteAccess Read or write access
2350	*/
2351	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2352	{
2353	RT_NOREF(pVM);
2354	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2355	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2356
2357	switch (GCPhysOffset >> 2)
2358	{
2359	case SVGA_FIFO_MIN:
2360	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2361	break;
2362	case SVGA_FIFO_MAX:
2363	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2364	break;
2365	case SVGA_FIFO_NEXT_CMD:
2366	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2367	break;
2368	case SVGA_FIFO_STOP:
2369	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2370	break;
2371	case SVGA_FIFO_CAPABILITIES:
2372	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2373	break;
2374	case SVGA_FIFO_FLAGS:
2375	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2376	break;
2377	case SVGA_FIFO_FENCE:
2378	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2379	break;
2380	case SVGA_FIFO_3D_HWVERSION:
2381	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2382	break;
2383	case SVGA_FIFO_PITCHLOCK:
2384	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2385	break;
2386	case SVGA_FIFO_CURSOR_ON:
2387	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2388	break;
2389	case SVGA_FIFO_CURSOR_X:
2390	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2391	break;
2392	case SVGA_FIFO_CURSOR_Y:
2393	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2394	break;
2395	case SVGA_FIFO_CURSOR_COUNT:
2396	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2397	break;
2398	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2399	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2400	break;
2401	case SVGA_FIFO_RESERVED:
2402	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2403	break;
2404	case SVGA_FIFO_CURSOR_SCREEN_ID:
2405	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2406	break;
2407	case SVGA_FIFO_DEAD:
2408	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2409	break;
2410	case SVGA_FIFO_3D_HWVERSION_REVISED:
2411	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2412	break;
2413	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2414	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2415	break;
2416	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2417	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2418	break;
2419	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2420	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2421	break;
2422	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2423	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2424	break;
2425	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2426	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2427	break;
2428	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2429	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2430	break;
2431	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2432	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2433	break;
2434	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2435	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2436	break;
2437	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2438	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2439	break;
2440	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2441	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2442	break;
2443	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2444	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2445	break;
2446	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2447	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2448	break;
2449	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2450	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2451	break;
2452	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2453	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2454	break;
2455	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2456	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2457	break;
2458	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2459	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2460	break;
2461	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2462	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2463	break;
2464	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2465	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2466	break;
2467	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2468	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2469	break;
2470	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2471	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2472	break;
2473	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2474	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2475	break;
2476	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2477	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2478	break;
2479	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2480	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2481	break;
2482	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2483	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2484	break;
2485	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2486	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2487	break;
2488	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2489	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2490	break;
2491	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2492	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2493	break;
2494	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2495	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2496	break;
2497	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2498	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2499	break;
2500	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2501	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2502	break;
2503	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2504	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2505	break;
2506	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2507	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2508	break;
2509	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2510	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2511	break;
2512	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2513	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2514	break;
2515	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2516	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2517	break;
2518	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2519	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2520	break;
2521	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2522	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2523	break;
2524	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2525	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2526	break;
2527	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2528	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2529	break;
2530	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2531	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2532	break;
2533	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2534	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2535	break;
2536	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2537	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2538	break;
2539	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2540	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2541	break;
2542	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2543	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2544	break;
2545	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2546	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2547	break;
2548	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2549	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2550	break;
2551	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2552	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2553	break;
2554	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2555	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2556	break;
2557	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2558	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2559	break;
2560	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2561	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2562	break;
2563	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2564	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2565	break;
2566	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2567	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2568	break;
2569	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2570	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2571	break;
2572	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2573	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2574	break;
2575	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2576	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2577	break;
2578	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2579	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2580	break;
2581	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2582	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2583	break;
2584	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2585	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2586	break;
2587	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2588	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2589	break;
2590	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2591	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2592	break;
2593	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2594	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2595	break;
2596	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2597	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2598	break;
2599	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2600	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2601	break;
2602	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2603	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2604	break;
2605	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2606	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2607	break;
2608	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2609	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2610	break;
2611	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2612	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2613	break;
2614	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2615	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2616	break;
2617	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2618	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2619	break;
2620	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2621	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2622	break;
2623	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2624	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2625	break;
2626	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2627	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2628	break;
2629	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2630	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2631	break;
2632	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2633	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2634	break;
2635	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2636	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2637	break;
2638	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2639	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2640	break;
2641	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2642	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2643	break;
2644	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2645	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2646	break;
2647	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2648	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2649	break;
2650	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2651	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2652	break;
2653	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2654	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2655	break;
2656	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI1:
2657	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2658	break;
2659	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI2:
2660	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2661	break;
2662	case SVGA_FIFO_3D_CAPS_LAST:
2663	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2664	break;
2665	case SVGA_FIFO_GUEST_3D_HWVERSION:
2666	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2667	break;
2668	case SVGA_FIFO_FENCE_GOAL:
2669	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2670	break;
2671	case SVGA_FIFO_BUSY:
2672	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2673	break;
2674	default:
2675	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2676	break;
2677	}
2678
2679	return VINF_EM_RAW_EMULATE_INSTR;
2680	}
2681	# endif /* DEBUG_FIFO_ACCESS */
2682
2683	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2684	/**
2685	* HC access handler for the FIFO.
2686	*
2687	* @returns VINF_SUCCESS if the handler have carried out the operation.
2688	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2689	* @param pVM VM Handle.
2690	* @param pVCpu The cross context CPU structure for the calling EMT.
2691	* @param GCPhys The physical address the guest is writing to.
2692	* @param pvPhys The HC mapping of that address.
2693	* @param pvBuf What the guest is reading/writing.
2694	* @param cbBuf How much it's reading/writing.
2695	* @param enmAccessType The access type.
2696	* @param enmOrigin Who is making the access.
2697	* @param pvUser User argument.
2698	*/
2699	static DECLCALLBACK(VBOXSTRICTRC)
2700	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2701	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2702	{
2703	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2704	PVGASTATE pThis = (PVGASTATE)pvUser;
2705	AssertPtr(pThis);
2706
2707	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2708	/*
2709	* Wake up the FIFO thread as it might have work to do now.
2710	*/
2711	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2712	AssertLogRelRC(rc);
2713	# endif
2714
2715	# ifdef DEBUG_FIFO_ACCESS
2716	/*
2717	* When in debug-fifo-access mode, we do not disable the access handler,
2718	* but leave it on as we wish to catch all access.
2719	*/
2720	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2721	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2722	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2723	/*
2724	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2725	*/
2726	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
2727	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2728	# endif
2729	if (RT_SUCCESS(rc))
2730	return VINF_PGM_HANDLER_DO_DEFAULT;
2731	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2732	return rc;
2733	}
2734	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2735
2736	#endif /* IN_RING3 */
2737
2738	#ifdef DEBUG_GMR_ACCESS
2739	# ifdef IN_RING3
2740
2741	/**
2742	* HC access handler for GMRs.
2743	*
2744	* @returns VINF_SUCCESS if the handler have carried out the operation.
2745	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2746	* @param pVM VM Handle.
2747	* @param pVCpu The cross context CPU structure for the calling EMT.
2748	* @param GCPhys The physical address the guest is writing to.
2749	* @param pvPhys The HC mapping of that address.
2750	* @param pvBuf What the guest is reading/writing.
2751	* @param cbBuf How much it's reading/writing.
2752	* @param enmAccessType The access type.
2753	* @param enmOrigin Who is making the access.
2754	* @param pvUser User argument.
2755	*/
2756	static DECLCALLBACK(VBOXSTRICTRC)
2757	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2758	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2759	{
2760	PVGASTATE pThis = (PVGASTATE)pvUser;
2761	Assert(pThis);
2762	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2763	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2764
2765	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
2766
2767	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2768	{
2769	PGMR pGMR = &pSVGAState->paGMR[i];
2770
2771	if (pGMR->numDescriptors)
2772	{
2773	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2774	{
2775	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2776	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2777	{
2778	/*
2779	* Turn off the write handler for this particular page and make it R/W.
2780	* Then return telling the caller to restart the guest instruction.
2781	*/
2782	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2783	AssertRC(rc);
2784	return VINF_PGM_HANDLER_DO_DEFAULT;
2785	}
2786	}
2787	}
2788	}
2789
2790	return VINF_PGM_HANDLER_DO_DEFAULT;
2791	}
2792
2793	/** Callback handler for VMR3ReqCallWaitU */
2794	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2795	{
2796	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2797	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2798	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2799	int rc;
2800
2801	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2802	{
2803	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
2804	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2805	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2806	AssertRC(rc);
2807	}
2808	return VINF_SUCCESS;
2809	}
2810
2811	/** Callback handler for VMR3ReqCallWaitU */
2812	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2813	{
2814	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2815	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2816	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2817
2818	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2819	{
2820	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[i].GCPhys);
2821	AssertRC(rc);
2822	}
2823	return VINF_SUCCESS;
2824	}
2825
2826	/** Callback handler for VMR3ReqCallWaitU */
2827	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
2828	{
2829	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2830
2831	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2832	{
2833	PGMR pGMR = &pSVGAState->paGMR[i];
2834
2835	if (pGMR->numDescriptors)
2836	{
2837	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2838	{
2839	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[j].GCPhys);
2840	AssertRC(rc);
2841	}
2842	}
2843	}
2844	return VINF_SUCCESS;
2845	}
2846
2847	# endif /* IN_RING3 */
2848	#endif /* DEBUG_GMR_ACCESS */
2849
2850	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2851
2852	#ifdef IN_RING3
2853
2854
2855	/*
2856	*
2857	* Command buffer submission.
2858	*
2859	* Guest submits a buffer by writing to SVGA_REG_COMMAND_LOW register.
2860	*
2861	* EMT thread appends a command buffer to the context queue (VMSVGACMDBUFCTX::listSubmitted)
2862	* and wakes up the FIFO thread.
2863	*
2864	* FIFO thread fetches the command buffer from the queue, processes the commands and writes
2865	* the buffer header back to the guest memory.
2866	*
2867	* If buffers are preempted, then the EMT thread removes all buffers from the context queue.
2868	*
2869	*/
2870
2871
2872	/** Update a command buffer header 'status' and 'errorOffset' fields in the guest memory.
2873	*
2874	* @param pDevIns The device instance.
2875	* @param GCPhysCB Guest physical address of the command buffer header.
2876	* @param status Command buffer status (SVGA_CB_STATUS_*).
2877	* @param errorOffset Offset to the first byte of the failing command for SVGA_CB_STATUS_COMMAND_ERROR.
2878	* errorOffset is ignored if the status is not SVGA_CB_STATUS_COMMAND_ERROR.
2879	* @thread FIFO or EMT.
2880	*/
2881	static void vmsvgaR3CmdBufWriteStatus(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCB, SVGACBStatus status, uint32_t errorOffset)
2882	{
2883	SVGACBHeader hdr;
2884	hdr.status = status;
2885	hdr.errorOffset = errorOffset;
2886	AssertCompile( RT_OFFSETOF(SVGACBHeader, status) == 0
2887	&& RT_OFFSETOF(SVGACBHeader, errorOffset) == 4
2888	&& RT_OFFSETOF(SVGACBHeader, id) == 8);
2889	size_t const cbWrite = status == SVGA_CB_STATUS_COMMAND_ERROR
2890	? RT_UOFFSET_AFTER(SVGACBHeader, errorOffset) /* Both 'status' and 'errorOffset' fields. */
2891	: RT_UOFFSET_AFTER(SVGACBHeader, status); /* Only 'status' field. */
2892	PDMDevHlpPCIPhysWrite(pDevIns, GCPhysCB, &hdr, cbWrite);
2893	}
2894
2895
2896	/** Raise an IRQ.
2897	*
2898	* @param pDevIns The device instance.
2899	* @param pThis The shared VGA/VMSVGA state.
2900	* @param u32IrqStatus SVGA_IRQFLAG_* bits.
2901	* @thread FIFO or EMT.
2902	*/
2903	static void vmsvgaR3CmdBufRaiseIRQ(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t u32IrqStatus)
2904	{
2905	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
2906	AssertRC(rc);
2907
2908	if (pThis->svga.u32IrqMask & u32IrqStatus)
2909	{
2910	LogFunc(("Trigger interrupt with status %#x\n", u32IrqStatus));
2911	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
2912	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
2913	}
2914
2915	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
2916	}
2917
2918
2919	/** Allocate a command buffer structure.
2920	*
2921	* @param pCmdBufCtx The command buffer context which must allocate the buffer.
2922	* @return Pointer to the allocated command buffer structure.
2923	*/
2924	static PVMSVGACMDBUF vmsvgaR3CmdBufAlloc(PVMSVGACMDBUFCTX pCmdBufCtx)
2925	{
2926	if (!pCmdBufCtx)
2927	return NULL;
2928
2929	PVMSVGACMDBUF pCmdBuf = (PVMSVGACMDBUF)RTMemAllocZ(sizeof(*pCmdBuf));
2930	if (pCmdBuf)
2931	{
2932	// RT_ZERO(pCmdBuf->nodeBuffer);
2933	pCmdBuf->pCmdBufCtx = pCmdBufCtx;
2934	// pCmdBuf->GCPhysCB = 0;
2935	// RT_ZERO(pCmdBuf->hdr);
2936	// pCmdBuf->pvCommands = NULL;
2937	}
2938
2939	return pCmdBuf;
2940	}
2941
2942
2943	/** Free a command buffer structure.
2944	*
2945	* @param pCmdBuf The command buffer pointer.
2946	*/
2947	static void vmsvgaR3CmdBufFree(PVMSVGACMDBUF pCmdBuf)
2948	{
2949	if (pCmdBuf)
2950	RTMemFree(pCmdBuf->pvCommands);
2951	RTMemFree(pCmdBuf);
2952	}
2953
2954
2955	/** Initialize a command buffer context.
2956	*
2957	* @param pCmdBufCtx The command buffer context.
2958	*/
2959	static void vmsvgaR3CmdBufCtxInit(PVMSVGACMDBUFCTX pCmdBufCtx)
2960	{
2961	RTListInit(&pCmdBufCtx->listSubmitted);
2962	pCmdBufCtx->cSubmitted = 0;
2963	}
2964
2965
2966	/** Destroy a command buffer context.
2967	*
2968	* @param pCmdBufCtx The command buffer context pointer.
2969	*/
2970	static void vmsvgaR3CmdBufCtxTerm(PVMSVGACMDBUFCTX pCmdBufCtx)
2971	{
2972	if (!pCmdBufCtx)
2973	return;
2974
2975	if (pCmdBufCtx->listSubmitted.pNext)
2976	{
2977	/* If the list has been initialized. */
2978	PVMSVGACMDBUF pIter, pNext;
2979	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
2980	{
2981	RTListNodeRemove(&pIter->nodeBuffer);
2982	--pCmdBufCtx->cSubmitted;
2983	vmsvgaR3CmdBufFree(pIter);
2984	}
2985	}
2986	Assert(pCmdBufCtx->cSubmitted == 0);
2987	pCmdBufCtx->cSubmitted = 0;
2988	}
2989
2990
2991	/** Handles SVGA_DC_CMD_START_STOP_CONTEXT command.
2992	*
2993	* @param pSvgaR3State VMSVGA R3 state.
2994	* @param pCmd The command data.
2995	* @return SVGACBStatus code.
2996	* @thread EMT
2997	*/
2998	static SVGACBStatus vmsvgaR3CmdBufDCStartStop(PVMSVGAR3STATE pSvgaR3State, SVGADCCmdStartStop const *pCmd)
2999	{
3000	/* Create or destroy a regular command buffer context. */
3001	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3002	return SVGA_CB_STATUS_COMMAND_ERROR;
3003	RT_UNTRUSTED_VALIDATED_FENCE();
3004
3005	SVGACBStatus CBStatus = SVGA_CB_STATUS_COMPLETED;
3006
3007	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3008	AssertRC(rc);
3009	if (pCmd->enable)
3010	{
3011	pSvgaR3State->apCmdBufCtxs[pCmd->context] = (PVMSVGACMDBUFCTX)RTMemAlloc(sizeof(VMSVGACMDBUFCTX));
3012	if (pSvgaR3State->apCmdBufCtxs[pCmd->context])
3013	vmsvgaR3CmdBufCtxInit(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3014	else
3015	CBStatus = SVGA_CB_STATUS_QUEUE_FULL;
3016	}
3017	else
3018	{
3019	vmsvgaR3CmdBufCtxTerm(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3020	pSvgaR3State->apCmdBufCtxs[pCmd->context] = NULL;
3021	}
3022	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3023
3024	return CBStatus;
3025	}
3026
3027
3028	/** Handles SVGA_DC_CMD_PREEMPT command.
3029	*
3030	* @param pDevIns The device instance.
3031	* @param pSvgaR3State VMSVGA R3 state.
3032	* @param pCmd The command data.
3033	* @return SVGACBStatus code.
3034	* @thread EMT
3035	*/
3036	static SVGACBStatus vmsvgaR3CmdBufDCPreempt(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, SVGADCCmdPreempt const *pCmd)
3037	{
3038	/* Remove buffers from the processing queue of the specified context. */
3039	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3040	return SVGA_CB_STATUS_COMMAND_ERROR;
3041	RT_UNTRUSTED_VALIDATED_FENCE();
3042
3043	PVMSVGACMDBUFCTX const pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[pCmd->context];
3044	RTLISTANCHOR listPreempted;
3045
3046	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3047	AssertRC(rc);
3048	if (pCmd->ignoreIDZero)
3049	{
3050	RTListInit(&listPreempted);
3051
3052	PVMSVGACMDBUF pIter, pNext;
3053	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3054	{
3055	if (pIter->hdr.id == 0)
3056	continue;
3057
3058	RTListNodeRemove(&pIter->nodeBuffer);
3059	--pCmdBufCtx->cSubmitted;
3060	RTListAppend(&listPreempted, &pIter->nodeBuffer);
3061	}
3062	}
3063	else
3064	{
3065	RTListMove(&listPreempted, &pCmdBufCtx->listSubmitted);
3066	}
3067	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3068
3069	PVMSVGACMDBUF pIter, pNext;
3070	RTListForEachSafe(&listPreempted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3071	{
3072	RTListNodeRemove(&pIter->nodeBuffer);
3073	vmsvgaR3CmdBufWriteStatus(pDevIns, pIter->GCPhysCB, SVGA_CB_STATUS_PREEMPTED, 0);
3074	vmsvgaR3CmdBufFree(pIter);
3075	}
3076
3077	return SVGA_CB_STATUS_COMPLETED;
3078	}
3079
3080
3081	/** @def VMSVGA_INC_CMD_SIZE_BREAK
3082	* Increments the size of the command cbCmd by a_cbMore.
3083	* Checks that the command buffer has at least cbCmd bytes. Will break out of the switch if it doesn't.
3084	* Used by vmsvgaR3CmdBufProcessDC and vmsvgaR3CmdBufProcessCommands.
3085	*/
3086	#define VMSVGA_INC_CMD_SIZE_BREAK(a_cbMore) \
3087	if (1) { \
3088	cbCmd += (a_cbMore); \
3089	ASSERT_GUEST_MSG_STMT_BREAK(cbRemain >= cbCmd, ("size=%#x remain=%#zx\n", cbCmd, (size_t)cbRemain), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR); \
3090	RT_UNTRUSTED_VALIDATED_FENCE(); \
3091	} else do {} while (0)
3092
3093
3094	/** Processes Device Context command buffer.
3095	*
3096	* @param pDevIns The device instance.
3097	* @param pSvgaR3State VMSVGA R3 state.
3098	* @param pvCommands Pointer to the command buffer.
3099	* @param cbCommands Size of the command buffer.
3100	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3101	* @return SVGACBStatus code.
3102	* @thread EMT
3103	*/
3104	static SVGACBStatus vmsvgaR3CmdBufProcessDC(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd)
3105	{
3106	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3107
3108	uint8_t const pu8Cmd = (uint8_t )pvCommands;
3109	uint32_t cbRemain = cbCommands;
3110	while (cbRemain)
3111	{
3112	/* Command identifier is a 32 bit value. */
3113	if (cbRemain < sizeof(uint32_t))
3114	{
3115	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3116	break;
3117	}
3118
3119	/* Fetch the command id. */
3120	uint32_t const cmdId = (uint32_t )pu8Cmd;
3121	uint32_t cbCmd = sizeof(uint32_t);
3122	switch (cmdId)
3123	{
3124	case SVGA_DC_CMD_NOP:
3125	{
3126	/* NOP */
3127	break;
3128	}
3129
3130	case SVGA_DC_CMD_START_STOP_CONTEXT:
3131	{
3132	SVGADCCmdStartStop pCmd = (SVGADCCmdStartStop )&pu8Cmd[cbCmd];
3133	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3134	CBstatus = vmsvgaR3CmdBufDCStartStop(pSvgaR3State, pCmd);
3135	break;
3136	}
3137
3138	case SVGA_DC_CMD_PREEMPT:
3139	{
3140	SVGADCCmdPreempt pCmd = (SVGADCCmdPreempt )&pu8Cmd[cbCmd];
3141	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3142	CBstatus = vmsvgaR3CmdBufDCPreempt(pDevIns, pSvgaR3State, pCmd);
3143	break;
3144	}
3145
3146	default:
3147	{
3148	/* Unsupported command. */
3149	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3150	break;
3151	}
3152	}
3153
3154	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
3155	break;
3156
3157	pu8Cmd += cbCmd;
3158	cbRemain -= cbCmd;
3159	}
3160
3161	Assert(cbRemain <= cbCommands);
3162	*poffNextCmd = cbCommands - cbRemain;
3163	return CBstatus;
3164	}
3165
3166
3167	/** Submits a device context command buffer for synchronous processing.
3168	*
3169	* @param pDevIns The device instance.
3170	* @param pThisCC The VGA/VMSVGA state for the current context.
3171	* @param ppCmdBuf Pointer to the command buffer pointer.
3172	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3173	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3174	* @return SVGACBStatus code.
3175	* @thread EMT
3176	*/
3177	static SVGACBStatus vmsvgaR3CmdBufSubmitDC(PPDMDEVINS pDevIns, PVGASTATECC pThisCC, PVMSVGACMDBUF ppCmdBuf, uint32_t poffNextCmd)
3178	{
3179	/* Synchronously process the device context commands. */
3180	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3181	return vmsvgaR3CmdBufProcessDC(pDevIns, pSvgaR3State, (ppCmdBuf)->pvCommands, (ppCmdBuf)->hdr.length, poffNextCmd);
3182	}
3183
3184	/** Submits a command buffer for asynchronous processing by the FIFO thread.
3185	*
3186	* @param pDevIns The device instance.
3187	* @param pThis The shared VGA/VMSVGA state.
3188	* @param pThisCC The VGA/VMSVGA state for the current context.
3189	* @param ppCmdBuf Pointer to the command buffer pointer.
3190	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3191	* @return SVGACBStatus code.
3192	* @thread EMT
3193	*/
3194	static SVGACBStatus vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGACMDBUF *ppCmdBuf)
3195	{
3196	/* Command buffer submission. */
3197	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3198
3199	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3200
3201	PVMSVGACMDBUF const pCmdBuf = *ppCmdBuf;
3202	PVMSVGACMDBUFCTX const pCmdBufCtx = pCmdBuf->pCmdBufCtx;
3203
3204	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3205	AssertRC(rc);
3206
3207	if (RT_LIKELY(pCmdBufCtx->cSubmitted < SVGA_CB_MAX_QUEUED_PER_CONTEXT))
3208	{
3209	RTListAppend(&pCmdBufCtx->listSubmitted, &pCmdBuf->nodeBuffer);
3210	++pCmdBufCtx->cSubmitted;
3211	ppCmdBuf = NULL; / Consume the buffer. */
3212	ASMAtomicWriteU32(&pThisCC->svga.pSvgaR3State->fCmdBuf, 1);
3213	}
3214	else
3215	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3216
3217	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3218
3219	/* Inform the FIFO thread. */
3220	if (*ppCmdBuf == NULL)
3221	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3222
3223	return CBstatus;
3224	}
3225
3226
3227	/** SVGA_REG_COMMAND_LOW write handler.
3228	* Submits a command buffer to the FIFO thread or processes a device context command.
3229	*
3230	* @param pDevIns The device instance.
3231	* @param pThis The shared VGA/VMSVGA state.
3232	* @param pThisCC The VGA/VMSVGA state for the current context.
3233	* @param GCPhysCB Guest physical address of the command buffer header.
3234	* @param CBCtx Context the command buffer is submitted to.
3235	* @thread EMT
3236	*/
3237	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx)
3238	{
3239	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3240
3241	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3242	uint32_t offNextCmd = 0;
3243	uint32_t fIRQ = 0;
3244
3245	/* Get the context if the device has the capability. */
3246	PVMSVGACMDBUFCTX pCmdBufCtx = NULL;
3247	if (pThis->svga.u32DeviceCaps & SVGA_CAP_COMMAND_BUFFERS)
3248	{
3249	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3250	pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[CBCtx];
3251	else if (CBCtx == SVGA_CB_CONTEXT_DEVICE)
3252	pCmdBufCtx = &pSvgaR3State->CmdBufCtxDC;
3253	RT_UNTRUSTED_VALIDATED_FENCE();
3254	}
3255
3256	/* Allocate a new command buffer. */
3257	PVMSVGACMDBUF pCmdBuf = vmsvgaR3CmdBufAlloc(pCmdBufCtx);
3258	if (RT_LIKELY(pCmdBuf))
3259	{
3260	pCmdBuf->GCPhysCB = GCPhysCB;
3261
3262	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCB, &pCmdBuf->hdr, sizeof(pCmdBuf->hdr));
3263	if (RT_SUCCESS(rc))
3264	{
3265	/* Verify the command buffer header. */
3266	if (RT_LIKELY( pCmdBuf->hdr.status == SVGA_CB_STATUS_NONE
3267	&& (pCmdBuf->hdr.flags & ~(SVGA_CB_FLAG_NO_IRQ)) == 0 /* No unexpected flags. */
3268	&& pCmdBuf->hdr.length <= SVGA_CB_MAX_SIZE))
3269	{
3270	RT_UNTRUSTED_VALIDATED_FENCE();
3271
3272	/* Read the command buffer content. */
3273	pCmdBuf->pvCommands = RTMemAlloc(pCmdBuf->hdr.length);
3274	if (pCmdBuf->pvCommands)
3275	{
3276	RTGCPHYS const GCPhysCmd = (RTGCPHYS)pCmdBuf->hdr.ptr.pa;
3277	rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, pCmdBuf->pvCommands, pCmdBuf->hdr.length);
3278	if (RT_SUCCESS(rc))
3279	{
3280	/* Submit the buffer. Device context buffers will be processed synchronously. */
3281	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3282	/* This usually processes the CB async and sets pCmbBuf to NULL. */
3283	CBstatus = vmsvgaR3CmdBufSubmit(pDevIns, pThis, pThisCC, &pCmdBuf);
3284	else
3285	CBstatus = vmsvgaR3CmdBufSubmitDC(pDevIns, pThisCC, &pCmdBuf, &offNextCmd);
3286	}
3287	else
3288	{
3289	ASSERT_GUEST_MSG_FAILED(("Failed to read commands at %RGp\n", GCPhysCmd));
3290	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3291	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
3292	}
3293	}
3294	else
3295	{
3296	/* No memory for commands. */
3297	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3298	}
3299	}
3300	else
3301	{
3302	ASSERT_GUEST_MSG_FAILED(("Invalid buffer header\n"));
3303	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3304	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
3305	}
3306	}
3307	else
3308	{
3309	LogFunc(("Failed to read buffer header at %RGp\n", GCPhysCB));
3310	ASSERT_GUEST_FAILED();
3311	/* Do not attempt to write the status. */
3312	}
3313
3314	/* Free the buffer if pfnCmdBufSubmit did not consume it. */
3315	vmsvgaR3CmdBufFree(pCmdBuf);
3316	}
3317	else
3318	{
3319	LogFunc(("Can't allocate buffer for context id %#x\n", CBCtx));
3320	ASSERT_GUEST_FAILED();
3321	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3322	}
3323
3324	if (CBstatus != SVGA_CB_STATUS_NONE)
3325	{
3326	LogFunc(("Write status %#x, offNextCmd %#x (of %#x), fIRQ %#x\n", CBstatus, offNextCmd, pCmdBuf->hdr.length, fIRQ));
3327	vmsvgaR3CmdBufWriteStatus(pDevIns, GCPhysCB, CBstatus, offNextCmd);
3328	if (fIRQ)
3329	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, fIRQ);
3330	}
3331	}
3332
3333
3334	/** Checks if there are some buffers to be processed.
3335	*
3336	* @param pThisCC The VGA/VMSVGA state for the current context.
3337	* @return true if buffers must be processed.
3338	* @thread FIFO
3339	*/
3340	static bool vmsvgaR3CmdBufHasWork(PVGASTATECC pThisCC)
3341	{
3342	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3343	return RT_BOOL(ASMAtomicReadU32(&pSvgaR3State->fCmdBuf));
3344	}
3345
3346
3347	/** Processes a command buffer.
3348	*
3349	* @param pDevIns The device instance.
3350	* @param pThis The shared VGA/VMSVGA state.
3351	* @param pThisCC The VGA/VMSVGA state for the current context.
3352	* @param pvCommands Pointer to the command buffer.
3353	* @param cbCommands Size of the command buffer.
3354	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3355	* @param pu32IrqStatus Where to store SVGA_IRQFLAG_ if the IRQ is generated by the last command in the buffer.
3356	* @return SVGACBStatus code.
3357	* @thread FIFO
3358	*/
3359	static SVGACBStatus vmsvgaR3CmdBufProcessCommands(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd, uint32_t *pu32IrqStatus)
3360	{
3361	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3362	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3363
3364	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3365
3366	uint8_t const pu8Cmd = (uint8_t )pvCommands;
3367	uint32_t cbRemain = cbCommands;
3368	while (cbRemain)
3369	{
3370	/* Command identifier is a 32 bit value. */
3371	if (cbRemain < sizeof(uint32_t))
3372	{
3373	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3374	break;
3375	}
3376
3377	/* Fetch the command id.
3378	* 'cmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
3379	* warning. Because we support some obsolete and deprecated commands, which are not included in
3380	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
3381	*/
3382	uint32_t const cmdId = (uint32_t )pu8Cmd;
3383	uint32_t cbCmd = sizeof(uint32_t);
3384
3385	LogFlowFunc(("%s %d\n", vmsvgaR3FifoCmdToString(cmdId), cmdId));
3386
3387	/* At the end of the switch cbCmd is equal to the total length of the command including the cmdId.
3388	* I.e. pu8Cmd + cbCmd must point to the next command.
3389	* However if CBstatus is set to anything but SVGA_CB_STATUS_COMPLETED in the switch, then
3390	* the cbCmd value is ignored (and pu8Cmd still points to the failed command).
3391	*/
3392	/** @todo This code is very similar to the FIFO loop command processing. Think about merging. */
3393	switch (cmdId)
3394	{
3395	case SVGA_CMD_INVALID_CMD:
3396	{
3397	/* Nothing to do. */
3398	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdInvalidCmd);
3399	break;
3400	}
3401
3402	case SVGA_CMD_FENCE:
3403	{
3404	SVGAFifoCmdFence pCmd = (SVGAFifoCmdFence )&pu8Cmd[cbCmd];
3405	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3406	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdFence);
3407	Log(("SVGA_CMD_FENCE %#x\n", pCmd->fence));
3408
3409	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3410	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3411	{
3412	pFIFO[SVGA_FIFO_FENCE] = pCmd->fence;
3413
3414	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3415	{
3416	Log(("any fence irq\n"));
3417	*pu32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3418	}
3419	else if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3420	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3421	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmd->fence)
3422	{
3423	Log(("fence goal reached irq (fence=%#x)\n", pCmd->fence));
3424	*pu32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3425	}
3426	}
3427	else
3428	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3429	break;
3430	}
3431
3432	case SVGA_CMD_UPDATE:
3433	{
3434	SVGAFifoCmdUpdate pCmd = (SVGAFifoCmdUpdate )&pu8Cmd[cbCmd];
3435	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3436	vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
3437	break;
3438	}
3439
3440	case SVGA_CMD_UPDATE_VERBOSE:
3441	{
3442	SVGAFifoCmdUpdateVerbose pCmd = (SVGAFifoCmdUpdateVerbose )&pu8Cmd[cbCmd];
3443	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3444	vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
3445	break;
3446	}
3447
3448	case SVGA_CMD_DEFINE_CURSOR:
3449	{
3450	/* Followed by bitmap data. */
3451	SVGAFifoCmdDefineCursor pCmd = (SVGAFifoCmdDefineCursor )&pu8Cmd[cbCmd];
3452	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3453
3454	/* Figure out the size of the bitmap data. */
3455	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3456	ASSERT_GUEST_STMT_BREAK(pCmd->andMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3457	ASSERT_GUEST_STMT_BREAK(pCmd->xorMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3458	RT_UNTRUSTED_VALIDATED_FENCE();
3459
3460	uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
3461	uint32_t const cbAndMask = cbAndLine * pCmd->height;
3462	uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
3463	uint32_t const cbXorMask = cbXorLine * pCmd->height;
3464
3465	VMSVGA_INC_CMD_SIZE_BREAK(cbAndMask + cbXorMask);
3466	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
3467	break;
3468	}
3469
3470	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3471	{
3472	/* Followed by bitmap data. */
3473	SVGAFifoCmdDefineAlphaCursor pCmd = (SVGAFifoCmdDefineAlphaCursor )&pu8Cmd[cbCmd];
3474	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3475
3476	/* Figure out the size of the bitmap data. */
3477	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3478
3479	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->width * pCmd->height * sizeof(uint32_t)); /* 32-bit BRGA format */
3480	vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
3481	break;
3482	}
3483
3484	case SVGA_CMD_MOVE_CURSOR:
3485	{
3486	/* Deprecated; there should be no driver which requires this command. However, if
3487	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3488	* alignment.
3489	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3490	*/
3491	SVGAFifoCmdMoveCursor pCmd = (SVGAFifoCmdMoveCursor )&pu8Cmd[cbCmd];
3492	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3493	vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
3494	break;
3495	}
3496
3497	case SVGA_CMD_DISPLAY_CURSOR:
3498	{
3499	/* Deprecated; there should be no driver which requires this command. However, if
3500	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3501	* alignment.
3502	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3503	*/
3504	SVGAFifoCmdDisplayCursor pCmd = (SVGAFifoCmdDisplayCursor )&pu8Cmd[cbCmd];
3505	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3506	vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
3507	break;
3508	}
3509
3510	case SVGA_CMD_RECT_FILL:
3511	{
3512	SVGAFifoCmdRectFill pCmd = (SVGAFifoCmdRectFill )&pu8Cmd[cbCmd];
3513	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3514	vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
3515	break;
3516	}
3517
3518	case SVGA_CMD_RECT_COPY:
3519	{
3520	SVGAFifoCmdRectCopy pCmd = (SVGAFifoCmdRectCopy )&pu8Cmd[cbCmd];
3521	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3522	vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
3523	break;
3524	}
3525
3526	case SVGA_CMD_RECT_ROP_COPY:
3527	{
3528	SVGAFifoCmdRectRopCopy pCmd = (SVGAFifoCmdRectRopCopy )&pu8Cmd[cbCmd];
3529	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3530	vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
3531	break;
3532	}
3533
3534	case SVGA_CMD_ESCAPE:
3535	{
3536	/* Followed by 'size' bytes of data. */
3537	SVGAFifoCmdEscape pCmd = (SVGAFifoCmdEscape )&pu8Cmd[cbCmd];
3538	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3539
3540	ASSERT_GUEST_STMT_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3541	RT_UNTRUSTED_VALIDATED_FENCE();
3542
3543	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->size);
3544	vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
3545	break;
3546	}
3547	# ifdef VBOX_WITH_VMSVGA3D
3548	case SVGA_CMD_DEFINE_GMR2:
3549	{
3550	SVGAFifoCmdDefineGMR2 pCmd = (SVGAFifoCmdDefineGMR2 )&pu8Cmd[cbCmd];
3551	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3552	vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
3553	break;
3554	}
3555
3556	case SVGA_CMD_REMAP_GMR2:
3557	{
3558	/* Followed by page descriptors or guest ptr. */
3559	SVGAFifoCmdRemapGMR2 pCmd = (SVGAFifoCmdRemapGMR2 )&pu8Cmd[cbCmd];
3560	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3561
3562	/* Calculate the size of what comes after next and fetch it. */
3563	uint32_t cbMore = 0;
3564	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3565	cbMore = sizeof(SVGAGuestPtr);
3566	else
3567	{
3568	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3569	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3570	{
3571	cbMore = cbPageDesc;
3572	pCmd->numPages = 1;
3573	}
3574	else
3575	{
3576	ASSERT_GUEST_STMT_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3577	cbMore = cbPageDesc * pCmd->numPages;
3578	}
3579	}
3580	VMSVGA_INC_CMD_SIZE_BREAK(cbMore);
3581	vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
3582	# ifdef DEBUG_GMR_ACCESS
3583	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
3584	# endif
3585	break;
3586	}
3587	# endif /* VBOX_WITH_VMSVGA3D */
3588	case SVGA_CMD_DEFINE_SCREEN:
3589	{
3590	/* The size of this command is specified by the guest and depends on capabilities. */
3591	SVGAFifoCmdDefineScreen pCmd = (SVGAFifoCmdDefineScreen )&pu8Cmd[cbCmd];
3592	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(pCmd->screen.structSize));
3593	ASSERT_GUEST_STMT_BREAK(pCmd->screen.structSize < pThis->svga.cbFIFO, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3594	RT_UNTRUSTED_VALIDATED_FENCE();
3595
3596	VMSVGA_INC_CMD_SIZE_BREAK(RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize) - sizeof(pCmd->screen.structSize));
3597	vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
3598	break;
3599	}
3600
3601	case SVGA_CMD_DESTROY_SCREEN:
3602	{
3603	SVGAFifoCmdDestroyScreen pCmd = (SVGAFifoCmdDestroyScreen )&pu8Cmd[cbCmd];
3604	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3605	vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
3606	break;
3607	}
3608
3609	case SVGA_CMD_DEFINE_GMRFB:
3610	{
3611	SVGAFifoCmdDefineGMRFB pCmd = (SVGAFifoCmdDefineGMRFB )&pu8Cmd[cbCmd];
3612	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3613	vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
3614	break;
3615	}
3616
3617	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
3618	{
3619	SVGAFifoCmdBlitGMRFBToScreen pCmd = (SVGAFifoCmdBlitGMRFBToScreen )&pu8Cmd[cbCmd];
3620	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3621	vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
3622	break;
3623	}
3624
3625	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
3626	{
3627	SVGAFifoCmdBlitScreenToGMRFB pCmd = (SVGAFifoCmdBlitScreenToGMRFB )&pu8Cmd[cbCmd];
3628	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3629	vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
3630	break;
3631	}
3632
3633	case SVGA_CMD_ANNOTATION_FILL:
3634	{
3635	SVGAFifoCmdAnnotationFill pCmd = (SVGAFifoCmdAnnotationFill )&pu8Cmd[cbCmd];
3636	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3637	vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
3638	break;
3639	}
3640
3641	case SVGA_CMD_ANNOTATION_COPY:
3642	{
3643	SVGAFifoCmdAnnotationCopy pCmd = (SVGAFifoCmdAnnotationCopy )&pu8Cmd[cbCmd];
3644	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3645	vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
3646	break;
3647	}
3648
3649	default:
3650	{
3651	# ifdef VBOX_WITH_VMSVGA3D
3652	if ( cmdId >= SVGA_3D_CMD_BASE
3653	&& cmdId < SVGA_3D_CMD_MAX)
3654	{
3655	RT_UNTRUSTED_VALIDATED_FENCE();
3656
3657	/* All 3d commands start with a common header, which defines the identifier and the size
3658	* of the command. The identifier has been already read. Fetch the size.
3659	*/
3660	uint32_t const pcbMore = (uint32_t const )&pu8Cmd[cbCmd];
3661	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pcbMore));
3662	VMSVGA_INC_CMD_SIZE_BREAK(*pcbMore);
3663	if (RT_LIKELY(pThis->svga.f3DEnabled))
3664	{ /* likely */ }
3665	else
3666	{
3667	LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", cmdId));
3668	break;
3669	}
3670
3671	/* Command data begins after the 32 bit command length. */
3672	int rc = vmsvgaR3Process3dCmd(pThis, pThisCC, (SVGAFifo3dCmdId)cmdId, *pcbMore, pcbMore + 1);
3673	if (RT_SUCCESS(rc))
3674	{ /* likely */ }
3675	else
3676	{
3677	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3678	break;
3679	}
3680	}
3681	else
3682	# endif /* VBOX_WITH_VMSVGA3D */
3683	{
3684	/* Unsupported command. */
3685	STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
3686	ASSERT_GUEST_MSG_FAILED(("cmdId=%d\n", cmdId));
3687	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3688	break;
3689	}
3690	}
3691	}
3692
3693	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
3694	break;
3695
3696	pu8Cmd += cbCmd;
3697	cbRemain -= cbCmd;
3698
3699	/* If this is not the last command in the buffer, then generate IRQ, if required.
3700	* This avoids a double call to vmsvgaR3CmdBufRaiseIRQ if FENCE is the last command
3701	* in the buffer (usually the case).
3702	*/
3703	if (RT_LIKELY(!(cbRemain && *pu32IrqStatus)))
3704	{ /* likely */ }
3705	else
3706	{
3707	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, *pu32IrqStatus);
3708	*pu32IrqStatus = 0;
3709	}
3710	}
3711
3712	Assert(cbRemain <= cbCommands);
3713	*poffNextCmd = cbCommands - cbRemain;
3714	return CBstatus;
3715	}
3716
3717
3718	/** Process command buffers.
3719	*
3720	* @param pDevIns The device instance.
3721	* @param pThis The shared VGA/VMSVGA state.
3722	* @param pThisCC The VGA/VMSVGA state for the current context.
3723	* @param pThread Handle of the FIFO thread.
3724	* @thread FIFO
3725	*/
3726	static void vmsvgaR3CmdBufProcessBuffers(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PPDMTHREAD pThread)
3727	{
3728	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3729
3730	for (;;)
3731	{
3732	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3733	break;
3734
3735	/* See if there is a submitted buffer. */
3736	PVMSVGACMDBUF pCmdBuf = NULL;
3737
3738	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3739	AssertRC(rc);
3740
3741	/* It seems that a higher queue index has a higher priority.
3742	* See SVGACBContext in svga_reg.h from latest vmwgfx Linux driver.
3743	*/
3744	for (unsigned i = RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs); i > 0; --i)
3745	{
3746	PVMSVGACMDBUFCTX pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[i - 1];
3747	if (pCmdBufCtx)
3748	{
3749	pCmdBuf = RTListRemoveFirst(&pCmdBufCtx->listSubmitted, VMSVGACMDBUF, nodeBuffer);
3750	if (pCmdBuf)
3751	{
3752	Assert(pCmdBufCtx->cSubmitted > 0);
3753	--pCmdBufCtx->cSubmitted;
3754	break;
3755	}
3756	}
3757	}
3758
3759	if (!pCmdBuf)
3760	{
3761	ASMAtomicWriteU32(&pSvgaR3State->fCmdBuf, 0);
3762	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3763	break;
3764	}
3765
3766	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3767
3768	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3769	uint32_t offNextCmd = 0;
3770	uint32_t u32IrqStatus = 0;
3771
3772	/* Process one buffer. */
3773	CBstatus = vmsvgaR3CmdBufProcessCommands(pDevIns, pThis, pThisCC, pCmdBuf->pvCommands, pCmdBuf->hdr.length, &offNextCmd, &u32IrqStatus);
3774
3775	if (!RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_NO_IRQ))
3776	u32IrqStatus \|= SVGA_IRQFLAG_COMMAND_BUFFER;
3777	if (CBstatus == SVGA_CB_STATUS_COMMAND_ERROR)
3778	u32IrqStatus \|= SVGA_IRQFLAG_ERROR;
3779
3780	vmsvgaR3CmdBufWriteStatus(pDevIns, pCmdBuf->GCPhysCB, CBstatus, offNextCmd);
3781	if (u32IrqStatus)
3782	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, u32IrqStatus);
3783
3784	vmsvgaR3CmdBufFree(pCmdBuf);
3785	}
3786	}
3787
3788
3789	/**
3790	* Worker for vmsvgaR3FifoThread that handles an external command.
3791	*
3792	* @param pDevIns The device instance.
3793	* @param pThis The shared VGA/VMSVGA instance data.
3794	* @param pThisCC The VGA/VMSVGA state for ring-3.
3795	*/
3796	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3797	{
3798	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
3799	switch (pThis->svga.u8FIFOExtCommand)
3800	{
3801	case VMSVGA_FIFO_EXTCMD_RESET:
3802	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
3803	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3804
3805	vmsvgaR3ResetScreens(pThis, pThisCC);
3806	# ifdef VBOX_WITH_VMSVGA3D
3807	if (pThis->svga.f3DEnabled)
3808	{
3809	/* The 3d subsystem must be reset from the fifo thread. */
3810	vmsvga3dReset(pThisCC);
3811	}
3812	# endif
3813	break;
3814
3815	case VMSVGA_FIFO_EXTCMD_POWEROFF:
3816	Log(("vmsvgaR3FifoLoop: power off.\n"));
3817	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3818
3819	/* The screens must be reset on the FIFO thread, because they may use 3D resources. */
3820	vmsvgaR3ResetScreens(pThis, pThisCC);
3821	break;
3822
3823	case VMSVGA_FIFO_EXTCMD_TERMINATE:
3824	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
3825	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3826	# ifdef VBOX_WITH_VMSVGA3D
3827	if (pThis->svga.f3DEnabled)
3828	{
3829	/* The 3d subsystem must be shut down from the fifo thread. */
3830	vmsvga3dTerminate(pThisCC);
3831	}
3832	# endif
3833	break;
3834
3835	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
3836	{
3837	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
3838	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
3839	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
3840	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
3841	# ifdef VBOX_WITH_VMSVGA3D
3842	if (pThis->svga.f3DEnabled)
3843	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
3844	# endif
3845	break;
3846	}
3847
3848	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
3849	{
3850	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
3851	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
3852	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
3853	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3854	# ifdef VBOX_WITH_VMSVGA3D
3855	if (pThis->svga.f3DEnabled)
3856	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3857	# endif
3858	break;
3859	}
3860
3861	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
3862	{
3863	# ifdef VBOX_WITH_VMSVGA3D
3864	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
3865	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
3866	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
3867	# endif
3868	break;
3869	}
3870
3871
3872	default:
3873	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
3874	break;
3875	}
3876
3877	/*
3878	* Signal the end of the external command.
3879	*/
3880	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3881	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
3882	ASMMemoryFence(); /* paranoia^2 */
3883	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
3884	AssertLogRelRC(rc);
3885	}
3886
3887	/**
3888	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
3889	* doing a job on the FIFO thread (even when it's officially suspended).
3890	*
3891	* @returns VBox status code (fully asserted).
3892	* @param pDevIns The device instance.
3893	* @param pThis The shared VGA/VMSVGA instance data.
3894	* @param pThisCC The VGA/VMSVGA state for ring-3.
3895	* @param uExtCmd The command to execute on the FIFO thread.
3896	* @param pvParam Pointer to command parameters.
3897	* @param cMsWait The time to wait for the command, given in
3898	* milliseconds.
3899	*/
3900	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
3901	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
3902	{
3903	Assert(cMsWait >= RT_MS_1SEC * 5);
3904	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
3905	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
3906
3907	int rc;
3908	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
3909	PDMTHREADSTATE enmState = pThread->enmState;
3910	if (enmState == PDMTHREADSTATE_SUSPENDED)
3911	{
3912	/*
3913	* The thread is suspended, we have to temporarily wake it up so it can
3914	* perform the task.
3915	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
3916	*/
3917	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
3918	/* Post the request. */
3919	pThis->svga.fFifoExtCommandWakeup = true;
3920	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3921	pThis->svga.u8FIFOExtCommand = uExtCmd;
3922	ASMMemoryFence(); /* paranoia^3 */
3923
3924	/* Resume the thread. */
3925	rc = PDMDevHlpThreadResume(pDevIns, pThread);
3926	AssertLogRelRC(rc);
3927	if (RT_SUCCESS(rc))
3928	{
3929	/* Wait. Take care in case the semaphore was already posted (same as below). */
3930	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3931	if ( rc == VINF_SUCCESS
3932	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3933	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3934	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3935	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3936
3937	/* suspend the thread */
3938	pThis->svga.fFifoExtCommandWakeup = false;
3939	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
3940	AssertLogRelRC(rc2);
3941	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3942	rc = rc2;
3943	}
3944	pThis->svga.fFifoExtCommandWakeup = false;
3945	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3946	}
3947	else if (enmState == PDMTHREADSTATE_RUNNING)
3948	{
3949	/*
3950	* The thread is running, should only happen during reset and vmsvga3dsfc.
3951	* We ASSUME not racing code here, both wrt thread state and ext commands.
3952	*/
3953	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3954	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_POWEROFF);
3955
3956	/* Post the request. */
3957	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3958	pThis->svga.u8FIFOExtCommand = uExtCmd;
3959	ASMMemoryFence(); /* paranoia^2 */
3960	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3961	AssertLogRelRC(rc);
3962
3963	/* Wait. Take care in case the semaphore was already posted (same as above). */
3964	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3965	if ( rc == VINF_SUCCESS
3966	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3967	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3968	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3969	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3970
3971	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3972	}
3973	else
3974	{
3975	/*
3976	* Something is wrong with the thread!
3977	*/
3978	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3979	rc = VERR_INVALID_STATE;
3980	}
3981	return rc;
3982	}
3983
3984
3985	/**
3986	* Marks the FIFO non-busy, notifying any waiting EMTs.
3987	*
3988	* @param pDevIns The device instance.
3989	* @param pThis The shared VGA/VMSVGA instance data.
3990	* @param pThisCC The VGA/VMSVGA state for ring-3.
3991	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3992	* @param offFifoMin The start byte offset of the command FIFO.
3993	*/
3994	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3995	{
3996	ASMAtomicAndU32(&pThis->svga.fBusy, ~(VMSVGA_BUSY_F_FIFO \| VMSVGA_BUSY_F_EMT_FORCE));
3997	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3998	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
3999
4000	/* Wake up any waiting EMTs. */
4001	if (pSVGAState->cBusyDelayedEmts > 0)
4002	{
4003	# ifdef VMSVGA_USE_EMT_HALT_CODE
4004	PVM pVM = PDMDevHlpGetVM(pDevIns);
4005	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
4006	if (idCpu != NIL_VMCPUID)
4007	{
4008	VMR3NotifyCpuDeviceReady(pVM, idCpu);
4009	while (idCpu-- > 0)
4010	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
4011	VMR3NotifyCpuDeviceReady(pVM, idCpu);
4012	}
4013	# else
4014	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
4015	AssertRC(rc2);
4016	# endif
4017	}
4018	}
4019
4020	/**
4021	* Reads (more) payload into the command buffer.
4022	*
4023	* @returns pbBounceBuf on success
4024	* @retval (void *)1 if the thread was requested to stop.
4025	* @retval NULL on FIFO error.
4026	*
4027	* @param cbPayloadReq The number of bytes of payload requested.
4028	* @param pFIFO The FIFO.
4029	* @param offCurrentCmd The FIFO byte offset of the current command.
4030	* @param offFifoMin The start byte offset of the command FIFO.
4031	* @param offFifoMax The end byte offset of the command FIFO.
4032	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
4033	* always sufficient size.
4034	* @param pcbAlreadyRead How much payload we've already read into the bounce
4035	* buffer. (We will NEVER re-read anything.)
4036	* @param pThread The calling PDM thread handle.
4037	* @param pThis The shared VGA/VMSVGA instance data.
4038	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
4039	* statistics collection.
4040	* @param pDevIns The device instance.
4041	*/
4042	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
4043	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
4044	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
4045	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
4046	{
4047	Assert(pbBounceBuf);
4048	Assert(pcbAlreadyRead);
4049	Assert(offFifoMin < offFifoMax);
4050	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
4051	Assert(offFifoMax <= pThis->svga.cbFIFO);
4052
4053	/*
4054	* Check if the requested payload size has already been satisfied .
4055	* .
4056	* When called to read more, the caller is responsible for making sure the .
4057	* new command size (cbRequsted) never is smaller than what has already .
4058	* been read.
4059	*/
4060	uint32_t cbAlreadyRead = *pcbAlreadyRead;
4061	if (cbPayloadReq <= cbAlreadyRead)
4062	{
4063	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
4064	return pbBounceBuf;
4065	}
4066
4067	/*
4068	* Commands bigger than the fifo buffer are invalid.
4069	*/
4070	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
4071	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
4072	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
4073	NULL);
4074
4075	/*
4076	* Move offCurrentCmd past the command dword.
4077	*/
4078	offCurrentCmd += sizeof(uint32_t);
4079	if (offCurrentCmd >= offFifoMax)
4080	offCurrentCmd = offFifoMin;
4081
4082	/*
4083	* Do we have sufficient payload data available already?
4084	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
4085	*/
4086	uint32_t cbAfter, cbBefore;
4087	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4088	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4089	if (offNextCmd >= offCurrentCmd)
4090	{
4091	if (RT_LIKELY(offNextCmd < offFifoMax))
4092	cbAfter = offNextCmd - offCurrentCmd;
4093	else
4094	{
4095	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4096	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4097	offNextCmd, offFifoMin, offFifoMax));
4098	cbAfter = offFifoMax - offCurrentCmd;
4099	}
4100	cbBefore = 0;
4101	}
4102	else
4103	{
4104	cbAfter = offFifoMax - offCurrentCmd;
4105	if (offNextCmd >= offFifoMin)
4106	cbBefore = offNextCmd - offFifoMin;
4107	else
4108	{
4109	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4110	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4111	offNextCmd, offFifoMin, offFifoMax));
4112	cbBefore = 0;
4113	}
4114	}
4115	if (cbAfter + cbBefore < cbPayloadReq)
4116	{
4117	/*
4118	* Insufficient, must wait for it to arrive.
4119	*/
4120	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
4121	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
4122	for (uint32_t i = 0;; i++)
4123	{
4124	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4125	{
4126	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4127	return (void *)(uintptr_t)1;
4128	}
4129	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
4130	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
4131
4132	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
4133
4134	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4135	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4136	if (offNextCmd >= offCurrentCmd)
4137	{
4138	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
4139	cbBefore = 0;
4140	}
4141	else
4142	{
4143	cbAfter = offFifoMax - offCurrentCmd;
4144	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
4145	}
4146
4147	if (cbAfter + cbBefore >= cbPayloadReq)
4148	break;
4149	}
4150	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4151	}
4152
4153	/*
4154	* Copy out the memory and update what pcbAlreadyRead points to.
4155	*/
4156	if (cbAfter >= cbPayloadReq)
4157	memcpy(pbBounceBuf + cbAlreadyRead,
4158	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4159	cbPayloadReq - cbAlreadyRead);
4160	else
4161	{
4162	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
4163	if (cbAlreadyRead < cbAfter)
4164	{
4165	memcpy(pbBounceBuf + cbAlreadyRead,
4166	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4167	cbAfter - cbAlreadyRead);
4168	cbAlreadyRead = cbAfter;
4169	}
4170	memcpy(pbBounceBuf + cbAlreadyRead,
4171	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
4172	cbPayloadReq - cbAlreadyRead);
4173	}
4174	*pcbAlreadyRead = cbPayloadReq;
4175	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4176	return pbBounceBuf;
4177	}
4178
4179
4180	/**
4181	* Sends cursor position and visibility information from the FIFO to the front-end.
4182	* @returns SVGA_FIFO_CURSOR_COUNT value used.
4183	*/
4184	static uint32_t
4185	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
4186	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
4187	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
4188	{
4189	/*
4190	* Check if the cursor update counter has changed and try get a stable
4191	* set of values if it has. This is race-prone, especially consindering
4192	* the screen ID, but little we can do about that.
4193	*/
4194	uint32_t x, y, fVisible, idScreen;
4195	for (uint32_t i = 0; ; i++)
4196	{
4197	x = pFIFO[SVGA_FIFO_CURSOR_X];
4198	y = pFIFO[SVGA_FIFO_CURSOR_Y];
4199	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
4200	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
4201	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
4202	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
4203	\|\| i > 3)
4204	break;
4205	if (i == 0)
4206	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
4207	ASMNopPause();
4208	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4209	}
4210
4211	/*
4212	* Check if anything has changed, as calling into pDrv is not light-weight.
4213	*/
4214	if ( *pxLast == x
4215	&& *pyLast == y
4216	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
4217	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
4218	else
4219	{
4220	/*
4221	* Detected changes.
4222	*
4223	* We handle global, not per-screen visibility information by sending
4224	* pfnVBVAMousePointerShape without shape data.
4225	*/
4226	*pxLast = x;
4227	*pyLast = y;
4228	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
4229	if (idScreen != SVGA_ID_INVALID)
4230	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
4231	else if (*pfLastVisible != fVisible)
4232	{
4233	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
4234	*pfLastVisible = fVisible;
4235	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
4236	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
4237	}
4238	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
4239	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
4240	}
4241
4242	/*
4243	* Update done. Signal this to the guest.
4244	*/
4245	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
4246
4247	return uCursorUpdateCount;
4248	}
4249
4250
4251	/**
4252	* Checks if there is work to be done, either cursor updating or FIFO commands.
4253	*
4254	* @returns true if pending work, false if not.
4255	* @param pThisCC The VGA/VMSVGA state for ring-3.
4256	* @param uLastCursorCount The last cursor update counter value.
4257	*/
4258	DECLINLINE(bool) vmsvgaR3FifoHasWork(PVGASTATECC pThisCC, uint32_t uLastCursorCount)
4259	{
4260	/* If FIFO does not exist than there is nothing to do. Command buffers also require the enabled FIFO. */
4261	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4262	AssertReturn(pFIFO, false);
4263
4264	if (vmsvgaR3CmdBufHasWork(pThisCC))
4265	return true;
4266
4267	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
4268	return true;
4269
4270	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
4271	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
4272	return true;
4273
4274	return false;
4275	}
4276
4277
4278	/**
4279	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
4280	*
4281	* @param pDevIns The device instance.
4282	* @param pThis The shared VGA/VMSVGA instance data.
4283	* @param pThisCC The VGA/VMSVGA state for ring-3.
4284	*/
4285	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4286	{
4287	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
4288	to recheck it before doing the signalling. */
4289	if ( vmsvgaR3FifoHasWork(pThisCC, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
4290	&& pThis->svga.fFIFOThreadSleeping
4291	&& !ASMAtomicReadBool(&pThis->svga.fBadGuest))
4292	{
4293	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4294	AssertRC(rc);
4295	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
4296	}
4297	}
4298
4299
4300	/**
4301	* Called by the FIFO thread to process pending actions.
4302	*
4303	* @param pDevIns The device instance.
4304	* @param pThis The shared VGA/VMSVGA instance data.
4305	* @param pThisCC The VGA/VMSVGA state for ring-3.
4306	*/
4307	void vmsvgaR3FifoPendingActions(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4308	{
4309	RT_NOREF(pDevIns);
4310
4311	/* Currently just mode changes. */
4312	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
4313	{
4314	vmsvgaR3ChangeMode(pThis, pThisCC);
4315	# ifdef VBOX_WITH_VMSVGA3D
4316	if (pThisCC->svga.p3dState != NULL)
4317	vmsvga3dChangeMode(pThisCC);
4318	# endif
4319	}
4320	}
4321
4322
4323	/*
4324	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
4325	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
4326	*/
4327	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
4328	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
4329	*
4330	* Will break out of the switch on failure.
4331	* Will restart and quit the loop if the thread was requested to stop.
4332	*
4333	* @param a_PtrVar Request variable pointer.
4334	* @param a_Type Request typedef (not pointer) for casting.
4335	* @param a_cbPayloadReq How much payload to fetch.
4336	* @remarks Accesses a bunch of variables in the current scope!
4337	*/
4338	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4339	if (1) { \
4340	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
4341	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
4342	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
4343	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
4344	} else do {} while (0)
4345	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
4346	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
4347	* buffer after figuring out the actual command size.
4348	*
4349	* Will break out of the switch on failure.
4350	*
4351	* @param a_PtrVar Request variable pointer.
4352	* @param a_Type Request typedef (not pointer) for casting.
4353	* @param a_cbPayloadReq How much payload to fetch.
4354	* @remarks Accesses a bunch of variables in the current scope!
4355	*/
4356	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4357	if (1) { \
4358	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
4359	} else do {} while (0)
4360
4361	/**
4362	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
4363	*/
4364	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4365	{
4366	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4367	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
4368	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4369	int rc;
4370
4371	# if defined(VBOX_WITH_VMSVGA3D) && defined(RT_OS_LINUX)
4372	if (pThis->svga.f3DEnabled)
4373	{
4374	/* The FIFO thread may use X API for accelerated screen output. */
4375	XInitThreads();
4376	}
4377	# endif
4378
4379	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
4380	return VINF_SUCCESS;
4381
4382	/*
4383	* Special mode where we only execute an external command and the go back
4384	* to being suspended. Currently, all ext cmds ends up here, with the reset
4385	* one also being eligble for runtime execution further down as well.
4386	*/
4387	if (pThis->svga.fFifoExtCommandWakeup)
4388	{
4389	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4390	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4391	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
4392	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
4393	else
4394	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4395	return VINF_SUCCESS;
4396	}
4397
4398
4399	/*
4400	* Signal the semaphore to make sure we don't wait for 250ms after a
4401	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
4402	*/
4403	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4404
4405	/*
4406	* Allocate a bounce buffer for command we get from the FIFO.
4407	* (All code must return via the end of the function to free this buffer.)
4408	*/
4409	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
4410	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
4411
4412	/*
4413	* Polling/sleep interval config.
4414	*
4415	* We wait for an a short interval if the guest has recently given us work
4416	* to do, but the interval increases the longer we're kept idle. Once we've
4417	* reached the refresh timer interval, we'll switch to extended waits,
4418	* depending on it or the guest to kick us into action when needed.
4419	*
4420	* Should the refresh time go fishing, we'll just continue increasing the
4421	* sleep length till we reaches the 250 ms max after about 16 seconds.
4422	*/
4423	RTMSINTERVAL const cMsMinSleep = 16;
4424	RTMSINTERVAL const cMsIncSleep = 2;
4425	RTMSINTERVAL const cMsMaxSleep = 250;
4426	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
4427	RTMSINTERVAL cMsSleep = cMsMaxSleep;
4428
4429	/*
4430	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
4431	*
4432	* Initialize with values that will detect an update from the guest.
4433	* Make sure that if the guest never updates the cursor position, then the device does not report it.
4434	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
4435	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
4436	*/
4437	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4438	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4439	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
4440	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
4441	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
4442
4443	/*
4444	* The FIFO loop.
4445	*/
4446	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
4447	bool fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4448	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4449	{
4450	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
4451	/*
4452	* Should service the run loop every so often.
4453	*/
4454	if (pThis->svga.f3DEnabled)
4455	vmsvga3dCocoaServiceRunLoop();
4456	# endif
4457
4458	/* First check any pending actions. */
4459	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
4460
4461	/*
4462	* Unless there's already work pending, go to sleep for a short while.
4463	* (See polling/sleep interval config above.)
4464	*/
4465	if ( fBadOrDisabledFifo
4466	\|\| !vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4467	{
4468	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
4469	Assert(pThis->cMilliesRefreshInterval > 0);
4470	if (cMsSleep < pThis->cMilliesRefreshInterval)
4471	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
4472	else
4473	{
4474	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
4475	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
4476	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
4477	# endif
4478	if ( !fBadOrDisabledFifo
4479	&& vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4480	rc = VINF_SUCCESS;
4481	else
4482	{
4483	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
4484	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
4485	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
4486	}
4487	}
4488	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
4489	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
4490	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4491	{
4492	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
4493	break;
4494	}
4495	}
4496	else
4497	rc = VINF_SUCCESS;
4498	fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4499	if (rc == VERR_TIMEOUT)
4500	{
4501	if (!vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4502	{
4503	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
4504	continue;
4505	}
4506	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
4507
4508	Log(("vmsvgaR3FifoLoop: timeout\n"));
4509	}
4510	else if (vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4511	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
4512	cMsSleep = cMsMinSleep;
4513
4514	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
4515	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
4516	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
4517
4518	/*
4519	* Handle external commands (currently only reset).
4520	*/
4521	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
4522	{
4523	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4524	continue;
4525	}
4526
4527	/*
4528	* If guest misbehaves, then do nothing.
4529	*/
4530	if (ASMAtomicReadBool(&pThis->svga.fBadGuest))
4531	{
4532	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4533	cMsSleep = cMsExtendedSleep;
4534	LogRelMax(1, ("VMSVGA: FIFO processing stopped because of the guest misbehavior\n"));
4535	continue;
4536	}
4537
4538	/*
4539	* The device must be enabled and configured.
4540	*/
4541	if ( !pThis->svga.fEnabled
4542	\|\| !pThis->svga.fConfigured)
4543	{
4544	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4545	fBadOrDisabledFifo = true;
4546	cMsSleep = cMsMaxSleep; /* cheat */
4547	continue;
4548	}
4549
4550	/*
4551	* Get and check the min/max values. We ASSUME that they will remain
4552	* unchanged while we process requests. A further ASSUMPTION is that
4553	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
4554	* we don't read it back while in the loop.
4555	*/
4556	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
4557	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
4558	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
4559	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4560	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
4561	\|\| offFifoMax <= offFifoMin
4562	\|\| offFifoMax > pThis->svga.cbFIFO
4563	\|\| (offFifoMax & 3) != 0
4564	\|\| (offFifoMin & 3) != 0
4565	\|\| offCurrentCmd < offFifoMin
4566	\|\| offCurrentCmd > offFifoMax))
4567	{
4568	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4569	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
4570	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
4571	fBadOrDisabledFifo = true;
4572	continue;
4573	}
4574	RT_UNTRUSTED_VALIDATED_FENCE();
4575	if (RT_UNLIKELY(offCurrentCmd & 3))
4576	{
4577	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4578	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
4579	offCurrentCmd &= ~UINT32_C(3);
4580	}
4581
4582	/*
4583	* Update the cursor position before we start on the FIFO commands.
4584	*/
4585	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
4586	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
4587	{
4588	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4589	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
4590	{ /* halfways likely */ }
4591	else
4592	{
4593	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
4594	&xLastCursor, &yLastCursor, &fLastCursorVisible);
4595	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
4596	}
4597	}
4598
4599	/*
4600	* Mark the FIFO as busy.
4601	*/
4602	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO); // Clears VMSVGA_BUSY_F_EMT_FORCE!
4603	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
4604	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
4605
4606	/*
4607	* Process all submitted command buffers.
4608	*/
4609	vmsvgaR3CmdBufProcessBuffers(pDevIns, pThis, pThisCC, pThread);
4610
4611	/*
4612	* Execute all queued FIFO commands.
4613	* Quit if pending external command or changes in the thread state.
4614	*/
4615	bool fDone = false;
4616	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
4617	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
4618	{
4619	uint32_t cbPayload = 0;
4620	uint32_t u32IrqStatus = 0;
4621
4622	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
4623
4624	/* First check any pending actions. */
4625	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
4626
4627	/* Check for pending external commands (reset). */
4628	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
4629	break;
4630
4631	/*
4632	* Process the command.
4633	*/
4634	/* 'enmCmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
4635	* warning. Because we implement some obsolete and deprecated commands, which are not included in
4636	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
4637	*/
4638	uint32_t const enmCmdId = pFIFO[offCurrentCmd / sizeof(uint32_t)];
4639	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4640	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s %d\n",
4641	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
4642	switch (enmCmdId)
4643	{
4644	case SVGA_CMD_INVALID_CMD:
4645	/* Nothing to do. */
4646	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
4647	break;
4648
4649	case SVGA_CMD_FENCE:
4650	{
4651	SVGAFifoCmdFence *pCmdFence;
4652	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
4653	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
4654	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
4655	{
4656	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %#x\n", pCmdFence->fence));
4657	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
4658
4659	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
4660	{
4661	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
4662	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
4663	}
4664	else
4665	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
4666	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
4667	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
4668	{
4669	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%#x)\n", pCmdFence->fence));
4670	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
4671	}
4672	}
4673	else
4674	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
4675	break;
4676	}
4677
4678	case SVGA_CMD_UPDATE:
4679	{
4680	SVGAFifoCmdUpdate *pCmd;
4681	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdate, sizeof(*pCmd));
4682	vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
4683	break;
4684	}
4685
4686	case SVGA_CMD_UPDATE_VERBOSE:
4687	{
4688	SVGAFifoCmdUpdateVerbose *pCmd;
4689	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdateVerbose, sizeof(*pCmd));
4690	vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
4691	break;
4692	}
4693
4694	case SVGA_CMD_DEFINE_CURSOR:
4695	{
4696	/* Followed by bitmap data. */
4697	SVGAFifoCmdDefineCursor *pCmd;
4698	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, sizeof(*pCmd));
4699
4700	/* Figure out the size of the bitmap data. */
4701	ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
4702	ASSERT_GUEST_BREAK(pCmd->andMaskDepth <= 32);
4703	ASSERT_GUEST_BREAK(pCmd->xorMaskDepth <= 32);
4704	RT_UNTRUSTED_VALIDATED_FENCE();
4705
4706	uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
4707	uint32_t const cbAndMask = cbAndLine * pCmd->height;
4708	uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
4709	uint32_t const cbXorMask = cbXorLine * pCmd->height;
4710
4711	uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineCursor) + cbAndMask + cbXorMask;
4712	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, cbCmd);
4713	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
4714	break;
4715	}
4716
4717	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
4718	{
4719	/* Followed by bitmap data. */
4720	SVGAFifoCmdDefineAlphaCursor *pCmd;
4721	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCmd));
4722
4723	/* Figure out the size of the bitmap data. */
4724	ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
4725
4726	uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCmd->width * pCmd->height * sizeof(uint32_t) /* 32-bit BRGA format */;
4727	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, cbCmd);
4728	vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
4729	break;
4730	}
4731
4732	case SVGA_CMD_MOVE_CURSOR:
4733	{
4734	/* Deprecated; there should be no driver which requires this command. However, if
4735	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4736	* alignment.
4737	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4738	*/
4739	SVGAFifoCmdMoveCursor *pCmd;
4740	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdMoveCursor, sizeof(*pCmd));
4741	vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
4742	break;
4743	}
4744
4745	case SVGA_CMD_DISPLAY_CURSOR:
4746	{
4747	/* Deprecated; there should be no driver which requires this command. However, if
4748	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4749	* alignment.
4750	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4751	*/
4752	SVGAFifoCmdDisplayCursor *pCmd;
4753	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDisplayCursor, sizeof(*pCmd));
4754	vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
4755	break;
4756	}
4757
4758	case SVGA_CMD_RECT_FILL:
4759	{
4760	SVGAFifoCmdRectFill *pCmd;
4761	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectFill, sizeof(*pCmd));
4762	vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
4763	break;
4764	}
4765
4766	case SVGA_CMD_RECT_COPY:
4767	{
4768	SVGAFifoCmdRectCopy *pCmd;
4769	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectCopy, sizeof(*pCmd));
4770	vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
4771	break;
4772	}
4773
4774	case SVGA_CMD_RECT_ROP_COPY:
4775	{
4776	SVGAFifoCmdRectRopCopy *pCmd;
4777	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectRopCopy, sizeof(*pCmd));
4778	vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
4779	break;
4780	}
4781
4782	case SVGA_CMD_ESCAPE:
4783	{
4784	/* Followed by 'size' bytes of data. */
4785	SVGAFifoCmdEscape *pCmd;
4786	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, sizeof(*pCmd));
4787
4788	ASSERT_GUEST_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape));
4789	RT_UNTRUSTED_VALIDATED_FENCE();
4790
4791	uint32_t const cbCmd = sizeof(SVGAFifoCmdEscape) + pCmd->size;
4792	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, cbCmd);
4793	vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
4794	break;
4795	}
4796	# ifdef VBOX_WITH_VMSVGA3D
4797	case SVGA_CMD_DEFINE_GMR2:
4798	{
4799	SVGAFifoCmdDefineGMR2 *pCmd;
4800	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
4801	vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
4802	break;
4803	}
4804
4805	case SVGA_CMD_REMAP_GMR2:
4806	{
4807	/* Followed by page descriptors or guest ptr. */
4808	SVGAFifoCmdRemapGMR2 *pCmd;
4809	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
4810
4811	/* Calculate the size of what comes after next and fetch it. */
4812	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
4813	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4814	cbCmd += sizeof(SVGAGuestPtr);
4815	else
4816	{
4817	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
4818	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
4819	{
4820	cbCmd += cbPageDesc;
4821	pCmd->numPages = 1;
4822	}
4823	else
4824	{
4825	ASSERT_GUEST_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
4826	cbCmd += cbPageDesc * pCmd->numPages;
4827	}
4828	}
4829	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
4830	vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
4831	# ifdef DEBUG_GMR_ACCESS
4832	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
4833	# endif
4834	break;
4835	}
4836	# endif // VBOX_WITH_VMSVGA3D
4837	case SVGA_CMD_DEFINE_SCREEN:
4838	{
4839	/* The size of this command is specified by the guest and depends on capabilities. */
4840	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4841
4842	SVGAFifoCmdDefineScreen *pCmd;
4843	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4844	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4845	RT_UNTRUSTED_VALIDATED_FENCE();
4846
4847	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4848	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4849	vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
4850	break;
4851	}
4852
4853	case SVGA_CMD_DESTROY_SCREEN:
4854	{
4855	SVGAFifoCmdDestroyScreen *pCmd;
4856	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4857	vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
4858	break;
4859	}
4860
4861	case SVGA_CMD_DEFINE_GMRFB:
4862	{
4863	SVGAFifoCmdDefineGMRFB *pCmd;
4864	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4865	vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
4866	break;
4867	}
4868
4869	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4870	{
4871	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4872	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4873	vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
4874	break;
4875	}
4876
4877	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4878	{
4879	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4880	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4881	vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
4882	break;
4883	}
4884
4885	case SVGA_CMD_ANNOTATION_FILL:
4886	{
4887	SVGAFifoCmdAnnotationFill *pCmd;
4888	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4889	vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
4890	break;
4891	}
4892
4893	case SVGA_CMD_ANNOTATION_COPY:
4894	{
4895	SVGAFifoCmdAnnotationCopy *pCmd;
4896	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4897	vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
4898	break;
4899	}
4900
4901	default:
4902	# ifdef VBOX_WITH_VMSVGA3D
4903	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4904	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4905	{
4906	RT_UNTRUSTED_VALIDATED_FENCE();
4907
4908	/* All 3d commands start with a common header, which defines the identifier and the size
4909	* of the command. The identifier has been already read from FIFO. Fetch the size.
4910	*/
4911	uint32_t *pcbCmd;
4912	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pcbCmd, uint32_t, sizeof(*pcbCmd));
4913	uint32_t const cbCmd = *pcbCmd;
4914	AssertBreak(cbCmd < pThis->svga.cbFIFO);
4915	uint32_t *pu32Cmd;
4916	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pu32Cmd, uint32_t, sizeof(*pcbCmd) + cbCmd);
4917	pu32Cmd++; /* Skip the command size. */
4918
4919	if (RT_LIKELY(pThis->svga.f3DEnabled))
4920	{ /* likely */ }
4921	else
4922	{
4923	LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", enmCmdId));
4924	break;
4925	}
4926
4927	vmsvgaR3Process3dCmd(pThis, pThisCC, (SVGAFifo3dCmdId)enmCmdId, cbCmd, pu32Cmd);
4928	}
4929	else
4930	# endif // VBOX_WITH_VMSVGA3D
4931	{
4932	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4933	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4934	}
4935	}
4936
4937	/* Go to the next slot */
4938	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4939	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4940	if (offCurrentCmd >= offFifoMax)
4941	{
4942	offCurrentCmd -= offFifoMax - offFifoMin;
4943	Assert(offCurrentCmd >= offFifoMin);
4944	Assert(offCurrentCmd < offFifoMax);
4945	}
4946	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4947	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4948
4949	/*
4950	* Raise IRQ if required. Must enter the critical section here
4951	* before making final decisions here, otherwise cubebench and
4952	* others may end up waiting forever.
4953	*/
4954	if ( u32IrqStatus
4955	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4956	{
4957	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
4958	AssertRC(rc2);
4959
4960	/* FIFO progress might trigger an interrupt. */
4961	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4962	{
4963	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
4964	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4965	}
4966
4967	/* Unmasked IRQ pending? */
4968	if (pThis->svga.u32IrqMask & u32IrqStatus)
4969	{
4970	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4971	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4972	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4973	}
4974
4975	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4976	}
4977	}
4978
4979	/* If really done, clear the busy flag. */
4980	if (fDone)
4981	{
4982	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4983	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
4984	}
4985	}
4986
4987	/*
4988	* Free the bounce buffer. (There are no returns above!)
4989	*/
4990	RTMemFree(pbBounceBuf);
4991
4992	return VINF_SUCCESS;
4993	}
4994
4995	#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
4996	#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
4997
4998	/**
4999	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5000	* Unblock the FIFO I/O thread so it can respond to a state change.}
5001	*/
5002	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5003	{
5004	RT_NOREF(pDevIns);
5005	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5006	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5007	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5008	}
5009
5010	/**
5011	* Enables or disables dirty page tracking for the framebuffer
5012	*
5013	* @param pDevIns The device instance.
5014	* @param pThis The shared VGA/VMSVGA instance data.
5015	* @param fTraces Enable/disable traces
5016	*/
5017	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
5018	{
5019	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5020	&& !fTraces)
5021	{
5022	//Assert(pThis->svga.fTraces);
5023	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5024	return;
5025	}
5026
5027	pThis->svga.fTraces = fTraces;
5028	if (pThis->svga.fTraces)
5029	{
5030	unsigned cbFrameBuffer = pThis->vram_size;
5031
5032	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5033	/** @todo How does this work with screens? */
5034	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5035	{
5036	# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5037	Assert(pThis->svga.cbScanline);
5038	# endif
5039	/* Hardware enabled; return real framebuffer size .*/
5040	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5041	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5042	}
5043
5044	if (!pThis->svga.fVRAMTracking)
5045	{
5046	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5047	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
5048	pThis->svga.fVRAMTracking = true;
5049	}
5050	}
5051	else
5052	{
5053	if (pThis->svga.fVRAMTracking)
5054	{
5055	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5056	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5057	pThis->svga.fVRAMTracking = false;
5058	}
5059	}
5060	}
5061
5062	/**
5063	* @callback_method_impl{FNPCIIOREGIONMAP}
5064	*/
5065	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5066	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5067	{
5068	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5069	int rc;
5070	RT_NOREF(pPciDev);
5071	Assert(pPciDev == pDevIns->apPciDevs[0]);
5072
5073	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5074	AssertReturn( iRegion == pThis->pciRegions.iFIFO
5075	&& ( enmType == PCI_ADDRESS_SPACE_MEM
5076	\|\| (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
5077	, VERR_INTERNAL_ERROR);
5078	if (GCPhysAddress != NIL_RTGCPHYS)
5079	{
5080	/*
5081	* Mapping the FIFO RAM.
5082	*/
5083	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5084	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5085	AssertRC(rc);
5086
5087	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5088	if (RT_SUCCESS(rc))
5089	{
5090	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5091	# ifdef DEBUG_FIFO_ACCESS
5092	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5093	# else
5094	GCPhysAddress + PAGE_SIZE - 1,
5095	# endif
5096	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5097	"VMSVGA FIFO");
5098	AssertRC(rc);
5099	}
5100	# endif
5101	if (RT_SUCCESS(rc))
5102	{
5103	pThis->svga.GCPhysFIFO = GCPhysAddress;
5104	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5105	}
5106	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite errors here. */
5107	}
5108	else
5109	{
5110	Assert(pThis->svga.GCPhysFIFO);
5111	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5112	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5113	AssertRC(rc);
5114	# else
5115	rc = VINF_SUCCESS;
5116	# endif
5117	pThis->svga.GCPhysFIFO = 0;
5118	}
5119	return rc;
5120	}
5121
5122	# ifdef VBOX_WITH_VMSVGA3D
5123
5124	/**
5125	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5126	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5127	*
5128	* @param pDevIns The device instance.
5129	* @param pThis The The shared VGA/VMSVGA instance data.
5130	* @param pThisCC The VGA/VMSVGA state for ring-3.
5131	* @param sid Either UINT32_MAX or the ID of a specific surface. If
5132	* UINT32_MAX is used, all surfaces are processed.
5133	*/
5134	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
5135	{
5136	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5137	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5138	}
5139
5140
5141	/**
5142	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5143	*/
5144	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5145	{
5146	/* There might be a specific surface ID at the start of the
5147	arguments, if not show all surfaces. */
5148	uint32_t sid = UINT32_MAX;
5149	if (pszArgs)
5150	pszArgs = RTStrStripL(pszArgs);
5151	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5152	sid = RTStrToUInt32(pszArgs);
5153
5154	/* Verbose or terse display, we default to verbose. */
5155	bool fVerbose = true;
5156	if (RTStrIStr(pszArgs, "terse"))
5157	fVerbose = false;
5158
5159	/* The size of the ascii art (x direction, y is 3/4 of x). */
5160	uint32_t cxAscii = 80;
5161	if (RTStrIStr(pszArgs, "gigantic"))
5162	cxAscii = 300;
5163	else if (RTStrIStr(pszArgs, "huge"))
5164	cxAscii = 180;
5165	else if (RTStrIStr(pszArgs, "big"))
5166	cxAscii = 132;
5167	else if (RTStrIStr(pszArgs, "normal"))
5168	cxAscii = 80;
5169	else if (RTStrIStr(pszArgs, "medium"))
5170	cxAscii = 64;
5171	else if (RTStrIStr(pszArgs, "small"))
5172	cxAscii = 48;
5173	else if (RTStrIStr(pszArgs, "tiny"))
5174	cxAscii = 24;
5175
5176	/* Y invert the image when producing the ASCII art. */
5177	bool fInvY = false;
5178	if (RTStrIStr(pszArgs, "invy"))
5179	fInvY = true;
5180
5181	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5182	pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5183	}
5184
5185
5186	/**
5187	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5188	*/
5189	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5190	{
5191	/* pszArg = "sid[>dir]"
5192	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5193	*/
5194	char *pszBitmapPath = NULL;
5195	uint32_t sid = UINT32_MAX;
5196	if (pszArgs)
5197	pszArgs = RTStrStripL(pszArgs);
5198	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5199	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5200	if ( pszBitmapPath
5201	&& *pszBitmapPath == '>')
5202	++pszBitmapPath;
5203
5204	const bool fVerbose = true;
5205	const uint32_t cxAscii = 0; /* No ASCII */
5206	const bool fInvY = false; /* Do not invert. */
5207	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5208	pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5209	}
5210
5211	/**
5212	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5213	*/
5214	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5215	{
5216	/* There might be a specific surface ID at the start of the
5217	arguments, if not show all contexts. */
5218	uint32_t sid = UINT32_MAX;
5219	if (pszArgs)
5220	pszArgs = RTStrStripL(pszArgs);
5221	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5222	sid = RTStrToUInt32(pszArgs);
5223
5224	/* Verbose or terse display, we default to verbose. */
5225	bool fVerbose = true;
5226	if (RTStrIStr(pszArgs, "terse"))
5227	fVerbose = false;
5228
5229	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
5230	}
5231	# endif /* VBOX_WITH_VMSVGA3D */
5232
5233	/**
5234	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5235	*/
5236	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5237	{
5238	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5239	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5240	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5241	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
5242	RT_NOREF(pszArgs);
5243
5244	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5245	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5246	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5247	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5248	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5249	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5250	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5251	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5252	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5253	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5254	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5255	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5256	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5257	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5258	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5259	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5260	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5261	pHlp->pfnPrintf(pHlp, "Device Capabilites: %#x\n", pThis->svga.u32DeviceCaps);
5262	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5263	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5264	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5265	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5266	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5267	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5268	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5269
5270	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5271	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5272	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5273	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5274
5275	pHlp->pfnPrintf(pHlp, "FIFO cursor: state %u, screen %d\n", pFIFO[SVGA_FIFO_CURSOR_ON], pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID]);
5276	pHlp->pfnPrintf(pHlp, "FIFO cursor at: %u,%u\n", pFIFO[SVGA_FIFO_CURSOR_X], pFIFO[SVGA_FIFO_CURSOR_Y]);
5277
5278	pHlp->pfnPrintf(pHlp, "Legacy cursor: ID %u, state %u\n", pThis->svga.uCursorID, pThis->svga.uCursorOn);
5279	pHlp->pfnPrintf(pHlp, "Legacy cursor at: %u,%u\n", pThis->svga.uCursorX, pThis->svga.uCursorY);
5280
5281	# ifdef VBOX_WITH_VMSVGA3D
5282	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5283	# endif
5284	if (pThisCC->pDrv)
5285	{
5286	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
5287	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
5288	}
5289
5290	/* Dump screen information. */
5291	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
5292	{
5293	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, iScreen);
5294	if (pScreen)
5295	{
5296	pHlp->pfnPrintf(pHlp, "Screen %u defined (ID %u):\n", iScreen, pScreen->idScreen);
5297	pHlp->pfnPrintf(pHlp, " %u x %u x %ubpp @ %u, %u\n", pScreen->cWidth, pScreen->cHeight,
5298	pScreen->cBpp, pScreen->xOrigin, pScreen->yOrigin);
5299	pHlp->pfnPrintf(pHlp, " Pitch %u bytes, VRAM offset %X\n", pScreen->cbPitch, pScreen->offVRAM);
5300	pHlp->pfnPrintf(pHlp, " Flags %X", pScreen->fuScreen);
5301	if (pScreen->fuScreen != SVGA_SCREEN_MUST_BE_SET)
5302	{
5303	pHlp->pfnPrintf(pHlp, " (");
5304	if (pScreen->fuScreen & SVGA_SCREEN_IS_PRIMARY)
5305	pHlp->pfnPrintf(pHlp, " IS_PRIMARY");
5306	if (pScreen->fuScreen & SVGA_SCREEN_FULLSCREEN_HINT)
5307	pHlp->pfnPrintf(pHlp, " FULLSCREEN_HINT");
5308	if (pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE)
5309	pHlp->pfnPrintf(pHlp, " DEACTIVATE");
5310	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
5311	pHlp->pfnPrintf(pHlp, " BLANKING");
5312	pHlp->pfnPrintf(pHlp, " )");
5313	}
5314	pHlp->pfnPrintf(pHlp, ", %smodified\n", pScreen->fModified ? "" : "not ");
5315	}
5316	}
5317
5318	}
5319
5320	/**
5321	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
5322	*/
5323	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
5324	PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5325	{
5326	RT_NOREF(uPass);
5327
5328	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5329	int rc;
5330
5331	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5332	{
5333	uint32_t cScreens = 0;
5334	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5335	AssertRCReturn(rc, rc);
5336	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5337	("cScreens=%#x\n", cScreens),
5338	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5339
5340	for (uint32_t i = 0; i < cScreens; ++i)
5341	{
5342	VMSVGASCREENOBJECT screen;
5343	RT_ZERO(screen);
5344
5345	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5346	AssertLogRelRCReturn(rc, rc);
5347
5348	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5349	{
5350	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5351	*pScreen = screen;
5352	pScreen->fModified = true;
5353	}
5354	else
5355	{
5356	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5357	}
5358	}
5359	}
5360	else
5361	{
5362	/* Try to setup at least the first screen. */
5363	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5364	pScreen->fDefined = true;
5365	pScreen->fModified = true;
5366	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5367	pScreen->idScreen = 0;
5368	pScreen->xOrigin = 0;
5369	pScreen->yOrigin = 0;
5370	pScreen->offVRAM = pThis->svga.uScreenOffset;
5371	pScreen->cbPitch = pThis->svga.cbScanline;
5372	pScreen->cWidth = pThis->svga.uWidth;
5373	pScreen->cHeight = pThis->svga.uHeight;
5374	pScreen->cBpp = pThis->svga.uBpp;
5375	}
5376
5377	return VINF_SUCCESS;
5378	}
5379
5380	/**
5381	* @copydoc FNSSMDEVLOADEXEC
5382	*/
5383	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5384	{
5385	RT_NOREF(uPass);
5386	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5387	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5388	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5389	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5390	int rc;
5391
5392	/* Load our part of the VGAState */
5393	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5394	AssertRCReturn(rc, rc);
5395
5396	/* Load the VGA framebuffer. */
5397	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5398	uint32_t cbVgaFramebuffer = _32K;
5399	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5400	{
5401	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5402	AssertRCReturn(rc, rc);
5403	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5404	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5405	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5406	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5407	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5408	}
5409	rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5410	AssertRCReturn(rc, rc);
5411	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5412	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5413	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5414	RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5415
5416	/* Load the VMSVGA state. */
5417	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5418	AssertRCReturn(rc, rc);
5419
5420	/* Load the active cursor bitmaps. */
5421	if (pSVGAState->Cursor.fActive)
5422	{
5423	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5424	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5425
5426	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5427	AssertRCReturn(rc, rc);
5428	}
5429
5430	/* Load the GMR state. */
5431	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5432	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5433	{
5434	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5435	AssertRCReturn(rc, rc);
5436	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5437	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5438	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5439	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5440	}
5441
5442	if (pThis->svga.cGMR != cGMR)
5443	{
5444	/* Reallocate GMR array. */
5445	Assert(pSVGAState->paGMR != NULL);
5446	RTMemFree(pSVGAState->paGMR);
5447	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5448	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5449	pThis->svga.cGMR = cGMR;
5450	}
5451
5452	for (uint32_t i = 0; i < cGMR; ++i)
5453	{
5454	PGMR pGMR = &pSVGAState->paGMR[i];
5455
5456	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5457	AssertRCReturn(rc, rc);
5458
5459	if (pGMR->numDescriptors)
5460	{
5461	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5462	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5463	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5464
5465	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5466	{
5467	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5468	AssertRCReturn(rc, rc);
5469	}
5470	}
5471	}
5472
5473	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5474	vmsvga3dPowerOn(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC));
5475	# endif
5476
5477	VMSVGA_STATE_LOAD LoadState;
5478	LoadState.pSSM = pSSM;
5479	LoadState.uVersion = uVersion;
5480	LoadState.uPass = uPass;
5481	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5482	AssertLogRelRCReturn(rc, rc);
5483
5484	return VINF_SUCCESS;
5485	}
5486
5487	/**
5488	* Reinit the video mode after the state has been loaded.
5489	*/
5490	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
5491	{
5492	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5493	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5494	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5495
5496	/* Set the active cursor. */
5497	if (pSVGAState->Cursor.fActive)
5498	{
5499	/* We don't store the alpha flag, but we can take a guess that if
5500	* the old register interface was used, the cursor was B&W.
5501	*/
5502	bool fAlpha = pThis->svga.uCursorOn ? false : true;
5503
5504	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
5505	true /fVisible/,
5506	fAlpha,
5507	pSVGAState->Cursor.xHotspot,
5508	pSVGAState->Cursor.yHotspot,
5509	pSVGAState->Cursor.width,
5510	pSVGAState->Cursor.height,
5511	pSVGAState->Cursor.pData);
5512	AssertRC(rc);
5513
5514	if (pThis->svga.uCursorOn)
5515	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, VBVA_CURSOR_VALID_DATA, SVGA_ID_INVALID, pThis->svga.uCursorX, pThis->svga.uCursorY);
5516	}
5517
5518	/* If the VRAM handler should not be registered, we have to explicitly
5519	* unregister it here!
5520	*/
5521	if (!pThis->svga.fVRAMTracking)
5522	{
5523	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5524	}
5525
5526	/* Let the FIFO thread deal with changing the mode. */
5527	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5528
5529	return VINF_SUCCESS;
5530	}
5531
5532	/**
5533	* Portion of SVGA state which must be saved in the FIFO thread.
5534	*/
5535	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
5536	{
5537	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5538	int rc;
5539
5540	/* Save the screen objects. */
5541	/* Count defined screen object. */
5542	uint32_t cScreens = 0;
5543	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5544	{
5545	if (pSVGAState->aScreens[i].fDefined)
5546	++cScreens;
5547	}
5548
5549	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
5550	AssertLogRelRCReturn(rc, rc);
5551
5552	for (uint32_t i = 0; i < cScreens; ++i)
5553	{
5554	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5555
5556	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5557	AssertLogRelRCReturn(rc, rc);
5558	}
5559	return VINF_SUCCESS;
5560	}
5561
5562	/**
5563	* @copydoc FNSSMDEVSAVEEXEC
5564	*/
5565	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5566	{
5567	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5568	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5569	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5570	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5571	int rc;
5572
5573	/* Save our part of the VGAState */
5574	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5575	AssertLogRelRCReturn(rc, rc);
5576
5577	/* Save the framebuffer backup. */
5578	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5579	rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5580	AssertLogRelRCReturn(rc, rc);
5581
5582	/* Save the VMSVGA state. */
5583	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5584	AssertLogRelRCReturn(rc, rc);
5585
5586	/* Save the active cursor bitmaps. */
5587	if (pSVGAState->Cursor.fActive)
5588	{
5589	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5590	AssertLogRelRCReturn(rc, rc);
5591	}
5592
5593	/* Save the GMR state */
5594	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
5595	AssertLogRelRCReturn(rc, rc);
5596	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5597	{
5598	PGMR pGMR = &pSVGAState->paGMR[i];
5599
5600	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5601	AssertLogRelRCReturn(rc, rc);
5602
5603	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5604	{
5605	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5606	AssertLogRelRCReturn(rc, rc);
5607	}
5608	}
5609
5610	/*
5611	* Must save some state (3D in particular) in the FIFO thread.
5612	*/
5613	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5614	AssertLogRelRCReturn(rc, rc);
5615
5616	return VINF_SUCCESS;
5617	}
5618
5619	/**
5620	* Destructor for PVMSVGAR3STATE structure.
5621	*
5622	* @param pThis The shared VGA/VMSVGA instance data.
5623	* @param pSVGAState Pointer to the structure. It is not deallocated.
5624	*/
5625	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5626	{
5627	# ifndef VMSVGA_USE_EMT_HALT_CODE
5628	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5629	{
5630	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5631	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5632	}
5633	# endif
5634
5635	if (pSVGAState->Cursor.fActive)
5636	{
5637	RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5638	pSVGAState->Cursor.pData = NULL;
5639	pSVGAState->Cursor.fActive = false;
5640	}
5641
5642	if (pSVGAState->paGMR)
5643	{
5644	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5645	if (pSVGAState->paGMR[i].paDesc)
5646	RTMemFree(pSVGAState->paGMR[i].paDesc);
5647
5648	RTMemFree(pSVGAState->paGMR);
5649	pSVGAState->paGMR = NULL;
5650	}
5651
5652	if (RTCritSectIsInitialized(&pSVGAState->CritSectCmdBuf))
5653	{
5654	RTCritSectEnter(&pSVGAState->CritSectCmdBuf);
5655	for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->apCmdBufCtxs); ++i)
5656	{
5657	vmsvgaR3CmdBufCtxTerm(pSVGAState->apCmdBufCtxs[i]);
5658	pSVGAState->apCmdBufCtxs[i] = NULL;
5659	}
5660	vmsvgaR3CmdBufCtxTerm(&pSVGAState->CmdBufCtxDC);
5661	RTCritSectLeave(&pSVGAState->CritSectCmdBuf);
5662	RTCritSectDelete(&pSVGAState->CritSectCmdBuf);
5663	}
5664	}
5665
5666	/**
5667	* Constructor for PVMSVGAR3STATE structure.
5668	*
5669	* @returns VBox status code.
5670	* @param pDevIns The PDM device instance.
5671	* @param pThis The shared VGA/VMSVGA instance data.
5672	* @param pSVGAState Pointer to the structure. It is already allocated.
5673	*/
5674	static int vmsvgaR3StateInit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5675	{
5676	int rc = VINF_SUCCESS;
5677	RT_ZERO(*pSVGAState);
5678	pSVGAState->pDevIns = pDevIns;
5679
5680	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5681	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5682
5683	# ifndef VMSVGA_USE_EMT_HALT_CODE
5684	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5685	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5686	AssertRCReturn(rc, rc);
5687	# endif
5688
5689	rc = RTCritSectInit(&pSVGAState->CritSectCmdBuf);
5690	AssertRCReturn(rc, rc);
5691
5692	vmsvgaR3CmdBufCtxInit(&pSVGAState->CmdBufCtxDC);
5693
5694	RTListInit(&pSVGAState->MOBLRUList);
5695	return rc;
5696	}
5697
5698	/**
5699	* Initializes the host capabilities: device and FIFO.
5700	*
5701	* @returns VBox status code.
5702	* @param pThis The shared VGA/VMSVGA instance data.
5703	* @param pThisCC The VGA/VMSVGA state for ring-3.
5704	*/
5705	static void vmsvgaR3InitCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
5706	{
5707	/* Device caps. */
5708	pThis->svga.u32DeviceCaps = SVGA_CAP_GMR
5709	\| SVGA_CAP_GMR2
5710	\| SVGA_CAP_CURSOR
5711	\| SVGA_CAP_CURSOR_BYPASS
5712	\| SVGA_CAP_CURSOR_BYPASS_2
5713	\| SVGA_CAP_EXTENDED_FIFO
5714	\| SVGA_CAP_IRQMASK
5715	\| SVGA_CAP_PITCHLOCK
5716	\| SVGA_CAP_RECT_COPY
5717	\| SVGA_CAP_TRACES
5718	\| SVGA_CAP_SCREEN_OBJECT_2
5719	\| SVGA_CAP_ALPHA_CURSOR;
5720
5721	/* VGPU10 capabilities. */
5722	if (pThis->fVMSVGA10)
5723	{
5724	pThis->svga.u32DeviceCaps \|= SVGA_CAP_COMMAND_BUFFERS /* Enable register based command buffer submission. */
5725	// \| SVGA_CAP_CMD_BUFFERS_2 /* Support for SVGA_REG_CMD_PREPEND_LOW/HIGH */
5726	// \| SVGA_CAP_GBOBJECTS /* Enable guest-backed objects and surfaces. */
5727	// \| SVGA_CAP_CMD_BUFFERS_3 /* AKA SVGA_CAP_DX. Enable support for DX commands, and command buffers in a mob. */
5728	;
5729	}
5730
5731	# ifdef VBOX_WITH_VMSVGA3D
5732	pThis->svga.u32DeviceCaps \|= SVGA_CAP_3D;
5733	# endif
5734
5735	/* Clear the FIFO. */
5736	RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
5737
5738	/* Setup FIFO capabilities. */
5739	pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
5740	\| SVGA_FIFO_CAP_PITCHLOCK
5741	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
5742	\| SVGA_FIFO_CAP_RESERVE
5743	\| SVGA_FIFO_CAP_GMR2
5744	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
5745	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
5746
5747	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5748	pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5749	}
5750
5751	# ifdef VBOX_WITH_VMSVGA3D
5752	/**
5753	* Initializes the host 3D capabilities and writes them to FIFO memory.
5754	*
5755	* @returns VBox status code.
5756	* @param pThis The shared VGA/VMSVGA instance data.
5757	* @param pThisCC The VGA/VMSVGA state for ring-3.
5758	*/
5759	static void vmsvgaR3InitFifo3DCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
5760	{
5761	/* Query the capabilities and store them in the pThis->svga.au32DevCaps array. */
5762	bool const fSavedBuffering = RTLogRelSetBuffering(true);
5763
5764	for (unsigned i = 0; i < RT_ELEMENTS(pThis->svga.au32DevCaps); ++i)
5765	{
5766	uint32_t val = 0;
5767	int rc = vmsvga3dQueryCaps(pThisCC, (SVGA3dDevCapIndex)i, &val);
5768	if (RT_SUCCESS(rc))
5769	pThis->svga.au32DevCaps[i] = val;
5770	else
5771	pThis->svga.au32DevCaps[i] = 0;
5772
5773	/* LogRel the capability value. */
5774	if (i < SVGA3D_DEVCAP_MAX)
5775	{
5776	char const *pszDevCapName = &vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)i)[sizeof("SVGA3D_DEVCAP")];
5777	if (RT_SUCCESS(rc))
5778	{
5779	if ( i == SVGA3D_DEVCAP_MAX_POINT_SIZE
5780	\|\| i == SVGA3D_DEVCAP_MAX_LINE_WIDTH
5781	\|\| i == SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH)
5782	{
5783	float const fval = (float )&val;
5784	LogRel(("VMSVGA3d: cap[%u]=" FLOAT_FMT_STR " {%s}\n", i, FLOAT_FMT_ARGS(fval), pszDevCapName));
5785	}
5786	else
5787	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, pszDevCapName));
5788	}
5789	else
5790	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc {%s}\n", i, rc, pszDevCapName));
5791	}
5792	else
5793	LogRel(("VMSVGA3d: new cap[%u]=%#010x rc=%Rrc\n", i, val, rc));
5794	}
5795
5796	RTLogRelSetBuffering(fSavedBuffering);
5797
5798	/* 3d hardware version; latest and greatest */
5799	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
5800	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
5801
5802	/* Fill out 3d capabilities up to SVGA3D_DEVCAP_SURFACEFMT_ATI2 in the FIFO memory.
5803	* SVGA3D_DEVCAP_SURFACEFMT_ATI2 is the last capabiltiy for pre-SVGA_CAP_GBOBJECTS hardware.
5804	* If the VMSVGA device supports SVGA_CAP_GBOBJECTS capability, then the guest has to use SVGA_REG_DEV_CAP
5805	* register to query the devcaps. Older guests will still try to read the devcaps from FIFO.
5806	*/
5807	SVGA3dCapsRecord *pCaps;
5808	SVGA3dCapPair *pData;
5809
5810	pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
5811	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
5812	pData = (SVGA3dCapPair *)&pCaps->data;
5813
5814	AssertCompile(SVGA3D_DEVCAP_DEAD1 == SVGA3D_DEVCAP_SURFACEFMT_ATI2 + 1);
5815	for (unsigned i = 0; i < SVGA3D_DEVCAP_DEAD1; ++i)
5816	{
5817	pData[i][0] = i;
5818	pData[i][1] = pThis->svga.au32DevCaps[i];
5819	}
5820	pCaps->header.length = (sizeof(pCaps->header) + SVGA3D_DEVCAP_DEAD1 * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
5821	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
5822
5823	/* Mark end of record array (a zero word). */
5824	pCaps->header.length = 0;
5825	}
5826
5827	# endif
5828
5829	/**
5830	* Resets the SVGA hardware state
5831	*
5832	* @returns VBox status code.
5833	* @param pDevIns The device instance.
5834	*/
5835	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
5836	{
5837	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5838	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5839	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5840
5841	/* Reset before init? */
5842	if (!pSVGAState)
5843	return VINF_SUCCESS;
5844
5845	Log(("vmsvgaR3Reset\n"));
5846
5847	/* Reset the FIFO processing as well as the 3d state (if we have one). */
5848	pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
5849	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
5850
5851	/* Reset other stuff. */
5852	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
5853	RT_ZERO(pThis->svga.au32ScratchRegion);
5854
5855	ASMAtomicWriteBool(&pThis->svga.fBadGuest, false);
5856
5857	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
5858	vmsvgaR3StateInit(pDevIns, pThis, pThisCC->svga.pSvgaR3State);
5859
5860	RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5861
5862	/* Initialize FIFO and register capabilities. */
5863	vmsvgaR3InitCaps(pThis, pThisCC);
5864
5865	# ifdef VBOX_WITH_VMSVGA3D
5866	if (pThis->svga.f3DEnabled)
5867	vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
5868	# endif
5869
5870	/* VRAM tracking is enabled by default during bootup. */
5871	pThis->svga.fVRAMTracking = true;
5872	pThis->svga.fEnabled = false;
5873
5874	/* Invalidate current settings. */
5875	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
5876	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
5877	pThis->svga.uBpp = pThis->svga.uHostBpp;
5878	pThis->svga.cbScanline = 0;
5879	pThis->svga.u32PitchLock = 0;
5880
5881	return rc;
5882	}
5883
5884	/**
5885	* Cleans up the SVGA hardware state
5886	*
5887	* @returns VBox status code.
5888	* @param pDevIns The device instance.
5889	*/
5890	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
5891	{
5892	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5893	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5894
5895	/*
5896	* Ask the FIFO thread to terminate the 3d state and then terminate it.
5897	*/
5898	if (pThisCC->svga.pFIFOIOThread)
5899	{
5900	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
5901	NULL /pvParam/, 30000 /ms/);
5902	AssertLogRelRC(rc);
5903
5904	rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
5905	AssertLogRelRC(rc);
5906	pThisCC->svga.pFIFOIOThread = NULL;
5907	}
5908
5909	/*
5910	* Destroy the special SVGA state.
5911	*/
5912	if (pThisCC->svga.pSvgaR3State)
5913	{
5914	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
5915
5916	RTMemFree(pThisCC->svga.pSvgaR3State);
5917	pThisCC->svga.pSvgaR3State = NULL;
5918	}
5919
5920	/*
5921	* Free our resources residing in the VGA state.
5922	*/
5923	if (pThisCC->svga.pbVgaFrameBufferR3)
5924	{
5925	RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
5926	pThisCC->svga.pbVgaFrameBufferR3 = NULL;
5927	}
5928	if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
5929	{
5930	RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
5931	pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
5932	}
5933	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
5934	{
5935	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
5936	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
5937	}
5938
5939	return VINF_SUCCESS;
5940	}
5941
5942	/**
5943	* Initialize the SVGA hardware state
5944	*
5945	* @returns VBox status code.
5946	* @param pDevIns The device instance.
5947	*/
5948	int vmsvgaR3Init(PPDMDEVINS pDevIns)
5949	{
5950	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5951	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5952	PVMSVGAR3STATE pSVGAState;
5953	int rc;
5954
5955	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
5956	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
5957
5958	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
5959
5960	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
5961	pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
5962	AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
5963
5964	/* Create event semaphore. */
5965	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
5966	AssertRCReturn(rc, rc);
5967
5968	/* Create event semaphore. */
5969	rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
5970	AssertRCReturn(rc, rc);
5971
5972	pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAllocZ(sizeof(VMSVGAR3STATE));
5973	AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
5974
5975	rc = vmsvgaR3StateInit(pDevIns, pThis, pThisCC->svga.pSvgaR3State);
5976	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
5977
5978	pSVGAState = pThisCC->svga.pSvgaR3State;
5979
5980	/* Register the write-protected GBO access handler type. */
5981	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
5982	vmsvgaR3GboAccessHandler,
5983	NULL, NULL, NULL,
5984	NULL, NULL, NULL,
5985	"VMSVGA GBO", &pSVGAState->hGboAccessHandlerType);
5986	AssertRCReturn(rc, rc);
5987
5988	/* Initialize FIFO and register capabilities. */
5989	vmsvgaR3InitCaps(pThis, pThisCC);
5990
5991	# ifdef VBOX_WITH_VMSVGA3D
5992	if (pThis->svga.f3DEnabled)
5993	{
5994	rc = vmsvga3dInit(pDevIns, pThis, pThisCC);
5995	if (RT_FAILURE(rc))
5996	{
5997	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
5998	pThis->svga.f3DEnabled = false;
5999	}
6000	}
6001	# endif
6002	/* VRAM tracking is enabled by default during bootup. */
6003	pThis->svga.fVRAMTracking = true;
6004
6005	/* Set up the host bpp. This value is as a default for the programmable
6006	* bpp value. On old implementations, SVGA_REG_HOST_BITS_PER_PIXEL did not
6007	* exist and SVGA_REG_BITS_PER_PIXEL was read-only, returning what was later
6008	* separated as SVGA_REG_HOST_BITS_PER_PIXEL.
6009	*
6010	* NB: The driver cBits value is currently constant for the lifetime of the
6011	* VM. If that changes, the host bpp logic might need revisiting.
6012	*/
6013	pThis->svga.uHostBpp = (pThisCC->pDrv->cBits + 7) & ~7;
6014
6015	/* Invalidate current settings. */
6016	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6017	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6018	pThis->svga.uBpp = pThis->svga.uHostBpp;
6019	pThis->svga.cbScanline = 0;
6020
6021	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6022	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6023	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6024	{
6025	pThis->svga.u32MaxWidth -= 256;
6026	pThis->svga.u32MaxHeight -= 256;
6027	}
6028	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6029
6030	# ifdef DEBUG_GMR_ACCESS
6031	/* Register the GMR access handler type. */
6032	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
6033	vmsvgaR3GmrAccessHandler,
6034	NULL, NULL, NULL,
6035	NULL, NULL, NULL,
6036	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6037	AssertRCReturn(rc, rc);
6038	# endif
6039
6040	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6041	/* Register the FIFO access handler type. In addition to
6042	debugging FIFO access, this is also used to facilitate
6043	extended fifo thread sleeps. */
6044	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns),
6045	# ifdef DEBUG_FIFO_ACCESS
6046	PGMPHYSHANDLERKIND_ALL,
6047	# else
6048	PGMPHYSHANDLERKIND_WRITE,
6049	# endif
6050	vmsvgaR3FifoAccessHandler,
6051	NULL, NULL, NULL,
6052	NULL, NULL, NULL,
6053	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6054	AssertRCReturn(rc, rc);
6055	# endif
6056
6057	/* Create the async IO thread. */
6058	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
6059	RTTHREADTYPE_IO, "VMSVGA FIFO");
6060	if (RT_FAILURE(rc))
6061	{
6062	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6063	return rc;
6064	}
6065
6066	/*
6067	* Statistics.
6068	*/
6069	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6070	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6071	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6072	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6073	# ifdef VBOX_WITH_STATISTICS
6074	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6075	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6076	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6077	# endif
6078	REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
6079	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6080	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6081	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6082	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6083	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6084	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6085	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6086	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6087	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6088	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6089	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6090	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6091	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6092	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6093	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6094	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6095	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6096	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6097	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6098	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6099	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6100	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6101	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6102	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6103	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6104	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6105	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6106	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6107	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6108	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6109	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6110	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6111	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6112	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6113	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6114	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6115	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6116	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6117	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6118	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6119	REG_CNT(&pSVGAState->StatR3CmdMoveCursor, "VMSVGA/Cmd/MoveCursor", "SVGA_CMD_MOVE_CURSOR");
6120	REG_CNT(&pSVGAState->StatR3CmdDisplayCursor, "VMSVGA/Cmd/DisplayCursor", "SVGA_CMD_DISPLAY_CURSOR");
6121	REG_CNT(&pSVGAState->StatR3CmdRectFill, "VMSVGA/Cmd/RectFill", "SVGA_CMD_RECT_FILL");
6122	REG_CNT(&pSVGAState->StatR3CmdRectCopy, "VMSVGA/Cmd/RectCopy", "SVGA_CMD_RECT_COPY");
6123	REG_CNT(&pSVGAState->StatR3CmdRectRopCopy, "VMSVGA/Cmd/RectRopCopy", "SVGA_CMD_RECT_ROP_COPY");
6124	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6125	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6126	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6127	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6128	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6129	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6130	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6131	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6132	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6133	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6134	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6135	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6136	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6137
6138	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6139	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6140	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6141	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6142	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6143	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6144	REG_CNT(&pThis->svga.StatRegCursorXWr, "VMSVGA/Reg/CursorXWrite", "SVGA_REG_CURSOR_X writes.");
6145	REG_CNT(&pThis->svga.StatRegCursorYWr, "VMSVGA/Reg/CursorYWrite", "SVGA_REG_CURSOR_Y writes.");
6146	REG_CNT(&pThis->svga.StatRegCursorIdWr, "VMSVGA/Reg/CursorIdWrite", "SVGA_REG_CURSOR_ID writes.");
6147	REG_CNT(&pThis->svga.StatRegCursorOnWr, "VMSVGA/Reg/CursorOnWrite", "SVGA_REG_CURSOR_ON writes.");
6148	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6149	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6150	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6151	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6152	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6153	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6154	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6155	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6156	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6157	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6158	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6159	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6160	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6161	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6162	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6163	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6164	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6165	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6166	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6167	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6168	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6169	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6170	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6171	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6172	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6173	REG_CNT(&pThis->svga.StatRegCommandLowWr, "VMSVGA/Reg/CommandLowWrite", "SVGA_REG_COMMAND_LOW writes.");
6174	REG_CNT(&pThis->svga.StatRegCommandHighWr, "VMSVGA/Reg/CommandHighWrite", "SVGA_REG_COMMAND_HIGH writes.");
6175	REG_CNT(&pThis->svga.StatRegDevCapWr, "VMSVGA/Reg/DevCapWrite", "SVGA_REG_DEV_CAP writes.");
6176	REG_CNT(&pThis->svga.StatRegCmdPrependLowWr, "VMSVGA/Reg/CmdPrependLowWrite", "SVGA_REG_CMD_PREPEND_LOW writes.");
6177	REG_CNT(&pThis->svga.StatRegCmdPrependHighWr, "VMSVGA/Reg/CmdPrependHighWrite", "SVGA_REG_iCMD_PREPEND_HIGH writes.");
6178
6179	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6180	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6181	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6182	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6183	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6184	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6185	REG_CNT(&pThis->svga.StatRegCursorXRd, "VMSVGA/Reg/CursorXRead", "SVGA_REG_CURSOR_X reads.");
6186	REG_CNT(&pThis->svga.StatRegCursorYRd, "VMSVGA/Reg/CursorYRead", "SVGA_REG_CURSOR_Y reads.");
6187	REG_CNT(&pThis->svga.StatRegCursorIdRd, "VMSVGA/Reg/CursorIdRead", "SVGA_REG_CURSOR_ID reads.");
6188	REG_CNT(&pThis->svga.StatRegCursorOnRd, "VMSVGA/Reg/CursorOnRead", "SVGA_REG_CURSOR_ON reads.");
6189	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6190	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6191	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6192	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6193	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6194	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6195	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6196	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6197	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6198	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6199	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6200	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6201	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6202	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6203	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6204	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6205	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6206	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6207	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6208	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6209	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6210	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6211	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6212	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6213	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6214	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6215	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6216	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6217	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6218	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6219	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6220	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6221	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6222	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6223	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6224	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6225	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6226	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6227	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6228	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6229	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6230	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6231	REG_CNT(&pThis->svga.StatRegCommandLowRd, "VMSVGA/Reg/CommandLowRead", "SVGA_REG_COMMAND_LOW reads.");
6232	REG_CNT(&pThis->svga.StatRegCommandHighRd, "VMSVGA/Reg/CommandHighRead", "SVGA_REG_COMMAND_HIGH reads.");
6233	REG_CNT(&pThis->svga.StatRegMaxPrimBBMemRd, "VMSVGA/Reg/MaxPrimBBMemRead", "SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM reads.");
6234	REG_CNT(&pThis->svga.StatRegGBMemSizeRd, "VMSVGA/Reg/GBMemSizeRead", "SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB reads.");
6235	REG_CNT(&pThis->svga.StatRegDevCapRd, "VMSVGA/Reg/DevCapRead", "SVGA_REG_DEV_CAP reads.");
6236	REG_CNT(&pThis->svga.StatRegCmdPrependLowRd, "VMSVGA/Reg/CmdPrependLowRead", "SVGA_REG_CMD_PREPEND_LOW reads.");
6237	REG_CNT(&pThis->svga.StatRegCmdPrependHighRd, "VMSVGA/Reg/CmdPrependHighRead", "SVGA_REG_iCMD_PREPEND_HIGH reads.");
6238	REG_CNT(&pThis->svga.StatRegScrnTgtMaxWidthRd, "VMSVGA/Reg/ScrnTgtMaxWidthRead", "SVGA_REG_SCREENTARGET_MAX_WIDTH reads.");
6239	REG_CNT(&pThis->svga.StatRegScrnTgtMaxHeightRd, "VMSVGA/Reg/ScrnTgtMaxHeightRead", "SVGA_REG_SCREENTARGET_MAX_HEIGHT reads.");
6240	REG_CNT(&pThis->svga.StatRegMobMaxSizeRd, "VMSVGA/Reg/MobMaxSizeRead", "SVGA_REG_MOB_MAX_SIZE reads.");
6241
6242	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6243	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6244	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6245	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6246	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6247	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6248	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6249	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6250	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6251	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6252	# endif
6253	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6254	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6255	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6256	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6257	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6258
6259	# undef REG_CNT
6260	# undef REG_PRF
6261
6262	/*
6263	* Info handlers.
6264	*/
6265	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6266	# ifdef VBOX_WITH_VMSVGA3D
6267	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6268	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6269	"VMSVGA 3d surface details. "
6270	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6271	vmsvgaR3Info3dSurface);
6272	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6273	"VMSVGA 3d surface details and bitmap: "
6274	"sid[>dir]",
6275	vmsvgaR3Info3dSurfaceBmp);
6276	# endif
6277
6278	return VINF_SUCCESS;
6279	}
6280
6281	/**
6282	* Power On notification.
6283	*
6284	* @returns VBox status code.
6285	* @param pDevIns The device instance data.
6286	*
6287	* @remarks Caller enters the device critical section.
6288	*/
6289	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6290	{
6291	# ifdef VBOX_WITH_VMSVGA3D
6292	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6293	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6294	if (pThis->svga.f3DEnabled)
6295	{
6296	int rc = vmsvga3dPowerOn(pDevIns, pThis, pThisCC);
6297	if (RT_SUCCESS(rc))
6298	{
6299	/* Initialize FIFO 3D capabilities. */
6300	vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
6301	}
6302	}
6303	# else /* !VBOX_WITH_VMSVGA3D */
6304	RT_NOREF(pDevIns);
6305	# endif /* !VBOX_WITH_VMSVGA3D */
6306	}
6307
6308	/**
6309	* Power Off notification.
6310	*
6311	* @param pDevIns The device instance data.
6312	*
6313	* @remarks Caller enters the device critical section.
6314	*/
6315	DECLCALLBACK(void) vmsvgaR3PowerOff(PPDMDEVINS pDevIns)
6316	{
6317	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6318	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6319
6320	/*
6321	* Notify the FIFO thread.
6322	*/
6323	if (pThisCC->svga.pFIFOIOThread)
6324	{
6325	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_POWEROFF,
6326	NULL /pvParam/, 30000 /ms/);
6327	AssertLogRelRC(rc);
6328	}
6329	}
6330
6331	#endif /* IN_RING3 */

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 86864

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