DevVGA-SVGA.cpp@ 83278

Last change on this file since 83278 was 83278, checked in by vboxsync, 5 years ago
VMSVGA: The SVGA_REG_BITS_PER_PIXEL must be initialized to the host bpp value and can't contain an invalid value, since it used to be read-only. Fixes old X11 drivers.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 303.0 KB

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1	/* $Id: DevVGA-SVGA.cpp 83278 2020-03-13 11:43:47Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	* - LogRel for the usual important stuff.
13	* - LogRel2 for cursor.
14	* - LogRel3 for 3D performance data.
15	*/
16
17	/*
18	* Copyright (C) 2013-2020 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.215389.xyz. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29
30	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
31	*
32	* This device emulation was contributed by trivirt AG. It offers an
33	* alternative to our Bochs based VGA graphics and 3d emulations. This is
34	* valuable for Xorg based guests, as there is driver support shipping with Xorg
35	* since it forked from XFree86.
36	*
37	*
38	* @section sec_dev_vmsvga_sdk The VMware SDK
39	*
40	* This is officially deprecated now, however it's still quite useful,
41	* especially for getting the old features working:
42	* http://vmware-svga.sourceforge.net/
43	*
44	* They currently point developers at the following resources.
45	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
46	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
47	* - http://cgit.freedesktop.org/mesa/vmwgfx/
48	*
49	* @subsection subsec_dev_vmsvga_sdk_results Test results
50	*
51	* Test results:
52	* - 2dmark.img:
53	* + todo
54	* - backdoor-tclo.img:
55	* + todo
56	* - blit-cube.img:
57	* + todo
58	* - bunnies.img:
59	* + todo
60	* - cube.img:
61	* + todo
62	* - cubemark.img:
63	* + todo
64	* - dynamic-vertex-stress.img:
65	* + todo
66	* - dynamic-vertex.img:
67	* + todo
68	* - fence-stress.img:
69	* + todo
70	* - gmr-test.img:
71	* + todo
72	* - half-float-test.img:
73	* + todo
74	* - noscreen-cursor.img:
75	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
76	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
77	* visible though.)
78	* - Cursor animation via the palette doesn't work.
79	* - During debugging, it turns out that the framebuffer content seems to
80	* be halfways ignore or something (memset(fb, 0xcc, lots)).
81	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
82	* grow it 0x10 fold (128KB -> 2MB like in WS10).
83	* - null.img:
84	* + todo
85	* - pong.img:
86	* + todo
87	* - presentReadback.img:
88	* + todo
89	* - resolution-set.img:
90	* + todo
91	* - rt-gamma-test.img:
92	* + todo
93	* - screen-annotation.img:
94	* + todo
95	* - screen-cursor.img:
96	* + todo
97	* - screen-dma-coalesce.img:
98	* + todo
99	* - screen-gmr-discontig.img:
100	* + todo
101	* - screen-gmr-remap.img:
102	* + todo
103	* - screen-multimon.img:
104	* + todo
105	* - screen-present-clip.img:
106	* + todo
107	* - screen-render-test.img:
108	* + todo
109	* - screen-simple.img:
110	* + todo
111	* - screen-text.img:
112	* + todo
113	* - simple-shaders.img:
114	* + todo
115	* - simple_blit.img:
116	* + todo
117	* - tiny-2d-updates.img:
118	* + todo
119	* - video-formats.img:
120	* + todo
121	* - video-sync.img:
122	* + todo
123	*
124	*/
125
126
127	/*********************************************************************************************************************************
128	* Header Files *
129	*********************************************************************************************************************************/
130	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
131	#define VMSVGA_USE_EMT_HALT_CODE
132	#include <VBox/vmm/pdmdev.h>
133	#include <VBox/version.h>
134	#include <VBox/err.h>
135	#include <VBox/log.h>
136	#include <VBox/vmm/pgm.h>
137	#ifdef VMSVGA_USE_EMT_HALT_CODE
138	# include <VBox/vmm/vmapi.h>
139	# include <VBox/vmm/vmcpuset.h>
140	#endif
141	#include <VBox/sup.h>
142
143	#include <iprt/assert.h>
144	#include <iprt/semaphore.h>
145	#include <iprt/uuid.h>
146	#ifdef IN_RING3
147	# include <iprt/ctype.h>
148	# include <iprt/mem.h>
149	# ifdef VBOX_STRICT
150	# include <iprt/time.h>
151	# endif
152	#endif
153
154	#include <VBox/AssertGuest.h>
155	#include <VBox/VMMDev.h>
156	#include <VBoxVideo.h>
157	#include <VBox/bioslogo.h>
158
159	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
160	#include "DevVGA.h"
161
162	#include "DevVGA-SVGA.h"
163	#include "vmsvga/svga_escape.h"
164	#include "vmsvga/svga_overlay.h"
165	#include "vmsvga/svga3d_caps.h"
166	#ifdef VBOX_WITH_VMSVGA3D
167	# include "DevVGA-SVGA3d.h"
168	# ifdef RT_OS_DARWIN
169	# include "DevVGA-SVGA3d-cocoa.h"
170	# endif
171	#endif
172
173
174	/*********************************************************************************************************************************
175	* Defined Constants And Macros *
176	*********************************************************************************************************************************/
177	/**
178	* Macro for checking if a fixed FIFO register is valid according to the
179	* current FIFO configuration.
180	*
181	* @returns true / false.
182	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
183	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
184	*/
185	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
186
187
188	/*********************************************************************************************************************************
189	* Structures and Typedefs *
190	*********************************************************************************************************************************/
191	/**
192	* 64-bit GMR descriptor.
193	*/
194	typedef struct
195	{
196	RTGCPHYS GCPhys;
197	uint64_t numPages;
198	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
199
200	/**
201	* GMR slot
202	*/
203	typedef struct
204	{
205	uint32_t cMaxPages;
206	uint32_t cbTotal;
207	uint32_t numDescriptors;
208	PVMSVGAGMRDESCRIPTOR paDesc;
209	} GMR, *PGMR;
210
211	#ifdef IN_RING3
212	/**
213	* Internal SVGA ring-3 only state.
214	*/
215	typedef struct VMSVGAR3STATE
216	{
217	GMR *paGMR; // [VMSVGAState::cGMR]
218	struct
219	{
220	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
221	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
222	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
223	} GMRFB;
224	struct
225	{
226	bool fActive;
227	uint32_t xHotspot;
228	uint32_t yHotspot;
229	uint32_t width;
230	uint32_t height;
231	uint32_t cbData;
232	void *pData;
233	} Cursor;
234	SVGAColorBGRX colorAnnotation;
235
236	# ifdef VMSVGA_USE_EMT_HALT_CODE
237	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
238	uint32_t volatile cBusyDelayedEmts;
239	/** Set of EMTs that are */
240	VMCPUSET BusyDelayedEmts;
241	# else
242	/** Number of EMTs waiting on hBusyDelayedEmts. */
243	uint32_t volatile cBusyDelayedEmts;
244	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
245	* busy (ugly). */
246	RTSEMEVENTMULTI hBusyDelayedEmts;
247	# endif
248
249	/** Information obout screens. */
250	VMSVGASCREENOBJECT aScreens[64];
251
252	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
253	STAMPROFILE StatBusyDelayEmts;
254
255	STAMPROFILE StatR3Cmd3dPresentProf;
256	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
257	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
258	STAMPROFILE StatR3Cmd3dBlitSurfaceToScreenProf;
259	STAMCOUNTER StatR3CmdDefineGmr2;
260	STAMCOUNTER StatR3CmdDefineGmr2Free;
261	STAMCOUNTER StatR3CmdDefineGmr2Modify;
262	STAMCOUNTER StatR3CmdRemapGmr2;
263	STAMCOUNTER StatR3CmdRemapGmr2Modify;
264	STAMCOUNTER StatR3CmdInvalidCmd;
265	STAMCOUNTER StatR3CmdFence;
266	STAMCOUNTER StatR3CmdUpdate;
267	STAMCOUNTER StatR3CmdUpdateVerbose;
268	STAMCOUNTER StatR3CmdDefineCursor;
269	STAMCOUNTER StatR3CmdDefineAlphaCursor;
270	STAMCOUNTER StatR3CmdMoveCursor;
271	STAMCOUNTER StatR3CmdDisplayCursor;
272	STAMCOUNTER StatR3CmdEscape;
273	STAMCOUNTER StatR3CmdDefineScreen;
274	STAMCOUNTER StatR3CmdDestroyScreen;
275	STAMCOUNTER StatR3CmdDefineGmrFb;
276	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
277	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
278	STAMCOUNTER StatR3CmdAnnotationFill;
279	STAMCOUNTER StatR3CmdAnnotationCopy;
280	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
281	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
282	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
283	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
284	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
285	STAMCOUNTER StatR3Cmd3dSurfaceDma;
286	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
287	STAMCOUNTER StatR3Cmd3dContextDefine;
288	STAMCOUNTER StatR3Cmd3dContextDestroy;
289	STAMCOUNTER StatR3Cmd3dSetTransform;
290	STAMCOUNTER StatR3Cmd3dSetZRange;
291	STAMCOUNTER StatR3Cmd3dSetRenderState;
292	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
293	STAMCOUNTER StatR3Cmd3dSetTextureState;
294	STAMCOUNTER StatR3Cmd3dSetMaterial;
295	STAMCOUNTER StatR3Cmd3dSetLightData;
296	STAMCOUNTER StatR3Cmd3dSetLightEnable;
297	STAMCOUNTER StatR3Cmd3dSetViewPort;
298	STAMCOUNTER StatR3Cmd3dSetClipPlane;
299	STAMCOUNTER StatR3Cmd3dClear;
300	STAMCOUNTER StatR3Cmd3dPresent;
301	STAMCOUNTER StatR3Cmd3dPresentReadBack;
302	STAMCOUNTER StatR3Cmd3dShaderDefine;
303	STAMCOUNTER StatR3Cmd3dShaderDestroy;
304	STAMCOUNTER StatR3Cmd3dSetShader;
305	STAMCOUNTER StatR3Cmd3dSetShaderConst;
306	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
307	STAMCOUNTER StatR3Cmd3dSetScissorRect;
308	STAMCOUNTER StatR3Cmd3dBeginQuery;
309	STAMCOUNTER StatR3Cmd3dEndQuery;
310	STAMCOUNTER StatR3Cmd3dWaitForQuery;
311	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
312	STAMCOUNTER StatR3Cmd3dActivateSurface;
313	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
314
315	STAMCOUNTER StatR3RegConfigDoneWr;
316	STAMCOUNTER StatR3RegGmrDescriptorWr;
317	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
318	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
319
320	STAMCOUNTER StatFifoCommands;
321	STAMCOUNTER StatFifoErrors;
322	STAMCOUNTER StatFifoUnkCmds;
323	STAMCOUNTER StatFifoTodoTimeout;
324	STAMCOUNTER StatFifoTodoWoken;
325	STAMPROFILE StatFifoStalls;
326	STAMPROFILE StatFifoExtendedSleep;
327	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
328	STAMCOUNTER StatFifoAccessHandler;
329	# endif
330	STAMCOUNTER StatFifoCursorFetchAgain;
331	STAMCOUNTER StatFifoCursorNoChange;
332	STAMCOUNTER StatFifoCursorPosition;
333	STAMCOUNTER StatFifoCursorVisiblity;
334	STAMCOUNTER StatFifoWatchdogWakeUps;
335	} VMSVGAR3STATE, *PVMSVGAR3STATE;
336	#endif /* IN_RING3 */
337
338
339	/*********************************************************************************************************************************
340	* Internal Functions *
341	*********************************************************************************************************************************/
342	#ifdef IN_RING3
343	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
344	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
345	# endif
346	# ifdef DEBUG_GMR_ACCESS
347	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
348	# endif
349	#endif
350
351
352	/*********************************************************************************************************************************
353	* Global Variables *
354	*********************************************************************************************************************************/
355	#ifdef IN_RING3
356
357	/**
358	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
359	*/
360	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
361	{
362	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
363	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
364	SSMFIELD_ENTRY_TERM()
365	};
366
367	/**
368	* SSM descriptor table for the GMR structure.
369	*/
370	static SSMFIELD const g_aGMRFields[] =
371	{
372	SSMFIELD_ENTRY( GMR, cMaxPages),
373	SSMFIELD_ENTRY( GMR, cbTotal),
374	SSMFIELD_ENTRY( GMR, numDescriptors),
375	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
376	SSMFIELD_ENTRY_TERM()
377	};
378
379	/**
380	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
381	*/
382	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
383	{
384	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
385	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
386	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
387	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
388	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
389	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
390	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
391	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
392	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
393	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
394	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
395	SSMFIELD_ENTRY_TERM()
396	};
397
398	/**
399	* SSM descriptor table for the VMSVGAR3STATE structure.
400	*/
401	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
402	{
403	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
404	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
405	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
406	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
407	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
408	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
409	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
410	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
411	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
412	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
414	#ifdef VMSVGA_USE_EMT_HALT_CODE
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
416	#else
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
418	#endif
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdMoveCursor),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDisplayCursor),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
470	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
474	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
475	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
479
480	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
483	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
484
485	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
488	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
489	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
490	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
491	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
492	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
493	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
494	# endif
495	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
496	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
497	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
498	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
499
500	SSMFIELD_ENTRY_TERM()
501	};
502
503	/**
504	* SSM descriptor table for the VGAState.svga structure.
505	*/
506	static SSMFIELD const g_aVGAStateSVGAFields[] =
507	{
508	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
509	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
510	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
511	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
512	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
513	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
514	SSMFIELD_ENTRY( VMSVGAState, fBusy),
515	SSMFIELD_ENTRY( VMSVGAState, fTraces),
516	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
517	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
518	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
519	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
520	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
521	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
522	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
523	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
524	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
525	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
526	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
527	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
528	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
529	SSMFIELD_ENTRY( VMSVGAState, uWidth),
530	SSMFIELD_ENTRY( VMSVGAState, uHeight),
531	SSMFIELD_ENTRY( VMSVGAState, uBpp),
532	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
533	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
534	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorX, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
535	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorY, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
536	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorID, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
537	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorOn, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
538	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
539	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
540	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
541	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
542	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
543	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
544	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
545	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
546	SSMFIELD_ENTRY_TERM()
547	};
548	#endif /* IN_RING3 */
549
550
551	/*********************************************************************************************************************************
552	* Internal Functions *
553	*********************************************************************************************************************************/
554	#ifdef IN_RING3
555	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
556	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
557	uint32_t uVersion, uint32_t uPass);
558	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
559	# ifdef VBOX_WITH_VMSVGA3D
560	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR);
561	# endif /* VBOX_WITH_VMSVGA3D */
562	#endif /* IN_RING3 */
563
564
565
566	#ifdef IN_RING3
567	VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
568	{
569	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
570	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
571	&& pSVGAState
572	&& pSVGAState->aScreens[idScreen].fDefined)
573	{
574	return &pSVGAState->aScreens[idScreen];
575	}
576	return NULL;
577	}
578	#endif /* IN_RING3 */
579
580	#ifdef LOG_ENABLED
581
582	/**
583	* Index register string name lookup
584	*
585	* @returns Index register string or "UNKNOWN"
586	* @param pThis The shared VGA/VMSVGA state.
587	* @param idxReg The index register.
588	*/
589	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
590	{
591	switch (idxReg)
592	{
593	case SVGA_REG_ID: return "SVGA_REG_ID";
594	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
595	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
596	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
597	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
598	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
599	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
600	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
601	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
602	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
603	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
604	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
605	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
606	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
607	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
608	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
609	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
610	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
611	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
612	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
613	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
614	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
615	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
616	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
617	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
618	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
619	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
620	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
621	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
622	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
623	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
624	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
625	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
626	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
627	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
628	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
629	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
630	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
631	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
632	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
633	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
634	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
635	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
636	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
637	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
638	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
639	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
640	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
641	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
642	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
643
644	default:
645	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
646	return "SVGA_SCRATCH_BASE reg";
647	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
648	return "SVGA_PALETTE_BASE reg";
649	return "UNKNOWN";
650	}
651	}
652
653	#ifdef IN_RING3
654	/**
655	* FIFO command name lookup
656	*
657	* @returns FIFO command string or "UNKNOWN"
658	* @param u32Cmd FIFO command
659	*/
660	static const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
661	{
662	switch (u32Cmd)
663	{
664	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
665	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
666	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
667	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
668	case SVGA_CMD_DISPLAY_CURSOR: return "SVGA_CMD_DISPLAY_CURSOR";
669	case SVGA_CMD_MOVE_CURSOR: return "SVGA_CMD_MOVE_CURSOR";
670	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
671	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
672	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
673	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
674	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
675	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
676	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
677	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
678	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
679	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
680	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
681	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
682	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
683	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
684	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
685	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
686	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
687	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
688	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
689	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
690	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
691	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
692	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
693	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
694	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
695	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
696	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
697	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
698	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
699	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
700	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
701	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
702	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
703	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
704	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
705	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
706	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
707	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
708	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
709	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
710	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
711	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
712	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
713	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
714	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
715	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
716	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
717	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
718	default: return "UNKNOWN";
719	}
720	}
721	# endif /* IN_RING3 */
722
723	#endif /* LOG_ENABLED */
724	#ifdef IN_RING3
725
726	/**
727	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
728	*/
729	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
730	{
731	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
732	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
733
734	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
735	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
736
737	/** @todo Test how it interacts with multiple screen objects. */
738	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
739	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
740	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
741
742	if (x < uWidth)
743	{
744	pThis->svga.viewport.x = x;
745	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
746	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
747	}
748	else
749	{
750	pThis->svga.viewport.x = uWidth;
751	pThis->svga.viewport.cx = 0;
752	pThis->svga.viewport.xRight = uWidth;
753	}
754	if (y < uHeight)
755	{
756	pThis->svga.viewport.y = y;
757	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
758	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
759	pThis->svga.viewport.yHighWC = uHeight - y;
760	}
761	else
762	{
763	pThis->svga.viewport.y = uHeight;
764	pThis->svga.viewport.cy = 0;
765	pThis->svga.viewport.yLowWC = 0;
766	pThis->svga.viewport.yHighWC = 0;
767	}
768
769	# ifdef VBOX_WITH_VMSVGA3D
770	/*
771	* Now inform the 3D backend.
772	*/
773	if (pThis->svga.f3DEnabled)
774	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
775	# else
776	RT_NOREF(OldViewport);
777	# endif
778	}
779
780
781	/**
782	* Updating screen information in API
783	*
784	* @param pThis The The shared VGA/VMSVGA instance data.
785	* @param pThisCC The VGA/VMSVGA state for ring-3.
786	*/
787	void vmsvgaR3VBVAResize(PVGASTATE pThis, PVGASTATECC pThisCC)
788	{
789	int rc;
790
791	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
792
793	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
794	{
795	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
796	if (!pScreen->fModified)
797	continue;
798
799	pScreen->fModified = false;
800
801	VBVAINFOVIEW view;
802	RT_ZERO(view);
803	view.u32ViewIndex = pScreen->idScreen;
804	// view.u32ViewOffset = 0;
805	view.u32ViewSize = pThis->vram_size;
806	view.u32MaxScreenSize = pThis->vram_size;
807
808	VBVAINFOSCREEN screen;
809	RT_ZERO(screen);
810	screen.u32ViewIndex = pScreen->idScreen;
811
812	if (pScreen->fDefined)
813	{
814	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
815	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
816	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
817	{
818	Assert(pThis->svga.fGFBRegisters);
819	continue;
820	}
821
822	screen.i32OriginX = pScreen->xOrigin;
823	screen.i32OriginY = pScreen->yOrigin;
824	screen.u32StartOffset = pScreen->offVRAM;
825	screen.u32LineSize = pScreen->cbPitch;
826	screen.u32Width = pScreen->cWidth;
827	screen.u32Height = pScreen->cHeight;
828	screen.u16BitsPerPixel = pScreen->cBpp;
829	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
830	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
831	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
832	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
833	}
834	else
835	{
836	/* Screen is destroyed. */
837	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
838	}
839
840	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pThisCC->pbVRam, /fResetInputMapping=/ true);
841	AssertRC(rc);
842	}
843	}
844
845
846	/**
847	* @interface_method_impl{PDMIDISPLAYPORT,pfnReportMonitorPositions}
848	*
849	* Used to update screen offsets (positions) since appearently vmwgfx fails to
850	* pass correct offsets thru FIFO.
851	*/
852	DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PCRTPOINT paPositions)
853	{
854	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
855	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
856	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
857
858	/* We assume cPositions is the # of outputs Xserver reports and paPositions is (-1, -1) for disabled monitors. */
859	cPositions = RT_MIN(cPositions, RT_ELEMENTS(pSVGAState->aScreens));
860	for (uint32_t i = 0; i < cPositions; ++i)
861	{
862	if ( pSVGAState->aScreens[i].xOrigin == paPositions[i].x
863	&& pSVGAState->aScreens[i].yOrigin == paPositions[i].y)
864	continue;
865
866	if (pSVGAState->aScreens[i].xOrigin == -1)
867	continue;
868	if (pSVGAState->aScreens[i].yOrigin == -1)
869	continue;
870
871	pSVGAState->aScreens[i].xOrigin = paPositions[i].x;
872	pSVGAState->aScreens[i].yOrigin = paPositions[i].y;
873	pSVGAState->aScreens[i].fModified = true;
874	}
875
876	vmsvgaR3VBVAResize(pThis, pThisCC);
877	}
878
879	#endif /* IN_RING3 */
880
881	/**
882	* Read port register
883	*
884	* @returns VBox status code.
885	* @param pDevIns The device instance.
886	* @param pThis The shared VGA/VMSVGA state.
887	* @param pu32 Where to store the read value
888	*/
889	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
890	{
891	#ifdef IN_RING3
892	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
893	#endif
894	int rc = VINF_SUCCESS;
895	*pu32 = 0;
896
897	/* Rough index register validation. */
898	uint32_t idxReg = pThis->svga.u32IndexReg;
899	#if !defined(IN_RING3) && defined(VBOX_STRICT)
900	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
901	VINF_IOM_R3_IOPORT_READ);
902	#else
903	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
904	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
905	VINF_SUCCESS);
906	#endif
907	RT_UNTRUSTED_VALIDATED_FENCE();
908
909	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
910	if ( idxReg >= SVGA_REG_CAPABILITIES
911	&& pThis->svga.u32SVGAId == SVGA_ID_0)
912	{
913	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
914	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
915	}
916
917	switch (idxReg)
918	{
919	case SVGA_REG_ID:
920	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
921	*pu32 = pThis->svga.u32SVGAId;
922	break;
923
924	case SVGA_REG_ENABLE:
925	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
926	*pu32 = pThis->svga.fEnabled;
927	break;
928
929	case SVGA_REG_WIDTH:
930	{
931	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
932	if ( pThis->svga.fEnabled
933	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
934	*pu32 = pThis->svga.uWidth;
935	else
936	{
937	#ifndef IN_RING3
938	rc = VINF_IOM_R3_IOPORT_READ;
939	#else
940	*pu32 = pThisCC->pDrv->cx;
941	#endif
942	}
943	break;
944	}
945
946	case SVGA_REG_HEIGHT:
947	{
948	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
949	if ( pThis->svga.fEnabled
950	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
951	*pu32 = pThis->svga.uHeight;
952	else
953	{
954	#ifndef IN_RING3
955	rc = VINF_IOM_R3_IOPORT_READ;
956	#else
957	*pu32 = pThisCC->pDrv->cy;
958	#endif
959	}
960	break;
961	}
962
963	case SVGA_REG_MAX_WIDTH:
964	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
965	*pu32 = pThis->svga.u32MaxWidth;
966	break;
967
968	case SVGA_REG_MAX_HEIGHT:
969	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
970	*pu32 = pThis->svga.u32MaxHeight;
971	break;
972
973	case SVGA_REG_DEPTH:
974	/* This returns the color depth of the current mode. */
975	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
976	switch (pThis->svga.uBpp)
977	{
978	case 15:
979	case 16:
980	case 24:
981	*pu32 = pThis->svga.uBpp;
982	break;
983
984	default:
985	case 32:
986	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
987	break;
988	}
989	break;
990
991	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
992	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
993	*pu32 = pThis->svga.uHostBpp;
994	break;
995
996	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
997	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
998	*pu32 = pThis->svga.uBpp;
999	break;
1000
1001	case SVGA_REG_PSEUDOCOLOR:
1002	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
1003	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
1004	break;
1005
1006	case SVGA_REG_RED_MASK:
1007	case SVGA_REG_GREEN_MASK:
1008	case SVGA_REG_BLUE_MASK:
1009	{
1010	uint32_t uBpp;
1011
1012	if (pThis->svga.fEnabled)
1013	uBpp = pThis->svga.uBpp;
1014	else
1015	uBpp = pThis->svga.uHostBpp;
1016
1017	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
1018	switch (uBpp)
1019	{
1020	case 8:
1021	u32RedMask = 0x07;
1022	u32GreenMask = 0x38;
1023	u32BlueMask = 0xc0;
1024	break;
1025
1026	case 15:
1027	u32RedMask = 0x0000001f;
1028	u32GreenMask = 0x000003e0;
1029	u32BlueMask = 0x00007c00;
1030	break;
1031
1032	case 16:
1033	u32RedMask = 0x0000001f;
1034	u32GreenMask = 0x000007e0;
1035	u32BlueMask = 0x0000f800;
1036	break;
1037
1038	case 24:
1039	case 32:
1040	default:
1041	u32RedMask = 0x00ff0000;
1042	u32GreenMask = 0x0000ff00;
1043	u32BlueMask = 0x000000ff;
1044	break;
1045	}
1046	switch (idxReg)
1047	{
1048	case SVGA_REG_RED_MASK:
1049	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
1050	*pu32 = u32RedMask;
1051	break;
1052
1053	case SVGA_REG_GREEN_MASK:
1054	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
1055	*pu32 = u32GreenMask;
1056	break;
1057
1058	case SVGA_REG_BLUE_MASK:
1059	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
1060	*pu32 = u32BlueMask;
1061	break;
1062	}
1063	break;
1064	}
1065
1066	case SVGA_REG_BYTES_PER_LINE:
1067	{
1068	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
1069	if ( pThis->svga.fEnabled
1070	&& pThis->svga.cbScanline)
1071	*pu32 = pThis->svga.cbScanline;
1072	else
1073	{
1074	#ifndef IN_RING3
1075	rc = VINF_IOM_R3_IOPORT_READ;
1076	#else
1077	*pu32 = pThisCC->pDrv->cbScanline;
1078	#endif
1079	}
1080	break;
1081	}
1082
1083	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1084	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1085	*pu32 = pThis->vram_size;
1086	break;
1087
1088	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1089	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1090	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1091	*pu32 = pThis->GCPhysVRAM;
1092	break;
1093
1094	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1095	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1096	/* Always zero in our case. */
1097	*pu32 = 0;
1098	break;
1099
1100	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1101	{
1102	#ifndef IN_RING3
1103	rc = VINF_IOM_R3_IOPORT_READ;
1104	#else
1105	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1106
1107	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1108	if ( pThis->svga.fEnabled
1109	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1110	{
1111	/* Hardware enabled; return real framebuffer size .*/
1112	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1113	}
1114	else
1115	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1116
1117	pu32 = RT_MIN(pThis->vram_size, pu32);
1118	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1119	#endif
1120	break;
1121	}
1122
1123	case SVGA_REG_CAPABILITIES:
1124	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1125	*pu32 = pThis->svga.u32RegCaps;
1126	break;
1127
1128	case SVGA_REG_MEM_START: /* FIFO start */
1129	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1130	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1131	*pu32 = pThis->svga.GCPhysFIFO;
1132	break;
1133
1134	case SVGA_REG_MEM_SIZE: /* FIFO size */
1135	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1136	*pu32 = pThis->svga.cbFIFO;
1137	break;
1138
1139	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1140	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1141	*pu32 = pThis->svga.fConfigured;
1142	break;
1143
1144	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1145	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1146	*pu32 = 0;
1147	break;
1148
1149	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1150	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1151	if (pThis->svga.fBusy)
1152	{
1153	#ifndef IN_RING3
1154	/* Go to ring-3 and halt the CPU. */
1155	rc = VINF_IOM_R3_IOPORT_READ;
1156	RT_NOREF(pDevIns);
1157	break;
1158	#else
1159	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1160	/* The guest is basically doing a HLT via the device here, but with
1161	a special wake up condition on FIFO completion. */
1162	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1163	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1164	PVM pVM = PDMDevHlpGetVM(pDevIns);
1165	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1166	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1167	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1168	if (pThis->svga.fBusy)
1169	{
1170	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1171	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1172	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1173	}
1174	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1175	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1176	# else
1177
1178	/* Delay the EMT a bit so the FIFO and others can get some work done.
1179	This used to be a crude 50 ms sleep. The current code tries to be
1180	more efficient, but the consept is still very crude. */
1181	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1182	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1183	RTThreadYield();
1184	if (pThis->svga.fBusy)
1185	{
1186	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1187
1188	if (pThis->svga.fBusy && cRefs == 1)
1189	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1190	if (pThis->svga.fBusy)
1191	{
1192	/** @todo If this code is going to stay, we need to call into the halt/wait
1193	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1194	* suffer when the guest is polling on a busy FIFO. */
1195	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns));
1196	if (cNsMaxWait >= RT_NS_100US)
1197	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1198	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1199	RT_MIN(cNsMaxWait, RT_NS_10MS));
1200	}
1201
1202	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1203	}
1204	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1205	# endif
1206	*pu32 = pThis->svga.fBusy != 0;
1207	#endif
1208	}
1209	else
1210	*pu32 = false;
1211	break;
1212
1213	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1214	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1215	*pu32 = pThis->svga.u32GuestId;
1216	break;
1217
1218	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1219	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1220	*pu32 = pThis->svga.cScratchRegion;
1221	break;
1222
1223	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1224	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1225	*pu32 = SVGA_FIFO_NUM_REGS;
1226	break;
1227
1228	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1229	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1230	*pu32 = pThis->svga.u32PitchLock;
1231	break;
1232
1233	case SVGA_REG_IRQMASK: /* Interrupt mask */
1234	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1235	*pu32 = pThis->svga.u32IrqMask;
1236	break;
1237
1238	/* See "Guest memory regions" below. */
1239	case SVGA_REG_GMR_ID:
1240	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1241	*pu32 = pThis->svga.u32CurrentGMRId;
1242	break;
1243
1244	case SVGA_REG_GMR_DESCRIPTOR:
1245	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1246	/* Write only */
1247	*pu32 = 0;
1248	break;
1249
1250	case SVGA_REG_GMR_MAX_IDS:
1251	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1252	*pu32 = pThis->svga.cGMR;
1253	break;
1254
1255	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1256	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1257	*pu32 = VMSVGA_MAX_GMR_PAGES;
1258	break;
1259
1260	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1261	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1262	*pu32 = pThis->svga.fTraces;
1263	break;
1264
1265	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1266	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1267	*pu32 = VMSVGA_MAX_GMR_PAGES;
1268	break;
1269
1270	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1271	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1272	*pu32 = VMSVGA_SURFACE_SIZE;
1273	break;
1274
1275	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1276	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1277	break;
1278
1279	/* Mouse cursor support. */
1280	case SVGA_REG_CURSOR_ID:
1281	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdRd);
1282	*pu32 = pThis->svga.uCursorID;
1283	break;
1284
1285	case SVGA_REG_CURSOR_X:
1286	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXRd);
1287	*pu32 = pThis->svga.uCursorX;
1288	break;
1289
1290	case SVGA_REG_CURSOR_Y:
1291	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYRd);
1292	*pu32 = pThis->svga.uCursorY;
1293	break;
1294
1295	case SVGA_REG_CURSOR_ON:
1296	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnRd);
1297	*pu32 = pThis->svga.uCursorOn;
1298	break;
1299
1300	/* Legacy multi-monitor support */
1301	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1302	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1303	*pu32 = 1;
1304	break;
1305
1306	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1307	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1308	*pu32 = 0;
1309	break;
1310
1311	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1312	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1313	*pu32 = 0;
1314	break;
1315
1316	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1317	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1318	*pu32 = 0;
1319	break;
1320
1321	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1322	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1323	*pu32 = 0;
1324	break;
1325
1326	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1327	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1328	*pu32 = pThis->svga.uWidth;
1329	break;
1330
1331	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1332	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1333	*pu32 = pThis->svga.uHeight;
1334	break;
1335
1336	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1337	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1338	/* We must return something sensible here otherwise the Linux driver
1339	will take a legacy code path without 3d support. This number also
1340	limits how many screens Linux guests will allow. */
1341	*pu32 = pThis->cMonitors;
1342	break;
1343
1344	default:
1345	{
1346	uint32_t offReg;
1347	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1348	{
1349	RT_UNTRUSTED_VALIDATED_FENCE();
1350	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1351	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1352	}
1353	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1354	{
1355	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1356	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1357	RT_UNTRUSTED_VALIDATED_FENCE();
1358	uint32_t u32 = pThis->last_palette[offReg / 3];
1359	switch (offReg % 3)
1360	{
1361	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1362	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1363	case 2: pu32 = u32 & 0xff; break; / blue */
1364	}
1365	}
1366	else
1367	{
1368	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1369	rc = VINF_IOM_R3_IOPORT_READ;
1370	#else
1371	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1372
1373	/* Do not assert. The guest might be reading all registers. */
1374	LogFunc(("Unknown reg=%#x\n", idxReg));
1375	#endif
1376	}
1377	break;
1378	}
1379	}
1380	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1381	return rc;
1382	}
1383
1384	#ifdef IN_RING3
1385	/**
1386	* Apply the current resolution settings to change the video mode.
1387	*
1388	* @returns VBox status code.
1389	* @param pThis The shared VGA state.
1390	* @param pThisCC The ring-3 VGA state.
1391	*/
1392	static int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1393	{
1394	/* Always do changemode on FIFO thread. */
1395	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1396
1397	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1398
1399	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1400
1401	if (pThis->svga.fGFBRegisters)
1402	{
1403	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1404	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1405	* deletes all screens other than screen #0, and redefines screen
1406	* #0 according to the specified mode. Drivers that use
1407	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1408	*/
1409
1410	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1411	pScreen->fDefined = true;
1412	pScreen->fModified = true;
1413	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1414	pScreen->idScreen = 0;
1415	pScreen->xOrigin = 0;
1416	pScreen->yOrigin = 0;
1417	pScreen->offVRAM = 0;
1418	pScreen->cbPitch = pThis->svga.cbScanline;
1419	pScreen->cWidth = pThis->svga.uWidth;
1420	pScreen->cHeight = pThis->svga.uHeight;
1421	pScreen->cBpp = pThis->svga.uBpp;
1422
1423	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1424	{
1425	/* Delete screen. */
1426	pScreen = &pSVGAState->aScreens[iScreen];
1427	if (pScreen->fDefined)
1428	{
1429	pScreen->fModified = true;
1430	pScreen->fDefined = false;
1431	}
1432	}
1433	}
1434	else
1435	{
1436	/* "If Screen Objects are supported, they can be used to fully
1437	* replace the functionality provided by the framebuffer registers
1438	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1439	*/
1440	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1441	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1442	pThis->svga.uBpp = pThis->svga.uHostBpp;
1443	}
1444
1445	vmsvgaR3VBVAResize(pThis, pThisCC);
1446
1447	/* Last stuff. For the VGA device screenshot. */
1448	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1449	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1450	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1451	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1452	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1453
1454	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1455	if ( pThis->svga.viewport.cx == 0
1456	&& pThis->svga.viewport.cy == 0)
1457	{
1458	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1459	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1460	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1461	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1462	pThis->svga.viewport.yLowWC = 0;
1463	}
1464
1465	return VINF_SUCCESS;
1466	}
1467
1468	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1469	{
1470	VBVACMDHDR cmd;
1471	cmd.x = (int16_t)(pScreen->xOrigin + x);
1472	cmd.y = (int16_t)(pScreen->yOrigin + y);
1473	cmd.w = (uint16_t)w;
1474	cmd.h = (uint16_t)h;
1475
1476	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1477	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1478	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1479	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1480
1481	return VINF_SUCCESS;
1482	}
1483
1484	#endif /* IN_RING3 */
1485	#if defined(IN_RING0) \|\| defined(IN_RING3)
1486
1487	/**
1488	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1489	*
1490	* @param pThis The shared VGA/VMSVGA instance data.
1491	* @param pThisCC The VGA/VMSVGA state for the current context.
1492	* @param fState The busy state.
1493	*/
1494	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1495	{
1496	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1497
1498	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1499	{
1500	/* Race / unfortunately scheduling. Highly unlikly. */
1501	uint32_t cLoops = 64;
1502	do
1503	{
1504	ASMNopPause();
1505	fState = (pThis->svga.fBusy != 0);
1506	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1507	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1508	}
1509	}
1510
1511
1512	/**
1513	* Update the scanline pitch in response to the guest changing mode
1514	* width/bpp.
1515	*
1516	* @param pThis The shared VGA/VMSVGA state.
1517	* @param pThisCC The VGA/VMSVGA state for the current context.
1518	*/
1519	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1520	{
1521	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1522	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1523	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1524	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1525
1526	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1527	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1528	* location but it has a different meaning.
1529	*/
1530	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1531	uFifoPitchLock = 0;
1532
1533	/* Sanitize values. */
1534	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1535	uFifoPitchLock = 0;
1536	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1537	uRegPitchLock = 0;
1538
1539	/* Prefer the register value to the FIFO value.*/
1540	if (uRegPitchLock)
1541	pThis->svga.cbScanline = uRegPitchLock;
1542	else if (uFifoPitchLock)
1543	pThis->svga.cbScanline = uFifoPitchLock;
1544	else
1545	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1546
1547	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1548	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1549	}
1550
1551	#endif /* IN_RING0 \|\| IN_RING3 */
1552
1553	#ifdef IN_RING3
1554
1555	/**
1556	* Sends cursor position and visibility information from legacy
1557	* SVGA registers to the front-end.
1558	*/
1559	static void vmsvgaR3RegUpdateCursor(PVGASTATECC pThisCC, PVGASTATE pThis, uint32_t uCursorOn)
1560	{
1561	/*
1562	* Writing the X/Y/ID registers does not trigger changes; only writing the
1563	* SVGA_REG_CURSOR_ON register does. That minimizes the overhead.
1564	* We boldly assume that guests aren't stupid and aren't writing the CURSOR_ON
1565	* register if they don't have to.
1566	*/
1567	uint32_t x, y, idScreen;
1568	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
1569
1570	x = pThis->svga.uCursorX;
1571	y = pThis->svga.uCursorY;
1572	idScreen = SVGA_ID_INVALID; /* The old register interface is single screen only. */
1573
1574	/* The original values for SVGA_REG_CURSOR_ON were off (0) and on (1); later, the values
1575	* were extended as follows:
1576	*
1577	* SVGA_CURSOR_ON_HIDE 0
1578	* SVGA_CURSOR_ON_SHOW 1
1579	* SVGA_CURSOR_ON_REMOVE_FROM_FB 2 - cursor on but not in the framebuffer
1580	* SVGA_CURSOR_ON_RESTORE_TO_FB 3 - cursor on, possibly in the framebuffer
1581	*
1582	* Since we never draw the cursor into the guest's framebuffer, we do not need to
1583	* distinguish between the non-zero values but still remember them.
1584	*/
1585	if (RT_BOOL(pThis->svga.uCursorOn) != RT_BOOL(uCursorOn))
1586	{
1587	LogRel2(("vmsvgaR3RegUpdateCursor: uCursorOn %d prev CursorOn %d (%d,%d)\n", uCursorOn, pThis->svga.uCursorOn, x, y));
1588	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(uCursorOn), false, 0, 0, 0, 0, NULL);
1589	}
1590	pThis->svga.uCursorOn = uCursorOn;
1591	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
1592	}
1593
1594	#endif /* IN_RING3 */
1595
1596
1597	/**
1598	* Write port register
1599	*
1600	* @returns Strict VBox status code.
1601	* @param pDevIns The device instance.
1602	* @param pThis The shared VGA/VMSVGA state.
1603	* @param pThisCC The VGA/VMSVGA state for the current context.
1604	* @param u32 Value to write
1605	*/
1606	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1607	{
1608	#ifdef IN_RING3
1609	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1610	#endif
1611	VBOXSTRICTRC rc = VINF_SUCCESS;
1612	RT_NOREF(pThisCC);
1613
1614	/* Rough index register validation. */
1615	uint32_t idxReg = pThis->svga.u32IndexReg;
1616	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1617	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1618	VINF_IOM_R3_IOPORT_WRITE);
1619	#else
1620	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1621	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1622	VINF_SUCCESS);
1623	#endif
1624	RT_UNTRUSTED_VALIDATED_FENCE();
1625
1626	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1627	if ( idxReg >= SVGA_REG_CAPABILITIES
1628	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1629	{
1630	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1631	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1632	}
1633	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1634	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1635	switch (idxReg)
1636	{
1637	case SVGA_REG_WIDTH:
1638	case SVGA_REG_HEIGHT:
1639	case SVGA_REG_PITCHLOCK:
1640	case SVGA_REG_BITS_PER_PIXEL:
1641	pThis->svga.fGFBRegisters = true;
1642	break;
1643	default:
1644	break;
1645	}
1646
1647	switch (idxReg)
1648	{
1649	case SVGA_REG_ID:
1650	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1651	if ( u32 == SVGA_ID_0
1652	\|\| u32 == SVGA_ID_1
1653	\|\| u32 == SVGA_ID_2)
1654	pThis->svga.u32SVGAId = u32;
1655	else
1656	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1657	break;
1658
1659	case SVGA_REG_ENABLE:
1660	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1661	#ifdef IN_RING3
1662	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1663	&& pThis->svga.fEnabled == false)
1664	{
1665	/* Make a backup copy of the first 512kb in order to save font data etc. */
1666	/** @todo should probably swap here, rather than copy + zero */
1667	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1668	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1669	}
1670
1671	pThis->svga.fEnabled = u32;
1672	if (pThis->svga.fEnabled)
1673	{
1674	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1675	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED)
1676	{
1677	/* Keep the current mode. */
1678	pThis->svga.uWidth = pThisCC->pDrv->cx;
1679	pThis->svga.uHeight = pThisCC->pDrv->cy;
1680	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1681	}
1682
1683	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1684	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1685	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1686	# ifdef LOG_ENABLED
1687	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1688	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1689	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1690	# endif
1691
1692	/* Disable or enable dirty page tracking according to the current fTraces value. */
1693	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1694
1695	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1696	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1697	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
1698	}
1699	else
1700	{
1701	/* Restore the text mode backup. */
1702	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1703
1704	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1705
1706	/* Enable dirty page tracking again when going into legacy mode. */
1707	vmsvgaR3SetTraces(pDevIns, pThis, true);
1708
1709	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1710	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1711	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1712
1713	/* Clear the pitch lock. */
1714	pThis->svga.u32PitchLock = 0;
1715	}
1716	#else /* !IN_RING3 */
1717	rc = VINF_IOM_R3_IOPORT_WRITE;
1718	#endif /* !IN_RING3 */
1719	break;
1720
1721	case SVGA_REG_WIDTH:
1722	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1723	if (pThis->svga.uWidth != u32)
1724	{
1725	#if defined(IN_RING3) \|\| defined(IN_RING0)
1726	pThis->svga.uWidth = u32;
1727	vmsvgaHCUpdatePitch(pThis, pThisCC);
1728	if (pThis->svga.fEnabled)
1729	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1730	#else
1731	rc = VINF_IOM_R3_IOPORT_WRITE;
1732	#endif
1733	}
1734	/* else: nop */
1735	break;
1736
1737	case SVGA_REG_HEIGHT:
1738	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1739	if (pThis->svga.uHeight != u32)
1740	{
1741	pThis->svga.uHeight = u32;
1742	if (pThis->svga.fEnabled)
1743	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1744	}
1745	/* else: nop */
1746	break;
1747
1748	case SVGA_REG_DEPTH:
1749	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1750	/** @todo read-only?? */
1751	break;
1752
1753	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1754	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1755	if (pThis->svga.uBpp != u32)
1756	{
1757	#if defined(IN_RING3) \|\| defined(IN_RING0)
1758	pThis->svga.uBpp = u32;
1759	vmsvgaHCUpdatePitch(pThis, pThisCC);
1760	if (pThis->svga.fEnabled)
1761	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1762	#else
1763	rc = VINF_IOM_R3_IOPORT_WRITE;
1764	#endif
1765	}
1766	/* else: nop */
1767	break;
1768
1769	case SVGA_REG_PSEUDOCOLOR:
1770	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1771	break;
1772
1773	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1774	#ifdef IN_RING3
1775	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1776	pThis->svga.fConfigured = u32;
1777	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1778	if (!pThis->svga.fConfigured)
1779	pThis->svga.fTraces = true;
1780	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1781	#else
1782	rc = VINF_IOM_R3_IOPORT_WRITE;
1783	#endif
1784	break;
1785
1786	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1787	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1788	if ( pThis->svga.fEnabled
1789	&& pThis->svga.fConfigured)
1790	{
1791	#if defined(IN_RING3) \|\| defined(IN_RING0)
1792	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
1793	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1794	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
1795	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
1796
1797	/* Kick the FIFO thread to start processing commands again. */
1798	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
1799	#else
1800	rc = VINF_IOM_R3_IOPORT_WRITE;
1801	#endif
1802	}
1803	/* else nothing to do. */
1804	else
1805	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1806
1807	break;
1808
1809	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1810	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1811	break;
1812
1813	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1814	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1815	pThis->svga.u32GuestId = u32;
1816	break;
1817
1818	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1819	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1820	pThis->svga.u32PitchLock = u32;
1821	/* Should this also update the FIFO pitch lock? Unclear. */
1822	break;
1823
1824	case SVGA_REG_IRQMASK: /* Interrupt mask */
1825	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1826	pThis->svga.u32IrqMask = u32;
1827
1828	/* Irq pending after the above change? */
1829	if (pThis->svga.u32IrqStatus & u32)
1830	{
1831	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1832	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
1833	}
1834	else
1835	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1836	break;
1837
1838	/* Mouse cursor support */
1839	case SVGA_REG_CURSOR_ID:
1840	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdWr);
1841	pThis->svga.uCursorID = u32;
1842	break;
1843
1844	case SVGA_REG_CURSOR_X:
1845	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXWr);
1846	pThis->svga.uCursorX = u32;
1847	break;
1848
1849	case SVGA_REG_CURSOR_Y:
1850	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYWr);
1851	pThis->svga.uCursorY = u32;
1852	break;
1853
1854	case SVGA_REG_CURSOR_ON:
1855	#ifdef IN_RING3
1856	/* The cursor is only updated when SVGA_REG_CURSOR_ON is written. */
1857	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnWr);
1858	vmsvgaR3RegUpdateCursor(pThisCC, pThis, u32);
1859	#else
1860	rc = VINF_IOM_R3_IOPORT_WRITE;
1861	#endif
1862	break;
1863
1864	/* Legacy multi-monitor support */
1865	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1866	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1867	break;
1868	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1869	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1870	break;
1871	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1872	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1873	break;
1874	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1875	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1876	break;
1877	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1878	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1879	break;
1880	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1881	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1882	break;
1883	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1884	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1885	break;
1886	#ifdef VBOX_WITH_VMSVGA3D
1887	/* See "Guest memory regions" below. */
1888	case SVGA_REG_GMR_ID:
1889	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1890	pThis->svga.u32CurrentGMRId = u32;
1891	break;
1892
1893	case SVGA_REG_GMR_DESCRIPTOR:
1894	# ifndef IN_RING3
1895	rc = VINF_IOM_R3_IOPORT_WRITE;
1896	break;
1897	# else /* IN_RING3 */
1898	{
1899	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1900
1901	/* Validate current GMR id. */
1902	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1903	AssertBreak(idGMR < pThis->svga.cGMR);
1904	RT_UNTRUSTED_VALIDATED_FENCE();
1905
1906	/* Free the old GMR if present. */
1907	vmsvgaR3GmrFree(pThisCC, idGMR);
1908
1909	/* Just undefine the GMR? */
1910	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1911	if (GCPhys == 0)
1912	{
1913	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1914	break;
1915	}
1916
1917
1918	/* Never cross a page boundary automatically. */
1919	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1920	uint32_t cPagesTotal = 0;
1921	uint32_t iDesc = 0;
1922	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1923	uint32_t cLoops = 0;
1924	RTGCPHYS GCPhysBase = GCPhys;
1925	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1926	{
1927	/* Read descriptor. */
1928	SVGAGuestMemDescriptor desc;
1929	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
1930	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
1931
1932	if (desc.numPages != 0)
1933	{
1934	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1935	cPagesTotal += desc.numPages;
1936	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1937
1938	if ((iDesc & 15) == 0)
1939	{
1940	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1941	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1942	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1943	}
1944
1945	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1946	paDescs[iDesc++].numPages = desc.numPages;
1947
1948	/* Continue with the next descriptor. */
1949	GCPhys += sizeof(desc);
1950	}
1951	else if (desc.ppn == 0)
1952	break; /* terminator */
1953	else /* Pointer to the next physical page of descriptors. */
1954	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1955
1956	cLoops++;
1957	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1958	}
1959
1960	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1961	if (RT_SUCCESS(rc))
1962	{
1963	/* Commit the GMR. */
1964	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1965	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1966	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1967	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1968	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1969	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1970	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1971	}
1972	else
1973	{
1974	RTMemFree(paDescs);
1975	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1976	}
1977	break;
1978	}
1979	# endif /* IN_RING3 */
1980	#endif // VBOX_WITH_VMSVGA3D
1981
1982	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1983	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1984	if (pThis->svga.fTraces == u32)
1985	break; /* nothing to do */
1986
1987	#ifdef IN_RING3
1988	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
1989	#else
1990	rc = VINF_IOM_R3_IOPORT_WRITE;
1991	#endif
1992	break;
1993
1994	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1995	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1996	break;
1997
1998	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1999	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
2000	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
2001	break;
2002
2003	case SVGA_REG_FB_START:
2004	case SVGA_REG_MEM_START:
2005	case SVGA_REG_HOST_BITS_PER_PIXEL:
2006	case SVGA_REG_MAX_WIDTH:
2007	case SVGA_REG_MAX_HEIGHT:
2008	case SVGA_REG_VRAM_SIZE:
2009	case SVGA_REG_FB_SIZE:
2010	case SVGA_REG_CAPABILITIES:
2011	case SVGA_REG_MEM_SIZE:
2012	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
2013	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
2014	case SVGA_REG_BYTES_PER_LINE:
2015	case SVGA_REG_FB_OFFSET:
2016	case SVGA_REG_RED_MASK:
2017	case SVGA_REG_GREEN_MASK:
2018	case SVGA_REG_BLUE_MASK:
2019	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
2020	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
2021	case SVGA_REG_GMR_MAX_IDS:
2022	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
2023	/* Read only - ignore. */
2024	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
2025	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
2026	break;
2027
2028	default:
2029	{
2030	uint32_t offReg;
2031	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
2032	{
2033	RT_UNTRUSTED_VALIDATED_FENCE();
2034	pThis->svga.au32ScratchRegion[offReg] = u32;
2035	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
2036	}
2037	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
2038	{
2039	/* Note! Using last_palette rather than palette here to preserve the VGA one.
2040	Btw, see rgb_to_pixel32. */
2041	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
2042	u32 &= 0xff;
2043	RT_UNTRUSTED_VALIDATED_FENCE();
2044	uint32_t uRgb = pThis->last_palette[offReg / 3];
2045	switch (offReg % 3)
2046	{
2047	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
2048	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
2049	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
2050	}
2051	pThis->last_palette[offReg / 3] = uRgb;
2052	}
2053	else
2054	{
2055	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2056	rc = VINF_IOM_R3_IOPORT_WRITE;
2057	#else
2058	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
2059	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
2060	#endif
2061	}
2062	break;
2063	}
2064	}
2065	return rc;
2066	}
2067
2068	/**
2069	* @callback_method_impl{FNIOMIOPORTNEWIN}
2070	*/
2071	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2072	{
2073	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2074	RT_NOREF_PV(pvUser);
2075
2076	/* Only dword accesses. */
2077	if (cb == 4)
2078	{
2079	switch (offPort)
2080	{
2081	case SVGA_INDEX_PORT:
2082	*pu32 = pThis->svga.u32IndexReg;
2083	break;
2084
2085	case SVGA_VALUE_PORT:
2086	return vmsvgaReadPort(pDevIns, pThis, pu32);
2087
2088	case SVGA_BIOS_PORT:
2089	Log(("Ignoring BIOS port read\n"));
2090	*pu32 = 0;
2091	break;
2092
2093	case SVGA_IRQSTATUS_PORT:
2094	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2095	*pu32 = pThis->svga.u32IrqStatus;
2096	break;
2097
2098	default:
2099	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
2100	*pu32 = UINT32_MAX;
2101	break;
2102	}
2103	}
2104	else
2105	{
2106	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2107	*pu32 = UINT32_MAX;
2108	}
2109	return VINF_SUCCESS;
2110	}
2111
2112	/**
2113	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2114	*/
2115	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2116	{
2117	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2118	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2119	RT_NOREF_PV(pvUser);
2120
2121	/* Only dword accesses. */
2122	if (cb == 4)
2123	switch (offPort)
2124	{
2125	case SVGA_INDEX_PORT:
2126	pThis->svga.u32IndexReg = u32;
2127	break;
2128
2129	case SVGA_VALUE_PORT:
2130	return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2131
2132	case SVGA_BIOS_PORT:
2133	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2134	break;
2135
2136	case SVGA_IRQSTATUS_PORT:
2137	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2138	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2139	/* Clear the irq in case all events have been cleared. */
2140	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2141	{
2142	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2143	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2144	}
2145	break;
2146
2147	default:
2148	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2149	break;
2150	}
2151	else
2152	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2153
2154	return VINF_SUCCESS;
2155	}
2156
2157	#ifdef IN_RING3
2158
2159	# ifdef DEBUG_FIFO_ACCESS
2160	/**
2161	* Handle FIFO memory access.
2162	* @returns VBox status code.
2163	* @param pVM VM handle.
2164	* @param pThis The shared VGA/VMSVGA instance data.
2165	* @param GCPhys The access physical address.
2166	* @param fWriteAccess Read or write access
2167	*/
2168	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2169	{
2170	RT_NOREF(pVM);
2171	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2172	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2173
2174	switch (GCPhysOffset >> 2)
2175	{
2176	case SVGA_FIFO_MIN:
2177	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2178	break;
2179	case SVGA_FIFO_MAX:
2180	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2181	break;
2182	case SVGA_FIFO_NEXT_CMD:
2183	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2184	break;
2185	case SVGA_FIFO_STOP:
2186	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2187	break;
2188	case SVGA_FIFO_CAPABILITIES:
2189	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2190	break;
2191	case SVGA_FIFO_FLAGS:
2192	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2193	break;
2194	case SVGA_FIFO_FENCE:
2195	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2196	break;
2197	case SVGA_FIFO_3D_HWVERSION:
2198	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2199	break;
2200	case SVGA_FIFO_PITCHLOCK:
2201	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2202	break;
2203	case SVGA_FIFO_CURSOR_ON:
2204	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2205	break;
2206	case SVGA_FIFO_CURSOR_X:
2207	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2208	break;
2209	case SVGA_FIFO_CURSOR_Y:
2210	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2211	break;
2212	case SVGA_FIFO_CURSOR_COUNT:
2213	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2214	break;
2215	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2216	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2217	break;
2218	case SVGA_FIFO_RESERVED:
2219	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2220	break;
2221	case SVGA_FIFO_CURSOR_SCREEN_ID:
2222	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2223	break;
2224	case SVGA_FIFO_DEAD:
2225	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2226	break;
2227	case SVGA_FIFO_3D_HWVERSION_REVISED:
2228	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2229	break;
2230	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2231	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2232	break;
2233	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2234	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2235	break;
2236	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2237	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2238	break;
2239	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2240	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2241	break;
2242	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2243	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2244	break;
2245	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2246	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2247	break;
2248	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2249	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2250	break;
2251	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2252	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2253	break;
2254	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2255	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2256	break;
2257	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2258	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2259	break;
2260	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2261	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2262	break;
2263	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2264	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2265	break;
2266	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2267	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2268	break;
2269	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2270	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2271	break;
2272	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2273	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2274	break;
2275	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2276	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2277	break;
2278	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2279	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2280	break;
2281	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2282	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2283	break;
2284	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2285	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2286	break;
2287	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2288	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2289	break;
2290	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2291	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2292	break;
2293	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2294	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2295	break;
2296	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2297	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2298	break;
2299	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2300	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2301	break;
2302	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2303	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2304	break;
2305	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2306	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2307	break;
2308	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2309	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2310	break;
2311	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2312	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2313	break;
2314	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2315	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2316	break;
2317	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2318	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2319	break;
2320	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2321	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2322	break;
2323	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2324	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2325	break;
2326	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2327	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2328	break;
2329	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2330	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2331	break;
2332	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2333	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2334	break;
2335	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2336	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2337	break;
2338	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2339	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2340	break;
2341	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2342	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2343	break;
2344	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2345	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2346	break;
2347	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2348	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2349	break;
2350	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2351	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2352	break;
2353	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2354	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2355	break;
2356	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2357	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2358	break;
2359	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2360	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2361	break;
2362	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2363	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2364	break;
2365	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2366	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2367	break;
2368	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2369	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2370	break;
2371	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2372	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2373	break;
2374	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2375	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2376	break;
2377	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2378	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2379	break;
2380	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2381	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2382	break;
2383	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2384	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2385	break;
2386	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2387	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2388	break;
2389	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2390	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2391	break;
2392	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2393	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2394	break;
2395	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2396	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2397	break;
2398	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2399	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2400	break;
2401	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2402	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2403	break;
2404	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2405	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2406	break;
2407	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2408	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2409	break;
2410	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2411	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2412	break;
2413	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2414	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2415	break;
2416	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2417	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2418	break;
2419	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2420	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2421	break;
2422	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2423	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2424	break;
2425	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2426	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2427	break;
2428	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2429	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2430	break;
2431	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2432	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2433	break;
2434	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2435	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2436	break;
2437	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2438	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2439	break;
2440	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2441	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2442	break;
2443	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2444	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2445	break;
2446	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2447	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2448	break;
2449	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2450	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2451	break;
2452	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2453	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2454	break;
2455	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2456	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2457	break;
2458	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2459	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2460	break;
2461	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2462	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2463	break;
2464	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2465	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2466	break;
2467	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2468	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2469	break;
2470	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2471	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2472	break;
2473	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2474	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2475	break;
2476	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2477	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2478	break;
2479	case SVGA_FIFO_3D_CAPS_LAST:
2480	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2481	break;
2482	case SVGA_FIFO_GUEST_3D_HWVERSION:
2483	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2484	break;
2485	case SVGA_FIFO_FENCE_GOAL:
2486	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2487	break;
2488	case SVGA_FIFO_BUSY:
2489	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2490	break;
2491	default:
2492	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2493	break;
2494	}
2495
2496	return VINF_EM_RAW_EMULATE_INSTR;
2497	}
2498	# endif /* DEBUG_FIFO_ACCESS */
2499
2500	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2501	/**
2502	* HC access handler for the FIFO.
2503	*
2504	* @returns VINF_SUCCESS if the handler have carried out the operation.
2505	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2506	* @param pVM VM Handle.
2507	* @param pVCpu The cross context CPU structure for the calling EMT.
2508	* @param GCPhys The physical address the guest is writing to.
2509	* @param pvPhys The HC mapping of that address.
2510	* @param pvBuf What the guest is reading/writing.
2511	* @param cbBuf How much it's reading/writing.
2512	* @param enmAccessType The access type.
2513	* @param enmOrigin Who is making the access.
2514	* @param pvUser User argument.
2515	*/
2516	static DECLCALLBACK(VBOXSTRICTRC)
2517	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2518	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2519	{
2520	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2521	PVGASTATE pThis = (PVGASTATE)pvUser;
2522	AssertPtr(pThis);
2523
2524	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2525	/*
2526	* Wake up the FIFO thread as it might have work to do now.
2527	*/
2528	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2529	AssertLogRelRC(rc);
2530	# endif
2531
2532	# ifdef DEBUG_FIFO_ACCESS
2533	/*
2534	* When in debug-fifo-access mode, we do not disable the access handler,
2535	* but leave it on as we wish to catch all access.
2536	*/
2537	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2538	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2539	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2540	/*
2541	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2542	*/
2543	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
2544	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2545	# endif
2546	if (RT_SUCCESS(rc))
2547	return VINF_PGM_HANDLER_DO_DEFAULT;
2548	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2549	return rc;
2550	}
2551	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2552
2553	#endif /* IN_RING3 */
2554
2555	#ifdef DEBUG_GMR_ACCESS
2556	# ifdef IN_RING3
2557
2558	/**
2559	* HC access handler for the FIFO.
2560	*
2561	* @returns VINF_SUCCESS if the handler have carried out the operation.
2562	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2563	* @param pVM VM Handle.
2564	* @param pVCpu The cross context CPU structure for the calling EMT.
2565	* @param GCPhys The physical address the guest is writing to.
2566	* @param pvPhys The HC mapping of that address.
2567	* @param pvBuf What the guest is reading/writing.
2568	* @param cbBuf How much it's reading/writing.
2569	* @param enmAccessType The access type.
2570	* @param enmOrigin Who is making the access.
2571	* @param pvUser User argument.
2572	*/
2573	static DECLCALLBACK(VBOXSTRICTRC)
2574	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2575	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2576	{
2577	PVGASTATE pThis = (PVGASTATE)pvUser;
2578	Assert(pThis);
2579	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2580	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2581
2582	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
2583
2584	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2585	{
2586	PGMR pGMR = &pSVGAState->paGMR[i];
2587
2588	if (pGMR->numDescriptors)
2589	{
2590	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2591	{
2592	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2593	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2594	{
2595	/*
2596	* Turn off the write handler for this particular page and make it R/W.
2597	* Then return telling the caller to restart the guest instruction.
2598	*/
2599	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2600	AssertRC(rc);
2601	return VINF_PGM_HANDLER_DO_DEFAULT;
2602	}
2603	}
2604	}
2605	}
2606
2607	return VINF_PGM_HANDLER_DO_DEFAULT;
2608	}
2609
2610	/** Callback handler for VMR3ReqCallWaitU */
2611	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2612	{
2613	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2614	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2615	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2616	int rc;
2617
2618	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2619	{
2620	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
2621	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2622	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2623	AssertRC(rc);
2624	}
2625	return VINF_SUCCESS;
2626	}
2627
2628	/** Callback handler for VMR3ReqCallWaitU */
2629	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2630	{
2631	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2632	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2633	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2634
2635	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2636	{
2637	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[i].GCPhys);
2638	AssertRC(rc);
2639	}
2640	return VINF_SUCCESS;
2641	}
2642
2643	/** Callback handler for VMR3ReqCallWaitU */
2644	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
2645	{
2646	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2647
2648	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2649	{
2650	PGMR pGMR = &pSVGAState->paGMR[i];
2651
2652	if (pGMR->numDescriptors)
2653	{
2654	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2655	{
2656	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[j].GCPhys);
2657	AssertRC(rc);
2658	}
2659	}
2660	}
2661	return VINF_SUCCESS;
2662	}
2663
2664	# endif /* IN_RING3 */
2665	#endif /* DEBUG_GMR_ACCESS */
2666
2667	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2668
2669	#ifdef IN_RING3
2670
2671
2672	/**
2673	* Common worker for changing the pointer shape.
2674	*
2675	* @param pThisCC The VGA/VMSVGA state for ring-3.
2676	* @param pSVGAState The VMSVGA ring-3 instance data.
2677	* @param fAlpha Whether there is alpha or not.
2678	* @param xHot Hotspot x coordinate.
2679	* @param yHot Hotspot y coordinate.
2680	* @param cx Width.
2681	* @param cy Height.
2682	* @param pbData Heap copy of the cursor data. Consumed.
2683	* @param cbData The size of the data.
2684	*/
2685	static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2686	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2687	{
2688	LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2689	# ifdef LOG_ENABLED
2690	if (LogIs2Enabled())
2691	{
2692	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2693	if (!fAlpha)
2694	{
2695	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2696	for (uint32_t y = 0; y < cy; y++)
2697	{
2698	Log2(("%3u:", y));
2699	uint8_t const pbLine = &pbData[y cbAndLine];
2700	for (uint32_t x = 0; x < cx; x += 8)
2701	{
2702	uint8_t b = pbLine[x / 8];
2703	char szByte[12];
2704	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2705	szByte[1] = b & 0x40 ? '*' : ' ';
2706	szByte[2] = b & 0x20 ? '*' : ' ';
2707	szByte[3] = b & 0x10 ? '*' : ' ';
2708	szByte[4] = b & 0x08 ? '*' : ' ';
2709	szByte[5] = b & 0x04 ? '*' : ' ';
2710	szByte[6] = b & 0x02 ? '*' : ' ';
2711	szByte[7] = b & 0x01 ? '*' : ' ';
2712	szByte[8] = '\0';
2713	Log2(("%s", szByte));
2714	}
2715	Log2(("\n"));
2716	}
2717	}
2718
2719	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2720	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2721	for (uint32_t y = 0; y < cy; y++)
2722	{
2723	Log2(("%3u:", y));
2724	uint32_t const pu32Line = &pu32Xor[y cx];
2725	for (uint32_t x = 0; x < cx; x++)
2726	Log2((" %08x", pu32Line[x]));
2727	Log2(("\n"));
2728	}
2729	}
2730	# endif
2731
2732	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2733	AssertRC(rc);
2734
2735	if (pSVGAState->Cursor.fActive)
2736	RTMemFree(pSVGAState->Cursor.pData);
2737
2738	pSVGAState->Cursor.fActive = true;
2739	pSVGAState->Cursor.xHotspot = xHot;
2740	pSVGAState->Cursor.yHotspot = yHot;
2741	pSVGAState->Cursor.width = cx;
2742	pSVGAState->Cursor.height = cy;
2743	pSVGAState->Cursor.cbData = cbData;
2744	pSVGAState->Cursor.pData = pbData;
2745	}
2746
2747
2748	/**
2749	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2750	*
2751	* @param pThis The shared VGA/VMSVGA state.
2752	* @param pThisCC The VGA/VMSVGA state for ring-3.
2753	* @param pSVGAState The VMSVGA ring-3 instance data.
2754	* @param pCursor The cursor.
2755	* @param pbSrcAndMask The AND mask.
2756	* @param cbSrcAndLine The scanline length of the AND mask.
2757	* @param pbSrcXorMask The XOR mask.
2758	* @param cbSrcXorLine The scanline length of the XOR mask.
2759	*/
2760	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState,
2761	SVGAFifoCmdDefineCursor const *pCursor,
2762	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2763	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2764	{
2765	uint32_t const cx = pCursor->width;
2766	uint32_t const cy = pCursor->height;
2767
2768	/*
2769	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2770	* The AND data uses 8-bit aligned scanlines.
2771	* The XOR data must be starting on a 32-bit boundrary.
2772	*/
2773	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2774	uint32_t cbDstAndMask = cbDstAndLine * cy;
2775	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2776	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2777
2778	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2779	AssertReturnVoid(pbCopy);
2780
2781	/* Convert the AND mask. */
2782	uint8_t *pbDst = pbCopy;
2783	uint8_t const *pbSrc = pbSrcAndMask;
2784	switch (pCursor->andMaskDepth)
2785	{
2786	case 1:
2787	if (cbSrcAndLine == cbDstAndLine)
2788	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2789	else
2790	{
2791	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2792	for (uint32_t y = 0; y < cy; y++)
2793	{
2794	memcpy(pbDst, pbSrc, cbDstAndLine);
2795	pbDst += cbDstAndLine;
2796	pbSrc += cbSrcAndLine;
2797	}
2798	}
2799	break;
2800	/* Should take the XOR mask into account for the multi-bit AND mask. */
2801	case 8:
2802	for (uint32_t y = 0; y < cy; y++)
2803	{
2804	for (uint32_t x = 0; x < cx; )
2805	{
2806	uint8_t bDst = 0;
2807	uint8_t fBit = 0x80;
2808	do
2809	{
2810	uintptr_t const idxPal = pbSrc[x] * 3;
2811	if ((( pThis->last_palette[idxPal]
2812	\| (pThis->last_palette[idxPal] >> 8)
2813	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2814	bDst \|= fBit;
2815	fBit >>= 1;
2816	x++;
2817	} while (x < cx && (x & 7));
2818	pbDst[(x - 1) / 8] = bDst;
2819	}
2820	pbDst += cbDstAndLine;
2821	pbSrc += cbSrcAndLine;
2822	}
2823	break;
2824	case 15:
2825	for (uint32_t y = 0; y < cy; y++)
2826	{
2827	for (uint32_t x = 0; x < cx; )
2828	{
2829	uint8_t bDst = 0;
2830	uint8_t fBit = 0x80;
2831	do
2832	{
2833	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2834	bDst \|= fBit;
2835	fBit >>= 1;
2836	x++;
2837	} while (x < cx && (x & 7));
2838	pbDst[(x - 1) / 8] = bDst;
2839	}
2840	pbDst += cbDstAndLine;
2841	pbSrc += cbSrcAndLine;
2842	}
2843	break;
2844	case 16:
2845	for (uint32_t y = 0; y < cy; y++)
2846	{
2847	for (uint32_t x = 0; x < cx; )
2848	{
2849	uint8_t bDst = 0;
2850	uint8_t fBit = 0x80;
2851	do
2852	{
2853	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2854	bDst \|= fBit;
2855	fBit >>= 1;
2856	x++;
2857	} while (x < cx && (x & 7));
2858	pbDst[(x - 1) / 8] = bDst;
2859	}
2860	pbDst += cbDstAndLine;
2861	pbSrc += cbSrcAndLine;
2862	}
2863	break;
2864	case 24:
2865	for (uint32_t y = 0; y < cy; y++)
2866	{
2867	for (uint32_t x = 0; x < cx; )
2868	{
2869	uint8_t bDst = 0;
2870	uint8_t fBit = 0x80;
2871	do
2872	{
2873	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2874	bDst \|= fBit;
2875	fBit >>= 1;
2876	x++;
2877	} while (x < cx && (x & 7));
2878	pbDst[(x - 1) / 8] = bDst;
2879	}
2880	pbDst += cbDstAndLine;
2881	pbSrc += cbSrcAndLine;
2882	}
2883	break;
2884	case 32:
2885	for (uint32_t y = 0; y < cy; y++)
2886	{
2887	for (uint32_t x = 0; x < cx; )
2888	{
2889	uint8_t bDst = 0;
2890	uint8_t fBit = 0x80;
2891	do
2892	{
2893	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2894	bDst \|= fBit;
2895	fBit >>= 1;
2896	x++;
2897	} while (x < cx && (x & 7));
2898	pbDst[(x - 1) / 8] = bDst;
2899	}
2900	pbDst += cbDstAndLine;
2901	pbSrc += cbSrcAndLine;
2902	}
2903	break;
2904	default:
2905	RTMemFree(pbCopy);
2906	AssertFailedReturnVoid();
2907	}
2908
2909	/* Convert the XOR mask. */
2910	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2911	pbSrc = pbSrcXorMask;
2912	switch (pCursor->xorMaskDepth)
2913	{
2914	case 1:
2915	for (uint32_t y = 0; y < cy; y++)
2916	{
2917	for (uint32_t x = 0; x < cx; )
2918	{
2919	/* most significant bit is the left most one. */
2920	uint8_t bSrc = pbSrc[x / 8];
2921	do
2922	{
2923	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2924	bSrc <<= 1;
2925	x++;
2926	} while ((x & 7) && x < cx);
2927	}
2928	pbSrc += cbSrcXorLine;
2929	}
2930	break;
2931	case 8:
2932	for (uint32_t y = 0; y < cy; y++)
2933	{
2934	for (uint32_t x = 0; x < cx; x++)
2935	{
2936	uint32_t u = pThis->last_palette[pbSrc[x]];
2937	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2938	}
2939	pbSrc += cbSrcXorLine;
2940	}
2941	break;
2942	case 15: /* Src: RGB-5-5-5 */
2943	for (uint32_t y = 0; y < cy; y++)
2944	{
2945	for (uint32_t x = 0; x < cx; x++)
2946	{
2947	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2948	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2949	((uValue >> 5) & 0x1f) << 3,
2950	((uValue >> 10) & 0x1f) << 3, 0);
2951	}
2952	pbSrc += cbSrcXorLine;
2953	}
2954	break;
2955	case 16: /* Src: RGB-5-6-5 */
2956	for (uint32_t y = 0; y < cy; y++)
2957	{
2958	for (uint32_t x = 0; x < cx; x++)
2959	{
2960	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2961	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2962	((uValue >> 5) & 0x3f) << 2,
2963	((uValue >> 11) & 0x1f) << 3, 0);
2964	}
2965	pbSrc += cbSrcXorLine;
2966	}
2967	break;
2968	case 24:
2969	for (uint32_t y = 0; y < cy; y++)
2970	{
2971	for (uint32_t x = 0; x < cx; x++)
2972	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2973	pbSrc += cbSrcXorLine;
2974	}
2975	break;
2976	case 32:
2977	for (uint32_t y = 0; y < cy; y++)
2978	{
2979	for (uint32_t x = 0; x < cx; x++)
2980	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2981	pbSrc += cbSrcXorLine;
2982	}
2983	break;
2984	default:
2985	RTMemFree(pbCopy);
2986	AssertFailedReturnVoid();
2987	}
2988
2989	/*
2990	* Pass it to the frontend/whatever.
2991	*/
2992	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2993	}
2994
2995
2996	/**
2997	* Worker for vmsvgaR3FifoThread that handles an external command.
2998	*
2999	* @param pDevIns The device instance.
3000	* @param pThis The shared VGA/VMSVGA instance data.
3001	* @param pThisCC The VGA/VMSVGA state for ring-3.
3002	*/
3003	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3004	{
3005	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
3006	switch (pThis->svga.u8FIFOExtCommand)
3007	{
3008	case VMSVGA_FIFO_EXTCMD_RESET:
3009	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
3010	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3011	# ifdef VBOX_WITH_VMSVGA3D
3012	if (pThis->svga.f3DEnabled)
3013	{
3014	/* The 3d subsystem must be reset from the fifo thread. */
3015	vmsvga3dReset(pThisCC);
3016	}
3017	# endif
3018	break;
3019
3020	case VMSVGA_FIFO_EXTCMD_TERMINATE:
3021	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
3022	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3023	# ifdef VBOX_WITH_VMSVGA3D
3024	if (pThis->svga.f3DEnabled)
3025	{
3026	/* The 3d subsystem must be shut down from the fifo thread. */
3027	vmsvga3dTerminate(pThisCC);
3028	}
3029	# endif
3030	break;
3031
3032	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
3033	{
3034	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
3035	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
3036	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
3037	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
3038	# ifdef VBOX_WITH_VMSVGA3D
3039	if (pThis->svga.f3DEnabled)
3040	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
3041	# endif
3042	break;
3043	}
3044
3045	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
3046	{
3047	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
3048	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
3049	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
3050	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3051	# ifdef VBOX_WITH_VMSVGA3D
3052	if (pThis->svga.f3DEnabled)
3053	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3054	# endif
3055	break;
3056	}
3057
3058	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
3059	{
3060	# ifdef VBOX_WITH_VMSVGA3D
3061	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
3062	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
3063	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
3064	# endif
3065	break;
3066	}
3067
3068
3069	default:
3070	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
3071	break;
3072	}
3073
3074	/*
3075	* Signal the end of the external command.
3076	*/
3077	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3078	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
3079	ASMMemoryFence(); /* paranoia^2 */
3080	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
3081	AssertLogRelRC(rc);
3082	}
3083
3084	/**
3085	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
3086	* doing a job on the FIFO thread (even when it's officially suspended).
3087	*
3088	* @returns VBox status code (fully asserted).
3089	* @param pDevIns The device instance.
3090	* @param pThis The shared VGA/VMSVGA instance data.
3091	* @param pThisCC The VGA/VMSVGA state for ring-3.
3092	* @param uExtCmd The command to execute on the FIFO thread.
3093	* @param pvParam Pointer to command parameters.
3094	* @param cMsWait The time to wait for the command, given in
3095	* milliseconds.
3096	*/
3097	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
3098	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
3099	{
3100	Assert(cMsWait >= RT_MS_1SEC * 5);
3101	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
3102	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
3103
3104	int rc;
3105	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
3106	PDMTHREADSTATE enmState = pThread->enmState;
3107	if (enmState == PDMTHREADSTATE_SUSPENDED)
3108	{
3109	/*
3110	* The thread is suspended, we have to temporarily wake it up so it can
3111	* perform the task.
3112	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
3113	*/
3114	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
3115	/* Post the request. */
3116	pThis->svga.fFifoExtCommandWakeup = true;
3117	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3118	pThis->svga.u8FIFOExtCommand = uExtCmd;
3119	ASMMemoryFence(); /* paranoia^3 */
3120
3121	/* Resume the thread. */
3122	rc = PDMDevHlpThreadResume(pDevIns, pThread);
3123	AssertLogRelRC(rc);
3124	if (RT_SUCCESS(rc))
3125	{
3126	/* Wait. Take care in case the semaphore was already posted (same as below). */
3127	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3128	if ( rc == VINF_SUCCESS
3129	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3130	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3131	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3132	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3133
3134	/* suspend the thread */
3135	pThis->svga.fFifoExtCommandWakeup = false;
3136	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
3137	AssertLogRelRC(rc2);
3138	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3139	rc = rc2;
3140	}
3141	pThis->svga.fFifoExtCommandWakeup = false;
3142	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3143	}
3144	else if (enmState == PDMTHREADSTATE_RUNNING)
3145	{
3146	/*
3147	* The thread is running, should only happen during reset and vmsvga3dsfc.
3148	* We ASSUME not racing code here, both wrt thread state and ext commands.
3149	*/
3150	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3151	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
3152
3153	/* Post the request. */
3154	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3155	pThis->svga.u8FIFOExtCommand = uExtCmd;
3156	ASMMemoryFence(); /* paranoia^2 */
3157	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3158	AssertLogRelRC(rc);
3159
3160	/* Wait. Take care in case the semaphore was already posted (same as above). */
3161	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3162	if ( rc == VINF_SUCCESS
3163	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3164	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3165	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3166	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3167
3168	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3169	}
3170	else
3171	{
3172	/*
3173	* Something is wrong with the thread!
3174	*/
3175	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3176	rc = VERR_INVALID_STATE;
3177	}
3178	return rc;
3179	}
3180
3181
3182	/**
3183	* Marks the FIFO non-busy, notifying any waiting EMTs.
3184	*
3185	* @param pDevIns The device instance.
3186	* @param pThis The shared VGA/VMSVGA instance data.
3187	* @param pThisCC The VGA/VMSVGA state for ring-3.
3188	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3189	* @param offFifoMin The start byte offset of the command FIFO.
3190	*/
3191	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3192	{
3193	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
3194	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3195	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
3196
3197	/* Wake up any waiting EMTs. */
3198	if (pSVGAState->cBusyDelayedEmts > 0)
3199	{
3200	# ifdef VMSVGA_USE_EMT_HALT_CODE
3201	PVM pVM = PDMDevHlpGetVM(pDevIns);
3202	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3203	if (idCpu != NIL_VMCPUID)
3204	{
3205	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3206	while (idCpu-- > 0)
3207	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3208	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3209	}
3210	# else
3211	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3212	AssertRC(rc2);
3213	# endif
3214	}
3215	}
3216
3217	/**
3218	* Reads (more) payload into the command buffer.
3219	*
3220	* @returns pbBounceBuf on success
3221	* @retval (void *)1 if the thread was requested to stop.
3222	* @retval NULL on FIFO error.
3223	*
3224	* @param cbPayloadReq The number of bytes of payload requested.
3225	* @param pFIFO The FIFO.
3226	* @param offCurrentCmd The FIFO byte offset of the current command.
3227	* @param offFifoMin The start byte offset of the command FIFO.
3228	* @param offFifoMax The end byte offset of the command FIFO.
3229	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3230	* always sufficient size.
3231	* @param pcbAlreadyRead How much payload we've already read into the bounce
3232	* buffer. (We will NEVER re-read anything.)
3233	* @param pThread The calling PDM thread handle.
3234	* @param pThis The shared VGA/VMSVGA instance data.
3235	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3236	* statistics collection.
3237	* @param pDevIns The device instance.
3238	*/
3239	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3240	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3241	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3242	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
3243	{
3244	Assert(pbBounceBuf);
3245	Assert(pcbAlreadyRead);
3246	Assert(offFifoMin < offFifoMax);
3247	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3248	Assert(offFifoMax <= pThis->svga.cbFIFO);
3249
3250	/*
3251	* Check if the requested payload size has already been satisfied .
3252	* .
3253	* When called to read more, the caller is responsible for making sure the .
3254	* new command size (cbRequsted) never is smaller than what has already .
3255	* been read.
3256	*/
3257	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3258	if (cbPayloadReq <= cbAlreadyRead)
3259	{
3260	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3261	return pbBounceBuf;
3262	}
3263
3264	/*
3265	* Commands bigger than the fifo buffer are invalid.
3266	*/
3267	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3268	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3269	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3270	NULL);
3271
3272	/*
3273	* Move offCurrentCmd past the command dword.
3274	*/
3275	offCurrentCmd += sizeof(uint32_t);
3276	if (offCurrentCmd >= offFifoMax)
3277	offCurrentCmd = offFifoMin;
3278
3279	/*
3280	* Do we have sufficient payload data available already?
3281	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3282	*/
3283	uint32_t cbAfter, cbBefore;
3284	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3285	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3286	if (offNextCmd >= offCurrentCmd)
3287	{
3288	if (RT_LIKELY(offNextCmd < offFifoMax))
3289	cbAfter = offNextCmd - offCurrentCmd;
3290	else
3291	{
3292	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3293	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3294	offNextCmd, offFifoMin, offFifoMax));
3295	cbAfter = offFifoMax - offCurrentCmd;
3296	}
3297	cbBefore = 0;
3298	}
3299	else
3300	{
3301	cbAfter = offFifoMax - offCurrentCmd;
3302	if (offNextCmd >= offFifoMin)
3303	cbBefore = offNextCmd - offFifoMin;
3304	else
3305	{
3306	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3307	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3308	offNextCmd, offFifoMin, offFifoMax));
3309	cbBefore = 0;
3310	}
3311	}
3312	if (cbAfter + cbBefore < cbPayloadReq)
3313	{
3314	/*
3315	* Insufficient, must wait for it to arrive.
3316	*/
3317	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3318	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3319	for (uint32_t i = 0;; i++)
3320	{
3321	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3322	{
3323	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3324	return (void *)(uintptr_t)1;
3325	}
3326	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3327	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3328
3329	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
3330
3331	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3332	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3333	if (offNextCmd >= offCurrentCmd)
3334	{
3335	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3336	cbBefore = 0;
3337	}
3338	else
3339	{
3340	cbAfter = offFifoMax - offCurrentCmd;
3341	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3342	}
3343
3344	if (cbAfter + cbBefore >= cbPayloadReq)
3345	break;
3346	}
3347	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3348	}
3349
3350	/*
3351	* Copy out the memory and update what pcbAlreadyRead points to.
3352	*/
3353	if (cbAfter >= cbPayloadReq)
3354	memcpy(pbBounceBuf + cbAlreadyRead,
3355	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3356	cbPayloadReq - cbAlreadyRead);
3357	else
3358	{
3359	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3360	if (cbAlreadyRead < cbAfter)
3361	{
3362	memcpy(pbBounceBuf + cbAlreadyRead,
3363	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3364	cbAfter - cbAlreadyRead);
3365	cbAlreadyRead = cbAfter;
3366	}
3367	memcpy(pbBounceBuf + cbAlreadyRead,
3368	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3369	cbPayloadReq - cbAlreadyRead);
3370	}
3371	*pcbAlreadyRead = cbPayloadReq;
3372	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3373	return pbBounceBuf;
3374	}
3375
3376
3377	/**
3378	* Sends cursor position and visibility information from the FIFO to the front-end.
3379	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3380	*/
3381	static uint32_t
3382	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3383	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3384	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3385	{
3386	/*
3387	* Check if the cursor update counter has changed and try get a stable
3388	* set of values if it has. This is race-prone, especially consindering
3389	* the screen ID, but little we can do about that.
3390	*/
3391	uint32_t x, y, fVisible, idScreen;
3392	for (uint32_t i = 0; ; i++)
3393	{
3394	x = pFIFO[SVGA_FIFO_CURSOR_X];
3395	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3396	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3397	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3398	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3399	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3400	\|\| i > 3)
3401	break;
3402	if (i == 0)
3403	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3404	ASMNopPause();
3405	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3406	}
3407
3408	/*
3409	* Check if anything has changed, as calling into pDrv is not light-weight.
3410	*/
3411	if ( *pxLast == x
3412	&& *pyLast == y
3413	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3414	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3415	else
3416	{
3417	/*
3418	* Detected changes.
3419	*
3420	* We handle global, not per-screen visibility information by sending
3421	* pfnVBVAMousePointerShape without shape data.
3422	*/
3423	*pxLast = x;
3424	*pyLast = y;
3425	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3426	if (idScreen != SVGA_ID_INVALID)
3427	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3428	else if (*pfLastVisible != fVisible)
3429	{
3430	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
3431	*pfLastVisible = fVisible;
3432	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3433	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3434	}
3435	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
3436	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3437	}
3438
3439	/*
3440	* Update done. Signal this to the guest.
3441	*/
3442	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3443
3444	return uCursorUpdateCount;
3445	}
3446
3447
3448	/**
3449	* Checks if there is work to be done, either cursor updating or FIFO commands.
3450	*
3451	* @returns true if pending work, false if not.
3452	* @param pFIFO The FIFO to examine.
3453	* @param uLastCursorCount The last cursor update counter value.
3454	*/
3455	DECLINLINE(bool) vmsvgaR3FifoHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3456	{
3457	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3458	return true;
3459
3460	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3461	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3462	return true;
3463
3464	return false;
3465	}
3466
3467
3468	/**
3469	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3470	*
3471	* @param pDevIns The device instance.
3472	* @param pThis The shared VGA/VMSVGA instance data.
3473	* @param pThisCC The VGA/VMSVGA state for ring-3.
3474	*/
3475	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3476	{
3477	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3478	to recheck it before doing the signalling. */
3479	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3480	AssertReturnVoid(pFIFO);
3481	if ( vmsvgaR3FifoHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
3482	&& pThis->svga.fFIFOThreadSleeping)
3483	{
3484	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3485	AssertRC(rc);
3486	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3487	}
3488	}
3489
3490
3491	/*
3492	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
3493	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
3494	*/
3495	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3496	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
3497	*
3498	* Will break out of the switch on failure.
3499	* Will restart and quit the loop if the thread was requested to stop.
3500	*
3501	* @param a_PtrVar Request variable pointer.
3502	* @param a_Type Request typedef (not pointer) for casting.
3503	* @param a_cbPayloadReq How much payload to fetch.
3504	* @remarks Accesses a bunch of variables in the current scope!
3505	*/
3506	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3507	if (1) { \
3508	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3509	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
3510	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3511	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3512	} else do {} while (0)
3513	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3514	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
3515	* buffer after figuring out the actual command size.
3516	*
3517	* Will break out of the switch on failure.
3518	*
3519	* @param a_PtrVar Request variable pointer.
3520	* @param a_Type Request typedef (not pointer) for casting.
3521	* @param a_cbPayloadReq How much payload to fetch.
3522	* @remarks Accesses a bunch of variables in the current scope!
3523	*/
3524	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3525	if (1) { \
3526	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3527	} else do {} while (0)
3528
3529	/**
3530	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
3531	*/
3532	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3533	{
3534	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3535	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3536	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3537	int rc;
3538
3539	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3540	return VINF_SUCCESS;
3541
3542	/*
3543	* Special mode where we only execute an external command and the go back
3544	* to being suspended. Currently, all ext cmds ends up here, with the reset
3545	* one also being eligble for runtime execution further down as well.
3546	*/
3547	if (pThis->svga.fFifoExtCommandWakeup)
3548	{
3549	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3550	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3551	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3552	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
3553	else
3554	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3555	return VINF_SUCCESS;
3556	}
3557
3558
3559	/*
3560	* Signal the semaphore to make sure we don't wait for 250ms after a
3561	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
3562	*/
3563	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3564
3565	/*
3566	* Allocate a bounce buffer for command we get from the FIFO.
3567	* (All code must return via the end of the function to free this buffer.)
3568	*/
3569	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3570	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3571
3572	/*
3573	* Polling/sleep interval config.
3574	*
3575	* We wait for an a short interval if the guest has recently given us work
3576	* to do, but the interval increases the longer we're kept idle. Once we've
3577	* reached the refresh timer interval, we'll switch to extended waits,
3578	* depending on it or the guest to kick us into action when needed.
3579	*
3580	* Should the refresh time go fishing, we'll just continue increasing the
3581	* sleep length till we reaches the 250 ms max after about 16 seconds.
3582	*/
3583	RTMSINTERVAL const cMsMinSleep = 16;
3584	RTMSINTERVAL const cMsIncSleep = 2;
3585	RTMSINTERVAL const cMsMaxSleep = 250;
3586	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3587	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3588
3589	/*
3590	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3591	*
3592	* Initialize with values that will detect an update from the guest.
3593	* Make sure that if the guest never updates the cursor position, then the device does not report it.
3594	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
3595	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
3596	*/
3597	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3598	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3599	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3600	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3601	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3602
3603	/*
3604	* The FIFO loop.
3605	*/
3606	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
3607	bool fBadOrDisabledFifo = false;
3608	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3609	{
3610	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3611	/*
3612	* Should service the run loop every so often.
3613	*/
3614	if (pThis->svga.f3DEnabled)
3615	vmsvga3dCocoaServiceRunLoop();
3616	# endif
3617
3618	/*
3619	* Unless there's already work pending, go to sleep for a short while.
3620	* (See polling/sleep interval config above.)
3621	*/
3622	if ( fBadOrDisabledFifo
3623	\|\| !vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3624	{
3625	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3626	Assert(pThis->cMilliesRefreshInterval > 0);
3627	if (cMsSleep < pThis->cMilliesRefreshInterval)
3628	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
3629	else
3630	{
3631	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3632	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3633	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3634	# endif
3635	if ( !fBadOrDisabledFifo
3636	&& vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3637	rc = VINF_SUCCESS;
3638	else
3639	{
3640	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3641	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
3642	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3643	}
3644	}
3645	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3646	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3647	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3648	{
3649	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
3650	break;
3651	}
3652	}
3653	else
3654	rc = VINF_SUCCESS;
3655	fBadOrDisabledFifo = false;
3656	if (rc == VERR_TIMEOUT)
3657	{
3658	if (!vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3659	{
3660	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3661	continue;
3662	}
3663	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3664
3665	Log(("vmsvgaR3FifoLoop: timeout\n"));
3666	}
3667	else if (vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3668	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3669	cMsSleep = cMsMinSleep;
3670
3671	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
3672	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3673	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3674
3675	/*
3676	* Handle external commands (currently only reset).
3677	*/
3678	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3679	{
3680	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3681	continue;
3682	}
3683
3684	/*
3685	* The device must be enabled and configured.
3686	*/
3687	if ( !pThis->svga.fEnabled
3688	\|\| !pThis->svga.fConfigured)
3689	{
3690	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3691	fBadOrDisabledFifo = true;
3692	cMsSleep = cMsMaxSleep; /* cheat */
3693	continue;
3694	}
3695
3696	/*
3697	* Get and check the min/max values. We ASSUME that they will remain
3698	* unchanged while we process requests. A further ASSUMPTION is that
3699	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3700	* we don't read it back while in the loop.
3701	*/
3702	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3703	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3704	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3705	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3706	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3707	\|\| offFifoMax <= offFifoMin
3708	\|\| offFifoMax > pThis->svga.cbFIFO
3709	\|\| (offFifoMax & 3) != 0
3710	\|\| (offFifoMin & 3) != 0
3711	\|\| offCurrentCmd < offFifoMin
3712	\|\| offCurrentCmd > offFifoMax))
3713	{
3714	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3715	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3716	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
3717	fBadOrDisabledFifo = true;
3718	continue;
3719	}
3720	RT_UNTRUSTED_VALIDATED_FENCE();
3721	if (RT_UNLIKELY(offCurrentCmd & 3))
3722	{
3723	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3724	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3725	offCurrentCmd &= ~UINT32_C(3);
3726	}
3727
3728	/*
3729	* Update the cursor position before we start on the FIFO commands.
3730	*/
3731	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3732	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3733	{
3734	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3735	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
3736	{ /* halfways likely */ }
3737	else
3738	{
3739	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3740	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3741	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
3742	}
3743	}
3744
3745	/*
3746	* Mark the FIFO as busy.
3747	*/
3748	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3749	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3750	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3751
3752	/*
3753	* Execute all queued FIFO commands.
3754	* Quit if pending external command or changes in the thread state.
3755	*/
3756	bool fDone = false;
3757	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3758	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3759	{
3760	uint32_t cbPayload = 0;
3761	uint32_t u32IrqStatus = 0;
3762
3763	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3764
3765	/* First check any pending actions. */
3766	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3767	{
3768	vmsvgaR3ChangeMode(pThis, pThisCC);
3769	# ifdef VBOX_WITH_VMSVGA3D
3770	if (pThisCC->svga.p3dState != NULL)
3771	vmsvga3dChangeMode(pThisCC);
3772	# endif
3773	}
3774
3775	/* Check for pending external commands (reset). */
3776	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3777	break;
3778
3779	/*
3780	* Process the command.
3781	*/
3782	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3783	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3784	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3785	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
3786	switch (enmCmdId)
3787	{
3788	case SVGA_CMD_INVALID_CMD:
3789	/* Nothing to do. */
3790	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3791	break;
3792
3793	case SVGA_CMD_FENCE:
3794	{
3795	SVGAFifoCmdFence *pCmdFence;
3796	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3797	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3798	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3799	{
3800	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3801	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3802
3803	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3804	{
3805	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
3806	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3807	}
3808	else
3809	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3810	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3811	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3812	{
3813	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3814	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3815	}
3816	}
3817	else
3818	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3819	break;
3820	}
3821	case SVGA_CMD_UPDATE:
3822	case SVGA_CMD_UPDATE_VERBOSE:
3823	{
3824	SVGAFifoCmdUpdate *pUpdate;
3825	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3826	if (enmCmdId == SVGA_CMD_UPDATE)
3827	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3828	else
3829	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3830	Log(("vmsvgaR3FifoLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3831	/** @todo Multiple screens? */
3832	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
3833	AssertBreak(pScreen);
3834	vmsvgaR3UpdateScreen(pThisCC, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3835	break;
3836	}
3837
3838	case SVGA_CMD_DEFINE_CURSOR:
3839	{
3840	/* Followed by bitmap data. */
3841	SVGAFifoCmdDefineCursor *pCursor;
3842	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3843	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3844
3845	Log(("vmsvgaR3FifoLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3846	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3847	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3848	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3849	AssertBreak(pCursor->andMaskDepth <= 32);
3850	AssertBreak(pCursor->xorMaskDepth <= 32);
3851	RT_UNTRUSTED_VALIDATED_FENCE();
3852
3853	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3854	uint32_t cbAndMask = cbAndLine * pCursor->height;
3855	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3856	uint32_t cbXorMask = cbXorLine * pCursor->height;
3857	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3858
3859	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3860	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3861	break;
3862	}
3863
3864	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3865	{
3866	/* Followed by bitmap data. */
3867	uint32_t cbCursorShape, cbAndMask;
3868	uint8_t *pCursorCopy;
3869	uint32_t cbCmd;
3870
3871	SVGAFifoCmdDefineAlphaCursor *pCursor;
3872	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3873	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3874
3875	Log(("vmsvgaR3FifoLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3876
3877	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3878	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3879	RT_UNTRUSTED_VALIDATED_FENCE();
3880
3881	/* Refetch the bitmap data as well. */
3882	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3883	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3884	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3885
3886	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3887	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3888	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3889	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3890
3891	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3892	AssertBreak(pCursorCopy);
3893
3894	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3895	memset(pCursorCopy, 0xff, cbAndMask);
3896	/* Colour data */
3897	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3898
3899	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3900	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3901	break;
3902	}
3903
3904	case SVGA_CMD_MOVE_CURSOR:
3905	{
3906	/* Deprecated; there should be no driver which requires this command. However, if
3907	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3908	* alignment.
3909	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3910	*/
3911	SVGAFifoCmdMoveCursor *pMoveCursor;
3912	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pMoveCursor, SVGAFifoCmdMoveCursor, sizeof(*pMoveCursor));
3913	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdMoveCursor);
3914
3915	Log(("vmsvgaR3FifoLoop: MOVE CURSOR to %d,%d\n", pMoveCursor->pos.x, pMoveCursor->pos.y));
3916	LogRelMax(4, ("Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
3917	break;
3918	}
3919
3920	case SVGA_CMD_DISPLAY_CURSOR:
3921	{
3922	/* Deprecated; there should be no driver which requires this command. However, if
3923	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3924	* alignment.
3925	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3926	*/
3927	SVGAFifoCmdDisplayCursor *pDisplayCursor;
3928	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pDisplayCursor, SVGAFifoCmdDisplayCursor, sizeof(*pDisplayCursor));
3929	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDisplayCursor);
3930
3931	Log(("vmsvgaR3FifoLoop: DISPLAY CURSOR id=%d state=%d\n", pDisplayCursor->id, pDisplayCursor->state));
3932	LogRelMax(4, ("Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
3933	break;
3934	}
3935
3936	case SVGA_CMD_ESCAPE:
3937	{
3938	/* Followed by nsize bytes of data. */
3939	SVGAFifoCmdEscape *pEscape;
3940	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3941	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3942
3943	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3944	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3945	RT_UNTRUSTED_VALIDATED_FENCE();
3946	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3947	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3948
3949	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3950	{
3951	AssertBreak(pEscape->size >= sizeof(uint32_t));
3952	RT_UNTRUSTED_VALIDATED_FENCE();
3953	uint32_t cmd = (uint32_t )(pEscape + 1);
3954	Log(("vmsvgaR3FifoLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3955
3956	switch (cmd)
3957	{
3958	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3959	{
3960	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3961	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3962	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3963
3964	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3965	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3966	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3967
3968	RT_NOREF_PV(pVideoCmd);
3969	break;
3970
3971	}
3972
3973	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3974	{
3975	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3976	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3977	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3978	RT_NOREF_PV(pVideoCmd);
3979	break;
3980	}
3981
3982	default:
3983	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
3984	break;
3985	}
3986	}
3987	else
3988	Log(("vmsvgaR3FifoLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3989
3990	break;
3991	}
3992	# ifdef VBOX_WITH_VMSVGA3D
3993	case SVGA_CMD_DEFINE_GMR2:
3994	{
3995	SVGAFifoCmdDefineGMR2 *pCmd;
3996	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3997	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3998	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3999
4000	/* Validate current GMR id. */
4001	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
4002	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
4003	RT_UNTRUSTED_VALIDATED_FENCE();
4004
4005	if (!pCmd->numPages)
4006	{
4007	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
4008	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
4009	}
4010	else
4011	{
4012	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
4013	if (pGMR->cMaxPages)
4014	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
4015
4016	/* Not sure if we should always free the descriptor, but for simplicity
4017	we do so if the new size is smaller than the current. */
4018	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
4019	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
4020	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
4021
4022	pGMR->cMaxPages = pCmd->numPages;
4023	/* The rest is done by the REMAP_GMR2 command. */
4024	}
4025	break;
4026	}
4027
4028	case SVGA_CMD_REMAP_GMR2:
4029	{
4030	/* Followed by page descriptors or guest ptr. */
4031	SVGAFifoCmdRemapGMR2 *pCmd;
4032	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
4033	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
4034
4035	Log(("vmsvgaR3FifoLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
4036	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
4037	RT_UNTRUSTED_VALIDATED_FENCE();
4038
4039	/* Calculate the size of what comes after next and fetch it. */
4040	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
4041	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4042	cbCmd += sizeof(SVGAGuestPtr);
4043	else
4044	{
4045	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
4046	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
4047	{
4048	cbCmd += cbPageDesc;
4049	pCmd->numPages = 1;
4050	}
4051	else
4052	{
4053	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
4054	cbCmd += cbPageDesc * pCmd->numPages;
4055	}
4056	}
4057	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
4058
4059	/* Validate current GMR id and size. */
4060	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
4061	RT_UNTRUSTED_VALIDATED_FENCE();
4062	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
4063	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
4064	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
4065	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
4066
4067	if (pCmd->numPages == 0)
4068	break;
4069
4070	/** @todo Move to a separate function vmsvgaGMRRemap() */
4071
4072	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
4073	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
4074
4075	/*
4076	* We flatten the existing descriptors into a page array, overwrite the
4077	* pages specified in this command and then recompress the descriptor.
4078	*/
4079	/** @todo Optimize the GMR remap algorithm! */
4080
4081	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
4082	uint64_t *paNewPage64 = NULL;
4083	if (pGMR->paDesc)
4084	{
4085	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
4086
4087	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
4088	AssertBreak(paNewPage64);
4089
4090	uint32_t idxPage = 0;
4091	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
4092	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
4093	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
4094	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
4095	RT_UNTRUSTED_VALIDATED_FENCE();
4096	}
4097
4098	/* Free the old GMR if present. */
4099	if (pGMR->paDesc)
4100	RTMemFree(pGMR->paDesc);
4101
4102	/* Allocate the maximum amount possible (everything non-continuous) */
4103	PVMSVGAGMRDESCRIPTOR paDescs;
4104	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
4105	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
4106
4107	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4108	{
4109	/** @todo */
4110	AssertFailed();
4111	pGMR->numDescriptors = 0;
4112	}
4113	else
4114	{
4115	uint32_t paPages32 = (uint32_t )(pCmd + 1);
4116	uint64_t paPages64 = (uint64_t )(pCmd + 1);
4117	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
4118
4119	if (paNewPage64)
4120	{
4121	/* Overwrite the old page array with the new page values. */
4122	if (fGCPhys64)
4123	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
4124	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
4125	else
4126	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
4127	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
4128
4129	/* Use the updated page array instead of the command data. */
4130	fGCPhys64 = true;
4131	paPages64 = paNewPage64;
4132	pCmd->numPages = cNewTotalPages;
4133	}
4134
4135	/* The first page. */
4136	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
4137	* applied to paNewPage64. */
4138	RTGCPHYS GCPhys;
4139	if (fGCPhys64)
4140	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4141	else
4142	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
4143	paDescs[0].GCPhys = GCPhys;
4144	paDescs[0].numPages = 1;
4145
4146	/* Subsequent pages. */
4147	uint32_t iDescriptor = 0;
4148	for (uint32_t i = 1; i < pCmd->numPages; i++)
4149	{
4150	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
4151	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4152	else
4153	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
4154
4155	/* Continuous physical memory? */
4156	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
4157	{
4158	Assert(paDescs[iDescriptor].numPages);
4159	paDescs[iDescriptor].numPages++;
4160	Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
4161	}
4162	else
4163	{
4164	iDescriptor++;
4165	paDescs[iDescriptor].GCPhys = GCPhys;
4166	paDescs[iDescriptor].numPages = 1;
4167	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
4168	}
4169	}
4170
4171	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
4172	Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
4173	pGMR->numDescriptors = iDescriptor + 1;
4174	}
4175
4176	if (paNewPage64)
4177	RTMemFree(paNewPage64);
4178
4179	# ifdef DEBUG_GMR_ACCESS
4180	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
4181	# endif
4182	break;
4183	}
4184	# endif // VBOX_WITH_VMSVGA3D
4185	case SVGA_CMD_DEFINE_SCREEN:
4186	{
4187	/* The size of this command is specified by the guest and depends on capabilities. */
4188	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4189
4190	SVGAFifoCmdDefineScreen *pCmd;
4191	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4192	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4193	RT_UNTRUSTED_VALIDATED_FENCE();
4194
4195	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4196	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4197	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4198
4199	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4200	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4201	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4202
4203	uint32_t const idScreen = pCmd->screen.id;
4204	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4205
4206	uint32_t const uWidth = pCmd->screen.size.width;
4207	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4208
4209	uint32_t const uHeight = pCmd->screen.size.height;
4210	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4211
4212	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4213	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4214	AssertBreak(cbWidth <= cbPitch);
4215
4216	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4217	AssertBreak(uScreenOffset < pThis->vram_size);
4218
4219	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4220	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4221	AssertBreak( (uHeight == 0 && cbPitch == 0)
4222	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4223	RT_UNTRUSTED_VALIDATED_FENCE();
4224
4225	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4226
4227	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4228
4229	pScreen->fDefined = true;
4230	pScreen->fModified = true;
4231	pScreen->fuScreen = pCmd->screen.flags;
4232	pScreen->idScreen = idScreen;
4233	if (!fBlank)
4234	{
4235	AssertBreak(uWidth > 0 && uHeight > 0);
4236
4237	pScreen->xOrigin = pCmd->screen.root.x;
4238	pScreen->yOrigin = pCmd->screen.root.y;
4239	pScreen->cWidth = uWidth;
4240	pScreen->cHeight = uHeight;
4241	pScreen->offVRAM = uScreenOffset;
4242	pScreen->cbPitch = cbPitch;
4243	pScreen->cBpp = 32;
4244	}
4245	else
4246	{
4247	/* Keep old values. */
4248	}
4249
4250	pThis->svga.fGFBRegisters = false;
4251	vmsvgaR3ChangeMode(pThis, pThisCC);
4252	break;
4253	}
4254
4255	case SVGA_CMD_DESTROY_SCREEN:
4256	{
4257	SVGAFifoCmdDestroyScreen *pCmd;
4258	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4259	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4260
4261	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4262
4263	uint32_t const idScreen = pCmd->screenId;
4264	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4265	RT_UNTRUSTED_VALIDATED_FENCE();
4266
4267	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4268	pScreen->fModified = true;
4269	pScreen->fDefined = false;
4270	pScreen->idScreen = idScreen;
4271
4272	vmsvgaR3ChangeMode(pThis, pThisCC);
4273	break;
4274	}
4275
4276	case SVGA_CMD_DEFINE_GMRFB:
4277	{
4278	SVGAFifoCmdDefineGMRFB *pCmd;
4279	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4280	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4281
4282	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4283	pSVGAState->GMRFB.ptr = pCmd->ptr;
4284	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4285	pSVGAState->GMRFB.format = pCmd->format;
4286	break;
4287	}
4288
4289	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4290	{
4291	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4292	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4293	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4294
4295	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4296	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4297
4298	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4299	RT_UNTRUSTED_VALIDATED_FENCE();
4300
4301	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
4302	AssertBreak(pScreen);
4303
4304	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4305	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4306
4307	/* Clip destRect to the screen dimensions. */
4308	SVGASignedRect screenRect;
4309	screenRect.left = 0;
4310	screenRect.top = 0;
4311	screenRect.right = pScreen->cWidth;
4312	screenRect.bottom = pScreen->cHeight;
4313	SVGASignedRect clipRect = pCmd->destRect;
4314	vmsvgaR3ClipRect(&screenRect, &clipRect);
4315	RT_UNTRUSTED_VALIDATED_FENCE();
4316
4317	uint32_t const width = clipRect.right - clipRect.left;
4318	uint32_t const height = clipRect.bottom - clipRect.top;
4319
4320	if ( width == 0
4321	\|\| height == 0)
4322	break; /* Nothing to do. */
4323
4324	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4325	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4326
4327	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4328	* Prepare parameters for vmsvgaR3GmrTransfer.
4329	*/
4330	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4331
4332	/* Destination: host buffer which describes the screen 0 VRAM.
4333	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4334	*/
4335	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4336	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4337	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4338	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4339	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4340	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4341	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4342	+ cbScanline * clipRect.top;
4343	int32_t const cbHstPitch = cbScanline;
4344
4345	/* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4346	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4347	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4348	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4349	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4350
4351	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
4352	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4353	gstPtr, offGst, cbGstPitch,
4354	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4355	AssertRC(rc);
4356	vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
4357	break;
4358	}
4359
4360	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4361	{
4362	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4363	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4364	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4365
4366	/* Note! This can fetch 3d render results as well!! */
4367	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4368	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4369
4370	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4371	RT_UNTRUSTED_VALIDATED_FENCE();
4372
4373	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
4374	AssertBreak(pScreen);
4375
4376	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4377	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4378
4379	/* Clip destRect to the screen dimensions. */
4380	SVGASignedRect screenRect;
4381	screenRect.left = 0;
4382	screenRect.top = 0;
4383	screenRect.right = pScreen->cWidth;
4384	screenRect.bottom = pScreen->cHeight;
4385	SVGASignedRect clipRect = pCmd->srcRect;
4386	vmsvgaR3ClipRect(&screenRect, &clipRect);
4387	RT_UNTRUSTED_VALIDATED_FENCE();
4388
4389	uint32_t const width = clipRect.right - clipRect.left;
4390	uint32_t const height = clipRect.bottom - clipRect.top;
4391
4392	if ( width == 0
4393	\|\| height == 0)
4394	break; /* Nothing to do. */
4395
4396	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4397	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4398
4399	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4400	* Prepare parameters for vmsvgaR3GmrTransfer.
4401	*/
4402	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4403
4404	/* Source: host buffer which describes the screen 0 VRAM.
4405	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4406	*/
4407	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4408	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4409	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4410	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4411	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4412	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4413	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4414	+ cbScanline * clipRect.top;
4415	int32_t const cbHstPitch = cbScanline;
4416
4417	/* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4418	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4419	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4420	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4421	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4422
4423	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
4424	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4425	gstPtr, offGst, cbGstPitch,
4426	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4427	AssertRC(rc);
4428	break;
4429	}
4430
4431	case SVGA_CMD_ANNOTATION_FILL:
4432	{
4433	SVGAFifoCmdAnnotationFill *pCmd;
4434	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4435	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4436
4437	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4438	pSVGAState->colorAnnotation = pCmd->color;
4439	break;
4440	}
4441
4442	case SVGA_CMD_ANNOTATION_COPY:
4443	{
4444	SVGAFifoCmdAnnotationCopy *pCmd;
4445	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4446	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4447
4448	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4449	AssertFailed();
4450	break;
4451	}
4452
4453	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
4454
4455	default:
4456	# ifdef VBOX_WITH_VMSVGA3D
4457	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4458	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4459	{
4460	RT_UNTRUSTED_VALIDATED_FENCE();
4461
4462	/* All 3d commands start with a common header, which defines the size of the command. */
4463	SVGA3dCmdHeader *pHdr;
4464	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4465	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4466	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4467	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4468
4469	if (RT_LIKELY(pThis->svga.f3DEnabled))
4470	{ /* likely */ }
4471	else
4472	{
4473	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4474	break;
4475	}
4476
4477	/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4478	* Check that the 3D command has at least a_cbMin of payload bytes after the
4479	* header. Will break out of the switch if it doesn't.
4480	*/
4481	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4482	if (1) { \
4483	AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4484	RT_UNTRUSTED_VALIDATED_FENCE(); \
4485	} else do {} while (0)
4486	switch ((int)enmCmdId)
4487	{
4488	case SVGA_3D_CMD_SURFACE_DEFINE:
4489	{
4490	uint32_t cMipLevels;
4491	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4492	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4493	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4494
4495	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4496	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4497	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4498	# ifdef DEBUG_GMR_ACCESS
4499	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4500	# endif
4501	break;
4502	}
4503
4504	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4505	{
4506	uint32_t cMipLevels;
4507	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4508	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4509	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4510
4511	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4512	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4513	pCmd->multisampleCount, pCmd->autogenFilter,
4514	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4515	break;
4516	}
4517
4518	case SVGA_3D_CMD_SURFACE_DESTROY:
4519	{
4520	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4521	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4522	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4523	rc = vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
4524	break;
4525	}
4526
4527	case SVGA_3D_CMD_SURFACE_COPY:
4528	{
4529	uint32_t cCopyBoxes;
4530	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4531	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4532	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4533
4534	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4535	rc = vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4536	break;
4537	}
4538
4539	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4540	{
4541	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4542	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4543	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4544
4545	rc = vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
4546	&pCmd->src, &pCmd->boxSrc, pCmd->mode);
4547	break;
4548	}
4549
4550	case SVGA_3D_CMD_SURFACE_DMA:
4551	{
4552	uint32_t cCopyBoxes;
4553	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4554	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4555	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4556
4557	uint64_t u64NanoTS = 0;
4558	if (LogRelIs3Enabled())
4559	u64NanoTS = RTTimeNanoTS();
4560	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4561	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4562	rc = vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
4563	cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4564	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4565	if (LogRelIs3Enabled())
4566	{
4567	if (cCopyBoxes)
4568	{
4569	SVGA3dCopyBox pFirstBox = (SVGA3dCopyBox )(pCmd + 1);
4570	LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
4571	(RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
4572	pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
4573	pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
4574	}
4575	}
4576	break;
4577	}
4578
4579	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4580	{
4581	uint32_t cRects;
4582	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4583	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4584	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4585
4586	uint64_t u64NanoTS = 0;
4587	if (LogRelIs3Enabled())
4588	u64NanoTS = RTTimeNanoTS();
4589	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4590	STAM_REL_PROFILE_START(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4591	rc = vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
4592	pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4593	STAM_REL_PROFILE_STOP(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4594	if (LogRelIs3Enabled())
4595	{
4596	SVGASignedRect pFirstRect = cRects ? (SVGASignedRect )(pCmd + 1) : &pCmd->destRect;
4597	LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
4598	(RTTimeNanoTS() - u64NanoTS) / 1000ULL, cRects,
4599	pFirstRect->left, pFirstRect->top,
4600	pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
4601	}
4602	break;
4603	}
4604
4605	case SVGA_3D_CMD_CONTEXT_DEFINE:
4606	{
4607	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4608	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4609	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4610
4611	rc = vmsvga3dContextDefine(pThisCC, pCmd->cid);
4612	break;
4613	}
4614
4615	case SVGA_3D_CMD_CONTEXT_DESTROY:
4616	{
4617	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4618	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4619	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4620
4621	rc = vmsvga3dContextDestroy(pThisCC, pCmd->cid);
4622	break;
4623	}
4624
4625	case SVGA_3D_CMD_SETTRANSFORM:
4626	{
4627	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4628	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4629	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4630
4631	rc = vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
4632	break;
4633	}
4634
4635	case SVGA_3D_CMD_SETZRANGE:
4636	{
4637	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4638	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4639	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4640
4641	rc = vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
4642	break;
4643	}
4644
4645	case SVGA_3D_CMD_SETRENDERSTATE:
4646	{
4647	uint32_t cRenderStates;
4648	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4649	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4650	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4651
4652	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4653	rc = vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4654	break;
4655	}
4656
4657	case SVGA_3D_CMD_SETRENDERTARGET:
4658	{
4659	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4660	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4661	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4662
4663	rc = vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
4664	break;
4665	}
4666
4667	case SVGA_3D_CMD_SETTEXTURESTATE:
4668	{
4669	uint32_t cTextureStates;
4670	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4671	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4672	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4673
4674	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4675	rc = vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4676	break;
4677	}
4678
4679	case SVGA_3D_CMD_SETMATERIAL:
4680	{
4681	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4682	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4683	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4684
4685	rc = vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
4686	break;
4687	}
4688
4689	case SVGA_3D_CMD_SETLIGHTDATA:
4690	{
4691	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4692	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4693	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4694
4695	rc = vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
4696	break;
4697	}
4698
4699	case SVGA_3D_CMD_SETLIGHTENABLED:
4700	{
4701	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4702	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4703	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4704
4705	rc = vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
4706	break;
4707	}
4708
4709	case SVGA_3D_CMD_SETVIEWPORT:
4710	{
4711	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4712	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4713	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4714
4715	rc = vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4716	break;
4717	}
4718
4719	case SVGA_3D_CMD_SETCLIPPLANE:
4720	{
4721	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4722	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4723	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4724
4725	rc = vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4726	break;
4727	}
4728
4729	case SVGA_3D_CMD_CLEAR:
4730	{
4731	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4732	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4733	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4734
4735	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4736	rc = vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4737	break;
4738	}
4739
4740	case SVGA_3D_CMD_PRESENT:
4741	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4742	{
4743	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4744	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4745	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4746	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4747	else
4748	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4749
4750	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4751
4752	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4753	rc = vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4754	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4755	break;
4756	}
4757
4758	case SVGA_3D_CMD_SHADER_DEFINE:
4759	{
4760	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4761	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4762	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4763
4764	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4765	rc = vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4766	break;
4767	}
4768
4769	case SVGA_3D_CMD_SHADER_DESTROY:
4770	{
4771	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4772	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4773	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4774
4775	rc = vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
4776	break;
4777	}
4778
4779	case SVGA_3D_CMD_SET_SHADER:
4780	{
4781	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4782	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4783	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4784
4785	rc = vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4786	break;
4787	}
4788
4789	case SVGA_3D_CMD_SET_SHADER_CONST:
4790	{
4791	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4792	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4793	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4794
4795	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4796	rc = vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4797	break;
4798	}
4799
4800	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4801	{
4802	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4803	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4804	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4805
4806	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4807	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4808	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4809	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4810	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4811
4812	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4813	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4814
4815	RT_UNTRUSTED_VALIDATED_FENCE();
4816
4817	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4818	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4819	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4820
4821	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4822	rc = vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4823	pNumRange, cVertexDivisor, pVertexDivisor);
4824	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4825	break;
4826	}
4827
4828	case SVGA_3D_CMD_SETSCISSORRECT:
4829	{
4830	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4831	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4832	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4833
4834	rc = vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
4835	break;
4836	}
4837
4838	case SVGA_3D_CMD_BEGIN_QUERY:
4839	{
4840	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4841	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4842	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4843
4844	rc = vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
4845	break;
4846	}
4847
4848	case SVGA_3D_CMD_END_QUERY:
4849	{
4850	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4851	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4852	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4853
4854	rc = vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
4855	break;
4856	}
4857
4858	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4859	{
4860	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4861	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4862	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4863
4864	rc = vmsvga3dQueryWait(pThis, pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
4865	break;
4866	}
4867
4868	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4869	{
4870	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4871	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4872	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4873
4874	rc = vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
4875	break;
4876	}
4877
4878	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4879	/* context id + surface id? */
4880	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4881	break;
4882	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4883	/* context id + surface id? */
4884	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4885	break;
4886
4887	default:
4888	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4889	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4890	break;
4891	}
4892	}
4893	else
4894	# endif // VBOX_WITH_VMSVGA3D
4895	{
4896	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4897	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4898	}
4899	}
4900
4901	/* Go to the next slot */
4902	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4903	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4904	if (offCurrentCmd >= offFifoMax)
4905	{
4906	offCurrentCmd -= offFifoMax - offFifoMin;
4907	Assert(offCurrentCmd >= offFifoMin);
4908	Assert(offCurrentCmd < offFifoMax);
4909	}
4910	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4911	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4912
4913	/*
4914	* Raise IRQ if required. Must enter the critical section here
4915	* before making final decisions here, otherwise cubebench and
4916	* others may end up waiting forever.
4917	*/
4918	if ( u32IrqStatus
4919	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4920	{
4921	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
4922	AssertRC(rc2);
4923
4924	/* FIFO progress might trigger an interrupt. */
4925	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4926	{
4927	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
4928	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4929	}
4930
4931	/* Unmasked IRQ pending? */
4932	if (pThis->svga.u32IrqMask & u32IrqStatus)
4933	{
4934	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4935	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4936	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4937	}
4938
4939	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4940	}
4941	}
4942
4943	/* If really done, clear the busy flag. */
4944	if (fDone)
4945	{
4946	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4947	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
4948	}
4949	}
4950
4951	/*
4952	* Free the bounce buffer. (There are no returns above!)
4953	*/
4954	RTMemFree(pbBounceBuf);
4955
4956	return VINF_SUCCESS;
4957	}
4958
4959	#undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4960	#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
4961	#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
4962
4963	#ifdef VBOX_WITH_VMSVGA3D
4964	/**
4965	* Free the specified GMR
4966	*
4967	* @param pThisCC The VGA/VMSVGA state for ring-3.
4968	* @param idGMR GMR id
4969	*/
4970	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
4971	{
4972	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4973
4974	/* Free the old descriptor if present. */
4975	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4976	if ( pGMR->numDescriptors
4977	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4978	{
4979	# ifdef DEBUG_GMR_ACCESS
4980	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
4981	# endif
4982
4983	Assert(pGMR->paDesc);
4984	RTMemFree(pGMR->paDesc);
4985	pGMR->paDesc = NULL;
4986	pGMR->numDescriptors = 0;
4987	pGMR->cbTotal = 0;
4988	pGMR->cMaxPages = 0;
4989	}
4990	Assert(!pGMR->cMaxPages);
4991	Assert(!pGMR->cbTotal);
4992	}
4993	#endif /* VBOX_WITH_VMSVGA3D */
4994
4995	/**
4996	* Copy between a GMR and a host memory buffer.
4997	*
4998	* @returns VBox status code.
4999	* @param pThis The shared VGA/VMSVGA instance data.
5000	* @param pThisCC The VGA/VMSVGA state for ring-3.
5001	* @param enmTransferType Transfer type (read/write)
5002	* @param pbHstBuf Host buffer pointer (valid)
5003	* @param cbHstBuf Size of host buffer (valid)
5004	* @param offHst Host buffer offset of the first scanline
5005	* @param cbHstPitch Destination buffer pitch
5006	* @param gstPtr GMR description
5007	* @param offGst Guest buffer offset of the first scanline
5008	* @param cbGstPitch Guest buffer pitch
5009	* @param cbWidth Width in bytes to copy
5010	* @param cHeight Number of scanllines to copy
5011	*/
5012	int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
5013	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
5014	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
5015	uint32_t cbWidth, uint32_t cHeight)
5016	{
5017	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5018	PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
5019	int rc;
5020
5021	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
5022	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
5023	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
5024	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
5025	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
5026
5027	PGMR pGMR;
5028	uint32_t cbGmr; /* The GMR size in bytes. */
5029	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
5030	{
5031	pGMR = NULL;
5032	cbGmr = pThis->vram_size;
5033	}
5034	else
5035	{
5036	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
5037	RT_UNTRUSTED_VALIDATED_FENCE();
5038	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
5039	cbGmr = pGMR->cbTotal;
5040	}
5041
5042	/*
5043	* GMR
5044	*/
5045	/* Calculate GMR offset of the data to be copied. */
5046	AssertMsgReturn(gstPtr.offset < cbGmr,
5047	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5048	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5049	VERR_INVALID_PARAMETER);
5050	RT_UNTRUSTED_VALIDATED_FENCE();
5051	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
5052	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5053	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5054	VERR_INVALID_PARAMETER);
5055	RT_UNTRUSTED_VALIDATED_FENCE();
5056	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
5057
5058	/* Verify that cbWidth is less than scanline and fits into the GMR. */
5059	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
5060	AssertMsgReturn(cbGmrScanline != 0,
5061	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5062	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5063	VERR_INVALID_PARAMETER);
5064	RT_UNTRUSTED_VALIDATED_FENCE();
5065	AssertMsgReturn(cbWidth <= cbGmrScanline,
5066	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5067	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5068	VERR_INVALID_PARAMETER);
5069	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
5070	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5071	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5072	VERR_INVALID_PARAMETER);
5073	RT_UNTRUSTED_VALIDATED_FENCE();
5074
5075	/* How many bytes are available for the data in the GMR. */
5076	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
5077
5078	/* How many scanlines would fit into the available data. */
5079	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
5080	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
5081	if (cbWidth <= cbGmrLastScanline)
5082	++cGmrScanlines;
5083
5084	if (cHeight > cGmrScanlines)
5085	cHeight = cGmrScanlines;
5086
5087	AssertMsgReturn(cHeight > 0,
5088	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5089	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5090	VERR_INVALID_PARAMETER);
5091	RT_UNTRUSTED_VALIDATED_FENCE();
5092
5093	/*
5094	* Host buffer.
5095	*/
5096	AssertMsgReturn(offHst < cbHstBuf,
5097	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5098	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5099	VERR_INVALID_PARAMETER);
5100
5101	/* Verify that cbWidth is less than scanline and fits into the buffer. */
5102	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
5103	AssertMsgReturn(cbHstScanline != 0,
5104	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5105	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5106	VERR_INVALID_PARAMETER);
5107	AssertMsgReturn(cbWidth <= cbHstScanline,
5108	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5109	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5110	VERR_INVALID_PARAMETER);
5111	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
5112	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5113	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5114	VERR_INVALID_PARAMETER);
5115
5116	/* How many bytes are available for the data in the buffer. */
5117	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
5118
5119	/* How many scanlines would fit into the available data. */
5120	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
5121	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
5122	if (cbWidth <= cbHstLastScanline)
5123	++cHstScanlines;
5124
5125	if (cHeight > cHstScanlines)
5126	cHeight = cHstScanlines;
5127
5128	AssertMsgReturn(cHeight > 0,
5129	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5130	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5131	VERR_INVALID_PARAMETER);
5132
5133	uint8_t *pbHst = pbHstBuf + offHst;
5134
5135	/* Shortcut for the framebuffer. */
5136	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
5137	{
5138	uint8_t *pbGst = pThisCC->pbVRam + offGmr;
5139
5140	uint8_t const *pbSrc;
5141	int32_t cbSrcPitch;
5142	uint8_t *pbDst;
5143	int32_t cbDstPitch;
5144
5145	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
5146	{
5147	pbSrc = pbHst;
5148	cbSrcPitch = cbHstPitch;
5149	pbDst = pbGst;
5150	cbDstPitch = cbGstPitch;
5151	}
5152	else
5153	{
5154	pbSrc = pbGst;
5155	cbSrcPitch = cbGstPitch;
5156	pbDst = pbHst;
5157	cbDstPitch = cbHstPitch;
5158	}
5159
5160	if ( cbWidth == (uint32_t)cbGstPitch
5161	&& cbGstPitch == cbHstPitch)
5162	{
5163	/* Entire scanlines, positive pitch. */
5164	memcpy(pbDst, pbSrc, cbWidth * cHeight);
5165	}
5166	else
5167	{
5168	for (uint32_t i = 0; i < cHeight; ++i)
5169	{
5170	memcpy(pbDst, pbSrc, cbWidth);
5171
5172	pbDst += cbDstPitch;
5173	pbSrc += cbSrcPitch;
5174	}
5175	}
5176	return VINF_SUCCESS;
5177	}
5178
5179	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
5180	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
5181
5182	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
5183	uint32_t iDesc = 0; /* Index in the descriptor array. */
5184	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
5185	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
5186	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
5187	for (uint32_t i = 0; i < cHeight; ++i)
5188	{
5189	uint32_t cbCurrentWidth = cbWidth;
5190	uint32_t offGmrCurrent = offGmrScanline;
5191	uint8_t *pbCurrentHost = pbHstScanline;
5192
5193	/* Find the right descriptor */
5194	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
5195	{
5196	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5197	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
5198	++iDesc;
5199	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5200	}
5201
5202	while (cbCurrentWidth)
5203	{
5204	uint32_t cbToCopy;
5205
5206	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
5207	{
5208	cbToCopy = cbCurrentWidth;
5209	}
5210	else
5211	{
5212	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
5213	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
5214	}
5215
5216	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
5217
5218	Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
5219
5220	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
5221	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5222	else
5223	rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5224	AssertRCBreak(rc);
5225
5226	cbCurrentWidth -= cbToCopy;
5227	offGmrCurrent += cbToCopy;
5228	pbCurrentHost += cbToCopy;
5229
5230	/* Go to the next descriptor if there's anything left. */
5231	if (cbCurrentWidth)
5232	{
5233	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5234	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5235	++iDesc;
5236	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5237	}
5238	}
5239
5240	offGmrScanline += cbGstPitch;
5241	pbHstScanline += cbHstPitch;
5242	}
5243
5244	return VINF_SUCCESS;
5245	}
5246
5247
5248	/**
5249	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5250	*
5251	* @param pSizeSrc Source surface dimensions.
5252	* @param pSizeDest Destination surface dimensions.
5253	* @param pBox Coordinates to be clipped.
5254	*/
5255	void vmsvgaR3ClipCopyBox(const SVGA3dSize pSizeSrc, const SVGA3dSize pSizeDest, SVGA3dCopyBox *pBox)
5256	{
5257	/* Src x, w */
5258	if (pBox->srcx > pSizeSrc->width)
5259	pBox->srcx = pSizeSrc->width;
5260	if (pBox->w > pSizeSrc->width - pBox->srcx)
5261	pBox->w = pSizeSrc->width - pBox->srcx;
5262
5263	/* Src y, h */
5264	if (pBox->srcy > pSizeSrc->height)
5265	pBox->srcy = pSizeSrc->height;
5266	if (pBox->h > pSizeSrc->height - pBox->srcy)
5267	pBox->h = pSizeSrc->height - pBox->srcy;
5268
5269	/* Src z, d */
5270	if (pBox->srcz > pSizeSrc->depth)
5271	pBox->srcz = pSizeSrc->depth;
5272	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5273	pBox->d = pSizeSrc->depth - pBox->srcz;
5274
5275	/* Dest x, w */
5276	if (pBox->x > pSizeDest->width)
5277	pBox->x = pSizeDest->width;
5278	if (pBox->w > pSizeDest->width - pBox->x)
5279	pBox->w = pSizeDest->width - pBox->x;
5280
5281	/* Dest y, h */
5282	if (pBox->y > pSizeDest->height)
5283	pBox->y = pSizeDest->height;
5284	if (pBox->h > pSizeDest->height - pBox->y)
5285	pBox->h = pSizeDest->height - pBox->y;
5286
5287	/* Dest z, d */
5288	if (pBox->z > pSizeDest->depth)
5289	pBox->z = pSizeDest->depth;
5290	if (pBox->d > pSizeDest->depth - pBox->z)
5291	pBox->d = pSizeDest->depth - pBox->z;
5292	}
5293
5294	/**
5295	* Unsigned coordinates in pBox. Clip to [0; pSize).
5296	*
5297	* @param pSize Source surface dimensions.
5298	* @param pBox Coordinates to be clipped.
5299	*/
5300	void vmsvgaR3ClipBox(const SVGA3dSize pSize, SVGA3dBox pBox)
5301	{
5302	/* x, w */
5303	if (pBox->x > pSize->width)
5304	pBox->x = pSize->width;
5305	if (pBox->w > pSize->width - pBox->x)
5306	pBox->w = pSize->width - pBox->x;
5307
5308	/* y, h */
5309	if (pBox->y > pSize->height)
5310	pBox->y = pSize->height;
5311	if (pBox->h > pSize->height - pBox->y)
5312	pBox->h = pSize->height - pBox->y;
5313
5314	/* z, d */
5315	if (pBox->z > pSize->depth)
5316	pBox->z = pSize->depth;
5317	if (pBox->d > pSize->depth - pBox->z)
5318	pBox->d = pSize->depth - pBox->z;
5319	}
5320
5321	/**
5322	* Clip.
5323	*
5324	* @param pBound Bounding rectangle.
5325	* @param pRect Rectangle to be clipped.
5326	*/
5327	void vmsvgaR3ClipRect(SVGASignedRect const pBound, SVGASignedRect pRect)
5328	{
5329	int32_t left;
5330	int32_t top;
5331	int32_t right;
5332	int32_t bottom;
5333
5334	/* Right order. */
5335	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5336	if (pRect->left < pRect->right)
5337	{
5338	left = pRect->left;
5339	right = pRect->right;
5340	}
5341	else
5342	{
5343	left = pRect->right;
5344	right = pRect->left;
5345	}
5346	if (pRect->top < pRect->bottom)
5347	{
5348	top = pRect->top;
5349	bottom = pRect->bottom;
5350	}
5351	else
5352	{
5353	top = pRect->bottom;
5354	bottom = pRect->top;
5355	}
5356
5357	if (left < pBound->left)
5358	left = pBound->left;
5359	if (right < pBound->left)
5360	right = pBound->left;
5361
5362	if (left > pBound->right)
5363	left = pBound->right;
5364	if (right > pBound->right)
5365	right = pBound->right;
5366
5367	if (top < pBound->top)
5368	top = pBound->top;
5369	if (bottom < pBound->top)
5370	bottom = pBound->top;
5371
5372	if (top > pBound->bottom)
5373	top = pBound->bottom;
5374	if (bottom > pBound->bottom)
5375	bottom = pBound->bottom;
5376
5377	pRect->left = left;
5378	pRect->right = right;
5379	pRect->top = top;
5380	pRect->bottom = bottom;
5381	}
5382
5383	/**
5384	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5385	* Unblock the FIFO I/O thread so it can respond to a state change.}
5386	*/
5387	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5388	{
5389	RT_NOREF(pDevIns);
5390	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5391	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5392	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5393	}
5394
5395	/**
5396	* Enables or disables dirty page tracking for the framebuffer
5397	*
5398	* @param pDevIns The device instance.
5399	* @param pThis The shared VGA/VMSVGA instance data.
5400	* @param fTraces Enable/disable traces
5401	*/
5402	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
5403	{
5404	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5405	&& !fTraces)
5406	{
5407	//Assert(pThis->svga.fTraces);
5408	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5409	return;
5410	}
5411
5412	pThis->svga.fTraces = fTraces;
5413	if (pThis->svga.fTraces)
5414	{
5415	unsigned cbFrameBuffer = pThis->vram_size;
5416
5417	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5418	/** @todo How does this work with screens? */
5419	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5420	{
5421	# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5422	Assert(pThis->svga.cbScanline);
5423	# endif
5424	/* Hardware enabled; return real framebuffer size .*/
5425	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5426	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5427	}
5428
5429	if (!pThis->svga.fVRAMTracking)
5430	{
5431	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5432	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
5433	pThis->svga.fVRAMTracking = true;
5434	}
5435	}
5436	else
5437	{
5438	if (pThis->svga.fVRAMTracking)
5439	{
5440	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5441	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5442	pThis->svga.fVRAMTracking = false;
5443	}
5444	}
5445	}
5446
5447	/**
5448	* @callback_method_impl{FNPCIIOREGIONMAP}
5449	*/
5450	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5451	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5452	{
5453	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5454	int rc;
5455	RT_NOREF(pPciDev);
5456	Assert(pPciDev == pDevIns->apPciDevs[0]);
5457
5458	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5459	AssertReturn( iRegion == pThis->pciRegions.iFIFO
5460	&& ( enmType == PCI_ADDRESS_SPACE_MEM
5461	\|\| (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
5462	, VERR_INTERNAL_ERROR);
5463	if (GCPhysAddress != NIL_RTGCPHYS)
5464	{
5465	/*
5466	* Mapping the FIFO RAM.
5467	*/
5468	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5469	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5470	AssertRC(rc);
5471
5472	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5473	if (RT_SUCCESS(rc))
5474	{
5475	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5476	# ifdef DEBUG_FIFO_ACCESS
5477	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5478	# else
5479	GCPhysAddress + PAGE_SIZE - 1,
5480	# endif
5481	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5482	"VMSVGA FIFO");
5483	AssertRC(rc);
5484	}
5485	# endif
5486	if (RT_SUCCESS(rc))
5487	{
5488	pThis->svga.GCPhysFIFO = GCPhysAddress;
5489	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5490	}
5491	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite erros here. */
5492	}
5493	else
5494	{
5495	Assert(pThis->svga.GCPhysFIFO);
5496	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5497	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5498	AssertRC(rc);
5499	# else
5500	rc = VINF_SUCCESS;
5501	# endif
5502	pThis->svga.GCPhysFIFO = 0;
5503	}
5504	return rc;
5505	}
5506
5507	# ifdef VBOX_WITH_VMSVGA3D
5508
5509	/**
5510	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5511	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5512	*
5513	* @param pDevIns The device instance.
5514	* @param pThis The The shared VGA/VMSVGA instance data.
5515	* @param pThisCC The VGA/VMSVGA state for ring-3.
5516	* @param sid Either UINT32_MAX or the ID of a specific surface. If
5517	* UINT32_MAX is used, all surfaces are processed.
5518	*/
5519	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
5520	{
5521	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5522	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5523	}
5524
5525
5526	/**
5527	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5528	*/
5529	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5530	{
5531	/* There might be a specific surface ID at the start of the
5532	arguments, if not show all surfaces. */
5533	uint32_t sid = UINT32_MAX;
5534	if (pszArgs)
5535	pszArgs = RTStrStripL(pszArgs);
5536	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5537	sid = RTStrToUInt32(pszArgs);
5538
5539	/* Verbose or terse display, we default to verbose. */
5540	bool fVerbose = true;
5541	if (RTStrIStr(pszArgs, "terse"))
5542	fVerbose = false;
5543
5544	/* The size of the ascii art (x direction, y is 3/4 of x). */
5545	uint32_t cxAscii = 80;
5546	if (RTStrIStr(pszArgs, "gigantic"))
5547	cxAscii = 300;
5548	else if (RTStrIStr(pszArgs, "huge"))
5549	cxAscii = 180;
5550	else if (RTStrIStr(pszArgs, "big"))
5551	cxAscii = 132;
5552	else if (RTStrIStr(pszArgs, "normal"))
5553	cxAscii = 80;
5554	else if (RTStrIStr(pszArgs, "medium"))
5555	cxAscii = 64;
5556	else if (RTStrIStr(pszArgs, "small"))
5557	cxAscii = 48;
5558	else if (RTStrIStr(pszArgs, "tiny"))
5559	cxAscii = 24;
5560
5561	/* Y invert the image when producing the ASCII art. */
5562	bool fInvY = false;
5563	if (RTStrIStr(pszArgs, "invy"))
5564	fInvY = true;
5565
5566	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5567	pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5568	}
5569
5570
5571	/**
5572	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5573	*/
5574	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5575	{
5576	/* pszArg = "sid[>dir]"
5577	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5578	*/
5579	char *pszBitmapPath = NULL;
5580	uint32_t sid = UINT32_MAX;
5581	if (pszArgs)
5582	pszArgs = RTStrStripL(pszArgs);
5583	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5584	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5585	if ( pszBitmapPath
5586	&& *pszBitmapPath == '>')
5587	++pszBitmapPath;
5588
5589	const bool fVerbose = true;
5590	const uint32_t cxAscii = 0; /* No ASCII */
5591	const bool fInvY = false; /* Do not invert. */
5592	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5593	pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5594	}
5595
5596	/**
5597	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5598	*/
5599	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5600	{
5601	/* There might be a specific surface ID at the start of the
5602	arguments, if not show all contexts. */
5603	uint32_t sid = UINT32_MAX;
5604	if (pszArgs)
5605	pszArgs = RTStrStripL(pszArgs);
5606	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5607	sid = RTStrToUInt32(pszArgs);
5608
5609	/* Verbose or terse display, we default to verbose. */
5610	bool fVerbose = true;
5611	if (RTStrIStr(pszArgs, "terse"))
5612	fVerbose = false;
5613
5614	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
5615	}
5616	# endif /* VBOX_WITH_VMSVGA3D */
5617
5618	/**
5619	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5620	*/
5621	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5622	{
5623	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5624	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5625	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5626	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
5627	RT_NOREF(pszArgs);
5628
5629	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5630	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5631	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5632	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5633	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5634	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5635	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5636	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5637	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5638	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5639	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5640	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5641	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5642	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5643	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5644	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5645	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5646	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5647	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5648	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5649	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5650	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5651	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5652	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5653	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5654
5655	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5656	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5657	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5658	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5659
5660	pHlp->pfnPrintf(pHlp, "Legacy cursor: ID %u, state %u\n", pThis->svga.uCursorID, pThis->svga.uCursorOn);
5661	pHlp->pfnPrintf(pHlp, "Legacy cursor at: %u,%u\n", pThis->svga.uCursorX, pThis->svga.uCursorY);
5662	# ifdef VBOX_WITH_VMSVGA3D
5663	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5664	# endif
5665	if (pThisCC->pDrv)
5666	{
5667	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
5668	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
5669	}
5670
5671	/* Dump screen information. */
5672	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
5673	{
5674	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, iScreen);
5675	if (pScreen)
5676	{
5677	pHlp->pfnPrintf(pHlp, "Screen %u defined (ID %u):\n", iScreen, pScreen->idScreen);
5678	pHlp->pfnPrintf(pHlp, " %u x %u x %ubpp @ %u, %u\n", pScreen->cWidth, pScreen->cHeight,
5679	pScreen->cBpp, pScreen->xOrigin, pScreen->yOrigin);
5680	pHlp->pfnPrintf(pHlp, " Pitch %u bytes, VRAM offset %X\n", pScreen->cbPitch, pScreen->offVRAM);
5681	pHlp->pfnPrintf(pHlp, " Flags %X", pScreen->fuScreen);
5682	if (pScreen->fuScreen != SVGA_SCREEN_MUST_BE_SET)
5683	{
5684	pHlp->pfnPrintf(pHlp, " (");
5685	if (pScreen->fuScreen & SVGA_SCREEN_IS_PRIMARY)
5686	pHlp->pfnPrintf(pHlp, " IS_PRIMARY");
5687	if (pScreen->fuScreen & SVGA_SCREEN_FULLSCREEN_HINT)
5688	pHlp->pfnPrintf(pHlp, " FULLSCREEN_HINT");
5689	if (pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE)
5690	pHlp->pfnPrintf(pHlp, " DEACTIVATE");
5691	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
5692	pHlp->pfnPrintf(pHlp, " BLANKING");
5693	pHlp->pfnPrintf(pHlp, " )");
5694	}
5695	pHlp->pfnPrintf(pHlp, ", %smodified\n", pScreen->fModified ? "" : "not ");
5696	}
5697	}
5698
5699	}
5700
5701	/**
5702	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
5703	*/
5704	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
5705	PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5706	{
5707	RT_NOREF(uPass);
5708
5709	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5710	int rc;
5711
5712	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5713	{
5714	uint32_t cScreens = 0;
5715	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5716	AssertRCReturn(rc, rc);
5717	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5718	("cScreens=%#x\n", cScreens),
5719	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5720
5721	for (uint32_t i = 0; i < cScreens; ++i)
5722	{
5723	VMSVGASCREENOBJECT screen;
5724	RT_ZERO(screen);
5725
5726	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5727	AssertLogRelRCReturn(rc, rc);
5728
5729	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5730	{
5731	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5732	*pScreen = screen;
5733	pScreen->fModified = true;
5734	}
5735	else
5736	{
5737	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5738	}
5739	}
5740	}
5741	else
5742	{
5743	/* Try to setup at least the first screen. */
5744	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5745	pScreen->fDefined = true;
5746	pScreen->fModified = true;
5747	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5748	pScreen->idScreen = 0;
5749	pScreen->xOrigin = 0;
5750	pScreen->yOrigin = 0;
5751	pScreen->offVRAM = pThis->svga.uScreenOffset;
5752	pScreen->cbPitch = pThis->svga.cbScanline;
5753	pScreen->cWidth = pThis->svga.uWidth;
5754	pScreen->cHeight = pThis->svga.uHeight;
5755	pScreen->cBpp = pThis->svga.uBpp;
5756	}
5757
5758	return VINF_SUCCESS;
5759	}
5760
5761	/**
5762	* @copydoc FNSSMDEVLOADEXEC
5763	*/
5764	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5765	{
5766	RT_NOREF(uPass);
5767	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5768	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5769	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5770	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5771	int rc;
5772
5773	/* Load our part of the VGAState */
5774	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5775	AssertRCReturn(rc, rc);
5776
5777	/* Load the VGA framebuffer. */
5778	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5779	uint32_t cbVgaFramebuffer = _32K;
5780	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5781	{
5782	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5783	AssertRCReturn(rc, rc);
5784	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5785	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5786	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5787	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5788	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5789	}
5790	rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5791	AssertRCReturn(rc, rc);
5792	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5793	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5794	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5795	RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5796
5797	/* Load the VMSVGA state. */
5798	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5799	AssertRCReturn(rc, rc);
5800
5801	/* Load the active cursor bitmaps. */
5802	if (pSVGAState->Cursor.fActive)
5803	{
5804	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5805	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5806
5807	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5808	AssertRCReturn(rc, rc);
5809	}
5810
5811	/* Load the GMR state. */
5812	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5813	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5814	{
5815	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5816	AssertRCReturn(rc, rc);
5817	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5818	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5819	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5820	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5821	}
5822
5823	if (pThis->svga.cGMR != cGMR)
5824	{
5825	/* Reallocate GMR array. */
5826	Assert(pSVGAState->paGMR != NULL);
5827	RTMemFree(pSVGAState->paGMR);
5828	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5829	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5830	pThis->svga.cGMR = cGMR;
5831	}
5832
5833	for (uint32_t i = 0; i < cGMR; ++i)
5834	{
5835	PGMR pGMR = &pSVGAState->paGMR[i];
5836
5837	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5838	AssertRCReturn(rc, rc);
5839
5840	if (pGMR->numDescriptors)
5841	{
5842	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5843	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5844	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5845
5846	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5847	{
5848	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5849	AssertRCReturn(rc, rc);
5850	}
5851	}
5852	}
5853
5854	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5855	vmsvga3dPowerOn(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC));
5856	# endif
5857
5858	VMSVGA_STATE_LOAD LoadState;
5859	LoadState.pSSM = pSSM;
5860	LoadState.uVersion = uVersion;
5861	LoadState.uPass = uPass;
5862	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5863	AssertLogRelRCReturn(rc, rc);
5864
5865	return VINF_SUCCESS;
5866	}
5867
5868	/**
5869	* Reinit the video mode after the state has been loaded.
5870	*/
5871	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
5872	{
5873	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5874	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5875	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5876
5877	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5878
5879	/* Set the active cursor. */
5880	if (pSVGAState->Cursor.fActive)
5881	{
5882	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
5883	true /fVisible/,
5884	true /fAlpha/,
5885	pSVGAState->Cursor.xHotspot,
5886	pSVGAState->Cursor.yHotspot,
5887	pSVGAState->Cursor.width,
5888	pSVGAState->Cursor.height,
5889	pSVGAState->Cursor.pData);
5890	AssertRC(rc);
5891	}
5892
5893	/* If the VRAM handler should not be registered, we have to explicitly
5894	* unregister it here!
5895	*/
5896	if (!pThis->svga.fVRAMTracking)
5897	{
5898	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5899	}
5900
5901	return VINF_SUCCESS;
5902	}
5903
5904	/**
5905	* Portion of SVGA state which must be saved in the FIFO thread.
5906	*/
5907	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
5908	{
5909	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5910	int rc;
5911
5912	/* Save the screen objects. */
5913	/* Count defined screen object. */
5914	uint32_t cScreens = 0;
5915	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5916	{
5917	if (pSVGAState->aScreens[i].fDefined)
5918	++cScreens;
5919	}
5920
5921	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
5922	AssertLogRelRCReturn(rc, rc);
5923
5924	for (uint32_t i = 0; i < cScreens; ++i)
5925	{
5926	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5927
5928	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5929	AssertLogRelRCReturn(rc, rc);
5930	}
5931	return VINF_SUCCESS;
5932	}
5933
5934	/**
5935	* @copydoc FNSSMDEVSAVEEXEC
5936	*/
5937	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5938	{
5939	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5940	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5941	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5942	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5943	int rc;
5944
5945	/* Save our part of the VGAState */
5946	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5947	AssertLogRelRCReturn(rc, rc);
5948
5949	/* Save the framebuffer backup. */
5950	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5951	rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5952	AssertLogRelRCReturn(rc, rc);
5953
5954	/* Save the VMSVGA state. */
5955	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5956	AssertLogRelRCReturn(rc, rc);
5957
5958	/* Save the active cursor bitmaps. */
5959	if (pSVGAState->Cursor.fActive)
5960	{
5961	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5962	AssertLogRelRCReturn(rc, rc);
5963	}
5964
5965	/* Save the GMR state */
5966	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
5967	AssertLogRelRCReturn(rc, rc);
5968	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5969	{
5970	PGMR pGMR = &pSVGAState->paGMR[i];
5971
5972	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5973	AssertLogRelRCReturn(rc, rc);
5974
5975	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5976	{
5977	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5978	AssertLogRelRCReturn(rc, rc);
5979	}
5980	}
5981
5982	/*
5983	* Must save some state (3D in particular) in the FIFO thread.
5984	*/
5985	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5986	AssertLogRelRCReturn(rc, rc);
5987
5988	return VINF_SUCCESS;
5989	}
5990
5991	/**
5992	* Destructor for PVMSVGAR3STATE structure.
5993	*
5994	* @param pThis The shared VGA/VMSVGA instance data.
5995	* @param pSVGAState Pointer to the structure. It is not deallocated.
5996	*/
5997	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5998	{
5999	# ifndef VMSVGA_USE_EMT_HALT_CODE
6000	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
6001	{
6002	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
6003	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
6004	}
6005	# endif
6006
6007	if (pSVGAState->Cursor.fActive)
6008	{
6009	RTMemFree(pSVGAState->Cursor.pData);
6010	pSVGAState->Cursor.pData = NULL;
6011	pSVGAState->Cursor.fActive = false;
6012	}
6013
6014	if (pSVGAState->paGMR)
6015	{
6016	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
6017	if (pSVGAState->paGMR[i].paDesc)
6018	RTMemFree(pSVGAState->paGMR[i].paDesc);
6019
6020	RTMemFree(pSVGAState->paGMR);
6021	pSVGAState->paGMR = NULL;
6022	}
6023	}
6024
6025	/**
6026	* Constructor for PVMSVGAR3STATE structure.
6027	*
6028	* @returns VBox status code.
6029	* @param pThis The shared VGA/VMSVGA instance data.
6030	* @param pSVGAState Pointer to the structure. It is already allocated.
6031	*/
6032	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
6033	{
6034	int rc = VINF_SUCCESS;
6035	RT_ZERO(*pSVGAState);
6036
6037	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
6038	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
6039
6040	# ifndef VMSVGA_USE_EMT_HALT_CODE
6041	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
6042	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
6043	AssertRCReturn(rc, rc);
6044	# endif
6045
6046	return rc;
6047	}
6048
6049	/**
6050	* Initializes the host capabilities: registers and FIFO.
6051	*
6052	* @returns VBox status code.
6053	* @param pThis The shared VGA/VMSVGA instance data.
6054	* @param pThisCC The VGA/VMSVGA state for ring-3.
6055	*/
6056	static void vmsvgaR3InitCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
6057	{
6058	/* Register caps. */
6059	pThis->svga.u32RegCaps = SVGA_CAP_GMR
6060	\| SVGA_CAP_GMR2
6061	\| SVGA_CAP_CURSOR
6062	\| SVGA_CAP_CURSOR_BYPASS
6063	\| SVGA_CAP_CURSOR_BYPASS_2
6064	\| SVGA_CAP_EXTENDED_FIFO
6065	\| SVGA_CAP_IRQMASK
6066	\| SVGA_CAP_PITCHLOCK
6067	\| SVGA_CAP_TRACES
6068	\| SVGA_CAP_SCREEN_OBJECT_2
6069	\| SVGA_CAP_ALPHA_CURSOR;
6070	# ifdef VBOX_WITH_VMSVGA3D
6071	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
6072	# endif
6073
6074	/* Clear the FIFO. */
6075	RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
6076
6077	/* Setup FIFO capabilities. */
6078	pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
6079	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
6080	\| SVGA_FIFO_CAP_GMR2
6081	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
6082	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2
6083	\| SVGA_FIFO_CAP_RESERVE
6084	\| SVGA_FIFO_CAP_PITCHLOCK;
6085
6086	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
6087	pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
6088	}
6089
6090	# ifdef VBOX_WITH_VMSVGA3D
6091	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
6092	static const char * const g_apszVmSvgaDevCapNames[] =
6093	{
6094	"x3D", /* = 0 */
6095	"xMAX_LIGHTS",
6096	"xMAX_TEXTURES",
6097	"xMAX_CLIP_PLANES",
6098	"xVERTEX_SHADER_VERSION",
6099	"xVERTEX_SHADER",
6100	"xFRAGMENT_SHADER_VERSION",
6101	"xFRAGMENT_SHADER",
6102	"xMAX_RENDER_TARGETS",
6103	"xS23E8_TEXTURES",
6104	"xS10E5_TEXTURES",
6105	"xMAX_FIXED_VERTEXBLEND",
6106	"xD16_BUFFER_FORMAT",
6107	"xD24S8_BUFFER_FORMAT",
6108	"xD24X8_BUFFER_FORMAT",
6109	"xQUERY_TYPES",
6110	"xTEXTURE_GRADIENT_SAMPLING",
6111	"rMAX_POINT_SIZE",
6112	"xMAX_SHADER_TEXTURES",
6113	"xMAX_TEXTURE_WIDTH",
6114	"xMAX_TEXTURE_HEIGHT",
6115	"xMAX_VOLUME_EXTENT",
6116	"xMAX_TEXTURE_REPEAT",
6117	"xMAX_TEXTURE_ASPECT_RATIO",
6118	"xMAX_TEXTURE_ANISOTROPY",
6119	"xMAX_PRIMITIVE_COUNT",
6120	"xMAX_VERTEX_INDEX",
6121	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
6122	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
6123	"xMAX_VERTEX_SHADER_TEMPS",
6124	"xMAX_FRAGMENT_SHADER_TEMPS",
6125	"xTEXTURE_OPS",
6126	"xSURFACEFMT_X8R8G8B8",
6127	"xSURFACEFMT_A8R8G8B8",
6128	"xSURFACEFMT_A2R10G10B10",
6129	"xSURFACEFMT_X1R5G5B5",
6130	"xSURFACEFMT_A1R5G5B5",
6131	"xSURFACEFMT_A4R4G4B4",
6132	"xSURFACEFMT_R5G6B5",
6133	"xSURFACEFMT_LUMINANCE16",
6134	"xSURFACEFMT_LUMINANCE8_ALPHA8",
6135	"xSURFACEFMT_ALPHA8",
6136	"xSURFACEFMT_LUMINANCE8",
6137	"xSURFACEFMT_Z_D16",
6138	"xSURFACEFMT_Z_D24S8",
6139	"xSURFACEFMT_Z_D24X8",
6140	"xSURFACEFMT_DXT1",
6141	"xSURFACEFMT_DXT2",
6142	"xSURFACEFMT_DXT3",
6143	"xSURFACEFMT_DXT4",
6144	"xSURFACEFMT_DXT5",
6145	"xSURFACEFMT_BUMPX8L8V8U8",
6146	"xSURFACEFMT_A2W10V10U10",
6147	"xSURFACEFMT_BUMPU8V8",
6148	"xSURFACEFMT_Q8W8V8U8",
6149	"xSURFACEFMT_CxV8U8",
6150	"xSURFACEFMT_R_S10E5",
6151	"xSURFACEFMT_R_S23E8",
6152	"xSURFACEFMT_RG_S10E5",
6153	"xSURFACEFMT_RG_S23E8",
6154	"xSURFACEFMT_ARGB_S10E5",
6155	"xSURFACEFMT_ARGB_S23E8",
6156	"xMISSING62",
6157	"xMAX_VERTEX_SHADER_TEXTURES",
6158	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
6159	"xSURFACEFMT_V16U16",
6160	"xSURFACEFMT_G16R16",
6161	"xSURFACEFMT_A16B16G16R16",
6162	"xSURFACEFMT_UYVY",
6163	"xSURFACEFMT_YUY2",
6164	"xMULTISAMPLE_NONMASKABLESAMPLES",
6165	"xMULTISAMPLE_MASKABLESAMPLES",
6166	"xALPHATOCOVERAGE",
6167	"xSUPERSAMPLE",
6168	"xAUTOGENMIPMAPS",
6169	"xSURFACEFMT_NV12",
6170	"xSURFACEFMT_AYUV",
6171	"xMAX_CONTEXT_IDS",
6172	"xMAX_SURFACE_IDS",
6173	"xSURFACEFMT_Z_DF16",
6174	"xSURFACEFMT_Z_DF24",
6175	"xSURFACEFMT_Z_D24S8_INT",
6176	"xSURFACEFMT_BC4_UNORM",
6177	"xSURFACEFMT_BC5_UNORM", /* 83 */
6178	};
6179
6180	/**
6181	* Initializes the host 3D capabilities in FIFO.
6182	*
6183	* @returns VBox status code.
6184	* @param pThis The shared VGA/VMSVGA instance data.
6185	* @param pThisCC The VGA/VMSVGA state for ring-3.
6186	*/
6187	static void vmsvgaR3InitFifo3DCaps(PVGASTATECC pThisCC)
6188	{
6189	/** @todo Probably query the capabilities once and cache in a memory buffer. */
6190	bool fSavedBuffering = RTLogRelSetBuffering(true);
6191	SVGA3dCapsRecord *pCaps;
6192	SVGA3dCapPair *pData;
6193	uint32_t idxCap = 0;
6194
6195	/* 3d hardware version; latest and greatest */
6196	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
6197	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
6198
6199	pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
6200	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
6201	pData = (SVGA3dCapPair *)&pCaps->data;
6202
6203	/* Fill out all 3d capabilities. */
6204	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
6205	{
6206	uint32_t val = 0;
6207
6208	int rc = vmsvga3dQueryCaps(pThisCC, i, &val);
6209	if (RT_SUCCESS(rc))
6210	{
6211	pData[idxCap][0] = i;
6212	pData[idxCap][1] = val;
6213	idxCap++;
6214	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
6215	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
6216	else
6217	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
6218	&g_apszVmSvgaDevCapNames[i][1]));
6219	}
6220	else
6221	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
6222	}
6223	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6224	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6225
6226	/* Mark end of record array. */
6227	pCaps->header.length = 0;
6228
6229	RTLogRelSetBuffering(fSavedBuffering);
6230	}
6231
6232	# endif
6233
6234	/**
6235	* Resets the SVGA hardware state
6236	*
6237	* @returns VBox status code.
6238	* @param pDevIns The device instance.
6239	*/
6240	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
6241	{
6242	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6243	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6244	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6245
6246	/* Reset before init? */
6247	if (!pSVGAState)
6248	return VINF_SUCCESS;
6249
6250	Log(("vmsvgaR3Reset\n"));
6251
6252	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6253	pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6254	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6255
6256	/* Reset other stuff. */
6257	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6258	RT_ZERO(pThis->svga.au32ScratchRegion);
6259
6260	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6261	vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6262
6263	RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6264
6265	/* Initialize FIFO and register capabilities. */
6266	vmsvgaR3InitCaps(pThis, pThisCC);
6267
6268	# ifdef VBOX_WITH_VMSVGA3D
6269	if (pThis->svga.f3DEnabled)
6270	vmsvgaR3InitFifo3DCaps(pThisCC);
6271	# endif
6272
6273	/* VRAM tracking is enabled by default during bootup. */
6274	pThis->svga.fVRAMTracking = true;
6275	pThis->svga.fEnabled = false;
6276
6277	/* Invalidate current settings. */
6278	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6279	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6280	pThis->svga.uBpp = pThis->svga.uHostBpp;
6281	pThis->svga.cbScanline = 0;
6282	pThis->svga.u32PitchLock = 0;
6283
6284	return rc;
6285	}
6286
6287	/**
6288	* Cleans up the SVGA hardware state
6289	*
6290	* @returns VBox status code.
6291	* @param pDevIns The device instance.
6292	*/
6293	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
6294	{
6295	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6296	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6297
6298	/*
6299	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6300	*/
6301	if (pThisCC->svga.pFIFOIOThread)
6302	{
6303	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
6304	NULL /pvParam/, 30000 /ms/);
6305	AssertLogRelRC(rc);
6306
6307	rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
6308	AssertLogRelRC(rc);
6309	pThisCC->svga.pFIFOIOThread = NULL;
6310	}
6311
6312	/*
6313	* Destroy the special SVGA state.
6314	*/
6315	if (pThisCC->svga.pSvgaR3State)
6316	{
6317	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6318
6319	RTMemFree(pThisCC->svga.pSvgaR3State);
6320	pThisCC->svga.pSvgaR3State = NULL;
6321	}
6322
6323	/*
6324	* Free our resources residing in the VGA state.
6325	*/
6326	if (pThisCC->svga.pbVgaFrameBufferR3)
6327	{
6328	RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
6329	pThisCC->svga.pbVgaFrameBufferR3 = NULL;
6330	}
6331	if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
6332	{
6333	RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
6334	pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
6335	}
6336	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
6337	{
6338	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
6339	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
6340	}
6341
6342	return VINF_SUCCESS;
6343	}
6344
6345	/**
6346	* Initialize the SVGA hardware state
6347	*
6348	* @returns VBox status code.
6349	* @param pDevIns The device instance.
6350	*/
6351	int vmsvgaR3Init(PPDMDEVINS pDevIns)
6352	{
6353	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6354	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6355	PVMSVGAR3STATE pSVGAState;
6356	int rc;
6357
6358	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6359	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6360
6361	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6362
6363	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6364	pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6365	AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6366
6367	/* Create event semaphore. */
6368	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
6369	AssertRCReturn(rc, rc);
6370
6371	/* Create event semaphore. */
6372	rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
6373	AssertRCReturn(rc, rc);
6374
6375	pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
6376	AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
6377
6378	rc = vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6379	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6380
6381	pSVGAState = pThisCC->svga.pSvgaR3State;
6382
6383	/* Initialize FIFO and register capabilities. */
6384	vmsvgaR3InitCaps(pThis, pThisCC);
6385
6386	# ifdef VBOX_WITH_VMSVGA3D
6387	if (pThis->svga.f3DEnabled)
6388	{
6389	rc = vmsvga3dInit(pDevIns, pThis, pThisCC);
6390	if (RT_FAILURE(rc))
6391	{
6392	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6393	pThis->svga.f3DEnabled = false;
6394	}
6395	}
6396	# endif
6397	/* VRAM tracking is enabled by default during bootup. */
6398	pThis->svga.fVRAMTracking = true;
6399
6400	/* Set up the host bpp. This value is as a default for the programmable
6401	* bpp value. On old implementations, SVGA_REG_HOST_BITS_PER_PIXEL did not
6402	* exist and SVGA_REG_BITS_PER_PIXEL was read-only, returning what was later
6403	* separated as SVGA_REG_HOST_BITS_PER_PIXEL.
6404	*
6405	* NB: The driver cBits value is currently constant for the lifetime of the
6406	* VM. If that changes, the host bpp logic might need revisiting.
6407	*/
6408	pThis->svga.uHostBpp = (pThisCC->pDrv->cBits + 7) & ~7;
6409
6410	/* Invalidate current settings. */
6411	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6412	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6413	pThis->svga.uBpp = pThis->svga.uHostBpp;
6414	pThis->svga.cbScanline = 0;
6415
6416	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6417	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6418	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6419	{
6420	pThis->svga.u32MaxWidth -= 256;
6421	pThis->svga.u32MaxHeight -= 256;
6422	}
6423	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6424
6425	# ifdef DEBUG_GMR_ACCESS
6426	/* Register the GMR access handler type. */
6427	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
6428	vmsvgaR3GmrAccessHandler,
6429	NULL, NULL, NULL,
6430	NULL, NULL, NULL,
6431	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6432	AssertRCReturn(rc, rc);
6433	# endif
6434
6435	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6436	/* Register the FIFO access handler type. In addition to
6437	debugging FIFO access, this is also used to facilitate
6438	extended fifo thread sleeps. */
6439	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns),
6440	# ifdef DEBUG_FIFO_ACCESS
6441	PGMPHYSHANDLERKIND_ALL,
6442	# else
6443	PGMPHYSHANDLERKIND_WRITE,
6444	# endif
6445	vmsvgaR3FifoAccessHandler,
6446	NULL, NULL, NULL,
6447	NULL, NULL, NULL,
6448	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6449	AssertRCReturn(rc, rc);
6450	# endif
6451
6452	/* Create the async IO thread. */
6453	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
6454	RTTHREADTYPE_IO, "VMSVGA FIFO");
6455	if (RT_FAILURE(rc))
6456	{
6457	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6458	return rc;
6459	}
6460
6461	/*
6462	* Statistics.
6463	*/
6464	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6465	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6466	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6467	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6468	# ifdef VBOX_WITH_STATISTICS
6469	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6470	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6471	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6472	# endif
6473	REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
6474	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6475	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6476	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6477	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6478	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6479	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6480	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6481	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6482	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6483	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6484	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6485	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6486	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6487	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6488	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6489	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6490	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6491	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6492	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6493	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6494	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6495	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6496	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6497	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6498	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6499	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6500	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6501	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6502	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6503	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6504	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6505	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6506	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6507	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6508	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6509	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6510	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6511	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6512	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6513	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6514	REG_CNT(&pSVGAState->StatR3CmdMoveCursor, "VMSVGA/Cmd/MoveCursor", "SVGA_CMD_MOVE_CURSOR");
6515	REG_CNT(&pSVGAState->StatR3CmdDisplayCursor, "VMSVGA/Cmd/DisplayCursor", "SVGA_CMD_DISPLAY_CURSOR");
6516	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6517	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6518	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6519	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6520	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6521	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6522	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6523	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6524	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6525	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6526	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6527	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6528	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6529
6530	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6531	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6532	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6533	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6534	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6535	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6536	REG_CNT(&pThis->svga.StatRegCursorXWr, "VMSVGA/Reg/CursorXWrite", "SVGA_REG_CURSOR_X writes.");
6537	REG_CNT(&pThis->svga.StatRegCursorYWr, "VMSVGA/Reg/CursorYWrite", "SVGA_REG_CURSOR_Y writes.");
6538	REG_CNT(&pThis->svga.StatRegCursorIdWr, "VMSVGA/Reg/CursorIdWrite", "SVGA_REG_CURSOR_ID writes.");
6539	REG_CNT(&pThis->svga.StatRegCursorOnWr, "VMSVGA/Reg/CursorOnWrite", "SVGA_REG_CURSOR_ON writes.");
6540	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6541	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6542	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6543	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6544	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6545	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6546	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6547	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6548	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6549	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6550	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6551	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6552	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6553	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6554	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6555	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6556	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6557	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6558	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6559	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6560	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6561	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6562	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6563	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6564	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6565
6566	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6567	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6568	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6569	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6570	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6571	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6572	REG_CNT(&pThis->svga.StatRegCursorXRd, "VMSVGA/Reg/CursorXRead", "SVGA_REG_CURSOR_X reads.");
6573	REG_CNT(&pThis->svga.StatRegCursorYRd, "VMSVGA/Reg/CursorYRead", "SVGA_REG_CURSOR_Y reads.");
6574	REG_CNT(&pThis->svga.StatRegCursorIdRd, "VMSVGA/Reg/CursorIdRead", "SVGA_REG_CURSOR_ID reads.");
6575	REG_CNT(&pThis->svga.StatRegCursorOnRd, "VMSVGA/Reg/CursorOnRead", "SVGA_REG_CURSOR_ON reads.");
6576	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6577	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6578	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6579	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6580	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6581	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6582	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6583	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6584	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6585	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6586	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6587	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6588	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6589	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6590	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6591	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6592	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6593	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6594	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6595	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6596	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6597	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6598	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6599	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6600	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6601	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6602	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6603	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6604	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6605	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6606	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6607	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6608	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6609	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6610	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6611	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6612	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6613	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6614	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6615	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6616	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6617	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6618
6619	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6620	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6621	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6622	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6623	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6624	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6625	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6626	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6627	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6628	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6629	# endif
6630	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6631	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6632	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6633	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6634	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6635
6636	# undef REG_CNT
6637	# undef REG_PRF
6638
6639	/*
6640	* Info handlers.
6641	*/
6642	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6643	# ifdef VBOX_WITH_VMSVGA3D
6644	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6645	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6646	"VMSVGA 3d surface details. "
6647	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6648	vmsvgaR3Info3dSurface);
6649	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6650	"VMSVGA 3d surface details and bitmap: "
6651	"sid[>dir]",
6652	vmsvgaR3Info3dSurfaceBmp);
6653	# endif
6654
6655	return VINF_SUCCESS;
6656	}
6657
6658	/**
6659	* Power On notification.
6660	*
6661	* @returns VBox status code.
6662	* @param pDevIns The device instance data.
6663	*
6664	* @remarks Caller enters the device critical section.
6665	*/
6666	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6667	{
6668	# ifdef VBOX_WITH_VMSVGA3D
6669	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6670	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6671	if (pThis->svga.f3DEnabled)
6672	{
6673	int rc = vmsvga3dPowerOn(pDevIns, pThis, pThisCC);
6674
6675	if (RT_SUCCESS(rc))
6676	{
6677	/* Initialize FIFO 3D capabilities. */
6678	vmsvgaR3InitFifo3DCaps(pThisCC);
6679	}
6680	}
6681	# else /* !VBOX_WITH_VMSVGA3D */
6682	RT_NOREF(pDevIns);
6683	# endif /* !VBOX_WITH_VMSVGA3D */
6684	}
6685
6686	#endif /* IN_RING3 */

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 83278

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