DevVGA-SVGA.cpp@ 83274

Last change on this file since 83274 was 83274, checked in by vboxsync, 5 years ago
VMSVGA: Implemented register-based cursor movement interface used by old X11 drivers (see bugref:9424).
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 303.4 KB

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1	/* $Id: DevVGA-SVGA.cpp 83274 2020-03-12 17:12:56Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	* - LogRel for the usual important stuff.
13	* - LogRel2 for cursor.
14	* - LogRel3 for 3D performance data.
15	*/
16
17	/*
18	* Copyright (C) 2013-2020 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.215389.xyz. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29
30	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
31	*
32	* This device emulation was contributed by trivirt AG. It offers an
33	* alternative to our Bochs based VGA graphics and 3d emulations. This is
34	* valuable for Xorg based guests, as there is driver support shipping with Xorg
35	* since it forked from XFree86.
36	*
37	*
38	* @section sec_dev_vmsvga_sdk The VMware SDK
39	*
40	* This is officially deprecated now, however it's still quite useful,
41	* especially for getting the old features working:
42	* http://vmware-svga.sourceforge.net/
43	*
44	* They currently point developers at the following resources.
45	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
46	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
47	* - http://cgit.freedesktop.org/mesa/vmwgfx/
48	*
49	* @subsection subsec_dev_vmsvga_sdk_results Test results
50	*
51	* Test results:
52	* - 2dmark.img:
53	* + todo
54	* - backdoor-tclo.img:
55	* + todo
56	* - blit-cube.img:
57	* + todo
58	* - bunnies.img:
59	* + todo
60	* - cube.img:
61	* + todo
62	* - cubemark.img:
63	* + todo
64	* - dynamic-vertex-stress.img:
65	* + todo
66	* - dynamic-vertex.img:
67	* + todo
68	* - fence-stress.img:
69	* + todo
70	* - gmr-test.img:
71	* + todo
72	* - half-float-test.img:
73	* + todo
74	* - noscreen-cursor.img:
75	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
76	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
77	* visible though.)
78	* - Cursor animation via the palette doesn't work.
79	* - During debugging, it turns out that the framebuffer content seems to
80	* be halfways ignore or something (memset(fb, 0xcc, lots)).
81	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
82	* grow it 0x10 fold (128KB -> 2MB like in WS10).
83	* - null.img:
84	* + todo
85	* - pong.img:
86	* + todo
87	* - presentReadback.img:
88	* + todo
89	* - resolution-set.img:
90	* + todo
91	* - rt-gamma-test.img:
92	* + todo
93	* - screen-annotation.img:
94	* + todo
95	* - screen-cursor.img:
96	* + todo
97	* - screen-dma-coalesce.img:
98	* + todo
99	* - screen-gmr-discontig.img:
100	* + todo
101	* - screen-gmr-remap.img:
102	* + todo
103	* - screen-multimon.img:
104	* + todo
105	* - screen-present-clip.img:
106	* + todo
107	* - screen-render-test.img:
108	* + todo
109	* - screen-simple.img:
110	* + todo
111	* - screen-text.img:
112	* + todo
113	* - simple-shaders.img:
114	* + todo
115	* - simple_blit.img:
116	* + todo
117	* - tiny-2d-updates.img:
118	* + todo
119	* - video-formats.img:
120	* + todo
121	* - video-sync.img:
122	* + todo
123	*
124	*/
125
126
127	/*********************************************************************************************************************************
128	* Header Files *
129	*********************************************************************************************************************************/
130	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
131	#define VMSVGA_USE_EMT_HALT_CODE
132	#include <VBox/vmm/pdmdev.h>
133	#include <VBox/version.h>
134	#include <VBox/err.h>
135	#include <VBox/log.h>
136	#include <VBox/vmm/pgm.h>
137	#ifdef VMSVGA_USE_EMT_HALT_CODE
138	# include <VBox/vmm/vmapi.h>
139	# include <VBox/vmm/vmcpuset.h>
140	#endif
141	#include <VBox/sup.h>
142
143	#include <iprt/assert.h>
144	#include <iprt/semaphore.h>
145	#include <iprt/uuid.h>
146	#ifdef IN_RING3
147	# include <iprt/ctype.h>
148	# include <iprt/mem.h>
149	# ifdef VBOX_STRICT
150	# include <iprt/time.h>
151	# endif
152	#endif
153
154	#include <VBox/AssertGuest.h>
155	#include <VBox/VMMDev.h>
156	#include <VBoxVideo.h>
157	#include <VBox/bioslogo.h>
158
159	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
160	#include "DevVGA.h"
161
162	#include "DevVGA-SVGA.h"
163	#include "vmsvga/svga_escape.h"
164	#include "vmsvga/svga_overlay.h"
165	#include "vmsvga/svga3d_caps.h"
166	#ifdef VBOX_WITH_VMSVGA3D
167	# include "DevVGA-SVGA3d.h"
168	# ifdef RT_OS_DARWIN
169	# include "DevVGA-SVGA3d-cocoa.h"
170	# endif
171	#endif
172
173
174	/*********************************************************************************************************************************
175	* Defined Constants And Macros *
176	*********************************************************************************************************************************/
177	/**
178	* Macro for checking if a fixed FIFO register is valid according to the
179	* current FIFO configuration.
180	*
181	* @returns true / false.
182	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
183	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
184	*/
185	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
186
187
188	/*********************************************************************************************************************************
189	* Structures and Typedefs *
190	*********************************************************************************************************************************/
191	/**
192	* 64-bit GMR descriptor.
193	*/
194	typedef struct
195	{
196	RTGCPHYS GCPhys;
197	uint64_t numPages;
198	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
199
200	/**
201	* GMR slot
202	*/
203	typedef struct
204	{
205	uint32_t cMaxPages;
206	uint32_t cbTotal;
207	uint32_t numDescriptors;
208	PVMSVGAGMRDESCRIPTOR paDesc;
209	} GMR, *PGMR;
210
211	#ifdef IN_RING3
212	/**
213	* Internal SVGA ring-3 only state.
214	*/
215	typedef struct VMSVGAR3STATE
216	{
217	GMR *paGMR; // [VMSVGAState::cGMR]
218	struct
219	{
220	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
221	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
222	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
223	} GMRFB;
224	struct
225	{
226	bool fActive;
227	uint32_t xHotspot;
228	uint32_t yHotspot;
229	uint32_t width;
230	uint32_t height;
231	uint32_t cbData;
232	void *pData;
233	} Cursor;
234	SVGAColorBGRX colorAnnotation;
235
236	# ifdef VMSVGA_USE_EMT_HALT_CODE
237	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
238	uint32_t volatile cBusyDelayedEmts;
239	/** Set of EMTs that are */
240	VMCPUSET BusyDelayedEmts;
241	# else
242	/** Number of EMTs waiting on hBusyDelayedEmts. */
243	uint32_t volatile cBusyDelayedEmts;
244	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
245	* busy (ugly). */
246	RTSEMEVENTMULTI hBusyDelayedEmts;
247	# endif
248
249	/** Information obout screens. */
250	VMSVGASCREENOBJECT aScreens[64];
251
252	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
253	STAMPROFILE StatBusyDelayEmts;
254
255	STAMPROFILE StatR3Cmd3dPresentProf;
256	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
257	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
258	STAMPROFILE StatR3Cmd3dBlitSurfaceToScreenProf;
259	STAMCOUNTER StatR3CmdDefineGmr2;
260	STAMCOUNTER StatR3CmdDefineGmr2Free;
261	STAMCOUNTER StatR3CmdDefineGmr2Modify;
262	STAMCOUNTER StatR3CmdRemapGmr2;
263	STAMCOUNTER StatR3CmdRemapGmr2Modify;
264	STAMCOUNTER StatR3CmdInvalidCmd;
265	STAMCOUNTER StatR3CmdFence;
266	STAMCOUNTER StatR3CmdUpdate;
267	STAMCOUNTER StatR3CmdUpdateVerbose;
268	STAMCOUNTER StatR3CmdDefineCursor;
269	STAMCOUNTER StatR3CmdDefineAlphaCursor;
270	STAMCOUNTER StatR3CmdMoveCursor;
271	STAMCOUNTER StatR3CmdDisplayCursor;
272	STAMCOUNTER StatR3CmdEscape;
273	STAMCOUNTER StatR3CmdDefineScreen;
274	STAMCOUNTER StatR3CmdDestroyScreen;
275	STAMCOUNTER StatR3CmdDefineGmrFb;
276	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
277	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
278	STAMCOUNTER StatR3CmdAnnotationFill;
279	STAMCOUNTER StatR3CmdAnnotationCopy;
280	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
281	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
282	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
283	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
284	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
285	STAMCOUNTER StatR3Cmd3dSurfaceDma;
286	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
287	STAMCOUNTER StatR3Cmd3dContextDefine;
288	STAMCOUNTER StatR3Cmd3dContextDestroy;
289	STAMCOUNTER StatR3Cmd3dSetTransform;
290	STAMCOUNTER StatR3Cmd3dSetZRange;
291	STAMCOUNTER StatR3Cmd3dSetRenderState;
292	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
293	STAMCOUNTER StatR3Cmd3dSetTextureState;
294	STAMCOUNTER StatR3Cmd3dSetMaterial;
295	STAMCOUNTER StatR3Cmd3dSetLightData;
296	STAMCOUNTER StatR3Cmd3dSetLightEnable;
297	STAMCOUNTER StatR3Cmd3dSetViewPort;
298	STAMCOUNTER StatR3Cmd3dSetClipPlane;
299	STAMCOUNTER StatR3Cmd3dClear;
300	STAMCOUNTER StatR3Cmd3dPresent;
301	STAMCOUNTER StatR3Cmd3dPresentReadBack;
302	STAMCOUNTER StatR3Cmd3dShaderDefine;
303	STAMCOUNTER StatR3Cmd3dShaderDestroy;
304	STAMCOUNTER StatR3Cmd3dSetShader;
305	STAMCOUNTER StatR3Cmd3dSetShaderConst;
306	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
307	STAMCOUNTER StatR3Cmd3dSetScissorRect;
308	STAMCOUNTER StatR3Cmd3dBeginQuery;
309	STAMCOUNTER StatR3Cmd3dEndQuery;
310	STAMCOUNTER StatR3Cmd3dWaitForQuery;
311	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
312	STAMCOUNTER StatR3Cmd3dActivateSurface;
313	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
314
315	STAMCOUNTER StatR3RegConfigDoneWr;
316	STAMCOUNTER StatR3RegGmrDescriptorWr;
317	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
318	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
319
320	STAMCOUNTER StatFifoCommands;
321	STAMCOUNTER StatFifoErrors;
322	STAMCOUNTER StatFifoUnkCmds;
323	STAMCOUNTER StatFifoTodoTimeout;
324	STAMCOUNTER StatFifoTodoWoken;
325	STAMPROFILE StatFifoStalls;
326	STAMPROFILE StatFifoExtendedSleep;
327	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
328	STAMCOUNTER StatFifoAccessHandler;
329	# endif
330	STAMCOUNTER StatFifoCursorFetchAgain;
331	STAMCOUNTER StatFifoCursorNoChange;
332	STAMCOUNTER StatFifoCursorPosition;
333	STAMCOUNTER StatFifoCursorVisiblity;
334	STAMCOUNTER StatFifoWatchdogWakeUps;
335	} VMSVGAR3STATE, *PVMSVGAR3STATE;
336	#endif /* IN_RING3 */
337
338
339	/*********************************************************************************************************************************
340	* Internal Functions *
341	*********************************************************************************************************************************/
342	#ifdef IN_RING3
343	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
344	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
345	# endif
346	# ifdef DEBUG_GMR_ACCESS
347	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
348	# endif
349	#endif
350
351
352	/*********************************************************************************************************************************
353	* Global Variables *
354	*********************************************************************************************************************************/
355	#ifdef IN_RING3
356
357	/**
358	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
359	*/
360	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
361	{
362	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
363	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
364	SSMFIELD_ENTRY_TERM()
365	};
366
367	/**
368	* SSM descriptor table for the GMR structure.
369	*/
370	static SSMFIELD const g_aGMRFields[] =
371	{
372	SSMFIELD_ENTRY( GMR, cMaxPages),
373	SSMFIELD_ENTRY( GMR, cbTotal),
374	SSMFIELD_ENTRY( GMR, numDescriptors),
375	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
376	SSMFIELD_ENTRY_TERM()
377	};
378
379	/**
380	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
381	*/
382	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
383	{
384	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
385	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
386	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
387	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
388	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
389	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
390	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
391	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
392	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
393	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
394	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
395	SSMFIELD_ENTRY_TERM()
396	};
397
398	/**
399	* SSM descriptor table for the VMSVGAR3STATE structure.
400	*/
401	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
402	{
403	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
404	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
405	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
406	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
407	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
408	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
409	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
410	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
411	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
412	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
414	#ifdef VMSVGA_USE_EMT_HALT_CODE
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
416	#else
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
418	#endif
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdMoveCursor),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDisplayCursor),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
470	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
474	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
475	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
479
480	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
483	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
484
485	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
488	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
489	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
490	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
491	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
492	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
493	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
494	# endif
495	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
496	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
497	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
498	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
499
500	SSMFIELD_ENTRY_TERM()
501	};
502
503	/**
504	* SSM descriptor table for the VGAState.svga structure.
505	*/
506	static SSMFIELD const g_aVGAStateSVGAFields[] =
507	{
508	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
509	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
510	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
511	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
512	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
513	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
514	SSMFIELD_ENTRY( VMSVGAState, fBusy),
515	SSMFIELD_ENTRY( VMSVGAState, fTraces),
516	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
517	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
518	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
519	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
520	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
521	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
522	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
523	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
524	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
525	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
526	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
527	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
528	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
529	SSMFIELD_ENTRY( VMSVGAState, uWidth),
530	SSMFIELD_ENTRY( VMSVGAState, uHeight),
531	SSMFIELD_ENTRY( VMSVGAState, uBpp),
532	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
533	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
534	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorX, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
535	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorY, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
536	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorID, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
537	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorOn, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
538	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
539	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
540	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
541	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
542	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
543	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
544	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
545	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
546	SSMFIELD_ENTRY_TERM()
547	};
548	#endif /* IN_RING3 */
549
550
551	/*********************************************************************************************************************************
552	* Internal Functions *
553	*********************************************************************************************************************************/
554	#ifdef IN_RING3
555	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
556	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
557	uint32_t uVersion, uint32_t uPass);
558	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
559	# ifdef VBOX_WITH_VMSVGA3D
560	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR);
561	# endif /* VBOX_WITH_VMSVGA3D */
562	#endif /* IN_RING3 */
563
564
565
566	#ifdef IN_RING3
567	VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
568	{
569	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
570	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
571	&& pSVGAState
572	&& pSVGAState->aScreens[idScreen].fDefined)
573	{
574	return &pSVGAState->aScreens[idScreen];
575	}
576	return NULL;
577	}
578	#endif /* IN_RING3 */
579
580	#ifdef LOG_ENABLED
581
582	/**
583	* Index register string name lookup
584	*
585	* @returns Index register string or "UNKNOWN"
586	* @param pThis The shared VGA/VMSVGA state.
587	* @param idxReg The index register.
588	*/
589	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
590	{
591	switch (idxReg)
592	{
593	case SVGA_REG_ID: return "SVGA_REG_ID";
594	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
595	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
596	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
597	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
598	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
599	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
600	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
601	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
602	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
603	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
604	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
605	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
606	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
607	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
608	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
609	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
610	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
611	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
612	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
613	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
614	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
615	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
616	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
617	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
618	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
619	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
620	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
621	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
622	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
623	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
624	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
625	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
626	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
627	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
628	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
629	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
630	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
631	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
632	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
633	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
634	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
635	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
636	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
637	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
638	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
639	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
640	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
641	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
642	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
643
644	default:
645	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
646	return "SVGA_SCRATCH_BASE reg";
647	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
648	return "SVGA_PALETTE_BASE reg";
649	return "UNKNOWN";
650	}
651	}
652
653	#ifdef IN_RING3
654	/**
655	* FIFO command name lookup
656	*
657	* @returns FIFO command string or "UNKNOWN"
658	* @param u32Cmd FIFO command
659	*/
660	static const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
661	{
662	switch (u32Cmd)
663	{
664	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
665	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
666	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
667	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
668	case SVGA_CMD_DISPLAY_CURSOR: return "SVGA_CMD_DISPLAY_CURSOR";
669	case SVGA_CMD_MOVE_CURSOR: return "SVGA_CMD_MOVE_CURSOR";
670	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
671	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
672	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
673	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
674	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
675	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
676	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
677	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
678	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
679	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
680	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
681	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
682	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
683	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
684	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
685	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
686	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
687	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
688	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
689	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
690	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
691	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
692	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
693	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
694	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
695	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
696	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
697	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
698	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
699	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
700	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
701	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
702	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
703	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
704	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
705	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
706	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
707	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
708	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
709	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
710	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
711	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
712	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
713	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
714	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
715	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
716	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
717	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
718	default: return "UNKNOWN";
719	}
720	}
721	# endif /* IN_RING3 */
722
723	#endif /* LOG_ENABLED */
724	#ifdef IN_RING3
725
726	/**
727	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
728	*/
729	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
730	{
731	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
732	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
733
734	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
735	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
736
737	/** @todo Test how it interacts with multiple screen objects. */
738	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
739	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
740	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
741
742	if (x < uWidth)
743	{
744	pThis->svga.viewport.x = x;
745	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
746	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
747	}
748	else
749	{
750	pThis->svga.viewport.x = uWidth;
751	pThis->svga.viewport.cx = 0;
752	pThis->svga.viewport.xRight = uWidth;
753	}
754	if (y < uHeight)
755	{
756	pThis->svga.viewport.y = y;
757	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
758	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
759	pThis->svga.viewport.yHighWC = uHeight - y;
760	}
761	else
762	{
763	pThis->svga.viewport.y = uHeight;
764	pThis->svga.viewport.cy = 0;
765	pThis->svga.viewport.yLowWC = 0;
766	pThis->svga.viewport.yHighWC = 0;
767	}
768
769	# ifdef VBOX_WITH_VMSVGA3D
770	/*
771	* Now inform the 3D backend.
772	*/
773	if (pThis->svga.f3DEnabled)
774	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
775	# else
776	RT_NOREF(OldViewport);
777	# endif
778	}
779
780
781	/**
782	* Updating screen information in API
783	*
784	* @param pThis The The shared VGA/VMSVGA instance data.
785	* @param pThisCC The VGA/VMSVGA state for ring-3.
786	*/
787	void vmsvgaR3VBVAResize(PVGASTATE pThis, PVGASTATECC pThisCC)
788	{
789	int rc;
790
791	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
792
793	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
794	{
795	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
796	if (!pScreen->fModified)
797	continue;
798
799	pScreen->fModified = false;
800
801	VBVAINFOVIEW view;
802	RT_ZERO(view);
803	view.u32ViewIndex = pScreen->idScreen;
804	// view.u32ViewOffset = 0;
805	view.u32ViewSize = pThis->vram_size;
806	view.u32MaxScreenSize = pThis->vram_size;
807
808	VBVAINFOSCREEN screen;
809	RT_ZERO(screen);
810	screen.u32ViewIndex = pScreen->idScreen;
811
812	if (pScreen->fDefined)
813	{
814	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
815	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
816	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
817	{
818	Assert(pThis->svga.fGFBRegisters);
819	continue;
820	}
821
822	screen.i32OriginX = pScreen->xOrigin;
823	screen.i32OriginY = pScreen->yOrigin;
824	screen.u32StartOffset = pScreen->offVRAM;
825	screen.u32LineSize = pScreen->cbPitch;
826	screen.u32Width = pScreen->cWidth;
827	screen.u32Height = pScreen->cHeight;
828	screen.u16BitsPerPixel = pScreen->cBpp;
829	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
830	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
831	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
832	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
833	}
834	else
835	{
836	/* Screen is destroyed. */
837	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
838	}
839
840	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pThisCC->pbVRam, /fResetInputMapping=/ true);
841	AssertRC(rc);
842	}
843	}
844
845
846	/**
847	* @interface_method_impl{PDMIDISPLAYPORT,pfnReportMonitorPositions}
848	*
849	* Used to update screen offsets (positions) since appearently vmwgfx fails to
850	* pass correct offsets thru FIFO.
851	*/
852	DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PCRTPOINT paPositions)
853	{
854	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
855	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
856	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
857
858	/* We assume cPositions is the # of outputs Xserver reports and paPositions is (-1, -1) for disabled monitors. */
859	cPositions = RT_MIN(cPositions, RT_ELEMENTS(pSVGAState->aScreens));
860	for (uint32_t i = 0; i < cPositions; ++i)
861	{
862	if ( pSVGAState->aScreens[i].xOrigin == paPositions[i].x
863	&& pSVGAState->aScreens[i].yOrigin == paPositions[i].y)
864	continue;
865
866	if (pSVGAState->aScreens[i].xOrigin == -1)
867	continue;
868	if (pSVGAState->aScreens[i].yOrigin == -1)
869	continue;
870
871	pSVGAState->aScreens[i].xOrigin = paPositions[i].x;
872	pSVGAState->aScreens[i].yOrigin = paPositions[i].y;
873	pSVGAState->aScreens[i].fModified = true;
874	}
875
876	vmsvgaR3VBVAResize(pThis, pThisCC);
877	}
878
879	#endif /* IN_RING3 */
880
881	/**
882	* Read port register
883	*
884	* @returns VBox status code.
885	* @param pDevIns The device instance.
886	* @param pThis The shared VGA/VMSVGA state.
887	* @param pu32 Where to store the read value
888	*/
889	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
890	{
891	#ifdef IN_RING3
892	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
893	#endif
894	int rc = VINF_SUCCESS;
895	*pu32 = 0;
896
897	/* Rough index register validation. */
898	uint32_t idxReg = pThis->svga.u32IndexReg;
899	#if !defined(IN_RING3) && defined(VBOX_STRICT)
900	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
901	VINF_IOM_R3_IOPORT_READ);
902	#else
903	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
904	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
905	VINF_SUCCESS);
906	#endif
907	RT_UNTRUSTED_VALIDATED_FENCE();
908
909	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
910	if ( idxReg >= SVGA_REG_CAPABILITIES
911	&& pThis->svga.u32SVGAId == SVGA_ID_0)
912	{
913	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
914	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
915	}
916
917	switch (idxReg)
918	{
919	case SVGA_REG_ID:
920	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
921	*pu32 = pThis->svga.u32SVGAId;
922	break;
923
924	case SVGA_REG_ENABLE:
925	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
926	*pu32 = pThis->svga.fEnabled;
927	break;
928
929	case SVGA_REG_WIDTH:
930	{
931	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
932	if ( pThis->svga.fEnabled
933	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
934	*pu32 = pThis->svga.uWidth;
935	else
936	{
937	#ifndef IN_RING3
938	rc = VINF_IOM_R3_IOPORT_READ;
939	#else
940	*pu32 = pThisCC->pDrv->cx;
941	#endif
942	}
943	break;
944	}
945
946	case SVGA_REG_HEIGHT:
947	{
948	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
949	if ( pThis->svga.fEnabled
950	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
951	*pu32 = pThis->svga.uHeight;
952	else
953	{
954	#ifndef IN_RING3
955	rc = VINF_IOM_R3_IOPORT_READ;
956	#else
957	*pu32 = pThisCC->pDrv->cy;
958	#endif
959	}
960	break;
961	}
962
963	case SVGA_REG_MAX_WIDTH:
964	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
965	*pu32 = pThis->svga.u32MaxWidth;
966	break;
967
968	case SVGA_REG_MAX_HEIGHT:
969	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
970	*pu32 = pThis->svga.u32MaxHeight;
971	break;
972
973	case SVGA_REG_DEPTH:
974	/* This returns the color depth of the current mode. */
975	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
976	switch (pThis->svga.uBpp)
977	{
978	case 15:
979	case 16:
980	case 24:
981	*pu32 = pThis->svga.uBpp;
982	break;
983
984	default:
985	case 32:
986	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
987	break;
988	}
989	break;
990
991	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
992	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
993	if ( pThis->svga.fEnabled
994	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
995	*pu32 = pThis->svga.uBpp;
996	else
997	{
998	#ifndef IN_RING3
999	rc = VINF_IOM_R3_IOPORT_READ;
1000	#else
1001	*pu32 = pThisCC->pDrv->cBits;
1002	#endif
1003	}
1004	break;
1005
1006	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1007	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
1008	if ( pThis->svga.fEnabled
1009	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1010	*pu32 = (pThis->svga.uBpp + 7) & ~7;
1011	else
1012	{
1013	#ifndef IN_RING3
1014	rc = VINF_IOM_R3_IOPORT_READ;
1015	#else
1016	*pu32 = (pThisCC->pDrv->cBits + 7) & ~7;
1017	#endif
1018	}
1019	break;
1020
1021	case SVGA_REG_PSEUDOCOLOR:
1022	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
1023	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
1024	break;
1025
1026	case SVGA_REG_RED_MASK:
1027	case SVGA_REG_GREEN_MASK:
1028	case SVGA_REG_BLUE_MASK:
1029	{
1030	uint32_t uBpp;
1031
1032	if ( pThis->svga.fEnabled
1033	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1034	{
1035	uBpp = pThis->svga.uBpp;
1036	}
1037	else
1038	{
1039	#ifndef IN_RING3
1040	rc = VINF_IOM_R3_IOPORT_READ;
1041	break;
1042	#else
1043	uBpp = pThisCC->pDrv->cBits;
1044	#endif
1045	}
1046	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
1047	switch (uBpp)
1048	{
1049	case 8:
1050	u32RedMask = 0x07;
1051	u32GreenMask = 0x38;
1052	u32BlueMask = 0xc0;
1053	break;
1054
1055	case 15:
1056	u32RedMask = 0x0000001f;
1057	u32GreenMask = 0x000003e0;
1058	u32BlueMask = 0x00007c00;
1059	break;
1060
1061	case 16:
1062	u32RedMask = 0x0000001f;
1063	u32GreenMask = 0x000007e0;
1064	u32BlueMask = 0x0000f800;
1065	break;
1066
1067	case 24:
1068	case 32:
1069	default:
1070	u32RedMask = 0x00ff0000;
1071	u32GreenMask = 0x0000ff00;
1072	u32BlueMask = 0x000000ff;
1073	break;
1074	}
1075	switch (idxReg)
1076	{
1077	case SVGA_REG_RED_MASK:
1078	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
1079	*pu32 = u32RedMask;
1080	break;
1081
1082	case SVGA_REG_GREEN_MASK:
1083	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
1084	*pu32 = u32GreenMask;
1085	break;
1086
1087	case SVGA_REG_BLUE_MASK:
1088	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
1089	*pu32 = u32BlueMask;
1090	break;
1091	}
1092	break;
1093	}
1094
1095	case SVGA_REG_BYTES_PER_LINE:
1096	{
1097	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
1098	if ( pThis->svga.fEnabled
1099	&& pThis->svga.cbScanline)
1100	*pu32 = pThis->svga.cbScanline;
1101	else
1102	{
1103	#ifndef IN_RING3
1104	rc = VINF_IOM_R3_IOPORT_READ;
1105	#else
1106	*pu32 = pThisCC->pDrv->cbScanline;
1107	#endif
1108	}
1109	break;
1110	}
1111
1112	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1113	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1114	*pu32 = pThis->vram_size;
1115	break;
1116
1117	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1118	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1119	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1120	*pu32 = pThis->GCPhysVRAM;
1121	break;
1122
1123	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1124	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1125	/* Always zero in our case. */
1126	*pu32 = 0;
1127	break;
1128
1129	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1130	{
1131	#ifndef IN_RING3
1132	rc = VINF_IOM_R3_IOPORT_READ;
1133	#else
1134	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1135
1136	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1137	if ( pThis->svga.fEnabled
1138	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1139	{
1140	/* Hardware enabled; return real framebuffer size .*/
1141	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1142	}
1143	else
1144	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1145
1146	pu32 = RT_MIN(pThis->vram_size, pu32);
1147	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1148	#endif
1149	break;
1150	}
1151
1152	case SVGA_REG_CAPABILITIES:
1153	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1154	*pu32 = pThis->svga.u32RegCaps;
1155	break;
1156
1157	case SVGA_REG_MEM_START: /* FIFO start */
1158	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1159	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1160	*pu32 = pThis->svga.GCPhysFIFO;
1161	break;
1162
1163	case SVGA_REG_MEM_SIZE: /* FIFO size */
1164	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1165	*pu32 = pThis->svga.cbFIFO;
1166	break;
1167
1168	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1169	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1170	*pu32 = pThis->svga.fConfigured;
1171	break;
1172
1173	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1174	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1175	*pu32 = 0;
1176	break;
1177
1178	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1179	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1180	if (pThis->svga.fBusy)
1181	{
1182	#ifndef IN_RING3
1183	/* Go to ring-3 and halt the CPU. */
1184	rc = VINF_IOM_R3_IOPORT_READ;
1185	RT_NOREF(pDevIns);
1186	break;
1187	#else
1188	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1189	/* The guest is basically doing a HLT via the device here, but with
1190	a special wake up condition on FIFO completion. */
1191	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1192	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1193	PVM pVM = PDMDevHlpGetVM(pDevIns);
1194	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1195	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1196	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1197	if (pThis->svga.fBusy)
1198	{
1199	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1200	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1201	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1202	}
1203	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1204	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1205	# else
1206
1207	/* Delay the EMT a bit so the FIFO and others can get some work done.
1208	This used to be a crude 50 ms sleep. The current code tries to be
1209	more efficient, but the consept is still very crude. */
1210	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1211	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1212	RTThreadYield();
1213	if (pThis->svga.fBusy)
1214	{
1215	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1216
1217	if (pThis->svga.fBusy && cRefs == 1)
1218	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1219	if (pThis->svga.fBusy)
1220	{
1221	/** @todo If this code is going to stay, we need to call into the halt/wait
1222	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1223	* suffer when the guest is polling on a busy FIFO. */
1224	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns));
1225	if (cNsMaxWait >= RT_NS_100US)
1226	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1227	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1228	RT_MIN(cNsMaxWait, RT_NS_10MS));
1229	}
1230
1231	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1232	}
1233	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1234	# endif
1235	*pu32 = pThis->svga.fBusy != 0;
1236	#endif
1237	}
1238	else
1239	*pu32 = false;
1240	break;
1241
1242	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1243	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1244	*pu32 = pThis->svga.u32GuestId;
1245	break;
1246
1247	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1248	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1249	*pu32 = pThis->svga.cScratchRegion;
1250	break;
1251
1252	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1253	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1254	*pu32 = SVGA_FIFO_NUM_REGS;
1255	break;
1256
1257	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1258	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1259	*pu32 = pThis->svga.u32PitchLock;
1260	break;
1261
1262	case SVGA_REG_IRQMASK: /* Interrupt mask */
1263	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1264	*pu32 = pThis->svga.u32IrqMask;
1265	break;
1266
1267	/* See "Guest memory regions" below. */
1268	case SVGA_REG_GMR_ID:
1269	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1270	*pu32 = pThis->svga.u32CurrentGMRId;
1271	break;
1272
1273	case SVGA_REG_GMR_DESCRIPTOR:
1274	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1275	/* Write only */
1276	*pu32 = 0;
1277	break;
1278
1279	case SVGA_REG_GMR_MAX_IDS:
1280	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1281	*pu32 = pThis->svga.cGMR;
1282	break;
1283
1284	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1285	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1286	*pu32 = VMSVGA_MAX_GMR_PAGES;
1287	break;
1288
1289	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1290	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1291	*pu32 = pThis->svga.fTraces;
1292	break;
1293
1294	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1295	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1296	*pu32 = VMSVGA_MAX_GMR_PAGES;
1297	break;
1298
1299	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1300	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1301	*pu32 = VMSVGA_SURFACE_SIZE;
1302	break;
1303
1304	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1305	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1306	break;
1307
1308	/* Mouse cursor support. */
1309	case SVGA_REG_CURSOR_ID:
1310	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdRd);
1311	*pu32 = pThis->svga.uCursorID;
1312	break;
1313
1314	case SVGA_REG_CURSOR_X:
1315	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXRd);
1316	*pu32 = pThis->svga.uCursorX;
1317	break;
1318
1319	case SVGA_REG_CURSOR_Y:
1320	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYRd);
1321	*pu32 = pThis->svga.uCursorY;
1322	break;
1323
1324	case SVGA_REG_CURSOR_ON:
1325	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnRd);
1326	*pu32 = pThis->svga.uCursorOn;
1327	break;
1328
1329	/* Legacy multi-monitor support */
1330	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1331	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1332	*pu32 = 1;
1333	break;
1334
1335	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1336	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1337	*pu32 = 0;
1338	break;
1339
1340	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1341	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1342	*pu32 = 0;
1343	break;
1344
1345	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1346	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1347	*pu32 = 0;
1348	break;
1349
1350	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1351	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1352	*pu32 = 0;
1353	break;
1354
1355	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1356	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1357	*pu32 = pThis->svga.uWidth;
1358	break;
1359
1360	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1361	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1362	*pu32 = pThis->svga.uHeight;
1363	break;
1364
1365	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1366	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1367	/* We must return something sensible here otherwise the Linux driver
1368	will take a legacy code path without 3d support. This number also
1369	limits how many screens Linux guests will allow. */
1370	*pu32 = pThis->cMonitors;
1371	break;
1372
1373	default:
1374	{
1375	uint32_t offReg;
1376	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1377	{
1378	RT_UNTRUSTED_VALIDATED_FENCE();
1379	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1380	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1381	}
1382	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1383	{
1384	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1385	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1386	RT_UNTRUSTED_VALIDATED_FENCE();
1387	uint32_t u32 = pThis->last_palette[offReg / 3];
1388	switch (offReg % 3)
1389	{
1390	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1391	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1392	case 2: pu32 = u32 & 0xff; break; / blue */
1393	}
1394	}
1395	else
1396	{
1397	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1398	rc = VINF_IOM_R3_IOPORT_READ;
1399	#else
1400	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1401
1402	/* Do not assert. The guest might be reading all registers. */
1403	LogFunc(("Unknown reg=%#x\n", idxReg));
1404	#endif
1405	}
1406	break;
1407	}
1408	}
1409	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1410	return rc;
1411	}
1412
1413	#ifdef IN_RING3
1414	/**
1415	* Apply the current resolution settings to change the video mode.
1416	*
1417	* @returns VBox status code.
1418	* @param pThis The shared VGA state.
1419	* @param pThisCC The ring-3 VGA state.
1420	*/
1421	static int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1422	{
1423	/* Always do changemode on FIFO thread. */
1424	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1425
1426	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1427
1428	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1429
1430	if (pThis->svga.fGFBRegisters)
1431	{
1432	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1433	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1434	* deletes all screens other than screen #0, and redefines screen
1435	* #0 according to the specified mode. Drivers that use
1436	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1437	*/
1438
1439	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1440	pScreen->fDefined = true;
1441	pScreen->fModified = true;
1442	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1443	pScreen->idScreen = 0;
1444	pScreen->xOrigin = 0;
1445	pScreen->yOrigin = 0;
1446	pScreen->offVRAM = 0;
1447	pScreen->cbPitch = pThis->svga.cbScanline;
1448	pScreen->cWidth = pThis->svga.uWidth;
1449	pScreen->cHeight = pThis->svga.uHeight;
1450	pScreen->cBpp = pThis->svga.uBpp;
1451
1452	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1453	{
1454	/* Delete screen. */
1455	pScreen = &pSVGAState->aScreens[iScreen];
1456	if (pScreen->fDefined)
1457	{
1458	pScreen->fModified = true;
1459	pScreen->fDefined = false;
1460	}
1461	}
1462	}
1463	else
1464	{
1465	/* "If Screen Objects are supported, they can be used to fully
1466	* replace the functionality provided by the framebuffer registers
1467	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1468	*/
1469	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1470	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1471	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
1472	}
1473
1474	vmsvgaR3VBVAResize(pThis, pThisCC);
1475
1476	/* Last stuff. For the VGA device screenshot. */
1477	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1478	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1479	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1480	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1481	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1482
1483	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1484	if ( pThis->svga.viewport.cx == 0
1485	&& pThis->svga.viewport.cy == 0)
1486	{
1487	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1488	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1489	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1490	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1491	pThis->svga.viewport.yLowWC = 0;
1492	}
1493
1494	return VINF_SUCCESS;
1495	}
1496
1497	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1498	{
1499	VBVACMDHDR cmd;
1500	cmd.x = (int16_t)(pScreen->xOrigin + x);
1501	cmd.y = (int16_t)(pScreen->yOrigin + y);
1502	cmd.w = (uint16_t)w;
1503	cmd.h = (uint16_t)h;
1504
1505	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1506	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1507	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1508	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1509
1510	return VINF_SUCCESS;
1511	}
1512
1513	#endif /* IN_RING3 */
1514	#if defined(IN_RING0) \|\| defined(IN_RING3)
1515
1516	/**
1517	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1518	*
1519	* @param pThis The shared VGA/VMSVGA instance data.
1520	* @param pThisCC The VGA/VMSVGA state for the current context.
1521	* @param fState The busy state.
1522	*/
1523	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1524	{
1525	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1526
1527	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1528	{
1529	/* Race / unfortunately scheduling. Highly unlikly. */
1530	uint32_t cLoops = 64;
1531	do
1532	{
1533	ASMNopPause();
1534	fState = (pThis->svga.fBusy != 0);
1535	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1536	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1537	}
1538	}
1539
1540
1541	/**
1542	* Update the scanline pitch in response to the guest changing mode
1543	* width/bpp.
1544	*
1545	* @param pThis The shared VGA/VMSVGA state.
1546	* @param pThisCC The VGA/VMSVGA state for the current context.
1547	*/
1548	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1549	{
1550	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1551	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1552	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1553	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1554
1555	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1556	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1557	* location but it has a different meaning.
1558	*/
1559	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1560	uFifoPitchLock = 0;
1561
1562	/* Sanitize values. */
1563	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1564	uFifoPitchLock = 0;
1565	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1566	uRegPitchLock = 0;
1567
1568	/* Prefer the register value to the FIFO value.*/
1569	if (uRegPitchLock)
1570	pThis->svga.cbScanline = uRegPitchLock;
1571	else if (uFifoPitchLock)
1572	pThis->svga.cbScanline = uFifoPitchLock;
1573	else
1574	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1575
1576	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1577	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1578	}
1579
1580	#endif /* IN_RING0 \|\| IN_RING3 */
1581
1582	#ifdef IN_RING3
1583
1584	/**
1585	* Sends cursor position and visibility information from legacy
1586	* SVGA registers to the front-end.
1587	*/
1588	static void vmsvgaR3RegUpdateCursor(PVGASTATECC pThisCC, PVGASTATE pThis, uint32_t uCursorOn)
1589	{
1590	/*
1591	* Writing the X/Y/ID registers does not trigger changes; only writing the
1592	* SVGA_REG_CURSOR_ON register does. That minimizes the overhead.
1593	* We boldly assume that guests aren't stupid and aren't writing the CURSOR_ON
1594	* register if they don't have to.
1595	*/
1596	uint32_t x, y, idScreen;
1597	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
1598
1599	x = pThis->svga.uCursorX;
1600	y = pThis->svga.uCursorY;
1601	idScreen = SVGA_ID_INVALID; /* The old register interface is single screen only. */
1602
1603	/* The original values for SVGA_REG_CURSOR_ON were off (0) and on (1); later, the values
1604	* were extended as follows:
1605	*
1606	* SVGA_CURSOR_ON_HIDE 0
1607	* SVGA_CURSOR_ON_SHOW 1
1608	* SVGA_CURSOR_ON_REMOVE_FROM_FB 2 - cursor on but not in the framebuffer
1609	* SVGA_CURSOR_ON_RESTORE_TO_FB 3 - cursor on, possibly in the framebuffer
1610	*
1611	* Since we never draw the cursor into the guest's framebuffer, we do not need to
1612	* distinguish between the non-zero values but still remember them.
1613	*/
1614	if (RT_BOOL(pThis->svga.uCursorOn) != RT_BOOL(uCursorOn))
1615	{
1616	LogRel2(("vmsvgaR3RegUpdateCursor: uCursorOn %d prev CursorOn %d (%d,%d)\n", uCursorOn, pThis->svga.uCursorOn, x, y));
1617	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(uCursorOn), false, 0, 0, 0, 0, NULL);
1618	}
1619	pThis->svga.uCursorOn = uCursorOn;
1620	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
1621	}
1622
1623	#endif /* IN_RING3 */
1624
1625
1626	/**
1627	* Write port register
1628	*
1629	* @returns Strict VBox status code.
1630	* @param pDevIns The device instance.
1631	* @param pThis The shared VGA/VMSVGA state.
1632	* @param pThisCC The VGA/VMSVGA state for the current context.
1633	* @param u32 Value to write
1634	*/
1635	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1636	{
1637	#ifdef IN_RING3
1638	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1639	#endif
1640	VBOXSTRICTRC rc = VINF_SUCCESS;
1641	RT_NOREF(pThisCC);
1642
1643	/* Rough index register validation. */
1644	uint32_t idxReg = pThis->svga.u32IndexReg;
1645	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1646	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1647	VINF_IOM_R3_IOPORT_WRITE);
1648	#else
1649	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1650	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1651	VINF_SUCCESS);
1652	#endif
1653	RT_UNTRUSTED_VALIDATED_FENCE();
1654
1655	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1656	if ( idxReg >= SVGA_REG_CAPABILITIES
1657	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1658	{
1659	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1660	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1661	}
1662	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1663	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1664	switch (idxReg)
1665	{
1666	case SVGA_REG_WIDTH:
1667	case SVGA_REG_HEIGHT:
1668	case SVGA_REG_PITCHLOCK:
1669	case SVGA_REG_BITS_PER_PIXEL:
1670	pThis->svga.fGFBRegisters = true;
1671	break;
1672	default:
1673	break;
1674	}
1675
1676	switch (idxReg)
1677	{
1678	case SVGA_REG_ID:
1679	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1680	if ( u32 == SVGA_ID_0
1681	\|\| u32 == SVGA_ID_1
1682	\|\| u32 == SVGA_ID_2)
1683	pThis->svga.u32SVGAId = u32;
1684	else
1685	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1686	break;
1687
1688	case SVGA_REG_ENABLE:
1689	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1690	#ifdef IN_RING3
1691	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1692	&& pThis->svga.fEnabled == false)
1693	{
1694	/* Make a backup copy of the first 512kb in order to save font data etc. */
1695	/** @todo should probably swap here, rather than copy + zero */
1696	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1697	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1698	}
1699
1700	pThis->svga.fEnabled = u32;
1701	if (pThis->svga.fEnabled)
1702	{
1703	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1704	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1705	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1706	{
1707	/* Keep the current mode. */
1708	pThis->svga.uWidth = pThisCC->pDrv->cx;
1709	pThis->svga.uHeight = pThisCC->pDrv->cy;
1710	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1711	}
1712
1713	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1714	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1715	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1716	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1717	# ifdef LOG_ENABLED
1718	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1719	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1720	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1721	# endif
1722
1723	/* Disable or enable dirty page tracking according to the current fTraces value. */
1724	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1725
1726	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1727	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1728	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
1729	}
1730	else
1731	{
1732	/* Restore the text mode backup. */
1733	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1734
1735	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1736
1737	/* Enable dirty page tracking again when going into legacy mode. */
1738	vmsvgaR3SetTraces(pDevIns, pThis, true);
1739
1740	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1741	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1742	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1743
1744	/* Clear the pitch lock. */
1745	pThis->svga.u32PitchLock = 0;
1746	}
1747	#else /* !IN_RING3 */
1748	rc = VINF_IOM_R3_IOPORT_WRITE;
1749	#endif /* !IN_RING3 */
1750	break;
1751
1752	case SVGA_REG_WIDTH:
1753	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1754	if (pThis->svga.uWidth != u32)
1755	{
1756	#if defined(IN_RING3) \|\| defined(IN_RING0)
1757	pThis->svga.uWidth = u32;
1758	vmsvgaHCUpdatePitch(pThis, pThisCC);
1759	if (pThis->svga.fEnabled)
1760	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1761	#else
1762	rc = VINF_IOM_R3_IOPORT_WRITE;
1763	#endif
1764	}
1765	/* else: nop */
1766	break;
1767
1768	case SVGA_REG_HEIGHT:
1769	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1770	if (pThis->svga.uHeight != u32)
1771	{
1772	pThis->svga.uHeight = u32;
1773	if (pThis->svga.fEnabled)
1774	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1775	}
1776	/* else: nop */
1777	break;
1778
1779	case SVGA_REG_DEPTH:
1780	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1781	/** @todo read-only?? */
1782	break;
1783
1784	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1785	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1786	if (pThis->svga.uBpp != u32)
1787	{
1788	#if defined(IN_RING3) \|\| defined(IN_RING0)
1789	pThis->svga.uBpp = u32;
1790	vmsvgaHCUpdatePitch(pThis, pThisCC);
1791	if (pThis->svga.fEnabled)
1792	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1793	#else
1794	rc = VINF_IOM_R3_IOPORT_WRITE;
1795	#endif
1796	}
1797	/* else: nop */
1798	break;
1799
1800	case SVGA_REG_PSEUDOCOLOR:
1801	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1802	break;
1803
1804	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1805	#ifdef IN_RING3
1806	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1807	pThis->svga.fConfigured = u32;
1808	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1809	if (!pThis->svga.fConfigured)
1810	pThis->svga.fTraces = true;
1811	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1812	#else
1813	rc = VINF_IOM_R3_IOPORT_WRITE;
1814	#endif
1815	break;
1816
1817	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1818	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1819	if ( pThis->svga.fEnabled
1820	&& pThis->svga.fConfigured)
1821	{
1822	#if defined(IN_RING3) \|\| defined(IN_RING0)
1823	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
1824	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1825	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
1826	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
1827
1828	/* Kick the FIFO thread to start processing commands again. */
1829	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
1830	#else
1831	rc = VINF_IOM_R3_IOPORT_WRITE;
1832	#endif
1833	}
1834	/* else nothing to do. */
1835	else
1836	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1837
1838	break;
1839
1840	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1841	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1842	break;
1843
1844	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1845	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1846	pThis->svga.u32GuestId = u32;
1847	break;
1848
1849	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1850	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1851	pThis->svga.u32PitchLock = u32;
1852	/* Should this also update the FIFO pitch lock? Unclear. */
1853	break;
1854
1855	case SVGA_REG_IRQMASK: /* Interrupt mask */
1856	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1857	pThis->svga.u32IrqMask = u32;
1858
1859	/* Irq pending after the above change? */
1860	if (pThis->svga.u32IrqStatus & u32)
1861	{
1862	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1863	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
1864	}
1865	else
1866	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1867	break;
1868
1869	/* Mouse cursor support */
1870	case SVGA_REG_CURSOR_ID:
1871	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdWr);
1872	pThis->svga.uCursorID = u32;
1873	break;
1874
1875	case SVGA_REG_CURSOR_X:
1876	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXWr);
1877	pThis->svga.uCursorX = u32;
1878	break;
1879
1880	case SVGA_REG_CURSOR_Y:
1881	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYWr);
1882	pThis->svga.uCursorY = u32;
1883	break;
1884
1885	case SVGA_REG_CURSOR_ON:
1886	#ifdef IN_RING3
1887	/* The cursor is only updated when SVGA_REG_CURSOR_ON is written. */
1888	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnWr);
1889	vmsvgaR3RegUpdateCursor(pThisCC, pThis, u32);
1890	#else
1891	rc = VINF_IOM_R3_IOPORT_WRITE;
1892	#endif
1893	break;
1894
1895	/* Legacy multi-monitor support */
1896	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1897	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1898	break;
1899	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1900	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1901	break;
1902	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1903	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1904	break;
1905	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1906	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1907	break;
1908	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1909	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1910	break;
1911	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1912	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1913	break;
1914	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1915	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1916	break;
1917	#ifdef VBOX_WITH_VMSVGA3D
1918	/* See "Guest memory regions" below. */
1919	case SVGA_REG_GMR_ID:
1920	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1921	pThis->svga.u32CurrentGMRId = u32;
1922	break;
1923
1924	case SVGA_REG_GMR_DESCRIPTOR:
1925	# ifndef IN_RING3
1926	rc = VINF_IOM_R3_IOPORT_WRITE;
1927	break;
1928	# else /* IN_RING3 */
1929	{
1930	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1931
1932	/* Validate current GMR id. */
1933	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1934	AssertBreak(idGMR < pThis->svga.cGMR);
1935	RT_UNTRUSTED_VALIDATED_FENCE();
1936
1937	/* Free the old GMR if present. */
1938	vmsvgaR3GmrFree(pThisCC, idGMR);
1939
1940	/* Just undefine the GMR? */
1941	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1942	if (GCPhys == 0)
1943	{
1944	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1945	break;
1946	}
1947
1948
1949	/* Never cross a page boundary automatically. */
1950	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1951	uint32_t cPagesTotal = 0;
1952	uint32_t iDesc = 0;
1953	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1954	uint32_t cLoops = 0;
1955	RTGCPHYS GCPhysBase = GCPhys;
1956	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1957	{
1958	/* Read descriptor. */
1959	SVGAGuestMemDescriptor desc;
1960	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
1961	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
1962
1963	if (desc.numPages != 0)
1964	{
1965	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1966	cPagesTotal += desc.numPages;
1967	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1968
1969	if ((iDesc & 15) == 0)
1970	{
1971	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1972	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1973	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1974	}
1975
1976	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1977	paDescs[iDesc++].numPages = desc.numPages;
1978
1979	/* Continue with the next descriptor. */
1980	GCPhys += sizeof(desc);
1981	}
1982	else if (desc.ppn == 0)
1983	break; /* terminator */
1984	else /* Pointer to the next physical page of descriptors. */
1985	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1986
1987	cLoops++;
1988	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1989	}
1990
1991	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1992	if (RT_SUCCESS(rc))
1993	{
1994	/* Commit the GMR. */
1995	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1996	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1997	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1998	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1999	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
2000	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
2001	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
2002	}
2003	else
2004	{
2005	RTMemFree(paDescs);
2006	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
2007	}
2008	break;
2009	}
2010	# endif /* IN_RING3 */
2011	#endif // VBOX_WITH_VMSVGA3D
2012
2013	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
2014	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
2015	if (pThis->svga.fTraces == u32)
2016	break; /* nothing to do */
2017
2018	#ifdef IN_RING3
2019	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
2020	#else
2021	rc = VINF_IOM_R3_IOPORT_WRITE;
2022	#endif
2023	break;
2024
2025	case SVGA_REG_TOP: /* Must be 1 more than the last register */
2026	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
2027	break;
2028
2029	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
2030	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
2031	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
2032	break;
2033
2034	case SVGA_REG_FB_START:
2035	case SVGA_REG_MEM_START:
2036	case SVGA_REG_HOST_BITS_PER_PIXEL:
2037	case SVGA_REG_MAX_WIDTH:
2038	case SVGA_REG_MAX_HEIGHT:
2039	case SVGA_REG_VRAM_SIZE:
2040	case SVGA_REG_FB_SIZE:
2041	case SVGA_REG_CAPABILITIES:
2042	case SVGA_REG_MEM_SIZE:
2043	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
2044	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
2045	case SVGA_REG_BYTES_PER_LINE:
2046	case SVGA_REG_FB_OFFSET:
2047	case SVGA_REG_RED_MASK:
2048	case SVGA_REG_GREEN_MASK:
2049	case SVGA_REG_BLUE_MASK:
2050	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
2051	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
2052	case SVGA_REG_GMR_MAX_IDS:
2053	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
2054	/* Read only - ignore. */
2055	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
2056	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
2057	break;
2058
2059	default:
2060	{
2061	uint32_t offReg;
2062	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
2063	{
2064	RT_UNTRUSTED_VALIDATED_FENCE();
2065	pThis->svga.au32ScratchRegion[offReg] = u32;
2066	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
2067	}
2068	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
2069	{
2070	/* Note! Using last_palette rather than palette here to preserve the VGA one.
2071	Btw, see rgb_to_pixel32. */
2072	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
2073	u32 &= 0xff;
2074	RT_UNTRUSTED_VALIDATED_FENCE();
2075	uint32_t uRgb = pThis->last_palette[offReg / 3];
2076	switch (offReg % 3)
2077	{
2078	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
2079	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
2080	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
2081	}
2082	pThis->last_palette[offReg / 3] = uRgb;
2083	}
2084	else
2085	{
2086	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2087	rc = VINF_IOM_R3_IOPORT_WRITE;
2088	#else
2089	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
2090	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
2091	#endif
2092	}
2093	break;
2094	}
2095	}
2096	return rc;
2097	}
2098
2099	/**
2100	* @callback_method_impl{FNIOMIOPORTNEWIN}
2101	*/
2102	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2103	{
2104	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2105	RT_NOREF_PV(pvUser);
2106
2107	/* Only dword accesses. */
2108	if (cb == 4)
2109	{
2110	switch (offPort)
2111	{
2112	case SVGA_INDEX_PORT:
2113	*pu32 = pThis->svga.u32IndexReg;
2114	break;
2115
2116	case SVGA_VALUE_PORT:
2117	return vmsvgaReadPort(pDevIns, pThis, pu32);
2118
2119	case SVGA_BIOS_PORT:
2120	Log(("Ignoring BIOS port read\n"));
2121	*pu32 = 0;
2122	break;
2123
2124	case SVGA_IRQSTATUS_PORT:
2125	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2126	*pu32 = pThis->svga.u32IrqStatus;
2127	break;
2128
2129	default:
2130	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
2131	*pu32 = UINT32_MAX;
2132	break;
2133	}
2134	}
2135	else
2136	{
2137	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2138	*pu32 = UINT32_MAX;
2139	}
2140	return VINF_SUCCESS;
2141	}
2142
2143	/**
2144	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2145	*/
2146	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2147	{
2148	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2149	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2150	RT_NOREF_PV(pvUser);
2151
2152	/* Only dword accesses. */
2153	if (cb == 4)
2154	switch (offPort)
2155	{
2156	case SVGA_INDEX_PORT:
2157	pThis->svga.u32IndexReg = u32;
2158	break;
2159
2160	case SVGA_VALUE_PORT:
2161	return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2162
2163	case SVGA_BIOS_PORT:
2164	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2165	break;
2166
2167	case SVGA_IRQSTATUS_PORT:
2168	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2169	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2170	/* Clear the irq in case all events have been cleared. */
2171	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2172	{
2173	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2174	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2175	}
2176	break;
2177
2178	default:
2179	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2180	break;
2181	}
2182	else
2183	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2184
2185	return VINF_SUCCESS;
2186	}
2187
2188	#ifdef IN_RING3
2189
2190	# ifdef DEBUG_FIFO_ACCESS
2191	/**
2192	* Handle FIFO memory access.
2193	* @returns VBox status code.
2194	* @param pVM VM handle.
2195	* @param pThis The shared VGA/VMSVGA instance data.
2196	* @param GCPhys The access physical address.
2197	* @param fWriteAccess Read or write access
2198	*/
2199	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2200	{
2201	RT_NOREF(pVM);
2202	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2203	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2204
2205	switch (GCPhysOffset >> 2)
2206	{
2207	case SVGA_FIFO_MIN:
2208	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2209	break;
2210	case SVGA_FIFO_MAX:
2211	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2212	break;
2213	case SVGA_FIFO_NEXT_CMD:
2214	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2215	break;
2216	case SVGA_FIFO_STOP:
2217	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2218	break;
2219	case SVGA_FIFO_CAPABILITIES:
2220	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2221	break;
2222	case SVGA_FIFO_FLAGS:
2223	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2224	break;
2225	case SVGA_FIFO_FENCE:
2226	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2227	break;
2228	case SVGA_FIFO_3D_HWVERSION:
2229	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2230	break;
2231	case SVGA_FIFO_PITCHLOCK:
2232	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2233	break;
2234	case SVGA_FIFO_CURSOR_ON:
2235	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2236	break;
2237	case SVGA_FIFO_CURSOR_X:
2238	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2239	break;
2240	case SVGA_FIFO_CURSOR_Y:
2241	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2242	break;
2243	case SVGA_FIFO_CURSOR_COUNT:
2244	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2245	break;
2246	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2247	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2248	break;
2249	case SVGA_FIFO_RESERVED:
2250	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2251	break;
2252	case SVGA_FIFO_CURSOR_SCREEN_ID:
2253	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2254	break;
2255	case SVGA_FIFO_DEAD:
2256	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2257	break;
2258	case SVGA_FIFO_3D_HWVERSION_REVISED:
2259	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2260	break;
2261	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2262	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2263	break;
2264	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2265	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2266	break;
2267	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2268	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2269	break;
2270	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2271	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2272	break;
2273	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2274	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2275	break;
2276	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2277	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2278	break;
2279	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2280	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2281	break;
2282	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2283	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2284	break;
2285	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2286	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2287	break;
2288	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2289	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2290	break;
2291	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2292	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2293	break;
2294	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2295	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2296	break;
2297	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2298	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2299	break;
2300	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2301	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2302	break;
2303	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2304	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2305	break;
2306	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2307	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2308	break;
2309	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2310	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2311	break;
2312	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2313	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2314	break;
2315	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2316	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2317	break;
2318	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2319	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2320	break;
2321	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2322	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2323	break;
2324	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2325	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2326	break;
2327	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2328	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2329	break;
2330	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2331	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2332	break;
2333	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2334	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2335	break;
2336	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2337	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2338	break;
2339	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2340	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2341	break;
2342	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2343	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2344	break;
2345	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2346	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2347	break;
2348	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2349	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2350	break;
2351	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2352	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2353	break;
2354	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2355	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2356	break;
2357	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2358	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2359	break;
2360	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2361	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2362	break;
2363	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2364	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2365	break;
2366	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2367	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2368	break;
2369	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2370	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2371	break;
2372	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2373	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2374	break;
2375	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2376	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2377	break;
2378	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2379	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2380	break;
2381	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2382	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2383	break;
2384	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2385	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2386	break;
2387	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2388	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2389	break;
2390	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2391	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2392	break;
2393	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2394	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2395	break;
2396	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2397	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2398	break;
2399	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2400	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2401	break;
2402	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2403	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2404	break;
2405	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2406	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2407	break;
2408	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2409	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2410	break;
2411	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2412	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2413	break;
2414	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2415	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2416	break;
2417	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2418	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2419	break;
2420	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2421	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2422	break;
2423	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2424	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2425	break;
2426	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2427	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2428	break;
2429	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2430	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2431	break;
2432	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2433	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2434	break;
2435	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2436	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2437	break;
2438	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2439	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2440	break;
2441	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2442	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2443	break;
2444	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2445	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2446	break;
2447	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2448	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2449	break;
2450	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2451	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2452	break;
2453	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2454	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2455	break;
2456	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2457	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2458	break;
2459	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2460	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2461	break;
2462	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2463	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2464	break;
2465	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2466	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2467	break;
2468	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2469	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2470	break;
2471	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2472	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2473	break;
2474	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2475	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2476	break;
2477	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2478	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2479	break;
2480	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2481	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2482	break;
2483	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2484	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2485	break;
2486	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2487	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2488	break;
2489	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2490	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2491	break;
2492	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2493	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2494	break;
2495	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2496	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2497	break;
2498	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2499	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2500	break;
2501	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2502	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2503	break;
2504	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2505	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2506	break;
2507	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2508	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2509	break;
2510	case SVGA_FIFO_3D_CAPS_LAST:
2511	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2512	break;
2513	case SVGA_FIFO_GUEST_3D_HWVERSION:
2514	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2515	break;
2516	case SVGA_FIFO_FENCE_GOAL:
2517	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2518	break;
2519	case SVGA_FIFO_BUSY:
2520	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2521	break;
2522	default:
2523	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2524	break;
2525	}
2526
2527	return VINF_EM_RAW_EMULATE_INSTR;
2528	}
2529	# endif /* DEBUG_FIFO_ACCESS */
2530
2531	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2532	/**
2533	* HC access handler for the FIFO.
2534	*
2535	* @returns VINF_SUCCESS if the handler have carried out the operation.
2536	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2537	* @param pVM VM Handle.
2538	* @param pVCpu The cross context CPU structure for the calling EMT.
2539	* @param GCPhys The physical address the guest is writing to.
2540	* @param pvPhys The HC mapping of that address.
2541	* @param pvBuf What the guest is reading/writing.
2542	* @param cbBuf How much it's reading/writing.
2543	* @param enmAccessType The access type.
2544	* @param enmOrigin Who is making the access.
2545	* @param pvUser User argument.
2546	*/
2547	static DECLCALLBACK(VBOXSTRICTRC)
2548	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2549	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2550	{
2551	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2552	PVGASTATE pThis = (PVGASTATE)pvUser;
2553	AssertPtr(pThis);
2554
2555	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2556	/*
2557	* Wake up the FIFO thread as it might have work to do now.
2558	*/
2559	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2560	AssertLogRelRC(rc);
2561	# endif
2562
2563	# ifdef DEBUG_FIFO_ACCESS
2564	/*
2565	* When in debug-fifo-access mode, we do not disable the access handler,
2566	* but leave it on as we wish to catch all access.
2567	*/
2568	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2569	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2570	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2571	/*
2572	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2573	*/
2574	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
2575	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2576	# endif
2577	if (RT_SUCCESS(rc))
2578	return VINF_PGM_HANDLER_DO_DEFAULT;
2579	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2580	return rc;
2581	}
2582	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2583
2584	#endif /* IN_RING3 */
2585
2586	#ifdef DEBUG_GMR_ACCESS
2587	# ifdef IN_RING3
2588
2589	/**
2590	* HC access handler for the FIFO.
2591	*
2592	* @returns VINF_SUCCESS if the handler have carried out the operation.
2593	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2594	* @param pVM VM Handle.
2595	* @param pVCpu The cross context CPU structure for the calling EMT.
2596	* @param GCPhys The physical address the guest is writing to.
2597	* @param pvPhys The HC mapping of that address.
2598	* @param pvBuf What the guest is reading/writing.
2599	* @param cbBuf How much it's reading/writing.
2600	* @param enmAccessType The access type.
2601	* @param enmOrigin Who is making the access.
2602	* @param pvUser User argument.
2603	*/
2604	static DECLCALLBACK(VBOXSTRICTRC)
2605	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2606	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2607	{
2608	PVGASTATE pThis = (PVGASTATE)pvUser;
2609	Assert(pThis);
2610	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2611	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2612
2613	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
2614
2615	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2616	{
2617	PGMR pGMR = &pSVGAState->paGMR[i];
2618
2619	if (pGMR->numDescriptors)
2620	{
2621	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2622	{
2623	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2624	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2625	{
2626	/*
2627	* Turn off the write handler for this particular page and make it R/W.
2628	* Then return telling the caller to restart the guest instruction.
2629	*/
2630	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2631	AssertRC(rc);
2632	return VINF_PGM_HANDLER_DO_DEFAULT;
2633	}
2634	}
2635	}
2636	}
2637
2638	return VINF_PGM_HANDLER_DO_DEFAULT;
2639	}
2640
2641	/** Callback handler for VMR3ReqCallWaitU */
2642	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2643	{
2644	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2645	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2646	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2647	int rc;
2648
2649	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2650	{
2651	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
2652	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2653	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2654	AssertRC(rc);
2655	}
2656	return VINF_SUCCESS;
2657	}
2658
2659	/** Callback handler for VMR3ReqCallWaitU */
2660	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2661	{
2662	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2663	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2664	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2665
2666	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2667	{
2668	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[i].GCPhys);
2669	AssertRC(rc);
2670	}
2671	return VINF_SUCCESS;
2672	}
2673
2674	/** Callback handler for VMR3ReqCallWaitU */
2675	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
2676	{
2677	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2678
2679	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2680	{
2681	PGMR pGMR = &pSVGAState->paGMR[i];
2682
2683	if (pGMR->numDescriptors)
2684	{
2685	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2686	{
2687	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[j].GCPhys);
2688	AssertRC(rc);
2689	}
2690	}
2691	}
2692	return VINF_SUCCESS;
2693	}
2694
2695	# endif /* IN_RING3 */
2696	#endif /* DEBUG_GMR_ACCESS */
2697
2698	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2699
2700	#ifdef IN_RING3
2701
2702
2703	/**
2704	* Common worker for changing the pointer shape.
2705	*
2706	* @param pThisCC The VGA/VMSVGA state for ring-3.
2707	* @param pSVGAState The VMSVGA ring-3 instance data.
2708	* @param fAlpha Whether there is alpha or not.
2709	* @param xHot Hotspot x coordinate.
2710	* @param yHot Hotspot y coordinate.
2711	* @param cx Width.
2712	* @param cy Height.
2713	* @param pbData Heap copy of the cursor data. Consumed.
2714	* @param cbData The size of the data.
2715	*/
2716	static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2717	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2718	{
2719	LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2720	# ifdef LOG_ENABLED
2721	if (LogIs2Enabled())
2722	{
2723	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2724	if (!fAlpha)
2725	{
2726	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2727	for (uint32_t y = 0; y < cy; y++)
2728	{
2729	Log2(("%3u:", y));
2730	uint8_t const pbLine = &pbData[y cbAndLine];
2731	for (uint32_t x = 0; x < cx; x += 8)
2732	{
2733	uint8_t b = pbLine[x / 8];
2734	char szByte[12];
2735	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2736	szByte[1] = b & 0x40 ? '*' : ' ';
2737	szByte[2] = b & 0x20 ? '*' : ' ';
2738	szByte[3] = b & 0x10 ? '*' : ' ';
2739	szByte[4] = b & 0x08 ? '*' : ' ';
2740	szByte[5] = b & 0x04 ? '*' : ' ';
2741	szByte[6] = b & 0x02 ? '*' : ' ';
2742	szByte[7] = b & 0x01 ? '*' : ' ';
2743	szByte[8] = '\0';
2744	Log2(("%s", szByte));
2745	}
2746	Log2(("\n"));
2747	}
2748	}
2749
2750	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2751	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2752	for (uint32_t y = 0; y < cy; y++)
2753	{
2754	Log2(("%3u:", y));
2755	uint32_t const pu32Line = &pu32Xor[y cx];
2756	for (uint32_t x = 0; x < cx; x++)
2757	Log2((" %08x", pu32Line[x]));
2758	Log2(("\n"));
2759	}
2760	}
2761	# endif
2762
2763	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2764	AssertRC(rc);
2765
2766	if (pSVGAState->Cursor.fActive)
2767	RTMemFree(pSVGAState->Cursor.pData);
2768
2769	pSVGAState->Cursor.fActive = true;
2770	pSVGAState->Cursor.xHotspot = xHot;
2771	pSVGAState->Cursor.yHotspot = yHot;
2772	pSVGAState->Cursor.width = cx;
2773	pSVGAState->Cursor.height = cy;
2774	pSVGAState->Cursor.cbData = cbData;
2775	pSVGAState->Cursor.pData = pbData;
2776	}
2777
2778
2779	/**
2780	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2781	*
2782	* @param pThis The shared VGA/VMSVGA state.
2783	* @param pThisCC The VGA/VMSVGA state for ring-3.
2784	* @param pSVGAState The VMSVGA ring-3 instance data.
2785	* @param pCursor The cursor.
2786	* @param pbSrcAndMask The AND mask.
2787	* @param cbSrcAndLine The scanline length of the AND mask.
2788	* @param pbSrcXorMask The XOR mask.
2789	* @param cbSrcXorLine The scanline length of the XOR mask.
2790	*/
2791	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState,
2792	SVGAFifoCmdDefineCursor const *pCursor,
2793	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2794	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2795	{
2796	uint32_t const cx = pCursor->width;
2797	uint32_t const cy = pCursor->height;
2798
2799	/*
2800	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2801	* The AND data uses 8-bit aligned scanlines.
2802	* The XOR data must be starting on a 32-bit boundrary.
2803	*/
2804	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2805	uint32_t cbDstAndMask = cbDstAndLine * cy;
2806	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2807	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2808
2809	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2810	AssertReturnVoid(pbCopy);
2811
2812	/* Convert the AND mask. */
2813	uint8_t *pbDst = pbCopy;
2814	uint8_t const *pbSrc = pbSrcAndMask;
2815	switch (pCursor->andMaskDepth)
2816	{
2817	case 1:
2818	if (cbSrcAndLine == cbDstAndLine)
2819	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2820	else
2821	{
2822	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2823	for (uint32_t y = 0; y < cy; y++)
2824	{
2825	memcpy(pbDst, pbSrc, cbDstAndLine);
2826	pbDst += cbDstAndLine;
2827	pbSrc += cbSrcAndLine;
2828	}
2829	}
2830	break;
2831	/* Should take the XOR mask into account for the multi-bit AND mask. */
2832	case 8:
2833	for (uint32_t y = 0; y < cy; y++)
2834	{
2835	for (uint32_t x = 0; x < cx; )
2836	{
2837	uint8_t bDst = 0;
2838	uint8_t fBit = 0x80;
2839	do
2840	{
2841	uintptr_t const idxPal = pbSrc[x] * 3;
2842	if ((( pThis->last_palette[idxPal]
2843	\| (pThis->last_palette[idxPal] >> 8)
2844	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2845	bDst \|= fBit;
2846	fBit >>= 1;
2847	x++;
2848	} while (x < cx && (x & 7));
2849	pbDst[(x - 1) / 8] = bDst;
2850	}
2851	pbDst += cbDstAndLine;
2852	pbSrc += cbSrcAndLine;
2853	}
2854	break;
2855	case 15:
2856	for (uint32_t y = 0; y < cy; y++)
2857	{
2858	for (uint32_t x = 0; x < cx; )
2859	{
2860	uint8_t bDst = 0;
2861	uint8_t fBit = 0x80;
2862	do
2863	{
2864	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2865	bDst \|= fBit;
2866	fBit >>= 1;
2867	x++;
2868	} while (x < cx && (x & 7));
2869	pbDst[(x - 1) / 8] = bDst;
2870	}
2871	pbDst += cbDstAndLine;
2872	pbSrc += cbSrcAndLine;
2873	}
2874	break;
2875	case 16:
2876	for (uint32_t y = 0; y < cy; y++)
2877	{
2878	for (uint32_t x = 0; x < cx; )
2879	{
2880	uint8_t bDst = 0;
2881	uint8_t fBit = 0x80;
2882	do
2883	{
2884	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2885	bDst \|= fBit;
2886	fBit >>= 1;
2887	x++;
2888	} while (x < cx && (x & 7));
2889	pbDst[(x - 1) / 8] = bDst;
2890	}
2891	pbDst += cbDstAndLine;
2892	pbSrc += cbSrcAndLine;
2893	}
2894	break;
2895	case 24:
2896	for (uint32_t y = 0; y < cy; y++)
2897	{
2898	for (uint32_t x = 0; x < cx; )
2899	{
2900	uint8_t bDst = 0;
2901	uint8_t fBit = 0x80;
2902	do
2903	{
2904	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2905	bDst \|= fBit;
2906	fBit >>= 1;
2907	x++;
2908	} while (x < cx && (x & 7));
2909	pbDst[(x - 1) / 8] = bDst;
2910	}
2911	pbDst += cbDstAndLine;
2912	pbSrc += cbSrcAndLine;
2913	}
2914	break;
2915	case 32:
2916	for (uint32_t y = 0; y < cy; y++)
2917	{
2918	for (uint32_t x = 0; x < cx; )
2919	{
2920	uint8_t bDst = 0;
2921	uint8_t fBit = 0x80;
2922	do
2923	{
2924	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2925	bDst \|= fBit;
2926	fBit >>= 1;
2927	x++;
2928	} while (x < cx && (x & 7));
2929	pbDst[(x - 1) / 8] = bDst;
2930	}
2931	pbDst += cbDstAndLine;
2932	pbSrc += cbSrcAndLine;
2933	}
2934	break;
2935	default:
2936	RTMemFree(pbCopy);
2937	AssertFailedReturnVoid();
2938	}
2939
2940	/* Convert the XOR mask. */
2941	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2942	pbSrc = pbSrcXorMask;
2943	switch (pCursor->xorMaskDepth)
2944	{
2945	case 1:
2946	for (uint32_t y = 0; y < cy; y++)
2947	{
2948	for (uint32_t x = 0; x < cx; )
2949	{
2950	/* most significant bit is the left most one. */
2951	uint8_t bSrc = pbSrc[x / 8];
2952	do
2953	{
2954	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2955	bSrc <<= 1;
2956	x++;
2957	} while ((x & 7) && x < cx);
2958	}
2959	pbSrc += cbSrcXorLine;
2960	}
2961	break;
2962	case 8:
2963	for (uint32_t y = 0; y < cy; y++)
2964	{
2965	for (uint32_t x = 0; x < cx; x++)
2966	{
2967	uint32_t u = pThis->last_palette[pbSrc[x]];
2968	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2969	}
2970	pbSrc += cbSrcXorLine;
2971	}
2972	break;
2973	case 15: /* Src: RGB-5-5-5 */
2974	for (uint32_t y = 0; y < cy; y++)
2975	{
2976	for (uint32_t x = 0; x < cx; x++)
2977	{
2978	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2979	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2980	((uValue >> 5) & 0x1f) << 3,
2981	((uValue >> 10) & 0x1f) << 3, 0);
2982	}
2983	pbSrc += cbSrcXorLine;
2984	}
2985	break;
2986	case 16: /* Src: RGB-5-6-5 */
2987	for (uint32_t y = 0; y < cy; y++)
2988	{
2989	for (uint32_t x = 0; x < cx; x++)
2990	{
2991	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2992	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2993	((uValue >> 5) & 0x3f) << 2,
2994	((uValue >> 11) & 0x1f) << 3, 0);
2995	}
2996	pbSrc += cbSrcXorLine;
2997	}
2998	break;
2999	case 24:
3000	for (uint32_t y = 0; y < cy; y++)
3001	{
3002	for (uint32_t x = 0; x < cx; x++)
3003	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
3004	pbSrc += cbSrcXorLine;
3005	}
3006	break;
3007	case 32:
3008	for (uint32_t y = 0; y < cy; y++)
3009	{
3010	for (uint32_t x = 0; x < cx; x++)
3011	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
3012	pbSrc += cbSrcXorLine;
3013	}
3014	break;
3015	default:
3016	RTMemFree(pbCopy);
3017	AssertFailedReturnVoid();
3018	}
3019
3020	/*
3021	* Pass it to the frontend/whatever.
3022	*/
3023	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
3024	}
3025
3026
3027	/**
3028	* Worker for vmsvgaR3FifoThread that handles an external command.
3029	*
3030	* @param pDevIns The device instance.
3031	* @param pThis The shared VGA/VMSVGA instance data.
3032	* @param pThisCC The VGA/VMSVGA state for ring-3.
3033	*/
3034	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3035	{
3036	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
3037	switch (pThis->svga.u8FIFOExtCommand)
3038	{
3039	case VMSVGA_FIFO_EXTCMD_RESET:
3040	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
3041	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3042	# ifdef VBOX_WITH_VMSVGA3D
3043	if (pThis->svga.f3DEnabled)
3044	{
3045	/* The 3d subsystem must be reset from the fifo thread. */
3046	vmsvga3dReset(pThisCC);
3047	}
3048	# endif
3049	break;
3050
3051	case VMSVGA_FIFO_EXTCMD_TERMINATE:
3052	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
3053	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3054	# ifdef VBOX_WITH_VMSVGA3D
3055	if (pThis->svga.f3DEnabled)
3056	{
3057	/* The 3d subsystem must be shut down from the fifo thread. */
3058	vmsvga3dTerminate(pThisCC);
3059	}
3060	# endif
3061	break;
3062
3063	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
3064	{
3065	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
3066	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
3067	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
3068	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
3069	# ifdef VBOX_WITH_VMSVGA3D
3070	if (pThis->svga.f3DEnabled)
3071	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
3072	# endif
3073	break;
3074	}
3075
3076	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
3077	{
3078	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
3079	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
3080	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
3081	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3082	# ifdef VBOX_WITH_VMSVGA3D
3083	if (pThis->svga.f3DEnabled)
3084	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3085	# endif
3086	break;
3087	}
3088
3089	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
3090	{
3091	# ifdef VBOX_WITH_VMSVGA3D
3092	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
3093	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
3094	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
3095	# endif
3096	break;
3097	}
3098
3099
3100	default:
3101	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
3102	break;
3103	}
3104
3105	/*
3106	* Signal the end of the external command.
3107	*/
3108	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3109	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
3110	ASMMemoryFence(); /* paranoia^2 */
3111	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
3112	AssertLogRelRC(rc);
3113	}
3114
3115	/**
3116	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
3117	* doing a job on the FIFO thread (even when it's officially suspended).
3118	*
3119	* @returns VBox status code (fully asserted).
3120	* @param pDevIns The device instance.
3121	* @param pThis The shared VGA/VMSVGA instance data.
3122	* @param pThisCC The VGA/VMSVGA state for ring-3.
3123	* @param uExtCmd The command to execute on the FIFO thread.
3124	* @param pvParam Pointer to command parameters.
3125	* @param cMsWait The time to wait for the command, given in
3126	* milliseconds.
3127	*/
3128	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
3129	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
3130	{
3131	Assert(cMsWait >= RT_MS_1SEC * 5);
3132	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
3133	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
3134
3135	int rc;
3136	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
3137	PDMTHREADSTATE enmState = pThread->enmState;
3138	if (enmState == PDMTHREADSTATE_SUSPENDED)
3139	{
3140	/*
3141	* The thread is suspended, we have to temporarily wake it up so it can
3142	* perform the task.
3143	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
3144	*/
3145	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
3146	/* Post the request. */
3147	pThis->svga.fFifoExtCommandWakeup = true;
3148	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3149	pThis->svga.u8FIFOExtCommand = uExtCmd;
3150	ASMMemoryFence(); /* paranoia^3 */
3151
3152	/* Resume the thread. */
3153	rc = PDMDevHlpThreadResume(pDevIns, pThread);
3154	AssertLogRelRC(rc);
3155	if (RT_SUCCESS(rc))
3156	{
3157	/* Wait. Take care in case the semaphore was already posted (same as below). */
3158	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3159	if ( rc == VINF_SUCCESS
3160	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3161	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3162	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3163	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3164
3165	/* suspend the thread */
3166	pThis->svga.fFifoExtCommandWakeup = false;
3167	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
3168	AssertLogRelRC(rc2);
3169	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3170	rc = rc2;
3171	}
3172	pThis->svga.fFifoExtCommandWakeup = false;
3173	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3174	}
3175	else if (enmState == PDMTHREADSTATE_RUNNING)
3176	{
3177	/*
3178	* The thread is running, should only happen during reset and vmsvga3dsfc.
3179	* We ASSUME not racing code here, both wrt thread state and ext commands.
3180	*/
3181	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3182	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
3183
3184	/* Post the request. */
3185	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3186	pThis->svga.u8FIFOExtCommand = uExtCmd;
3187	ASMMemoryFence(); /* paranoia^2 */
3188	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3189	AssertLogRelRC(rc);
3190
3191	/* Wait. Take care in case the semaphore was already posted (same as above). */
3192	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3193	if ( rc == VINF_SUCCESS
3194	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3195	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3196	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3197	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3198
3199	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3200	}
3201	else
3202	{
3203	/*
3204	* Something is wrong with the thread!
3205	*/
3206	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3207	rc = VERR_INVALID_STATE;
3208	}
3209	return rc;
3210	}
3211
3212
3213	/**
3214	* Marks the FIFO non-busy, notifying any waiting EMTs.
3215	*
3216	* @param pDevIns The device instance.
3217	* @param pThis The shared VGA/VMSVGA instance data.
3218	* @param pThisCC The VGA/VMSVGA state for ring-3.
3219	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3220	* @param offFifoMin The start byte offset of the command FIFO.
3221	*/
3222	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3223	{
3224	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
3225	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3226	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
3227
3228	/* Wake up any waiting EMTs. */
3229	if (pSVGAState->cBusyDelayedEmts > 0)
3230	{
3231	# ifdef VMSVGA_USE_EMT_HALT_CODE
3232	PVM pVM = PDMDevHlpGetVM(pDevIns);
3233	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3234	if (idCpu != NIL_VMCPUID)
3235	{
3236	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3237	while (idCpu-- > 0)
3238	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3239	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3240	}
3241	# else
3242	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3243	AssertRC(rc2);
3244	# endif
3245	}
3246	}
3247
3248	/**
3249	* Reads (more) payload into the command buffer.
3250	*
3251	* @returns pbBounceBuf on success
3252	* @retval (void *)1 if the thread was requested to stop.
3253	* @retval NULL on FIFO error.
3254	*
3255	* @param cbPayloadReq The number of bytes of payload requested.
3256	* @param pFIFO The FIFO.
3257	* @param offCurrentCmd The FIFO byte offset of the current command.
3258	* @param offFifoMin The start byte offset of the command FIFO.
3259	* @param offFifoMax The end byte offset of the command FIFO.
3260	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3261	* always sufficient size.
3262	* @param pcbAlreadyRead How much payload we've already read into the bounce
3263	* buffer. (We will NEVER re-read anything.)
3264	* @param pThread The calling PDM thread handle.
3265	* @param pThis The shared VGA/VMSVGA instance data.
3266	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3267	* statistics collection.
3268	* @param pDevIns The device instance.
3269	*/
3270	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3271	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3272	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3273	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
3274	{
3275	Assert(pbBounceBuf);
3276	Assert(pcbAlreadyRead);
3277	Assert(offFifoMin < offFifoMax);
3278	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3279	Assert(offFifoMax <= pThis->svga.cbFIFO);
3280
3281	/*
3282	* Check if the requested payload size has already been satisfied .
3283	* .
3284	* When called to read more, the caller is responsible for making sure the .
3285	* new command size (cbRequsted) never is smaller than what has already .
3286	* been read.
3287	*/
3288	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3289	if (cbPayloadReq <= cbAlreadyRead)
3290	{
3291	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3292	return pbBounceBuf;
3293	}
3294
3295	/*
3296	* Commands bigger than the fifo buffer are invalid.
3297	*/
3298	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3299	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3300	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3301	NULL);
3302
3303	/*
3304	* Move offCurrentCmd past the command dword.
3305	*/
3306	offCurrentCmd += sizeof(uint32_t);
3307	if (offCurrentCmd >= offFifoMax)
3308	offCurrentCmd = offFifoMin;
3309
3310	/*
3311	* Do we have sufficient payload data available already?
3312	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3313	*/
3314	uint32_t cbAfter, cbBefore;
3315	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3316	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3317	if (offNextCmd >= offCurrentCmd)
3318	{
3319	if (RT_LIKELY(offNextCmd < offFifoMax))
3320	cbAfter = offNextCmd - offCurrentCmd;
3321	else
3322	{
3323	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3324	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3325	offNextCmd, offFifoMin, offFifoMax));
3326	cbAfter = offFifoMax - offCurrentCmd;
3327	}
3328	cbBefore = 0;
3329	}
3330	else
3331	{
3332	cbAfter = offFifoMax - offCurrentCmd;
3333	if (offNextCmd >= offFifoMin)
3334	cbBefore = offNextCmd - offFifoMin;
3335	else
3336	{
3337	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3338	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3339	offNextCmd, offFifoMin, offFifoMax));
3340	cbBefore = 0;
3341	}
3342	}
3343	if (cbAfter + cbBefore < cbPayloadReq)
3344	{
3345	/*
3346	* Insufficient, must wait for it to arrive.
3347	*/
3348	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3349	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3350	for (uint32_t i = 0;; i++)
3351	{
3352	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3353	{
3354	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3355	return (void *)(uintptr_t)1;
3356	}
3357	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3358	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3359
3360	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
3361
3362	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3363	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3364	if (offNextCmd >= offCurrentCmd)
3365	{
3366	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3367	cbBefore = 0;
3368	}
3369	else
3370	{
3371	cbAfter = offFifoMax - offCurrentCmd;
3372	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3373	}
3374
3375	if (cbAfter + cbBefore >= cbPayloadReq)
3376	break;
3377	}
3378	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3379	}
3380
3381	/*
3382	* Copy out the memory and update what pcbAlreadyRead points to.
3383	*/
3384	if (cbAfter >= cbPayloadReq)
3385	memcpy(pbBounceBuf + cbAlreadyRead,
3386	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3387	cbPayloadReq - cbAlreadyRead);
3388	else
3389	{
3390	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3391	if (cbAlreadyRead < cbAfter)
3392	{
3393	memcpy(pbBounceBuf + cbAlreadyRead,
3394	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3395	cbAfter - cbAlreadyRead);
3396	cbAlreadyRead = cbAfter;
3397	}
3398	memcpy(pbBounceBuf + cbAlreadyRead,
3399	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3400	cbPayloadReq - cbAlreadyRead);
3401	}
3402	*pcbAlreadyRead = cbPayloadReq;
3403	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3404	return pbBounceBuf;
3405	}
3406
3407
3408	/**
3409	* Sends cursor position and visibility information from the FIFO to the front-end.
3410	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3411	*/
3412	static uint32_t
3413	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3414	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3415	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3416	{
3417	/*
3418	* Check if the cursor update counter has changed and try get a stable
3419	* set of values if it has. This is race-prone, especially consindering
3420	* the screen ID, but little we can do about that.
3421	*/
3422	uint32_t x, y, fVisible, idScreen;
3423	for (uint32_t i = 0; ; i++)
3424	{
3425	x = pFIFO[SVGA_FIFO_CURSOR_X];
3426	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3427	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3428	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3429	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3430	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3431	\|\| i > 3)
3432	break;
3433	if (i == 0)
3434	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3435	ASMNopPause();
3436	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3437	}
3438
3439	/*
3440	* Check if anything has changed, as calling into pDrv is not light-weight.
3441	*/
3442	if ( *pxLast == x
3443	&& *pyLast == y
3444	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3445	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3446	else
3447	{
3448	/*
3449	* Detected changes.
3450	*
3451	* We handle global, not per-screen visibility information by sending
3452	* pfnVBVAMousePointerShape without shape data.
3453	*/
3454	*pxLast = x;
3455	*pyLast = y;
3456	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3457	if (idScreen != SVGA_ID_INVALID)
3458	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3459	else if (*pfLastVisible != fVisible)
3460	{
3461	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
3462	*pfLastVisible = fVisible;
3463	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3464	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3465	}
3466	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
3467	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3468	}
3469
3470	/*
3471	* Update done. Signal this to the guest.
3472	*/
3473	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3474
3475	return uCursorUpdateCount;
3476	}
3477
3478
3479	/**
3480	* Checks if there is work to be done, either cursor updating or FIFO commands.
3481	*
3482	* @returns true if pending work, false if not.
3483	* @param pFIFO The FIFO to examine.
3484	* @param uLastCursorCount The last cursor update counter value.
3485	*/
3486	DECLINLINE(bool) vmsvgaR3FifoHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3487	{
3488	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3489	return true;
3490
3491	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3492	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3493	return true;
3494
3495	return false;
3496	}
3497
3498
3499	/**
3500	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3501	*
3502	* @param pDevIns The device instance.
3503	* @param pThis The shared VGA/VMSVGA instance data.
3504	* @param pThisCC The VGA/VMSVGA state for ring-3.
3505	*/
3506	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3507	{
3508	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3509	to recheck it before doing the signalling. */
3510	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3511	AssertReturnVoid(pFIFO);
3512	if ( vmsvgaR3FifoHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
3513	&& pThis->svga.fFIFOThreadSleeping)
3514	{
3515	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3516	AssertRC(rc);
3517	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3518	}
3519	}
3520
3521
3522	/*
3523	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
3524	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
3525	*/
3526	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3527	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
3528	*
3529	* Will break out of the switch on failure.
3530	* Will restart and quit the loop if the thread was requested to stop.
3531	*
3532	* @param a_PtrVar Request variable pointer.
3533	* @param a_Type Request typedef (not pointer) for casting.
3534	* @param a_cbPayloadReq How much payload to fetch.
3535	* @remarks Accesses a bunch of variables in the current scope!
3536	*/
3537	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3538	if (1) { \
3539	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3540	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
3541	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3542	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3543	} else do {} while (0)
3544	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3545	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
3546	* buffer after figuring out the actual command size.
3547	*
3548	* Will break out of the switch on failure.
3549	*
3550	* @param a_PtrVar Request variable pointer.
3551	* @param a_Type Request typedef (not pointer) for casting.
3552	* @param a_cbPayloadReq How much payload to fetch.
3553	* @remarks Accesses a bunch of variables in the current scope!
3554	*/
3555	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3556	if (1) { \
3557	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3558	} else do {} while (0)
3559
3560	/**
3561	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
3562	*/
3563	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3564	{
3565	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3566	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3567	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3568	int rc;
3569
3570	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3571	return VINF_SUCCESS;
3572
3573	/*
3574	* Special mode where we only execute an external command and the go back
3575	* to being suspended. Currently, all ext cmds ends up here, with the reset
3576	* one also being eligble for runtime execution further down as well.
3577	*/
3578	if (pThis->svga.fFifoExtCommandWakeup)
3579	{
3580	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3581	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3582	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3583	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
3584	else
3585	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3586	return VINF_SUCCESS;
3587	}
3588
3589
3590	/*
3591	* Signal the semaphore to make sure we don't wait for 250ms after a
3592	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
3593	*/
3594	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3595
3596	/*
3597	* Allocate a bounce buffer for command we get from the FIFO.
3598	* (All code must return via the end of the function to free this buffer.)
3599	*/
3600	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3601	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3602
3603	/*
3604	* Polling/sleep interval config.
3605	*
3606	* We wait for an a short interval if the guest has recently given us work
3607	* to do, but the interval increases the longer we're kept idle. Once we've
3608	* reached the refresh timer interval, we'll switch to extended waits,
3609	* depending on it or the guest to kick us into action when needed.
3610	*
3611	* Should the refresh time go fishing, we'll just continue increasing the
3612	* sleep length till we reaches the 250 ms max after about 16 seconds.
3613	*/
3614	RTMSINTERVAL const cMsMinSleep = 16;
3615	RTMSINTERVAL const cMsIncSleep = 2;
3616	RTMSINTERVAL const cMsMaxSleep = 250;
3617	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3618	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3619
3620	/*
3621	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3622	*
3623	* Initialize with values that will detect an update from the guest.
3624	* Make sure that if the guest never updates the cursor position, then the device does not report it.
3625	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
3626	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
3627	*/
3628	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3629	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3630	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3631	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3632	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3633
3634	/*
3635	* The FIFO loop.
3636	*/
3637	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
3638	bool fBadOrDisabledFifo = false;
3639	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3640	{
3641	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3642	/*
3643	* Should service the run loop every so often.
3644	*/
3645	if (pThis->svga.f3DEnabled)
3646	vmsvga3dCocoaServiceRunLoop();
3647	# endif
3648
3649	/*
3650	* Unless there's already work pending, go to sleep for a short while.
3651	* (See polling/sleep interval config above.)
3652	*/
3653	if ( fBadOrDisabledFifo
3654	\|\| !vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3655	{
3656	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3657	Assert(pThis->cMilliesRefreshInterval > 0);
3658	if (cMsSleep < pThis->cMilliesRefreshInterval)
3659	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
3660	else
3661	{
3662	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3663	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3664	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3665	# endif
3666	if ( !fBadOrDisabledFifo
3667	&& vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3668	rc = VINF_SUCCESS;
3669	else
3670	{
3671	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3672	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
3673	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3674	}
3675	}
3676	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3677	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3678	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3679	{
3680	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
3681	break;
3682	}
3683	}
3684	else
3685	rc = VINF_SUCCESS;
3686	fBadOrDisabledFifo = false;
3687	if (rc == VERR_TIMEOUT)
3688	{
3689	if (!vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3690	{
3691	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3692	continue;
3693	}
3694	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3695
3696	Log(("vmsvgaR3FifoLoop: timeout\n"));
3697	}
3698	else if (vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3699	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3700	cMsSleep = cMsMinSleep;
3701
3702	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
3703	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3704	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3705
3706	/*
3707	* Handle external commands (currently only reset).
3708	*/
3709	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3710	{
3711	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3712	continue;
3713	}
3714
3715	/*
3716	* The device must be enabled and configured.
3717	*/
3718	if ( !pThis->svga.fEnabled
3719	\|\| !pThis->svga.fConfigured)
3720	{
3721	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3722	fBadOrDisabledFifo = true;
3723	cMsSleep = cMsMaxSleep; /* cheat */
3724	continue;
3725	}
3726
3727	/*
3728	* Get and check the min/max values. We ASSUME that they will remain
3729	* unchanged while we process requests. A further ASSUMPTION is that
3730	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3731	* we don't read it back while in the loop.
3732	*/
3733	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3734	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3735	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3736	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3737	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3738	\|\| offFifoMax <= offFifoMin
3739	\|\| offFifoMax > pThis->svga.cbFIFO
3740	\|\| (offFifoMax & 3) != 0
3741	\|\| (offFifoMin & 3) != 0
3742	\|\| offCurrentCmd < offFifoMin
3743	\|\| offCurrentCmd > offFifoMax))
3744	{
3745	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3746	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3747	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
3748	fBadOrDisabledFifo = true;
3749	continue;
3750	}
3751	RT_UNTRUSTED_VALIDATED_FENCE();
3752	if (RT_UNLIKELY(offCurrentCmd & 3))
3753	{
3754	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3755	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3756	offCurrentCmd &= ~UINT32_C(3);
3757	}
3758
3759	/*
3760	* Update the cursor position before we start on the FIFO commands.
3761	*/
3762	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3763	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3764	{
3765	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3766	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
3767	{ /* halfways likely */ }
3768	else
3769	{
3770	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3771	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3772	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
3773	}
3774	}
3775
3776	/*
3777	* Mark the FIFO as busy.
3778	*/
3779	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3780	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3781	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3782
3783	/*
3784	* Execute all queued FIFO commands.
3785	* Quit if pending external command or changes in the thread state.
3786	*/
3787	bool fDone = false;
3788	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3789	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3790	{
3791	uint32_t cbPayload = 0;
3792	uint32_t u32IrqStatus = 0;
3793
3794	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3795
3796	/* First check any pending actions. */
3797	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3798	{
3799	vmsvgaR3ChangeMode(pThis, pThisCC);
3800	# ifdef VBOX_WITH_VMSVGA3D
3801	if (pThisCC->svga.p3dState != NULL)
3802	vmsvga3dChangeMode(pThisCC);
3803	# endif
3804	}
3805
3806	/* Check for pending external commands (reset). */
3807	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3808	break;
3809
3810	/*
3811	* Process the command.
3812	*/
3813	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3814	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3815	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3816	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
3817	switch (enmCmdId)
3818	{
3819	case SVGA_CMD_INVALID_CMD:
3820	/* Nothing to do. */
3821	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3822	break;
3823
3824	case SVGA_CMD_FENCE:
3825	{
3826	SVGAFifoCmdFence *pCmdFence;
3827	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3828	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3829	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3830	{
3831	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3832	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3833
3834	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3835	{
3836	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
3837	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3838	}
3839	else
3840	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3841	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3842	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3843	{
3844	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3845	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3846	}
3847	}
3848	else
3849	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3850	break;
3851	}
3852	case SVGA_CMD_UPDATE:
3853	case SVGA_CMD_UPDATE_VERBOSE:
3854	{
3855	SVGAFifoCmdUpdate *pUpdate;
3856	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3857	if (enmCmdId == SVGA_CMD_UPDATE)
3858	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3859	else
3860	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3861	Log(("vmsvgaR3FifoLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3862	/** @todo Multiple screens? */
3863	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
3864	AssertBreak(pScreen);
3865	vmsvgaR3UpdateScreen(pThisCC, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3866	break;
3867	}
3868
3869	case SVGA_CMD_DEFINE_CURSOR:
3870	{
3871	/* Followed by bitmap data. */
3872	SVGAFifoCmdDefineCursor *pCursor;
3873	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3874	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3875
3876	Log(("vmsvgaR3FifoLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3877	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3878	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3879	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3880	AssertBreak(pCursor->andMaskDepth <= 32);
3881	AssertBreak(pCursor->xorMaskDepth <= 32);
3882	RT_UNTRUSTED_VALIDATED_FENCE();
3883
3884	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3885	uint32_t cbAndMask = cbAndLine * pCursor->height;
3886	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3887	uint32_t cbXorMask = cbXorLine * pCursor->height;
3888	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3889
3890	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3891	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3892	break;
3893	}
3894
3895	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3896	{
3897	/* Followed by bitmap data. */
3898	uint32_t cbCursorShape, cbAndMask;
3899	uint8_t *pCursorCopy;
3900	uint32_t cbCmd;
3901
3902	SVGAFifoCmdDefineAlphaCursor *pCursor;
3903	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3904	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3905
3906	Log(("vmsvgaR3FifoLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3907
3908	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3909	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3910	RT_UNTRUSTED_VALIDATED_FENCE();
3911
3912	/* Refetch the bitmap data as well. */
3913	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3914	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3915	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3916
3917	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3918	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3919	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3920	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3921
3922	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3923	AssertBreak(pCursorCopy);
3924
3925	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3926	memset(pCursorCopy, 0xff, cbAndMask);
3927	/* Colour data */
3928	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3929
3930	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3931	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3932	break;
3933	}
3934
3935	case SVGA_CMD_MOVE_CURSOR:
3936	{
3937	/* Deprecated; there should be no driver which requires this command. However, if
3938	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3939	* alignment.
3940	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3941	*/
3942	SVGAFifoCmdMoveCursor *pMoveCursor;
3943	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pMoveCursor, SVGAFifoCmdMoveCursor, sizeof(*pMoveCursor));
3944	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdMoveCursor);
3945
3946	Log(("vmsvgaR3FifoLoop: MOVE CURSOR to %d,%d\n", pMoveCursor->pos.x, pMoveCursor->pos.y));
3947	LogRelMax(4, ("Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
3948	break;
3949	}
3950
3951	case SVGA_CMD_DISPLAY_CURSOR:
3952	{
3953	/* Deprecated; there should be no driver which requires this command. However, if
3954	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3955	* alignment.
3956	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3957	*/
3958	SVGAFifoCmdDisplayCursor *pDisplayCursor;
3959	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pDisplayCursor, SVGAFifoCmdDisplayCursor, sizeof(*pDisplayCursor));
3960	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDisplayCursor);
3961
3962	Log(("vmsvgaR3FifoLoop: DISPLAY CURSOR id=%d state=%d\n", pDisplayCursor->id, pDisplayCursor->state));
3963	LogRelMax(4, ("Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
3964	break;
3965	}
3966
3967	case SVGA_CMD_ESCAPE:
3968	{
3969	/* Followed by nsize bytes of data. */
3970	SVGAFifoCmdEscape *pEscape;
3971	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3972	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3973
3974	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3975	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3976	RT_UNTRUSTED_VALIDATED_FENCE();
3977	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3978	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3979
3980	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3981	{
3982	AssertBreak(pEscape->size >= sizeof(uint32_t));
3983	RT_UNTRUSTED_VALIDATED_FENCE();
3984	uint32_t cmd = (uint32_t )(pEscape + 1);
3985	Log(("vmsvgaR3FifoLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3986
3987	switch (cmd)
3988	{
3989	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3990	{
3991	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3992	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3993	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3994
3995	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3996	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3997	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3998
3999	RT_NOREF_PV(pVideoCmd);
4000	break;
4001
4002	}
4003
4004	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
4005	{
4006	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
4007	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
4008	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
4009	RT_NOREF_PV(pVideoCmd);
4010	break;
4011	}
4012
4013	default:
4014	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
4015	break;
4016	}
4017	}
4018	else
4019	Log(("vmsvgaR3FifoLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
4020
4021	break;
4022	}
4023	# ifdef VBOX_WITH_VMSVGA3D
4024	case SVGA_CMD_DEFINE_GMR2:
4025	{
4026	SVGAFifoCmdDefineGMR2 *pCmd;
4027	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
4028	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
4029	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
4030
4031	/* Validate current GMR id. */
4032	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
4033	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
4034	RT_UNTRUSTED_VALIDATED_FENCE();
4035
4036	if (!pCmd->numPages)
4037	{
4038	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
4039	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
4040	}
4041	else
4042	{
4043	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
4044	if (pGMR->cMaxPages)
4045	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
4046
4047	/* Not sure if we should always free the descriptor, but for simplicity
4048	we do so if the new size is smaller than the current. */
4049	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
4050	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
4051	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
4052
4053	pGMR->cMaxPages = pCmd->numPages;
4054	/* The rest is done by the REMAP_GMR2 command. */
4055	}
4056	break;
4057	}
4058
4059	case SVGA_CMD_REMAP_GMR2:
4060	{
4061	/* Followed by page descriptors or guest ptr. */
4062	SVGAFifoCmdRemapGMR2 *pCmd;
4063	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
4064	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
4065
4066	Log(("vmsvgaR3FifoLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
4067	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
4068	RT_UNTRUSTED_VALIDATED_FENCE();
4069
4070	/* Calculate the size of what comes after next and fetch it. */
4071	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
4072	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4073	cbCmd += sizeof(SVGAGuestPtr);
4074	else
4075	{
4076	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
4077	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
4078	{
4079	cbCmd += cbPageDesc;
4080	pCmd->numPages = 1;
4081	}
4082	else
4083	{
4084	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
4085	cbCmd += cbPageDesc * pCmd->numPages;
4086	}
4087	}
4088	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
4089
4090	/* Validate current GMR id and size. */
4091	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
4092	RT_UNTRUSTED_VALIDATED_FENCE();
4093	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
4094	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
4095	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
4096	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
4097
4098	if (pCmd->numPages == 0)
4099	break;
4100
4101	/** @todo Move to a separate function vmsvgaGMRRemap() */
4102
4103	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
4104	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
4105
4106	/*
4107	* We flatten the existing descriptors into a page array, overwrite the
4108	* pages specified in this command and then recompress the descriptor.
4109	*/
4110	/** @todo Optimize the GMR remap algorithm! */
4111
4112	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
4113	uint64_t *paNewPage64 = NULL;
4114	if (pGMR->paDesc)
4115	{
4116	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
4117
4118	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
4119	AssertBreak(paNewPage64);
4120
4121	uint32_t idxPage = 0;
4122	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
4123	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
4124	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
4125	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
4126	RT_UNTRUSTED_VALIDATED_FENCE();
4127	}
4128
4129	/* Free the old GMR if present. */
4130	if (pGMR->paDesc)
4131	RTMemFree(pGMR->paDesc);
4132
4133	/* Allocate the maximum amount possible (everything non-continuous) */
4134	PVMSVGAGMRDESCRIPTOR paDescs;
4135	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
4136	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
4137
4138	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4139	{
4140	/** @todo */
4141	AssertFailed();
4142	pGMR->numDescriptors = 0;
4143	}
4144	else
4145	{
4146	uint32_t paPages32 = (uint32_t )(pCmd + 1);
4147	uint64_t paPages64 = (uint64_t )(pCmd + 1);
4148	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
4149
4150	if (paNewPage64)
4151	{
4152	/* Overwrite the old page array with the new page values. */
4153	if (fGCPhys64)
4154	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
4155	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
4156	else
4157	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
4158	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
4159
4160	/* Use the updated page array instead of the command data. */
4161	fGCPhys64 = true;
4162	paPages64 = paNewPage64;
4163	pCmd->numPages = cNewTotalPages;
4164	}
4165
4166	/* The first page. */
4167	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
4168	* applied to paNewPage64. */
4169	RTGCPHYS GCPhys;
4170	if (fGCPhys64)
4171	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4172	else
4173	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
4174	paDescs[0].GCPhys = GCPhys;
4175	paDescs[0].numPages = 1;
4176
4177	/* Subsequent pages. */
4178	uint32_t iDescriptor = 0;
4179	for (uint32_t i = 1; i < pCmd->numPages; i++)
4180	{
4181	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
4182	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4183	else
4184	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
4185
4186	/* Continuous physical memory? */
4187	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
4188	{
4189	Assert(paDescs[iDescriptor].numPages);
4190	paDescs[iDescriptor].numPages++;
4191	Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
4192	}
4193	else
4194	{
4195	iDescriptor++;
4196	paDescs[iDescriptor].GCPhys = GCPhys;
4197	paDescs[iDescriptor].numPages = 1;
4198	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
4199	}
4200	}
4201
4202	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
4203	Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
4204	pGMR->numDescriptors = iDescriptor + 1;
4205	}
4206
4207	if (paNewPage64)
4208	RTMemFree(paNewPage64);
4209
4210	# ifdef DEBUG_GMR_ACCESS
4211	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
4212	# endif
4213	break;
4214	}
4215	# endif // VBOX_WITH_VMSVGA3D
4216	case SVGA_CMD_DEFINE_SCREEN:
4217	{
4218	/* The size of this command is specified by the guest and depends on capabilities. */
4219	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4220
4221	SVGAFifoCmdDefineScreen *pCmd;
4222	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4223	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4224	RT_UNTRUSTED_VALIDATED_FENCE();
4225
4226	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4227	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4228	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4229
4230	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4231	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4232	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4233
4234	uint32_t const idScreen = pCmd->screen.id;
4235	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4236
4237	uint32_t const uWidth = pCmd->screen.size.width;
4238	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4239
4240	uint32_t const uHeight = pCmd->screen.size.height;
4241	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4242
4243	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4244	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4245	AssertBreak(cbWidth <= cbPitch);
4246
4247	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4248	AssertBreak(uScreenOffset < pThis->vram_size);
4249
4250	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4251	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4252	AssertBreak( (uHeight == 0 && cbPitch == 0)
4253	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4254	RT_UNTRUSTED_VALIDATED_FENCE();
4255
4256	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4257
4258	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4259
4260	pScreen->fDefined = true;
4261	pScreen->fModified = true;
4262	pScreen->fuScreen = pCmd->screen.flags;
4263	pScreen->idScreen = idScreen;
4264	if (!fBlank)
4265	{
4266	AssertBreak(uWidth > 0 && uHeight > 0);
4267
4268	pScreen->xOrigin = pCmd->screen.root.x;
4269	pScreen->yOrigin = pCmd->screen.root.y;
4270	pScreen->cWidth = uWidth;
4271	pScreen->cHeight = uHeight;
4272	pScreen->offVRAM = uScreenOffset;
4273	pScreen->cbPitch = cbPitch;
4274	pScreen->cBpp = 32;
4275	}
4276	else
4277	{
4278	/* Keep old values. */
4279	}
4280
4281	pThis->svga.fGFBRegisters = false;
4282	vmsvgaR3ChangeMode(pThis, pThisCC);
4283	break;
4284	}
4285
4286	case SVGA_CMD_DESTROY_SCREEN:
4287	{
4288	SVGAFifoCmdDestroyScreen *pCmd;
4289	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4290	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4291
4292	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4293
4294	uint32_t const idScreen = pCmd->screenId;
4295	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4296	RT_UNTRUSTED_VALIDATED_FENCE();
4297
4298	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4299	pScreen->fModified = true;
4300	pScreen->fDefined = false;
4301	pScreen->idScreen = idScreen;
4302
4303	vmsvgaR3ChangeMode(pThis, pThisCC);
4304	break;
4305	}
4306
4307	case SVGA_CMD_DEFINE_GMRFB:
4308	{
4309	SVGAFifoCmdDefineGMRFB *pCmd;
4310	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4311	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4312
4313	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4314	pSVGAState->GMRFB.ptr = pCmd->ptr;
4315	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4316	pSVGAState->GMRFB.format = pCmd->format;
4317	break;
4318	}
4319
4320	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4321	{
4322	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4323	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4324	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4325
4326	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4327	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4328
4329	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4330	RT_UNTRUSTED_VALIDATED_FENCE();
4331
4332	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
4333	AssertBreak(pScreen);
4334
4335	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4336	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4337
4338	/* Clip destRect to the screen dimensions. */
4339	SVGASignedRect screenRect;
4340	screenRect.left = 0;
4341	screenRect.top = 0;
4342	screenRect.right = pScreen->cWidth;
4343	screenRect.bottom = pScreen->cHeight;
4344	SVGASignedRect clipRect = pCmd->destRect;
4345	vmsvgaR3ClipRect(&screenRect, &clipRect);
4346	RT_UNTRUSTED_VALIDATED_FENCE();
4347
4348	uint32_t const width = clipRect.right - clipRect.left;
4349	uint32_t const height = clipRect.bottom - clipRect.top;
4350
4351	if ( width == 0
4352	\|\| height == 0)
4353	break; /* Nothing to do. */
4354
4355	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4356	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4357
4358	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4359	* Prepare parameters for vmsvgaR3GmrTransfer.
4360	*/
4361	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4362
4363	/* Destination: host buffer which describes the screen 0 VRAM.
4364	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4365	*/
4366	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4367	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4368	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4369	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4370	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4371	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4372	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4373	+ cbScanline * clipRect.top;
4374	int32_t const cbHstPitch = cbScanline;
4375
4376	/* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4377	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4378	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4379	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4380	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4381
4382	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
4383	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4384	gstPtr, offGst, cbGstPitch,
4385	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4386	AssertRC(rc);
4387	vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
4388	break;
4389	}
4390
4391	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4392	{
4393	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4394	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4395	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4396
4397	/* Note! This can fetch 3d render results as well!! */
4398	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4399	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4400
4401	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4402	RT_UNTRUSTED_VALIDATED_FENCE();
4403
4404	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
4405	AssertBreak(pScreen);
4406
4407	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4408	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4409
4410	/* Clip destRect to the screen dimensions. */
4411	SVGASignedRect screenRect;
4412	screenRect.left = 0;
4413	screenRect.top = 0;
4414	screenRect.right = pScreen->cWidth;
4415	screenRect.bottom = pScreen->cHeight;
4416	SVGASignedRect clipRect = pCmd->srcRect;
4417	vmsvgaR3ClipRect(&screenRect, &clipRect);
4418	RT_UNTRUSTED_VALIDATED_FENCE();
4419
4420	uint32_t const width = clipRect.right - clipRect.left;
4421	uint32_t const height = clipRect.bottom - clipRect.top;
4422
4423	if ( width == 0
4424	\|\| height == 0)
4425	break; /* Nothing to do. */
4426
4427	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4428	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4429
4430	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4431	* Prepare parameters for vmsvgaR3GmrTransfer.
4432	*/
4433	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4434
4435	/* Source: host buffer which describes the screen 0 VRAM.
4436	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4437	*/
4438	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4439	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4440	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4441	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4442	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4443	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4444	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4445	+ cbScanline * clipRect.top;
4446	int32_t const cbHstPitch = cbScanline;
4447
4448	/* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4449	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4450	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4451	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4452	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4453
4454	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
4455	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4456	gstPtr, offGst, cbGstPitch,
4457	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4458	AssertRC(rc);
4459	break;
4460	}
4461
4462	case SVGA_CMD_ANNOTATION_FILL:
4463	{
4464	SVGAFifoCmdAnnotationFill *pCmd;
4465	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4466	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4467
4468	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4469	pSVGAState->colorAnnotation = pCmd->color;
4470	break;
4471	}
4472
4473	case SVGA_CMD_ANNOTATION_COPY:
4474	{
4475	SVGAFifoCmdAnnotationCopy *pCmd;
4476	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4477	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4478
4479	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4480	AssertFailed();
4481	break;
4482	}
4483
4484	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
4485
4486	default:
4487	# ifdef VBOX_WITH_VMSVGA3D
4488	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4489	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4490	{
4491	RT_UNTRUSTED_VALIDATED_FENCE();
4492
4493	/* All 3d commands start with a common header, which defines the size of the command. */
4494	SVGA3dCmdHeader *pHdr;
4495	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4496	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4497	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4498	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4499
4500	if (RT_LIKELY(pThis->svga.f3DEnabled))
4501	{ /* likely */ }
4502	else
4503	{
4504	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4505	break;
4506	}
4507
4508	/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4509	* Check that the 3D command has at least a_cbMin of payload bytes after the
4510	* header. Will break out of the switch if it doesn't.
4511	*/
4512	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4513	if (1) { \
4514	AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4515	RT_UNTRUSTED_VALIDATED_FENCE(); \
4516	} else do {} while (0)
4517	switch ((int)enmCmdId)
4518	{
4519	case SVGA_3D_CMD_SURFACE_DEFINE:
4520	{
4521	uint32_t cMipLevels;
4522	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4523	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4524	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4525
4526	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4527	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4528	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4529	# ifdef DEBUG_GMR_ACCESS
4530	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4531	# endif
4532	break;
4533	}
4534
4535	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4536	{
4537	uint32_t cMipLevels;
4538	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4539	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4540	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4541
4542	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4543	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4544	pCmd->multisampleCount, pCmd->autogenFilter,
4545	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4546	break;
4547	}
4548
4549	case SVGA_3D_CMD_SURFACE_DESTROY:
4550	{
4551	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4552	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4553	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4554	rc = vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
4555	break;
4556	}
4557
4558	case SVGA_3D_CMD_SURFACE_COPY:
4559	{
4560	uint32_t cCopyBoxes;
4561	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4562	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4563	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4564
4565	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4566	rc = vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4567	break;
4568	}
4569
4570	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4571	{
4572	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4573	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4574	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4575
4576	rc = vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
4577	&pCmd->src, &pCmd->boxSrc, pCmd->mode);
4578	break;
4579	}
4580
4581	case SVGA_3D_CMD_SURFACE_DMA:
4582	{
4583	uint32_t cCopyBoxes;
4584	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4585	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4586	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4587
4588	uint64_t u64NanoTS = 0;
4589	if (LogRelIs3Enabled())
4590	u64NanoTS = RTTimeNanoTS();
4591	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4592	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4593	rc = vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
4594	cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4595	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4596	if (LogRelIs3Enabled())
4597	{
4598	if (cCopyBoxes)
4599	{
4600	SVGA3dCopyBox pFirstBox = (SVGA3dCopyBox )(pCmd + 1);
4601	LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
4602	(RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
4603	pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
4604	pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
4605	}
4606	}
4607	break;
4608	}
4609
4610	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4611	{
4612	uint32_t cRects;
4613	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4614	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4615	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4616
4617	uint64_t u64NanoTS = 0;
4618	if (LogRelIs3Enabled())
4619	u64NanoTS = RTTimeNanoTS();
4620	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4621	STAM_REL_PROFILE_START(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4622	rc = vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
4623	pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4624	STAM_REL_PROFILE_STOP(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4625	if (LogRelIs3Enabled())
4626	{
4627	SVGASignedRect pFirstRect = cRects ? (SVGASignedRect )(pCmd + 1) : &pCmd->destRect;
4628	LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
4629	(RTTimeNanoTS() - u64NanoTS) / 1000ULL, cRects,
4630	pFirstRect->left, pFirstRect->top,
4631	pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
4632	}
4633	break;
4634	}
4635
4636	case SVGA_3D_CMD_CONTEXT_DEFINE:
4637	{
4638	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4639	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4640	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4641
4642	rc = vmsvga3dContextDefine(pThisCC, pCmd->cid);
4643	break;
4644	}
4645
4646	case SVGA_3D_CMD_CONTEXT_DESTROY:
4647	{
4648	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4649	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4650	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4651
4652	rc = vmsvga3dContextDestroy(pThisCC, pCmd->cid);
4653	break;
4654	}
4655
4656	case SVGA_3D_CMD_SETTRANSFORM:
4657	{
4658	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4659	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4660	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4661
4662	rc = vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
4663	break;
4664	}
4665
4666	case SVGA_3D_CMD_SETZRANGE:
4667	{
4668	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4669	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4670	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4671
4672	rc = vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
4673	break;
4674	}
4675
4676	case SVGA_3D_CMD_SETRENDERSTATE:
4677	{
4678	uint32_t cRenderStates;
4679	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4680	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4681	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4682
4683	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4684	rc = vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4685	break;
4686	}
4687
4688	case SVGA_3D_CMD_SETRENDERTARGET:
4689	{
4690	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4691	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4692	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4693
4694	rc = vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
4695	break;
4696	}
4697
4698	case SVGA_3D_CMD_SETTEXTURESTATE:
4699	{
4700	uint32_t cTextureStates;
4701	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4702	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4703	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4704
4705	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4706	rc = vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4707	break;
4708	}
4709
4710	case SVGA_3D_CMD_SETMATERIAL:
4711	{
4712	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4713	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4714	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4715
4716	rc = vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
4717	break;
4718	}
4719
4720	case SVGA_3D_CMD_SETLIGHTDATA:
4721	{
4722	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4723	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4724	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4725
4726	rc = vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
4727	break;
4728	}
4729
4730	case SVGA_3D_CMD_SETLIGHTENABLED:
4731	{
4732	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4733	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4734	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4735
4736	rc = vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
4737	break;
4738	}
4739
4740	case SVGA_3D_CMD_SETVIEWPORT:
4741	{
4742	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4743	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4744	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4745
4746	rc = vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4747	break;
4748	}
4749
4750	case SVGA_3D_CMD_SETCLIPPLANE:
4751	{
4752	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4753	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4754	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4755
4756	rc = vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4757	break;
4758	}
4759
4760	case SVGA_3D_CMD_CLEAR:
4761	{
4762	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4763	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4764	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4765
4766	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4767	rc = vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4768	break;
4769	}
4770
4771	case SVGA_3D_CMD_PRESENT:
4772	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4773	{
4774	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4775	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4776	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4777	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4778	else
4779	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4780
4781	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4782
4783	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4784	rc = vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4785	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4786	break;
4787	}
4788
4789	case SVGA_3D_CMD_SHADER_DEFINE:
4790	{
4791	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4792	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4793	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4794
4795	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4796	rc = vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4797	break;
4798	}
4799
4800	case SVGA_3D_CMD_SHADER_DESTROY:
4801	{
4802	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4803	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4804	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4805
4806	rc = vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
4807	break;
4808	}
4809
4810	case SVGA_3D_CMD_SET_SHADER:
4811	{
4812	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4813	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4814	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4815
4816	rc = vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4817	break;
4818	}
4819
4820	case SVGA_3D_CMD_SET_SHADER_CONST:
4821	{
4822	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4823	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4824	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4825
4826	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4827	rc = vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4828	break;
4829	}
4830
4831	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4832	{
4833	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4834	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4835	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4836
4837	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4838	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4839	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4840	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4841	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4842
4843	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4844	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4845
4846	RT_UNTRUSTED_VALIDATED_FENCE();
4847
4848	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4849	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4850	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4851
4852	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4853	rc = vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4854	pNumRange, cVertexDivisor, pVertexDivisor);
4855	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4856	break;
4857	}
4858
4859	case SVGA_3D_CMD_SETSCISSORRECT:
4860	{
4861	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4862	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4863	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4864
4865	rc = vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
4866	break;
4867	}
4868
4869	case SVGA_3D_CMD_BEGIN_QUERY:
4870	{
4871	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4872	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4873	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4874
4875	rc = vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
4876	break;
4877	}
4878
4879	case SVGA_3D_CMD_END_QUERY:
4880	{
4881	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4882	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4883	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4884
4885	rc = vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
4886	break;
4887	}
4888
4889	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4890	{
4891	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4892	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4893	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4894
4895	rc = vmsvga3dQueryWait(pThis, pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
4896	break;
4897	}
4898
4899	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4900	{
4901	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4902	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4903	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4904
4905	rc = vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
4906	break;
4907	}
4908
4909	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4910	/* context id + surface id? */
4911	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4912	break;
4913	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4914	/* context id + surface id? */
4915	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4916	break;
4917
4918	default:
4919	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4920	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4921	break;
4922	}
4923	}
4924	else
4925	# endif // VBOX_WITH_VMSVGA3D
4926	{
4927	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4928	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4929	}
4930	}
4931
4932	/* Go to the next slot */
4933	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4934	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4935	if (offCurrentCmd >= offFifoMax)
4936	{
4937	offCurrentCmd -= offFifoMax - offFifoMin;
4938	Assert(offCurrentCmd >= offFifoMin);
4939	Assert(offCurrentCmd < offFifoMax);
4940	}
4941	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4942	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4943
4944	/*
4945	* Raise IRQ if required. Must enter the critical section here
4946	* before making final decisions here, otherwise cubebench and
4947	* others may end up waiting forever.
4948	*/
4949	if ( u32IrqStatus
4950	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4951	{
4952	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
4953	AssertRC(rc2);
4954
4955	/* FIFO progress might trigger an interrupt. */
4956	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4957	{
4958	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
4959	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4960	}
4961
4962	/* Unmasked IRQ pending? */
4963	if (pThis->svga.u32IrqMask & u32IrqStatus)
4964	{
4965	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4966	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4967	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4968	}
4969
4970	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4971	}
4972	}
4973
4974	/* If really done, clear the busy flag. */
4975	if (fDone)
4976	{
4977	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4978	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
4979	}
4980	}
4981
4982	/*
4983	* Free the bounce buffer. (There are no returns above!)
4984	*/
4985	RTMemFree(pbBounceBuf);
4986
4987	return VINF_SUCCESS;
4988	}
4989
4990	#undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4991	#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
4992	#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
4993
4994	#ifdef VBOX_WITH_VMSVGA3D
4995	/**
4996	* Free the specified GMR
4997	*
4998	* @param pThisCC The VGA/VMSVGA state for ring-3.
4999	* @param idGMR GMR id
5000	*/
5001	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
5002	{
5003	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5004
5005	/* Free the old descriptor if present. */
5006	PGMR pGMR = &pSVGAState->paGMR[idGMR];
5007	if ( pGMR->numDescriptors
5008	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
5009	{
5010	# ifdef DEBUG_GMR_ACCESS
5011	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
5012	# endif
5013
5014	Assert(pGMR->paDesc);
5015	RTMemFree(pGMR->paDesc);
5016	pGMR->paDesc = NULL;
5017	pGMR->numDescriptors = 0;
5018	pGMR->cbTotal = 0;
5019	pGMR->cMaxPages = 0;
5020	}
5021	Assert(!pGMR->cMaxPages);
5022	Assert(!pGMR->cbTotal);
5023	}
5024	#endif /* VBOX_WITH_VMSVGA3D */
5025
5026	/**
5027	* Copy between a GMR and a host memory buffer.
5028	*
5029	* @returns VBox status code.
5030	* @param pThis The shared VGA/VMSVGA instance data.
5031	* @param pThisCC The VGA/VMSVGA state for ring-3.
5032	* @param enmTransferType Transfer type (read/write)
5033	* @param pbHstBuf Host buffer pointer (valid)
5034	* @param cbHstBuf Size of host buffer (valid)
5035	* @param offHst Host buffer offset of the first scanline
5036	* @param cbHstPitch Destination buffer pitch
5037	* @param gstPtr GMR description
5038	* @param offGst Guest buffer offset of the first scanline
5039	* @param cbGstPitch Guest buffer pitch
5040	* @param cbWidth Width in bytes to copy
5041	* @param cHeight Number of scanllines to copy
5042	*/
5043	int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
5044	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
5045	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
5046	uint32_t cbWidth, uint32_t cHeight)
5047	{
5048	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5049	PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
5050	int rc;
5051
5052	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
5053	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
5054	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
5055	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
5056	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
5057
5058	PGMR pGMR;
5059	uint32_t cbGmr; /* The GMR size in bytes. */
5060	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
5061	{
5062	pGMR = NULL;
5063	cbGmr = pThis->vram_size;
5064	}
5065	else
5066	{
5067	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
5068	RT_UNTRUSTED_VALIDATED_FENCE();
5069	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
5070	cbGmr = pGMR->cbTotal;
5071	}
5072
5073	/*
5074	* GMR
5075	*/
5076	/* Calculate GMR offset of the data to be copied. */
5077	AssertMsgReturn(gstPtr.offset < cbGmr,
5078	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5079	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5080	VERR_INVALID_PARAMETER);
5081	RT_UNTRUSTED_VALIDATED_FENCE();
5082	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
5083	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5084	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5085	VERR_INVALID_PARAMETER);
5086	RT_UNTRUSTED_VALIDATED_FENCE();
5087	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
5088
5089	/* Verify that cbWidth is less than scanline and fits into the GMR. */
5090	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
5091	AssertMsgReturn(cbGmrScanline != 0,
5092	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5093	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5094	VERR_INVALID_PARAMETER);
5095	RT_UNTRUSTED_VALIDATED_FENCE();
5096	AssertMsgReturn(cbWidth <= cbGmrScanline,
5097	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5098	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5099	VERR_INVALID_PARAMETER);
5100	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
5101	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5102	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5103	VERR_INVALID_PARAMETER);
5104	RT_UNTRUSTED_VALIDATED_FENCE();
5105
5106	/* How many bytes are available for the data in the GMR. */
5107	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
5108
5109	/* How many scanlines would fit into the available data. */
5110	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
5111	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
5112	if (cbWidth <= cbGmrLastScanline)
5113	++cGmrScanlines;
5114
5115	if (cHeight > cGmrScanlines)
5116	cHeight = cGmrScanlines;
5117
5118	AssertMsgReturn(cHeight > 0,
5119	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5120	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5121	VERR_INVALID_PARAMETER);
5122	RT_UNTRUSTED_VALIDATED_FENCE();
5123
5124	/*
5125	* Host buffer.
5126	*/
5127	AssertMsgReturn(offHst < cbHstBuf,
5128	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5129	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5130	VERR_INVALID_PARAMETER);
5131
5132	/* Verify that cbWidth is less than scanline and fits into the buffer. */
5133	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
5134	AssertMsgReturn(cbHstScanline != 0,
5135	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5136	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5137	VERR_INVALID_PARAMETER);
5138	AssertMsgReturn(cbWidth <= cbHstScanline,
5139	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5140	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5141	VERR_INVALID_PARAMETER);
5142	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
5143	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5144	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5145	VERR_INVALID_PARAMETER);
5146
5147	/* How many bytes are available for the data in the buffer. */
5148	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
5149
5150	/* How many scanlines would fit into the available data. */
5151	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
5152	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
5153	if (cbWidth <= cbHstLastScanline)
5154	++cHstScanlines;
5155
5156	if (cHeight > cHstScanlines)
5157	cHeight = cHstScanlines;
5158
5159	AssertMsgReturn(cHeight > 0,
5160	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5161	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5162	VERR_INVALID_PARAMETER);
5163
5164	uint8_t *pbHst = pbHstBuf + offHst;
5165
5166	/* Shortcut for the framebuffer. */
5167	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
5168	{
5169	uint8_t *pbGst = pThisCC->pbVRam + offGmr;
5170
5171	uint8_t const *pbSrc;
5172	int32_t cbSrcPitch;
5173	uint8_t *pbDst;
5174	int32_t cbDstPitch;
5175
5176	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
5177	{
5178	pbSrc = pbHst;
5179	cbSrcPitch = cbHstPitch;
5180	pbDst = pbGst;
5181	cbDstPitch = cbGstPitch;
5182	}
5183	else
5184	{
5185	pbSrc = pbGst;
5186	cbSrcPitch = cbGstPitch;
5187	pbDst = pbHst;
5188	cbDstPitch = cbHstPitch;
5189	}
5190
5191	if ( cbWidth == (uint32_t)cbGstPitch
5192	&& cbGstPitch == cbHstPitch)
5193	{
5194	/* Entire scanlines, positive pitch. */
5195	memcpy(pbDst, pbSrc, cbWidth * cHeight);
5196	}
5197	else
5198	{
5199	for (uint32_t i = 0; i < cHeight; ++i)
5200	{
5201	memcpy(pbDst, pbSrc, cbWidth);
5202
5203	pbDst += cbDstPitch;
5204	pbSrc += cbSrcPitch;
5205	}
5206	}
5207	return VINF_SUCCESS;
5208	}
5209
5210	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
5211	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
5212
5213	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
5214	uint32_t iDesc = 0; /* Index in the descriptor array. */
5215	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
5216	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
5217	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
5218	for (uint32_t i = 0; i < cHeight; ++i)
5219	{
5220	uint32_t cbCurrentWidth = cbWidth;
5221	uint32_t offGmrCurrent = offGmrScanline;
5222	uint8_t *pbCurrentHost = pbHstScanline;
5223
5224	/* Find the right descriptor */
5225	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
5226	{
5227	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5228	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
5229	++iDesc;
5230	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5231	}
5232
5233	while (cbCurrentWidth)
5234	{
5235	uint32_t cbToCopy;
5236
5237	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
5238	{
5239	cbToCopy = cbCurrentWidth;
5240	}
5241	else
5242	{
5243	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
5244	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
5245	}
5246
5247	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
5248
5249	Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
5250
5251	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
5252	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5253	else
5254	rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5255	AssertRCBreak(rc);
5256
5257	cbCurrentWidth -= cbToCopy;
5258	offGmrCurrent += cbToCopy;
5259	pbCurrentHost += cbToCopy;
5260
5261	/* Go to the next descriptor if there's anything left. */
5262	if (cbCurrentWidth)
5263	{
5264	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5265	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5266	++iDesc;
5267	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5268	}
5269	}
5270
5271	offGmrScanline += cbGstPitch;
5272	pbHstScanline += cbHstPitch;
5273	}
5274
5275	return VINF_SUCCESS;
5276	}
5277
5278
5279	/**
5280	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5281	*
5282	* @param pSizeSrc Source surface dimensions.
5283	* @param pSizeDest Destination surface dimensions.
5284	* @param pBox Coordinates to be clipped.
5285	*/
5286	void vmsvgaR3ClipCopyBox(const SVGA3dSize pSizeSrc, const SVGA3dSize pSizeDest, SVGA3dCopyBox *pBox)
5287	{
5288	/* Src x, w */
5289	if (pBox->srcx > pSizeSrc->width)
5290	pBox->srcx = pSizeSrc->width;
5291	if (pBox->w > pSizeSrc->width - pBox->srcx)
5292	pBox->w = pSizeSrc->width - pBox->srcx;
5293
5294	/* Src y, h */
5295	if (pBox->srcy > pSizeSrc->height)
5296	pBox->srcy = pSizeSrc->height;
5297	if (pBox->h > pSizeSrc->height - pBox->srcy)
5298	pBox->h = pSizeSrc->height - pBox->srcy;
5299
5300	/* Src z, d */
5301	if (pBox->srcz > pSizeSrc->depth)
5302	pBox->srcz = pSizeSrc->depth;
5303	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5304	pBox->d = pSizeSrc->depth - pBox->srcz;
5305
5306	/* Dest x, w */
5307	if (pBox->x > pSizeDest->width)
5308	pBox->x = pSizeDest->width;
5309	if (pBox->w > pSizeDest->width - pBox->x)
5310	pBox->w = pSizeDest->width - pBox->x;
5311
5312	/* Dest y, h */
5313	if (pBox->y > pSizeDest->height)
5314	pBox->y = pSizeDest->height;
5315	if (pBox->h > pSizeDest->height - pBox->y)
5316	pBox->h = pSizeDest->height - pBox->y;
5317
5318	/* Dest z, d */
5319	if (pBox->z > pSizeDest->depth)
5320	pBox->z = pSizeDest->depth;
5321	if (pBox->d > pSizeDest->depth - pBox->z)
5322	pBox->d = pSizeDest->depth - pBox->z;
5323	}
5324
5325	/**
5326	* Unsigned coordinates in pBox. Clip to [0; pSize).
5327	*
5328	* @param pSize Source surface dimensions.
5329	* @param pBox Coordinates to be clipped.
5330	*/
5331	void vmsvgaR3ClipBox(const SVGA3dSize pSize, SVGA3dBox pBox)
5332	{
5333	/* x, w */
5334	if (pBox->x > pSize->width)
5335	pBox->x = pSize->width;
5336	if (pBox->w > pSize->width - pBox->x)
5337	pBox->w = pSize->width - pBox->x;
5338
5339	/* y, h */
5340	if (pBox->y > pSize->height)
5341	pBox->y = pSize->height;
5342	if (pBox->h > pSize->height - pBox->y)
5343	pBox->h = pSize->height - pBox->y;
5344
5345	/* z, d */
5346	if (pBox->z > pSize->depth)
5347	pBox->z = pSize->depth;
5348	if (pBox->d > pSize->depth - pBox->z)
5349	pBox->d = pSize->depth - pBox->z;
5350	}
5351
5352	/**
5353	* Clip.
5354	*
5355	* @param pBound Bounding rectangle.
5356	* @param pRect Rectangle to be clipped.
5357	*/
5358	void vmsvgaR3ClipRect(SVGASignedRect const pBound, SVGASignedRect pRect)
5359	{
5360	int32_t left;
5361	int32_t top;
5362	int32_t right;
5363	int32_t bottom;
5364
5365	/* Right order. */
5366	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5367	if (pRect->left < pRect->right)
5368	{
5369	left = pRect->left;
5370	right = pRect->right;
5371	}
5372	else
5373	{
5374	left = pRect->right;
5375	right = pRect->left;
5376	}
5377	if (pRect->top < pRect->bottom)
5378	{
5379	top = pRect->top;
5380	bottom = pRect->bottom;
5381	}
5382	else
5383	{
5384	top = pRect->bottom;
5385	bottom = pRect->top;
5386	}
5387
5388	if (left < pBound->left)
5389	left = pBound->left;
5390	if (right < pBound->left)
5391	right = pBound->left;
5392
5393	if (left > pBound->right)
5394	left = pBound->right;
5395	if (right > pBound->right)
5396	right = pBound->right;
5397
5398	if (top < pBound->top)
5399	top = pBound->top;
5400	if (bottom < pBound->top)
5401	bottom = pBound->top;
5402
5403	if (top > pBound->bottom)
5404	top = pBound->bottom;
5405	if (bottom > pBound->bottom)
5406	bottom = pBound->bottom;
5407
5408	pRect->left = left;
5409	pRect->right = right;
5410	pRect->top = top;
5411	pRect->bottom = bottom;
5412	}
5413
5414	/**
5415	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5416	* Unblock the FIFO I/O thread so it can respond to a state change.}
5417	*/
5418	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5419	{
5420	RT_NOREF(pDevIns);
5421	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5422	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5423	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5424	}
5425
5426	/**
5427	* Enables or disables dirty page tracking for the framebuffer
5428	*
5429	* @param pDevIns The device instance.
5430	* @param pThis The shared VGA/VMSVGA instance data.
5431	* @param fTraces Enable/disable traces
5432	*/
5433	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
5434	{
5435	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5436	&& !fTraces)
5437	{
5438	//Assert(pThis->svga.fTraces);
5439	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5440	return;
5441	}
5442
5443	pThis->svga.fTraces = fTraces;
5444	if (pThis->svga.fTraces)
5445	{
5446	unsigned cbFrameBuffer = pThis->vram_size;
5447
5448	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5449	/** @todo How does this work with screens? */
5450	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5451	{
5452	# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5453	Assert(pThis->svga.cbScanline);
5454	# endif
5455	/* Hardware enabled; return real framebuffer size .*/
5456	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5457	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5458	}
5459
5460	if (!pThis->svga.fVRAMTracking)
5461	{
5462	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5463	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
5464	pThis->svga.fVRAMTracking = true;
5465	}
5466	}
5467	else
5468	{
5469	if (pThis->svga.fVRAMTracking)
5470	{
5471	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5472	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5473	pThis->svga.fVRAMTracking = false;
5474	}
5475	}
5476	}
5477
5478	/**
5479	* @callback_method_impl{FNPCIIOREGIONMAP}
5480	*/
5481	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5482	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5483	{
5484	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5485	int rc;
5486	RT_NOREF(pPciDev);
5487	Assert(pPciDev == pDevIns->apPciDevs[0]);
5488
5489	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5490	AssertReturn( iRegion == pThis->pciRegions.iFIFO
5491	&& ( enmType == PCI_ADDRESS_SPACE_MEM
5492	\|\| (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
5493	, VERR_INTERNAL_ERROR);
5494	if (GCPhysAddress != NIL_RTGCPHYS)
5495	{
5496	/*
5497	* Mapping the FIFO RAM.
5498	*/
5499	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5500	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5501	AssertRC(rc);
5502
5503	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5504	if (RT_SUCCESS(rc))
5505	{
5506	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5507	# ifdef DEBUG_FIFO_ACCESS
5508	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5509	# else
5510	GCPhysAddress + PAGE_SIZE - 1,
5511	# endif
5512	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5513	"VMSVGA FIFO");
5514	AssertRC(rc);
5515	}
5516	# endif
5517	if (RT_SUCCESS(rc))
5518	{
5519	pThis->svga.GCPhysFIFO = GCPhysAddress;
5520	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5521	}
5522	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite erros here. */
5523	}
5524	else
5525	{
5526	Assert(pThis->svga.GCPhysFIFO);
5527	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5528	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5529	AssertRC(rc);
5530	# else
5531	rc = VINF_SUCCESS;
5532	# endif
5533	pThis->svga.GCPhysFIFO = 0;
5534	}
5535	return rc;
5536	}
5537
5538	# ifdef VBOX_WITH_VMSVGA3D
5539
5540	/**
5541	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5542	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5543	*
5544	* @param pDevIns The device instance.
5545	* @param pThis The The shared VGA/VMSVGA instance data.
5546	* @param pThisCC The VGA/VMSVGA state for ring-3.
5547	* @param sid Either UINT32_MAX or the ID of a specific surface. If
5548	* UINT32_MAX is used, all surfaces are processed.
5549	*/
5550	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
5551	{
5552	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5553	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5554	}
5555
5556
5557	/**
5558	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5559	*/
5560	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5561	{
5562	/* There might be a specific surface ID at the start of the
5563	arguments, if not show all surfaces. */
5564	uint32_t sid = UINT32_MAX;
5565	if (pszArgs)
5566	pszArgs = RTStrStripL(pszArgs);
5567	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5568	sid = RTStrToUInt32(pszArgs);
5569
5570	/* Verbose or terse display, we default to verbose. */
5571	bool fVerbose = true;
5572	if (RTStrIStr(pszArgs, "terse"))
5573	fVerbose = false;
5574
5575	/* The size of the ascii art (x direction, y is 3/4 of x). */
5576	uint32_t cxAscii = 80;
5577	if (RTStrIStr(pszArgs, "gigantic"))
5578	cxAscii = 300;
5579	else if (RTStrIStr(pszArgs, "huge"))
5580	cxAscii = 180;
5581	else if (RTStrIStr(pszArgs, "big"))
5582	cxAscii = 132;
5583	else if (RTStrIStr(pszArgs, "normal"))
5584	cxAscii = 80;
5585	else if (RTStrIStr(pszArgs, "medium"))
5586	cxAscii = 64;
5587	else if (RTStrIStr(pszArgs, "small"))
5588	cxAscii = 48;
5589	else if (RTStrIStr(pszArgs, "tiny"))
5590	cxAscii = 24;
5591
5592	/* Y invert the image when producing the ASCII art. */
5593	bool fInvY = false;
5594	if (RTStrIStr(pszArgs, "invy"))
5595	fInvY = true;
5596
5597	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5598	pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5599	}
5600
5601
5602	/**
5603	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5604	*/
5605	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5606	{
5607	/* pszArg = "sid[>dir]"
5608	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5609	*/
5610	char *pszBitmapPath = NULL;
5611	uint32_t sid = UINT32_MAX;
5612	if (pszArgs)
5613	pszArgs = RTStrStripL(pszArgs);
5614	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5615	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5616	if ( pszBitmapPath
5617	&& *pszBitmapPath == '>')
5618	++pszBitmapPath;
5619
5620	const bool fVerbose = true;
5621	const uint32_t cxAscii = 0; /* No ASCII */
5622	const bool fInvY = false; /* Do not invert. */
5623	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5624	pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5625	}
5626
5627	/**
5628	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5629	*/
5630	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5631	{
5632	/* There might be a specific surface ID at the start of the
5633	arguments, if not show all contexts. */
5634	uint32_t sid = UINT32_MAX;
5635	if (pszArgs)
5636	pszArgs = RTStrStripL(pszArgs);
5637	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5638	sid = RTStrToUInt32(pszArgs);
5639
5640	/* Verbose or terse display, we default to verbose. */
5641	bool fVerbose = true;
5642	if (RTStrIStr(pszArgs, "terse"))
5643	fVerbose = false;
5644
5645	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
5646	}
5647	# endif /* VBOX_WITH_VMSVGA3D */
5648
5649	/**
5650	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5651	*/
5652	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5653	{
5654	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5655	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5656	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5657	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
5658	RT_NOREF(pszArgs);
5659
5660	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5661	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5662	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5663	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5664	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5665	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5666	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5667	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5668	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5669	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5670	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5671	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5672	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5673	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5674	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5675	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5676	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5677	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5678	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5679	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5680	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5681	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5682	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5683	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5684	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5685
5686	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5687	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5688	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5689	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5690
5691	pHlp->pfnPrintf(pHlp, "Legacy cursor: ID %u, state %u\n", pThis->svga.uCursorID, pThis->svga.uCursorOn);
5692	pHlp->pfnPrintf(pHlp, "Legacy cursor at: %u,%u\n", pThis->svga.uCursorX, pThis->svga.uCursorY);
5693	# ifdef VBOX_WITH_VMSVGA3D
5694	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5695	# endif
5696	if (pThisCC->pDrv)
5697	{
5698	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
5699	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
5700	}
5701
5702	/* Dump screen information. */
5703	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
5704	{
5705	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, iScreen);
5706	if (pScreen)
5707	{
5708	pHlp->pfnPrintf(pHlp, "Screen %u defined (ID %u):\n", iScreen, pScreen->idScreen);
5709	pHlp->pfnPrintf(pHlp, " %u x %u x %ubpp @ %u, %u\n", pScreen->cWidth, pScreen->cHeight,
5710	pScreen->cBpp, pScreen->xOrigin, pScreen->yOrigin);
5711	pHlp->pfnPrintf(pHlp, " Pitch %u bytes, VRAM offset %X\n", pScreen->cbPitch, pScreen->offVRAM);
5712	pHlp->pfnPrintf(pHlp, " Flags %X", pScreen->fuScreen);
5713	if (pScreen->fuScreen != SVGA_SCREEN_MUST_BE_SET)
5714	{
5715	pHlp->pfnPrintf(pHlp, " (");
5716	if (pScreen->fuScreen & SVGA_SCREEN_IS_PRIMARY)
5717	pHlp->pfnPrintf(pHlp, " IS_PRIMARY");
5718	if (pScreen->fuScreen & SVGA_SCREEN_FULLSCREEN_HINT)
5719	pHlp->pfnPrintf(pHlp, " FULLSCREEN_HINT");
5720	if (pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE)
5721	pHlp->pfnPrintf(pHlp, " DEACTIVATE");
5722	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
5723	pHlp->pfnPrintf(pHlp, " BLANKING");
5724	pHlp->pfnPrintf(pHlp, " )");
5725	}
5726	pHlp->pfnPrintf(pHlp, ", %smodified\n", pScreen->fModified ? "" : "not ");
5727	}
5728	}
5729
5730	}
5731
5732	/**
5733	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
5734	*/
5735	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
5736	PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5737	{
5738	RT_NOREF(uPass);
5739
5740	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5741	int rc;
5742
5743	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5744	{
5745	uint32_t cScreens = 0;
5746	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5747	AssertRCReturn(rc, rc);
5748	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5749	("cScreens=%#x\n", cScreens),
5750	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5751
5752	for (uint32_t i = 0; i < cScreens; ++i)
5753	{
5754	VMSVGASCREENOBJECT screen;
5755	RT_ZERO(screen);
5756
5757	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5758	AssertLogRelRCReturn(rc, rc);
5759
5760	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5761	{
5762	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5763	*pScreen = screen;
5764	pScreen->fModified = true;
5765	}
5766	else
5767	{
5768	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5769	}
5770	}
5771	}
5772	else
5773	{
5774	/* Try to setup at least the first screen. */
5775	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5776	pScreen->fDefined = true;
5777	pScreen->fModified = true;
5778	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5779	pScreen->idScreen = 0;
5780	pScreen->xOrigin = 0;
5781	pScreen->yOrigin = 0;
5782	pScreen->offVRAM = pThis->svga.uScreenOffset;
5783	pScreen->cbPitch = pThis->svga.cbScanline;
5784	pScreen->cWidth = pThis->svga.uWidth;
5785	pScreen->cHeight = pThis->svga.uHeight;
5786	pScreen->cBpp = pThis->svga.uBpp;
5787	}
5788
5789	return VINF_SUCCESS;
5790	}
5791
5792	/**
5793	* @copydoc FNSSMDEVLOADEXEC
5794	*/
5795	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5796	{
5797	RT_NOREF(uPass);
5798	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5799	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5800	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5801	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5802	int rc;
5803
5804	/* Load our part of the VGAState */
5805	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5806	AssertRCReturn(rc, rc);
5807
5808	/* Load the VGA framebuffer. */
5809	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5810	uint32_t cbVgaFramebuffer = _32K;
5811	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5812	{
5813	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5814	AssertRCReturn(rc, rc);
5815	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5816	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5817	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5818	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5819	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5820	}
5821	rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5822	AssertRCReturn(rc, rc);
5823	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5824	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5825	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5826	RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5827
5828	/* Load the VMSVGA state. */
5829	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5830	AssertRCReturn(rc, rc);
5831
5832	/* Load the active cursor bitmaps. */
5833	if (pSVGAState->Cursor.fActive)
5834	{
5835	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5836	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5837
5838	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5839	AssertRCReturn(rc, rc);
5840	}
5841
5842	/* Load the GMR state. */
5843	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5844	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5845	{
5846	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5847	AssertRCReturn(rc, rc);
5848	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5849	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5850	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5851	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5852	}
5853
5854	if (pThis->svga.cGMR != cGMR)
5855	{
5856	/* Reallocate GMR array. */
5857	Assert(pSVGAState->paGMR != NULL);
5858	RTMemFree(pSVGAState->paGMR);
5859	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5860	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5861	pThis->svga.cGMR = cGMR;
5862	}
5863
5864	for (uint32_t i = 0; i < cGMR; ++i)
5865	{
5866	PGMR pGMR = &pSVGAState->paGMR[i];
5867
5868	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5869	AssertRCReturn(rc, rc);
5870
5871	if (pGMR->numDescriptors)
5872	{
5873	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5874	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5875	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5876
5877	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5878	{
5879	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5880	AssertRCReturn(rc, rc);
5881	}
5882	}
5883	}
5884
5885	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5886	vmsvga3dPowerOn(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC));
5887	# endif
5888
5889	VMSVGA_STATE_LOAD LoadState;
5890	LoadState.pSSM = pSSM;
5891	LoadState.uVersion = uVersion;
5892	LoadState.uPass = uPass;
5893	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5894	AssertLogRelRCReturn(rc, rc);
5895
5896	return VINF_SUCCESS;
5897	}
5898
5899	/**
5900	* Reinit the video mode after the state has been loaded.
5901	*/
5902	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
5903	{
5904	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5905	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5906	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5907
5908	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5909
5910	/* Set the active cursor. */
5911	if (pSVGAState->Cursor.fActive)
5912	{
5913	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
5914	true /fVisible/,
5915	true /fAlpha/,
5916	pSVGAState->Cursor.xHotspot,
5917	pSVGAState->Cursor.yHotspot,
5918	pSVGAState->Cursor.width,
5919	pSVGAState->Cursor.height,
5920	pSVGAState->Cursor.pData);
5921	AssertRC(rc);
5922	}
5923
5924	/* If the VRAM handler should not be registered, we have to explicitly
5925	* unregister it here!
5926	*/
5927	if (!pThis->svga.fVRAMTracking)
5928	{
5929	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5930	}
5931
5932	return VINF_SUCCESS;
5933	}
5934
5935	/**
5936	* Portion of SVGA state which must be saved in the FIFO thread.
5937	*/
5938	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
5939	{
5940	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5941	int rc;
5942
5943	/* Save the screen objects. */
5944	/* Count defined screen object. */
5945	uint32_t cScreens = 0;
5946	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5947	{
5948	if (pSVGAState->aScreens[i].fDefined)
5949	++cScreens;
5950	}
5951
5952	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
5953	AssertLogRelRCReturn(rc, rc);
5954
5955	for (uint32_t i = 0; i < cScreens; ++i)
5956	{
5957	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5958
5959	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5960	AssertLogRelRCReturn(rc, rc);
5961	}
5962	return VINF_SUCCESS;
5963	}
5964
5965	/**
5966	* @copydoc FNSSMDEVSAVEEXEC
5967	*/
5968	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5969	{
5970	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5971	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5972	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5973	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5974	int rc;
5975
5976	/* Save our part of the VGAState */
5977	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5978	AssertLogRelRCReturn(rc, rc);
5979
5980	/* Save the framebuffer backup. */
5981	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5982	rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5983	AssertLogRelRCReturn(rc, rc);
5984
5985	/* Save the VMSVGA state. */
5986	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5987	AssertLogRelRCReturn(rc, rc);
5988
5989	/* Save the active cursor bitmaps. */
5990	if (pSVGAState->Cursor.fActive)
5991	{
5992	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5993	AssertLogRelRCReturn(rc, rc);
5994	}
5995
5996	/* Save the GMR state */
5997	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
5998	AssertLogRelRCReturn(rc, rc);
5999	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
6000	{
6001	PGMR pGMR = &pSVGAState->paGMR[i];
6002
6003	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
6004	AssertLogRelRCReturn(rc, rc);
6005
6006	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
6007	{
6008	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
6009	AssertLogRelRCReturn(rc, rc);
6010	}
6011	}
6012
6013	/*
6014	* Must save some state (3D in particular) in the FIFO thread.
6015	*/
6016	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
6017	AssertLogRelRCReturn(rc, rc);
6018
6019	return VINF_SUCCESS;
6020	}
6021
6022	/**
6023	* Destructor for PVMSVGAR3STATE structure.
6024	*
6025	* @param pThis The shared VGA/VMSVGA instance data.
6026	* @param pSVGAState Pointer to the structure. It is not deallocated.
6027	*/
6028	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
6029	{
6030	# ifndef VMSVGA_USE_EMT_HALT_CODE
6031	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
6032	{
6033	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
6034	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
6035	}
6036	# endif
6037
6038	if (pSVGAState->Cursor.fActive)
6039	{
6040	RTMemFree(pSVGAState->Cursor.pData);
6041	pSVGAState->Cursor.pData = NULL;
6042	pSVGAState->Cursor.fActive = false;
6043	}
6044
6045	if (pSVGAState->paGMR)
6046	{
6047	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
6048	if (pSVGAState->paGMR[i].paDesc)
6049	RTMemFree(pSVGAState->paGMR[i].paDesc);
6050
6051	RTMemFree(pSVGAState->paGMR);
6052	pSVGAState->paGMR = NULL;
6053	}
6054	}
6055
6056	/**
6057	* Constructor for PVMSVGAR3STATE structure.
6058	*
6059	* @returns VBox status code.
6060	* @param pThis The shared VGA/VMSVGA instance data.
6061	* @param pSVGAState Pointer to the structure. It is already allocated.
6062	*/
6063	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
6064	{
6065	int rc = VINF_SUCCESS;
6066	RT_ZERO(*pSVGAState);
6067
6068	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
6069	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
6070
6071	# ifndef VMSVGA_USE_EMT_HALT_CODE
6072	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
6073	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
6074	AssertRCReturn(rc, rc);
6075	# endif
6076
6077	return rc;
6078	}
6079
6080	/**
6081	* Initializes the host capabilities: registers and FIFO.
6082	*
6083	* @returns VBox status code.
6084	* @param pThis The shared VGA/VMSVGA instance data.
6085	* @param pThisCC The VGA/VMSVGA state for ring-3.
6086	*/
6087	static void vmsvgaR3InitCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
6088	{
6089	/* Register caps. */
6090	pThis->svga.u32RegCaps = SVGA_CAP_GMR
6091	\| SVGA_CAP_GMR2
6092	\| SVGA_CAP_CURSOR
6093	\| SVGA_CAP_CURSOR_BYPASS
6094	\| SVGA_CAP_CURSOR_BYPASS_2
6095	\| SVGA_CAP_EXTENDED_FIFO
6096	\| SVGA_CAP_IRQMASK
6097	\| SVGA_CAP_PITCHLOCK
6098	\| SVGA_CAP_TRACES
6099	\| SVGA_CAP_SCREEN_OBJECT_2
6100	\| SVGA_CAP_ALPHA_CURSOR;
6101	# ifdef VBOX_WITH_VMSVGA3D
6102	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
6103	# endif
6104
6105	/* Clear the FIFO. */
6106	RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
6107
6108	/* Setup FIFO capabilities. */
6109	pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
6110	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
6111	\| SVGA_FIFO_CAP_GMR2
6112	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
6113	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2
6114	\| SVGA_FIFO_CAP_RESERVE
6115	\| SVGA_FIFO_CAP_PITCHLOCK;
6116
6117	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
6118	pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
6119	}
6120
6121	# ifdef VBOX_WITH_VMSVGA3D
6122	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
6123	static const char * const g_apszVmSvgaDevCapNames[] =
6124	{
6125	"x3D", /* = 0 */
6126	"xMAX_LIGHTS",
6127	"xMAX_TEXTURES",
6128	"xMAX_CLIP_PLANES",
6129	"xVERTEX_SHADER_VERSION",
6130	"xVERTEX_SHADER",
6131	"xFRAGMENT_SHADER_VERSION",
6132	"xFRAGMENT_SHADER",
6133	"xMAX_RENDER_TARGETS",
6134	"xS23E8_TEXTURES",
6135	"xS10E5_TEXTURES",
6136	"xMAX_FIXED_VERTEXBLEND",
6137	"xD16_BUFFER_FORMAT",
6138	"xD24S8_BUFFER_FORMAT",
6139	"xD24X8_BUFFER_FORMAT",
6140	"xQUERY_TYPES",
6141	"xTEXTURE_GRADIENT_SAMPLING",
6142	"rMAX_POINT_SIZE",
6143	"xMAX_SHADER_TEXTURES",
6144	"xMAX_TEXTURE_WIDTH",
6145	"xMAX_TEXTURE_HEIGHT",
6146	"xMAX_VOLUME_EXTENT",
6147	"xMAX_TEXTURE_REPEAT",
6148	"xMAX_TEXTURE_ASPECT_RATIO",
6149	"xMAX_TEXTURE_ANISOTROPY",
6150	"xMAX_PRIMITIVE_COUNT",
6151	"xMAX_VERTEX_INDEX",
6152	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
6153	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
6154	"xMAX_VERTEX_SHADER_TEMPS",
6155	"xMAX_FRAGMENT_SHADER_TEMPS",
6156	"xTEXTURE_OPS",
6157	"xSURFACEFMT_X8R8G8B8",
6158	"xSURFACEFMT_A8R8G8B8",
6159	"xSURFACEFMT_A2R10G10B10",
6160	"xSURFACEFMT_X1R5G5B5",
6161	"xSURFACEFMT_A1R5G5B5",
6162	"xSURFACEFMT_A4R4G4B4",
6163	"xSURFACEFMT_R5G6B5",
6164	"xSURFACEFMT_LUMINANCE16",
6165	"xSURFACEFMT_LUMINANCE8_ALPHA8",
6166	"xSURFACEFMT_ALPHA8",
6167	"xSURFACEFMT_LUMINANCE8",
6168	"xSURFACEFMT_Z_D16",
6169	"xSURFACEFMT_Z_D24S8",
6170	"xSURFACEFMT_Z_D24X8",
6171	"xSURFACEFMT_DXT1",
6172	"xSURFACEFMT_DXT2",
6173	"xSURFACEFMT_DXT3",
6174	"xSURFACEFMT_DXT4",
6175	"xSURFACEFMT_DXT5",
6176	"xSURFACEFMT_BUMPX8L8V8U8",
6177	"xSURFACEFMT_A2W10V10U10",
6178	"xSURFACEFMT_BUMPU8V8",
6179	"xSURFACEFMT_Q8W8V8U8",
6180	"xSURFACEFMT_CxV8U8",
6181	"xSURFACEFMT_R_S10E5",
6182	"xSURFACEFMT_R_S23E8",
6183	"xSURFACEFMT_RG_S10E5",
6184	"xSURFACEFMT_RG_S23E8",
6185	"xSURFACEFMT_ARGB_S10E5",
6186	"xSURFACEFMT_ARGB_S23E8",
6187	"xMISSING62",
6188	"xMAX_VERTEX_SHADER_TEXTURES",
6189	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
6190	"xSURFACEFMT_V16U16",
6191	"xSURFACEFMT_G16R16",
6192	"xSURFACEFMT_A16B16G16R16",
6193	"xSURFACEFMT_UYVY",
6194	"xSURFACEFMT_YUY2",
6195	"xMULTISAMPLE_NONMASKABLESAMPLES",
6196	"xMULTISAMPLE_MASKABLESAMPLES",
6197	"xALPHATOCOVERAGE",
6198	"xSUPERSAMPLE",
6199	"xAUTOGENMIPMAPS",
6200	"xSURFACEFMT_NV12",
6201	"xSURFACEFMT_AYUV",
6202	"xMAX_CONTEXT_IDS",
6203	"xMAX_SURFACE_IDS",
6204	"xSURFACEFMT_Z_DF16",
6205	"xSURFACEFMT_Z_DF24",
6206	"xSURFACEFMT_Z_D24S8_INT",
6207	"xSURFACEFMT_BC4_UNORM",
6208	"xSURFACEFMT_BC5_UNORM", /* 83 */
6209	};
6210
6211	/**
6212	* Initializes the host 3D capabilities in FIFO.
6213	*
6214	* @returns VBox status code.
6215	* @param pThis The shared VGA/VMSVGA instance data.
6216	* @param pThisCC The VGA/VMSVGA state for ring-3.
6217	*/
6218	static void vmsvgaR3InitFifo3DCaps(PVGASTATECC pThisCC)
6219	{
6220	/** @todo Probably query the capabilities once and cache in a memory buffer. */
6221	bool fSavedBuffering = RTLogRelSetBuffering(true);
6222	SVGA3dCapsRecord *pCaps;
6223	SVGA3dCapPair *pData;
6224	uint32_t idxCap = 0;
6225
6226	/* 3d hardware version; latest and greatest */
6227	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
6228	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
6229
6230	pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
6231	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
6232	pData = (SVGA3dCapPair *)&pCaps->data;
6233
6234	/* Fill out all 3d capabilities. */
6235	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
6236	{
6237	uint32_t val = 0;
6238
6239	int rc = vmsvga3dQueryCaps(pThisCC, i, &val);
6240	if (RT_SUCCESS(rc))
6241	{
6242	pData[idxCap][0] = i;
6243	pData[idxCap][1] = val;
6244	idxCap++;
6245	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
6246	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
6247	else
6248	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
6249	&g_apszVmSvgaDevCapNames[i][1]));
6250	}
6251	else
6252	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
6253	}
6254	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6255	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6256
6257	/* Mark end of record array. */
6258	pCaps->header.length = 0;
6259
6260	RTLogRelSetBuffering(fSavedBuffering);
6261	}
6262
6263	# endif
6264
6265	/**
6266	* Resets the SVGA hardware state
6267	*
6268	* @returns VBox status code.
6269	* @param pDevIns The device instance.
6270	*/
6271	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
6272	{
6273	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6274	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6275	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6276
6277	/* Reset before init? */
6278	if (!pSVGAState)
6279	return VINF_SUCCESS;
6280
6281	Log(("vmsvgaR3Reset\n"));
6282
6283	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6284	pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6285	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6286
6287	/* Reset other stuff. */
6288	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6289	RT_ZERO(pThis->svga.au32ScratchRegion);
6290
6291	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6292	vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6293
6294	RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6295
6296	/* Initialize FIFO and register capabilities. */
6297	vmsvgaR3InitCaps(pThis, pThisCC);
6298
6299	# ifdef VBOX_WITH_VMSVGA3D
6300	if (pThis->svga.f3DEnabled)
6301	vmsvgaR3InitFifo3DCaps(pThisCC);
6302	# endif
6303
6304	/* VRAM tracking is enabled by default during bootup. */
6305	pThis->svga.fVRAMTracking = true;
6306	pThis->svga.fEnabled = false;
6307
6308	/* Invalidate current settings. */
6309	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6310	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6311	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6312	pThis->svga.cbScanline = 0;
6313	pThis->svga.u32PitchLock = 0;
6314
6315	return rc;
6316	}
6317
6318	/**
6319	* Cleans up the SVGA hardware state
6320	*
6321	* @returns VBox status code.
6322	* @param pDevIns The device instance.
6323	*/
6324	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
6325	{
6326	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6327	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6328
6329	/*
6330	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6331	*/
6332	if (pThisCC->svga.pFIFOIOThread)
6333	{
6334	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
6335	NULL /pvParam/, 30000 /ms/);
6336	AssertLogRelRC(rc);
6337
6338	rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
6339	AssertLogRelRC(rc);
6340	pThisCC->svga.pFIFOIOThread = NULL;
6341	}
6342
6343	/*
6344	* Destroy the special SVGA state.
6345	*/
6346	if (pThisCC->svga.pSvgaR3State)
6347	{
6348	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6349
6350	RTMemFree(pThisCC->svga.pSvgaR3State);
6351	pThisCC->svga.pSvgaR3State = NULL;
6352	}
6353
6354	/*
6355	* Free our resources residing in the VGA state.
6356	*/
6357	if (pThisCC->svga.pbVgaFrameBufferR3)
6358	{
6359	RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
6360	pThisCC->svga.pbVgaFrameBufferR3 = NULL;
6361	}
6362	if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
6363	{
6364	RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
6365	pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
6366	}
6367	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
6368	{
6369	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
6370	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
6371	}
6372
6373	return VINF_SUCCESS;
6374	}
6375
6376	/**
6377	* Initialize the SVGA hardware state
6378	*
6379	* @returns VBox status code.
6380	* @param pDevIns The device instance.
6381	*/
6382	int vmsvgaR3Init(PPDMDEVINS pDevIns)
6383	{
6384	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6385	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6386	PVMSVGAR3STATE pSVGAState;
6387	int rc;
6388
6389	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6390	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6391
6392	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6393
6394	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6395	pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6396	AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6397
6398	/* Create event semaphore. */
6399	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
6400	AssertRCReturn(rc, rc);
6401
6402	/* Create event semaphore. */
6403	rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
6404	AssertRCReturn(rc, rc);
6405
6406	pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
6407	AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
6408
6409	rc = vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6410	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6411
6412	pSVGAState = pThisCC->svga.pSvgaR3State;
6413
6414	/* Initialize FIFO and register capabilities. */
6415	vmsvgaR3InitCaps(pThis, pThisCC);
6416
6417	# ifdef VBOX_WITH_VMSVGA3D
6418	if (pThis->svga.f3DEnabled)
6419	{
6420	rc = vmsvga3dInit(pDevIns, pThis, pThisCC);
6421	if (RT_FAILURE(rc))
6422	{
6423	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6424	pThis->svga.f3DEnabled = false;
6425	}
6426	}
6427	# endif
6428	/* VRAM tracking is enabled by default during bootup. */
6429	pThis->svga.fVRAMTracking = true;
6430
6431	/* Invalidate current settings. */
6432	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6433	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6434	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6435	pThis->svga.cbScanline = 0;
6436
6437	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6438	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6439	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6440	{
6441	pThis->svga.u32MaxWidth -= 256;
6442	pThis->svga.u32MaxHeight -= 256;
6443	}
6444	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6445
6446	# ifdef DEBUG_GMR_ACCESS
6447	/* Register the GMR access handler type. */
6448	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
6449	vmsvgaR3GmrAccessHandler,
6450	NULL, NULL, NULL,
6451	NULL, NULL, NULL,
6452	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6453	AssertRCReturn(rc, rc);
6454	# endif
6455
6456	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6457	/* Register the FIFO access handler type. In addition to
6458	debugging FIFO access, this is also used to facilitate
6459	extended fifo thread sleeps. */
6460	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns),
6461	# ifdef DEBUG_FIFO_ACCESS
6462	PGMPHYSHANDLERKIND_ALL,
6463	# else
6464	PGMPHYSHANDLERKIND_WRITE,
6465	# endif
6466	vmsvgaR3FifoAccessHandler,
6467	NULL, NULL, NULL,
6468	NULL, NULL, NULL,
6469	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6470	AssertRCReturn(rc, rc);
6471	# endif
6472
6473	/* Create the async IO thread. */
6474	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
6475	RTTHREADTYPE_IO, "VMSVGA FIFO");
6476	if (RT_FAILURE(rc))
6477	{
6478	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6479	return rc;
6480	}
6481
6482	/*
6483	* Statistics.
6484	*/
6485	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6486	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6487	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6488	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6489	# ifdef VBOX_WITH_STATISTICS
6490	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6491	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6492	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6493	# endif
6494	REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
6495	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6496	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6497	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6498	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6499	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6500	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6501	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6502	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6503	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6504	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6505	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6506	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6507	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6508	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6509	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6510	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6511	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6512	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6513	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6514	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6515	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6516	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6517	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6518	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6519	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6520	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6521	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6522	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6523	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6524	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6525	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6526	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6527	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6528	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6529	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6530	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6531	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6532	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6533	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6534	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6535	REG_CNT(&pSVGAState->StatR3CmdMoveCursor, "VMSVGA/Cmd/MoveCursor", "SVGA_CMD_MOVE_CURSOR");
6536	REG_CNT(&pSVGAState->StatR3CmdDisplayCursor, "VMSVGA/Cmd/DisplayCursor", "SVGA_CMD_DISPLAY_CURSOR");
6537	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6538	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6539	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6540	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6541	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6542	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6543	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6544	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6545	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6546	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6547	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6548	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6549	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6550
6551	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6552	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6553	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6554	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6555	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6556	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6557	REG_CNT(&pThis->svga.StatRegCursorXWr, "VMSVGA/Reg/CursorXWrite", "SVGA_REG_CURSOR_X writes.");
6558	REG_CNT(&pThis->svga.StatRegCursorYWr, "VMSVGA/Reg/CursorYWrite", "SVGA_REG_CURSOR_Y writes.");
6559	REG_CNT(&pThis->svga.StatRegCursorIdWr, "VMSVGA/Reg/CursorIdWrite", "SVGA_REG_CURSOR_ID writes.");
6560	REG_CNT(&pThis->svga.StatRegCursorOnWr, "VMSVGA/Reg/CursorOnWrite", "SVGA_REG_CURSOR_ON writes.");
6561	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6562	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6563	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6564	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6565	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6566	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6567	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6568	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6569	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6570	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6571	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6572	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6573	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6574	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6575	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6576	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6577	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6578	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6579	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6580	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6581	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6582	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6583	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6584	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6585	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6586
6587	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6588	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6589	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6590	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6591	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6592	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6593	REG_CNT(&pThis->svga.StatRegCursorXRd, "VMSVGA/Reg/CursorXRead", "SVGA_REG_CURSOR_X reads.");
6594	REG_CNT(&pThis->svga.StatRegCursorYRd, "VMSVGA/Reg/CursorYRead", "SVGA_REG_CURSOR_Y reads.");
6595	REG_CNT(&pThis->svga.StatRegCursorIdRd, "VMSVGA/Reg/CursorIdRead", "SVGA_REG_CURSOR_ID reads.");
6596	REG_CNT(&pThis->svga.StatRegCursorOnRd, "VMSVGA/Reg/CursorOnRead", "SVGA_REG_CURSOR_ON reads.");
6597	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6598	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6599	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6600	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6601	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6602	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6603	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6604	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6605	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6606	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6607	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6608	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6609	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6610	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6611	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6612	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6613	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6614	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6615	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6616	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6617	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6618	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6619	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6620	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6621	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6622	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6623	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6624	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6625	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6626	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6627	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6628	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6629	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6630	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6631	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6632	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6633	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6634	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6635	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6636	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6637	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6638	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6639
6640	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6641	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6642	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6643	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6644	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6645	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6646	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6647	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6648	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6649	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6650	# endif
6651	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6652	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6653	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6654	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6655	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6656
6657	# undef REG_CNT
6658	# undef REG_PRF
6659
6660	/*
6661	* Info handlers.
6662	*/
6663	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6664	# ifdef VBOX_WITH_VMSVGA3D
6665	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6666	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6667	"VMSVGA 3d surface details. "
6668	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6669	vmsvgaR3Info3dSurface);
6670	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6671	"VMSVGA 3d surface details and bitmap: "
6672	"sid[>dir]",
6673	vmsvgaR3Info3dSurfaceBmp);
6674	# endif
6675
6676	return VINF_SUCCESS;
6677	}
6678
6679	/**
6680	* Power On notification.
6681	*
6682	* @returns VBox status code.
6683	* @param pDevIns The device instance data.
6684	*
6685	* @remarks Caller enters the device critical section.
6686	*/
6687	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6688	{
6689	# ifdef VBOX_WITH_VMSVGA3D
6690	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6691	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6692	if (pThis->svga.f3DEnabled)
6693	{
6694	int rc = vmsvga3dPowerOn(pDevIns, pThis, pThisCC);
6695
6696	if (RT_SUCCESS(rc))
6697	{
6698	/* Initialize FIFO 3D capabilities. */
6699	vmsvgaR3InitFifo3DCaps(pThisCC);
6700	}
6701	}
6702	# else /* !VBOX_WITH_VMSVGA3D */
6703	RT_NOREF(pDevIns);
6704	# endif /* !VBOX_WITH_VMSVGA3D */
6705	}
6706
6707	#endif /* IN_RING3 */

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 83274

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