VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 57504

Last change on this file since 57504 was 57504, checked in by vboxsync, 10 years ago

VMSVGA3d/ogl: Banging my head vertical scrolling of the host 'monitor window. It's better now, but not quite there yet, at least not on windows.
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1/* $Id: DevVGA-SVGA.cpp 57504 2015-08-23 23:09:46Z vboxsync $ */
2/** @file
3 * VMWare SVGA device.
4 *
5 * Logging levels guidelines for this and related files:
6 * - Log() for normal bits.
7 * - LogFlow() for more info.
8 * - Log2 for hex dump of cursor data.
9 * - Log3 for hex dump of shader code.
10 * - Log4 for hex dumps of 3D data.
11 */
12
13/*
14 * Copyright (C) 2013-2015 Oracle Corporation
15 *
16 * This file is part of VirtualBox Open Source Edition (OSE), as
17 * available from http://www.215389.xyz. This file is free software;
18 * you can redistribute it and/or modify it under the terms of the GNU
19 * General Public License (GPL) as published by the Free Software
20 * Foundation, in version 2 as it comes in the "COPYING" file of the
21 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
22 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
23 */
24
25
26/*********************************************************************************************************************************
27* Header Files *
28*********************************************************************************************************************************/
29#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
30#define VMSVGA_USE_EMT_HALT_CODE
31#include <VBox/vmm/pdmdev.h>
32#include <VBox/version.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/vmm/pgm.h>
36#ifdef VMSVGA_USE_EMT_HALT_CODE
37# include <VBox/vmm/vmapi.h>
38# include <VBox/vmm/vmcpuset.h>
39#endif
40#include <VBox/sup.h>
41
42#include <iprt/assert.h>
43#include <iprt/semaphore.h>
44#include <iprt/uuid.h>
45#ifdef IN_RING3
46# include <iprt/ctype.h>
47# include <iprt/mem.h>
48#endif
49
50#include <VBox/VMMDev.h>
51#include <VBox/VBoxVideo.h>
52#include <VBox/bioslogo.h>
53
54/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
55#include "DevVGA.h"
56
57#ifdef DEBUG
58/* Enable to log FIFO register accesses. */
59//# define DEBUG_FIFO_ACCESS
60/* Enable to log GMR page accesses. */
61//# define DEBUG_GMR_ACCESS
62#endif
63
64#include "DevVGA-SVGA.h"
65#include "vmsvga/svga_reg.h"
66#include "vmsvga/svga_escape.h"
67#include "vmsvga/svga_overlay.h"
68#include "vmsvga/svga3d_reg.h"
69#include "vmsvga/svga3d_caps.h"
70#ifdef VBOX_WITH_VMSVGA3D
71# include "DevVGA-SVGA3d.h"
72# ifdef RT_OS_DARWIN
73# include "DevVGA-SVGA3d-cocoa.h"
74# endif
75#endif
76
77
78/*********************************************************************************************************************************
79* Defined Constants And Macros *
80*********************************************************************************************************************************/
81/**
82 * Macro for checking if a fixed FIFO register is valid according to the
83 * current FIFO configuration.
84 *
85 * @returns true / false.
86 * @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
87 * @param a_offFifoMin A valid SVGA_FIFO_MIN value.
88 */
89#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
90
91
92/*********************************************************************************************************************************
93* Structures and Typedefs *
94*********************************************************************************************************************************/
95/**
96 * 64-bit GMR descriptor.
97 */
98typedef struct
99{
100 RTGCPHYS GCPhys;
101 uint64_t numPages;
102} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
103
104/**
105 * GMR slot
106 */
107typedef struct
108{
109 uint32_t cMaxPages;
110 uint32_t cbTotal;
111 uint32_t numDescriptors;
112 PVMSVGAGMRDESCRIPTOR paDesc;
113} GMR, *PGMR;
114
115#ifdef IN_RING3
116/**
117 * Internal SVGA ring-3 only state.
118 */
119typedef struct VMSVGAR3STATE
120{
121 GMR aGMR[VMSVGA_MAX_GMR_IDS];
122 struct
123 {
124 SVGAGuestPtr ptr;
125 uint32_t bytesPerLine;
126 SVGAGMRImageFormat format;
127 } GMRFB;
128 struct
129 {
130 bool fActive;
131 uint32_t xHotspot;
132 uint32_t yHotspot;
133 uint32_t width;
134 uint32_t height;
135 uint32_t cbData;
136 void *pData;
137 } Cursor;
138 SVGAColorBGRX colorAnnotation;
139
140# ifdef VMSVGA_USE_EMT_HALT_CODE
141 /** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
142 uint32_t volatile cBusyDelayedEmts;
143 /** Set of EMTs that are */
144 VMCPUSET BusyDelayedEmts;
145# else
146 /** Number of EMTs waiting on hBusyDelayedEmts. */
147 uint32_t volatile cBusyDelayedEmts;
148 /** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
149 * busy (ugly). */
150 RTSEMEVENTMULTI hBusyDelayedEmts;
151# endif
152 /** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
153 STAMPROFILE StatBusyDelayEmts;
154
155 STAMPROFILE StatR3CmdPresent;
156 STAMPROFILE StatR3CmdDrawPrimitive;
157 STAMPROFILE StatR3CmdSurfaceDMA;
158
159 STAMCOUNTER StatFifoCommands;
160 STAMCOUNTER StatFifoErrors;
161 STAMCOUNTER StatFifoUnkCmds;
162 STAMCOUNTER StatFifoTodoTimeout;
163 STAMCOUNTER StatFifoTodoWoken;
164 STAMPROFILE StatFifoStalls;
165
166} VMSVGAR3STATE, *PVMSVGAR3STATE;
167#endif /* IN_RING3 */
168
169
170/*********************************************************************************************************************************
171* Internal Functions *
172*********************************************************************************************************************************/
173#ifdef IN_RING3
174# ifdef DEBUG_FIFO_ACCESS
175static FNPGMPHYSHANDLER vmsvgaR3FIFOAccessHandler;
176# endif
177# ifdef DEBUG_GMR_ACCESS
178static FNPGMPHYSHANDLER vmsvgaR3GMRAccessHandler;
179# endif
180#endif
181
182
183/*********************************************************************************************************************************
184* Global Variables *
185*********************************************************************************************************************************/
186#ifdef IN_RING3
187
188/**
189 * SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
190 */
191static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
192{
193 SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
194 SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
195 SSMFIELD_ENTRY_TERM()
196};
197
198/**
199 * SSM descriptor table for the GMR structure.
200 */
201static SSMFIELD const g_aGMRFields[] =
202{
203 SSMFIELD_ENTRY( GMR, cMaxPages),
204 SSMFIELD_ENTRY( GMR, cbTotal),
205 SSMFIELD_ENTRY( GMR, numDescriptors),
206 SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
207 SSMFIELD_ENTRY_TERM()
208};
209
210/**
211 * SSM descriptor table for the VMSVGAR3STATE structure.
212 */
213static SSMFIELD const g_aVMSVGAR3STATEFields[] =
214{
215 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, aGMR),
216 SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
217 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
218 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
219 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
220 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
221 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
222 SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
223 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
224 SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
225 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
226#ifdef VMSVGA_USE_EMT_HALT_CODE
227 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
228#else
229 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
230#endif
231 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
232 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdPresent),
233 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDrawPrimitive),
234 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdSurfaceDMA),
235 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
236 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
237 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
238 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
239 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
240 SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
241 SSMFIELD_ENTRY_TERM()
242};
243
244/**
245 * SSM descriptor table for the VGAState.svga structure.
246 */
247static SSMFIELD const g_aVGAStateSVGAFields[] =
248{
249 SSMFIELD_ENTRY_IGNORE( VMSVGAState, u64HostWindowId),
250 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),
251 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),
252 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSvgaR3State),
253 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),
254 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFrameBufferBackup),
255 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pvFIFOExtCmdParam),
256 SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
257 SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
258 SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
259 SSMFIELD_ENTRY( VMSVGAState, fEnabled),
260 SSMFIELD_ENTRY( VMSVGAState, fConfigured),
261 SSMFIELD_ENTRY( VMSVGAState, fBusy),
262 SSMFIELD_ENTRY( VMSVGAState, fTraces),
263 SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
264 SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
265 SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
266 SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
267 SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
268 SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
269 SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
270 SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
271 SSMFIELD_ENTRY_IGNORE( VMSVGAState, BasePort),
272 SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
273 SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
274 SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
275 SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
276 SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
277 SSMFIELD_ENTRY( VMSVGAState, uWidth),
278 SSMFIELD_ENTRY( VMSVGAState, uHeight),
279 SSMFIELD_ENTRY( VMSVGAState, uBpp),
280 SSMFIELD_ENTRY( VMSVGAState, cbScanline),
281 SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
282 SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
283 SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
284 SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
285 SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
286 SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
287 SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
288 SSMFIELD_ENTRY_TERM()
289};
290
291static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
292
293#endif /* IN_RING3 */
294
295
296#ifdef LOG_ENABLED
297/**
298 * Index register string name lookup
299 *
300 * @returns Index register string or "UNKNOWN"
301 * @param pThis VMSVGA State
302 */
303static const char *vmsvgaIndexToString(PVGASTATE pThis)
304{
305 switch (pThis->svga.u32IndexReg)
306 {
307 case SVGA_REG_ID:
308 return "SVGA_REG_ID";
309 case SVGA_REG_ENABLE:
310 return "SVGA_REG_ENABLE";
311 case SVGA_REG_WIDTH:
312 return "SVGA_REG_WIDTH";
313 case SVGA_REG_HEIGHT:
314 return "SVGA_REG_HEIGHT";
315 case SVGA_REG_MAX_WIDTH:
316 return "SVGA_REG_MAX_WIDTH";
317 case SVGA_REG_MAX_HEIGHT:
318 return "SVGA_REG_MAX_HEIGHT";
319 case SVGA_REG_DEPTH:
320 return "SVGA_REG_DEPTH";
321 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
322 return "SVGA_REG_BITS_PER_PIXEL";
323 case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
324 return "SVGA_REG_HOST_BITS_PER_PIXEL";
325 case SVGA_REG_PSEUDOCOLOR:
326 return "SVGA_REG_PSEUDOCOLOR";
327 case SVGA_REG_RED_MASK:
328 return "SVGA_REG_RED_MASK";
329 case SVGA_REG_GREEN_MASK:
330 return "SVGA_REG_GREEN_MASK";
331 case SVGA_REG_BLUE_MASK:
332 return "SVGA_REG_BLUE_MASK";
333 case SVGA_REG_BYTES_PER_LINE:
334 return "SVGA_REG_BYTES_PER_LINE";
335 case SVGA_REG_VRAM_SIZE: /* VRAM size */
336 return "SVGA_REG_VRAM_SIZE";
337 case SVGA_REG_FB_START: /* Frame buffer physical address. */
338 return "SVGA_REG_FB_START";
339 case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
340 return "SVGA_REG_FB_OFFSET";
341 case SVGA_REG_FB_SIZE: /* Frame buffer size */
342 return "SVGA_REG_FB_SIZE";
343 case SVGA_REG_CAPABILITIES:
344 return "SVGA_REG_CAPABILITIES";
345 case SVGA_REG_MEM_START: /* FIFO start */
346 return "SVGA_REG_MEM_START";
347 case SVGA_REG_MEM_SIZE: /* FIFO size */
348 return "SVGA_REG_MEM_SIZE";
349 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
350 return "SVGA_REG_CONFIG_DONE";
351 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
352 return "SVGA_REG_SYNC";
353 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
354 return "SVGA_REG_BUSY";
355 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
356 return "SVGA_REG_GUEST_ID";
357 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
358 return "SVGA_REG_SCRATCH_SIZE";
359 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
360 return "SVGA_REG_MEM_REGS";
361 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
362 return "SVGA_REG_PITCHLOCK";
363 case SVGA_REG_IRQMASK: /* Interrupt mask */
364 return "SVGA_REG_IRQMASK";
365 case SVGA_REG_GMR_ID:
366 return "SVGA_REG_GMR_ID";
367 case SVGA_REG_GMR_DESCRIPTOR:
368 return "SVGA_REG_GMR_DESCRIPTOR";
369 case SVGA_REG_GMR_MAX_IDS:
370 return "SVGA_REG_GMR_MAX_IDS";
371 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
372 return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
373 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
374 return "SVGA_REG_TRACES";
375 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
376 return "SVGA_REG_GMRS_MAX_PAGES";
377 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
378 return "SVGA_REG_MEMORY_SIZE";
379 case SVGA_REG_TOP: /* Must be 1 more than the last register */
380 return "SVGA_REG_TOP";
381 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
382 return "SVGA_PALETTE_BASE";
383 case SVGA_REG_CURSOR_ID:
384 return "SVGA_REG_CURSOR_ID";
385 case SVGA_REG_CURSOR_X:
386 return "SVGA_REG_CURSOR_X";
387 case SVGA_REG_CURSOR_Y:
388 return "SVGA_REG_CURSOR_Y";
389 case SVGA_REG_CURSOR_ON:
390 return "SVGA_REG_CURSOR_ON";
391 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
392 return "SVGA_REG_NUM_GUEST_DISPLAYS";
393 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
394 return "SVGA_REG_DISPLAY_ID";
395 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
396 return "SVGA_REG_DISPLAY_IS_PRIMARY";
397 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
398 return "SVGA_REG_DISPLAY_POSITION_X";
399 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
400 return "SVGA_REG_DISPLAY_POSITION_Y";
401 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
402 return "SVGA_REG_DISPLAY_WIDTH";
403 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
404 return "SVGA_REG_DISPLAY_HEIGHT";
405 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
406 return "SVGA_REG_NUM_DISPLAYS";
407
408 default:
409 if (pThis->svga.u32IndexReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
410 return "SVGA_SCRATCH_BASE reg";
411 if (pThis->svga.u32IndexReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
412 return "SVGA_PALETTE_BASE reg";
413 return "UNKNOWN";
414 }
415}
416
417/**
418 * FIFO command name lookup
419 *
420 * @returns FIFO command string or "UNKNOWN"
421 * @param u32Cmd FIFO command
422 */
423static const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
424{
425 switch (u32Cmd)
426 {
427 case SVGA_CMD_INVALID_CMD:
428 return "SVGA_CMD_INVALID_CMD";
429 case SVGA_CMD_UPDATE:
430 return "SVGA_CMD_UPDATE";
431 case SVGA_CMD_RECT_COPY:
432 return "SVGA_CMD_RECT_COPY";
433 case SVGA_CMD_DEFINE_CURSOR:
434 return "SVGA_CMD_DEFINE_CURSOR";
435 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
436 return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
437 case SVGA_CMD_UPDATE_VERBOSE:
438 return "SVGA_CMD_UPDATE_VERBOSE";
439 case SVGA_CMD_FRONT_ROP_FILL:
440 return "SVGA_CMD_FRONT_ROP_FILL";
441 case SVGA_CMD_FENCE:
442 return "SVGA_CMD_FENCE";
443 case SVGA_CMD_ESCAPE:
444 return "SVGA_CMD_ESCAPE";
445 case SVGA_CMD_DEFINE_SCREEN:
446 return "SVGA_CMD_DEFINE_SCREEN";
447 case SVGA_CMD_DESTROY_SCREEN:
448 return "SVGA_CMD_DESTROY_SCREEN";
449 case SVGA_CMD_DEFINE_GMRFB:
450 return "SVGA_CMD_DEFINE_GMRFB";
451 case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
452 return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
453 case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
454 return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
455 case SVGA_CMD_ANNOTATION_FILL:
456 return "SVGA_CMD_ANNOTATION_FILL";
457 case SVGA_CMD_ANNOTATION_COPY:
458 return "SVGA_CMD_ANNOTATION_COPY";
459 case SVGA_CMD_DEFINE_GMR2:
460 return "SVGA_CMD_DEFINE_GMR2";
461 case SVGA_CMD_REMAP_GMR2:
462 return "SVGA_CMD_REMAP_GMR2";
463 case SVGA_3D_CMD_SURFACE_DEFINE:
464 return "SVGA_3D_CMD_SURFACE_DEFINE";
465 case SVGA_3D_CMD_SURFACE_DESTROY:
466 return "SVGA_3D_CMD_SURFACE_DESTROY";
467 case SVGA_3D_CMD_SURFACE_COPY:
468 return "SVGA_3D_CMD_SURFACE_COPY";
469 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
470 return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
471 case SVGA_3D_CMD_SURFACE_DMA:
472 return "SVGA_3D_CMD_SURFACE_DMA";
473 case SVGA_3D_CMD_CONTEXT_DEFINE:
474 return "SVGA_3D_CMD_CONTEXT_DEFINE";
475 case SVGA_3D_CMD_CONTEXT_DESTROY:
476 return "SVGA_3D_CMD_CONTEXT_DESTROY";
477 case SVGA_3D_CMD_SETTRANSFORM:
478 return "SVGA_3D_CMD_SETTRANSFORM";
479 case SVGA_3D_CMD_SETZRANGE:
480 return "SVGA_3D_CMD_SETZRANGE";
481 case SVGA_3D_CMD_SETRENDERSTATE:
482 return "SVGA_3D_CMD_SETRENDERSTATE";
483 case SVGA_3D_CMD_SETRENDERTARGET:
484 return "SVGA_3D_CMD_SETRENDERTARGET";
485 case SVGA_3D_CMD_SETTEXTURESTATE:
486 return "SVGA_3D_CMD_SETTEXTURESTATE";
487 case SVGA_3D_CMD_SETMATERIAL:
488 return "SVGA_3D_CMD_SETMATERIAL";
489 case SVGA_3D_CMD_SETLIGHTDATA:
490 return "SVGA_3D_CMD_SETLIGHTDATA";
491 case SVGA_3D_CMD_SETLIGHTENABLED:
492 return "SVGA_3D_CMD_SETLIGHTENABLED";
493 case SVGA_3D_CMD_SETVIEWPORT:
494 return "SVGA_3D_CMD_SETVIEWPORT";
495 case SVGA_3D_CMD_SETCLIPPLANE:
496 return "SVGA_3D_CMD_SETCLIPPLANE";
497 case SVGA_3D_CMD_CLEAR:
498 return "SVGA_3D_CMD_CLEAR";
499 case SVGA_3D_CMD_PRESENT:
500 return "SVGA_3D_CMD_PRESENT";
501 case SVGA_3D_CMD_SHADER_DEFINE:
502 return "SVGA_3D_CMD_SHADER_DEFINE";
503 case SVGA_3D_CMD_SHADER_DESTROY:
504 return "SVGA_3D_CMD_SHADER_DESTROY";
505 case SVGA_3D_CMD_SET_SHADER:
506 return "SVGA_3D_CMD_SET_SHADER";
507 case SVGA_3D_CMD_SET_SHADER_CONST:
508 return "SVGA_3D_CMD_SET_SHADER_CONST";
509 case SVGA_3D_CMD_DRAW_PRIMITIVES:
510 return "SVGA_3D_CMD_DRAW_PRIMITIVES";
511 case SVGA_3D_CMD_SETSCISSORRECT:
512 return "SVGA_3D_CMD_SETSCISSORRECT";
513 case SVGA_3D_CMD_BEGIN_QUERY:
514 return "SVGA_3D_CMD_BEGIN_QUERY";
515 case SVGA_3D_CMD_END_QUERY:
516 return "SVGA_3D_CMD_END_QUERY";
517 case SVGA_3D_CMD_WAIT_FOR_QUERY:
518 return "SVGA_3D_CMD_WAIT_FOR_QUERY";
519 case SVGA_3D_CMD_PRESENT_READBACK:
520 return "SVGA_3D_CMD_PRESENT_READBACK";
521 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
522 return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
523 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
524 return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
525 case SVGA_3D_CMD_GENERATE_MIPMAPS:
526 return "SVGA_3D_CMD_GENERATE_MIPMAPS";
527 case SVGA_3D_CMD_ACTIVATE_SURFACE:
528 return "SVGA_3D_CMD_ACTIVATE_SURFACE";
529 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
530 return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
531 default:
532 return "UNKNOWN";
533 }
534}
535#endif
536
537/**
538 * @interface_method_impl{PDMIDISPLAYPORT::pfnSetViewport}
539 */
540DECLCALLBACK(void) vmsvgaPortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t uScreenId, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
541{
542 PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
543
544 Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", uScreenId, x, y, cx, cy));
545
546 if (x < pThis->svga.uWidth)
547 {
548 pThis->svga.viewport.x = x;
549 pThis->svga.viewport.cx = RT_MIN(cx, pThis->svga.uWidth - x);
550 pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
551 }
552 else
553 {
554 pThis->svga.viewport.x = pThis->svga.uWidth;
555 pThis->svga.viewport.cx = 0;
556 pThis->svga.viewport.xRight = pThis->svga.uWidth;
557 }
558 if (y < pThis->svga.uHeight)
559 {
560 pThis->svga.viewport.y = y;
561 pThis->svga.viewport.cy = RT_MIN(cy, pThis->svga.uHeight - y);
562 pThis->svga.viewport.yBottom = y + pThis->svga.viewport.cy;
563 }
564 else
565 {
566 pThis->svga.viewport.y = pThis->svga.uHeight;
567 pThis->svga.viewport.cy = 0;
568 pThis->svga.viewport.yBottom = y + pThis->svga.uHeight;
569 }
570}
571
572/**
573 * Read port register
574 *
575 * @returns VBox status code.
576 * @param pThis VMSVGA State
577 * @param pu32 Where to store the read value
578 */
579PDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)
580{
581 int rc = VINF_SUCCESS;
582
583 *pu32 = 0;
584 switch (pThis->svga.u32IndexReg)
585 {
586 case SVGA_REG_ID:
587 *pu32 = pThis->svga.u32SVGAId;
588 break;
589
590 case SVGA_REG_ENABLE:
591 *pu32 = pThis->svga.fEnabled;
592 break;
593
594 case SVGA_REG_WIDTH:
595 {
596 if ( pThis->svga.fEnabled
597 && pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
598 {
599 *pu32 = pThis->svga.uWidth;
600 }
601 else
602 {
603#ifndef IN_RING3
604 rc = VINF_IOM_R3_IOPORT_READ;
605#else
606 *pu32 = pThis->pDrv->cx;
607#endif
608 }
609 break;
610 }
611
612 case SVGA_REG_HEIGHT:
613 {
614 if ( pThis->svga.fEnabled
615 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
616 {
617 *pu32 = pThis->svga.uHeight;
618 }
619 else
620 {
621#ifndef IN_RING3
622 rc = VINF_IOM_R3_IOPORT_READ;
623#else
624 *pu32 = pThis->pDrv->cy;
625#endif
626 }
627 break;
628 }
629
630 case SVGA_REG_MAX_WIDTH:
631 *pu32 = pThis->svga.u32MaxWidth;
632 break;
633
634 case SVGA_REG_MAX_HEIGHT:
635 *pu32 = pThis->svga.u32MaxHeight;
636 break;
637
638 case SVGA_REG_DEPTH:
639 /* This returns the color depth of the current mode. */
640 switch (pThis->svga.uBpp)
641 {
642 case 15:
643 case 16:
644 case 24:
645 *pu32 = pThis->svga.uBpp;
646 break;
647
648 default:
649 case 32:
650 *pu32 = 24; /* The upper 8 bits are either alpha bits or not used. */
651 break;
652 }
653 break;
654
655 case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
656 if ( pThis->svga.fEnabled
657 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
658 {
659 *pu32 = pThis->svga.uBpp;
660 }
661 else
662 {
663#ifndef IN_RING3
664 rc = VINF_IOM_R3_IOPORT_READ;
665#else
666 *pu32 = pThis->pDrv->cBits;
667#endif
668 }
669 break;
670
671 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
672 if ( pThis->svga.fEnabled
673 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
674 {
675 *pu32 = (pThis->svga.uBpp + 7) & ~7;
676 }
677 else
678 {
679#ifndef IN_RING3
680 rc = VINF_IOM_R3_IOPORT_READ;
681#else
682 *pu32 = (pThis->pDrv->cBits + 7) & ~7;
683#endif
684 }
685 break;
686
687 case SVGA_REG_PSEUDOCOLOR:
688 *pu32 = 0;
689 break;
690
691 case SVGA_REG_RED_MASK:
692 case SVGA_REG_GREEN_MASK:
693 case SVGA_REG_BLUE_MASK:
694 {
695 uint32_t uBpp;
696
697 if ( pThis->svga.fEnabled
698 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
699 {
700 uBpp = pThis->svga.uBpp;
701 }
702 else
703 {
704#ifndef IN_RING3
705 rc = VINF_IOM_R3_IOPORT_READ;
706 break;
707#else
708 uBpp = pThis->pDrv->cBits;
709#endif
710 }
711 uint32_t u32RedMask, u32GreenMask, u32BlueMask;
712 switch (uBpp)
713 {
714 case 8:
715 u32RedMask = 0x07;
716 u32GreenMask = 0x38;
717 u32BlueMask = 0xc0;
718 break;
719
720 case 15:
721 u32RedMask = 0x0000001f;
722 u32GreenMask = 0x000003e0;
723 u32BlueMask = 0x00007c00;
724 break;
725
726 case 16:
727 u32RedMask = 0x0000001f;
728 u32GreenMask = 0x000007e0;
729 u32BlueMask = 0x0000f800;
730 break;
731
732 case 24:
733 case 32:
734 default:
735 u32RedMask = 0x00ff0000;
736 u32GreenMask = 0x0000ff00;
737 u32BlueMask = 0x000000ff;
738 break;
739 }
740 switch (pThis->svga.u32IndexReg)
741 {
742 case SVGA_REG_RED_MASK:
743 *pu32 = u32RedMask;
744 break;
745
746 case SVGA_REG_GREEN_MASK:
747 *pu32 = u32GreenMask;
748 break;
749
750 case SVGA_REG_BLUE_MASK:
751 *pu32 = u32BlueMask;
752 break;
753 }
754 break;
755 }
756
757 case SVGA_REG_BYTES_PER_LINE:
758 {
759 if ( pThis->svga.fEnabled
760 && pThis->svga.cbScanline)
761 {
762 *pu32 = pThis->svga.cbScanline;
763 }
764 else
765 {
766#ifndef IN_RING3
767 rc = VINF_IOM_R3_IOPORT_READ;
768#else
769 *pu32 = pThis->pDrv->cbScanline;
770#endif
771 }
772 break;
773 }
774
775 case SVGA_REG_VRAM_SIZE: /* VRAM size */
776 *pu32 = pThis->vram_size;
777 break;
778
779 case SVGA_REG_FB_START: /* Frame buffer physical address. */
780 Assert(pThis->GCPhysVRAM <= 0xffffffff);
781 *pu32 = pThis->GCPhysVRAM;
782 break;
783
784 case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
785 /* Always zero in our case. */
786 *pu32 = 0;
787 break;
788
789 case SVGA_REG_FB_SIZE: /* Frame buffer size */
790 {
791#ifndef IN_RING3
792 rc = VINF_IOM_R3_IOPORT_READ;
793#else
794 /* VMWare testcases want at least 4 MB in case the hardware is disabled. */
795 if ( pThis->svga.fEnabled
796 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
797 {
798 /* Hardware enabled; return real framebuffer size .*/
799 *pu32 = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
800 }
801 else
802 *pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy * pThis->pDrv->cbScanline);
803
804 *pu32 = RT_MIN(pThis->vram_size, *pu32);
805 Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
806#endif
807 break;
808 }
809
810 case SVGA_REG_CAPABILITIES:
811 *pu32 = pThis->svga.u32RegCaps;
812 break;
813
814 case SVGA_REG_MEM_START: /* FIFO start */
815 Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
816 *pu32 = pThis->svga.GCPhysFIFO;
817 break;
818
819 case SVGA_REG_MEM_SIZE: /* FIFO size */
820 *pu32 = pThis->svga.cbFIFO;
821 break;
822
823 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
824 *pu32 = pThis->svga.fConfigured;
825 break;
826
827 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
828 *pu32 = 0;
829 break;
830
831 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
832 if (pThis->svga.fBusy)
833 {
834#ifndef IN_RING3
835 /* Go to ring-3 and halt the CPU. */
836 rc = VINF_IOM_R3_IOPORT_READ;
837 break;
838#elif defined(VMSVGA_USE_EMT_HALT_CODE)
839 /* The guest is basically doing a HLT via the device here, but with
840 a special wake up condition on FIFO completion. */
841 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
842 STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
843 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
844 VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
845 VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
846 ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
847 if (pThis->svga.fBusy)
848 rc = VMR3WaitForDeviceReady(pVM, idCpu);
849 ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
850 VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
851#else
852
853 /* Delay the EMT a bit so the FIFO and others can get some work done.
854 This used to be a crude 50 ms sleep. The current code tries to be
855 more efficient, but the consept is still very crude. */
856 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
857 STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
858 RTThreadYield();
859 if (pThis->svga.fBusy)
860 {
861 uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
862
863 if (pThis->svga.fBusy && cRefs == 1)
864 RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
865 if (pThis->svga.fBusy)
866 {
867 /** @todo If this code is going to stay, we need to call into the halt/wait
868 * code in VMEmt.cpp here, otherwise all kind of EMT interaction will
869 * suffer when the guest is polling on a busy FIFO. */
870 uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
871 if (cNsMaxWait >= RT_NS_100US)
872 RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
873 RTSEMWAIT_FLAGS_NANOSECS | RTSEMWAIT_FLAGS_RELATIVE | RTSEMWAIT_FLAGS_NORESUME,
874 RT_MIN(cNsMaxWait, RT_NS_10MS));
875 }
876
877 ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
878 }
879 STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
880#endif
881 *pu32 = pThis->svga.fBusy != 0;
882 }
883 else
884 *pu32 = false;
885 break;
886
887 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
888 *pu32 = pThis->svga.u32GuestId;
889 break;
890
891 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
892 *pu32 = pThis->svga.cScratchRegion;
893 break;
894
895 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
896 *pu32 = SVGA_FIFO_NUM_REGS;
897 break;
898
899 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
900 *pu32 = pThis->svga.u32PitchLock;
901 break;
902
903 case SVGA_REG_IRQMASK: /* Interrupt mask */
904 *pu32 = pThis->svga.u32IrqMask;
905 break;
906
907 /* See "Guest memory regions" below. */
908 case SVGA_REG_GMR_ID:
909 *pu32 = pThis->svga.u32CurrentGMRId;
910 break;
911
912 case SVGA_REG_GMR_DESCRIPTOR:
913 /* Write only */
914 *pu32 = 0;
915 break;
916
917 case SVGA_REG_GMR_MAX_IDS:
918 *pu32 = VMSVGA_MAX_GMR_IDS;
919 break;
920
921 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
922 *pu32 = VMSVGA_MAX_GMR_PAGES;
923 break;
924
925 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
926 *pu32 = pThis->svga.fTraces;
927 break;
928
929 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
930 *pu32 = VMSVGA_MAX_GMR_PAGES;
931 break;
932
933 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
934 *pu32 = VMSVGA_SURFACE_SIZE;
935 break;
936
937 case SVGA_REG_TOP: /* Must be 1 more than the last register */
938 break;
939
940 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
941 break;
942 /* Next 768 (== 256*3) registers exist for colormap */
943
944 /* Mouse cursor support. */
945 case SVGA_REG_CURSOR_ID:
946 case SVGA_REG_CURSOR_X:
947 case SVGA_REG_CURSOR_Y:
948 case SVGA_REG_CURSOR_ON:
949 break;
950
951 /* Legacy multi-monitor support */
952 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
953 *pu32 = 1;
954 break;
955
956 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
957 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
958 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
959 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
960 *pu32 = 0;
961 break;
962
963 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
964 *pu32 = pThis->svga.uWidth;
965 break;
966
967 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
968 *pu32 = pThis->svga.uHeight;
969 break;
970
971 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
972 *pu32 = 1; /* Must return something sensible here otherwise the Linux driver will take a legacy code path without 3d support. */
973 break;
974
975 default:
976 if ( pThis->svga.u32IndexReg >= SVGA_SCRATCH_BASE
977 && pThis->svga.u32IndexReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion)
978 {
979 *pu32 = pThis->svga.au32ScratchRegion[pThis->svga.u32IndexReg - SVGA_SCRATCH_BASE];
980 }
981 break;
982 }
983 Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, *pu32, rc));
984 return rc;
985}
986
987#ifdef IN_RING3
988/**
989 * Apply the current resolution settings to change the video mode.
990 *
991 * @returns VBox status code.
992 * @param pThis VMSVGA State
993 */
994int vmsvgaChangeMode(PVGASTATE pThis)
995{
996 int rc;
997
998 if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
999 || pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1000 || pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1001 {
1002 /* Mode change in progress; wait for all values to be set. */
1003 Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1004 return VINF_SUCCESS;
1005 }
1006
1007 if ( pThis->svga.uWidth == 0
1008 || pThis->svga.uHeight == 0
1009 || pThis->svga.uBpp == 0)
1010 {
1011 /* Invalid mode change - BB does this early in the boot up. */
1012 Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1013 return VINF_SUCCESS;
1014 }
1015
1016 if ( pThis->last_bpp == (unsigned)pThis->svga.uBpp
1017 && pThis->last_scr_width == (unsigned)pThis->svga.uWidth
1018 && pThis->last_scr_height == (unsigned)pThis->svga.uHeight
1019 && pThis->last_width == (unsigned)pThis->svga.uWidth
1020 && pThis->last_height == (unsigned)pThis->svga.uHeight
1021 )
1022 {
1023 /* Nothing to do. */
1024 Log(("vmsvgaChangeMode: nothing changed; ignore\n"));
1025 return VINF_SUCCESS;
1026 }
1027
1028 Log(("vmsvgaChangeMode: sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
1029 pThis->svga.cbScanline = ((pThis->svga.uWidth * pThis->svga.uBpp + 7) & ~7) / 8;
1030
1031 pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);
1032 rc = pThis->pDrv->pfnResize(pThis->pDrv, pThis->svga.uBpp, pThis->CTX_SUFF(vram_ptr), pThis->svga.cbScanline, pThis->svga.uWidth, pThis->svga.uHeight);
1033 AssertRC(rc);
1034 AssertReturn(rc == VINF_SUCCESS || rc == VINF_VGA_RESIZE_IN_PROGRESS, rc);
1035
1036 /* last stuff */
1037 pThis->last_bpp = pThis->svga.uBpp;
1038 pThis->last_scr_width = pThis->svga.uWidth;
1039 pThis->last_scr_height = pThis->svga.uHeight;
1040 pThis->last_width = pThis->svga.uWidth;
1041 pThis->last_height = pThis->svga.uHeight;
1042
1043 ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1044
1045 /* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1046 if ( pThis->svga.viewport.cx == 0
1047 && pThis->svga.viewport.cy == 0)
1048 {
1049 pThis->svga.viewport.cx = pThis->svga.viewport.xRight = pThis->svga.uWidth;
1050 pThis->svga.viewport.cy = pThis->svga.viewport.yBottom = pThis->svga.uHeight;
1051 }
1052 return VINF_SUCCESS;
1053}
1054#endif /* IN_RING3 */
1055
1056#if defined(IN_RING0) || defined(IN_RING3)
1057/**
1058 * Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1059 *
1060 * @param pThis The VMSVGA state.
1061 * @param fState The busy state.
1062 */
1063DECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
1064{
1065 ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
1066
1067 if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1068 {
1069 /* Race / unfortunately scheduling. Highly unlikly. */
1070 uint32_t cLoops = 64;
1071 do
1072 {
1073 ASMNopPause();
1074 fState = (pThis->svga.fBusy != 0);
1075 ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
1076 } while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1077 }
1078}
1079#endif
1080
1081/**
1082 * Write port register
1083 *
1084 * @returns VBox status code.
1085 * @param pThis VMSVGA State
1086 * @param u32 Value to write
1087 */
1088PDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
1089{
1090#ifdef IN_RING3
1091 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1092#endif
1093 int rc = VINF_SUCCESS;
1094
1095 Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, u32));
1096 switch (pThis->svga.u32IndexReg)
1097 {
1098 case SVGA_REG_ID:
1099 if ( u32 == SVGA_ID_0
1100 || u32 == SVGA_ID_1
1101 || u32 == SVGA_ID_2)
1102 pThis->svga.u32SVGAId = u32;
1103 break;
1104
1105 case SVGA_REG_ENABLE:
1106 if ( pThis->svga.fEnabled == u32
1107 && pThis->last_bpp == (unsigned)pThis->svga.uBpp
1108 && pThis->last_scr_width == (unsigned)pThis->svga.uWidth
1109 && pThis->last_scr_height == (unsigned)pThis->svga.uHeight
1110 && pThis->last_width == (unsigned)pThis->svga.uWidth
1111 && pThis->last_height == (unsigned)pThis->svga.uHeight
1112 )
1113 /* Nothing to do. */
1114 break;
1115
1116#ifdef IN_RING3
1117 if ( u32 == 1
1118 && pThis->svga.fEnabled == false)
1119 {
1120 /* Make a backup copy of the first 32k in order to save font data etc. */
1121 memcpy(pThis->svga.pFrameBufferBackup, pThis->vram_ptrR3, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
1122 }
1123
1124 pThis->svga.fEnabled = u32;
1125 if (pThis->svga.fEnabled)
1126 {
1127 if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1128 && pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1129 && pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1130 {
1131 /* Keep the current mode. */
1132 pThis->svga.uWidth = pThis->pDrv->cx;
1133 pThis->svga.uHeight = pThis->pDrv->cy;
1134 pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;
1135 }
1136
1137 if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1138 && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1139 && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1140 {
1141 rc = vmsvgaChangeMode(pThis);
1142 AssertRCReturn(rc, rc);
1143 }
1144 Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
1145 uint32_t *pFIFO = pThis->svga.pFIFOR3;
1146 Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1147
1148 /* Disable or enable dirty page tracking according to the current fTraces value. */
1149 vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1150 }
1151 else
1152 {
1153 /* Restore the text mode backup. */
1154 memcpy(pThis->vram_ptrR3, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
1155
1156/* pThis->svga.uHeight = -1;
1157 pThis->svga.uWidth = -1;
1158 pThis->svga.uBpp = -1;
1159 pThis->svga.cbScanline = 0; */
1160 pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);
1161
1162 /* Enable dirty page tracking again when going into legacy mode. */
1163 vmsvgaSetTraces(pThis, true);
1164 }
1165#else
1166 rc = VINF_IOM_R3_IOPORT_WRITE;
1167#endif
1168 break;
1169
1170 case SVGA_REG_WIDTH:
1171 if (pThis->svga.uWidth != u32)
1172 {
1173 if (pThis->svga.fEnabled)
1174 {
1175#ifdef IN_RING3
1176 pThis->svga.uWidth = u32;
1177 rc = vmsvgaChangeMode(pThis);
1178 AssertRCReturn(rc, rc);
1179#else
1180 rc = VINF_IOM_R3_IOPORT_WRITE;
1181#endif
1182 }
1183 else
1184 pThis->svga.uWidth = u32;
1185 }
1186 /* else: nop */
1187 break;
1188
1189 case SVGA_REG_HEIGHT:
1190 if (pThis->svga.uHeight != u32)
1191 {
1192 if (pThis->svga.fEnabled)
1193 {
1194#ifdef IN_RING3
1195 pThis->svga.uHeight = u32;
1196 rc = vmsvgaChangeMode(pThis);
1197 AssertRCReturn(rc, rc);
1198#else
1199 rc = VINF_IOM_R3_IOPORT_WRITE;
1200#endif
1201 }
1202 else
1203 pThis->svga.uHeight = u32;
1204 }
1205 /* else: nop */
1206 break;
1207
1208 case SVGA_REG_DEPTH:
1209 /** @todo read-only?? */
1210 break;
1211
1212 case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1213 if (pThis->svga.uBpp != u32)
1214 {
1215 if (pThis->svga.fEnabled)
1216 {
1217#ifdef IN_RING3
1218 pThis->svga.uBpp = u32;
1219 rc = vmsvgaChangeMode(pThis);
1220 AssertRCReturn(rc, rc);
1221#else
1222 rc = VINF_IOM_R3_IOPORT_WRITE;
1223#endif
1224 }
1225 else
1226 pThis->svga.uBpp = u32;
1227 }
1228 /* else: nop */
1229 break;
1230
1231 case SVGA_REG_PSEUDOCOLOR:
1232 break;
1233
1234 case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1235#ifdef IN_RING3
1236 pThis->svga.fConfigured = u32;
1237 /* Disabling the FIFO enables tracing (dirty page detection) by default. */
1238 if (!pThis->svga.fConfigured)
1239 {
1240 pThis->svga.fTraces = true;
1241 }
1242 vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);
1243#else
1244 rc = VINF_IOM_R3_IOPORT_WRITE;
1245#endif
1246 break;
1247
1248 case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1249 if ( pThis->svga.fEnabled
1250 && pThis->svga.fConfigured)
1251 {
1252#if defined(IN_RING3) || defined(IN_RING0)
1253 Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
1254 ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE | VMSVGA_BUSY_F_FIFO);
1255 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
1256 vmsvgaSafeFifoBusyRegUpdate(pThis, true);
1257
1258 /* Kick the FIFO thread to start processing commands again. */
1259 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
1260#else
1261 rc = VINF_IOM_R3_IOPORT_WRITE;
1262#endif
1263 }
1264 /* else nothing to do. */
1265 else
1266 Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1267
1268 break;
1269
1270 case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1271 break;
1272
1273 case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1274 pThis->svga.u32GuestId = u32;
1275 break;
1276
1277 case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1278 pThis->svga.u32PitchLock = u32;
1279 break;
1280
1281 case SVGA_REG_IRQMASK: /* Interrupt mask */
1282 pThis->svga.u32IrqMask = u32;
1283
1284 /* Irq pending after the above change? */
1285 if (pThis->svga.u32IrqStatus & u32)
1286 {
1287 Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1288 PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
1289 }
1290 else
1291 PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
1292 break;
1293
1294 /* Mouse cursor support */
1295 case SVGA_REG_CURSOR_ID:
1296 case SVGA_REG_CURSOR_X:
1297 case SVGA_REG_CURSOR_Y:
1298 case SVGA_REG_CURSOR_ON:
1299 break;
1300
1301 /* Legacy multi-monitor support */
1302 case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1303 break;
1304 case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1305 break;
1306 case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1307 break;
1308 case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1309 break;
1310 case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1311 break;
1312 case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1313 break;
1314 case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1315 break;
1316#ifdef VBOX_WITH_VMSVGA3D
1317 /* See "Guest memory regions" below. */
1318 case SVGA_REG_GMR_ID:
1319 pThis->svga.u32CurrentGMRId = u32;
1320 break;
1321
1322 case SVGA_REG_GMR_DESCRIPTOR:
1323# ifndef IN_RING3
1324 rc = VINF_IOM_R3_IOPORT_WRITE;
1325 break;
1326# else /* IN_RING3 */
1327 {
1328 SVGAGuestMemDescriptor desc;
1329 RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1330 RTGCPHYS GCPhysBase = GCPhys;
1331 uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1332 uint32_t cDescriptorsAllocated = 16;
1333 uint32_t iDescriptor = 0;
1334
1335 /* Validate current GMR id. */
1336 AssertBreak(idGMR < VMSVGA_MAX_GMR_IDS);
1337
1338 /* Free the old GMR if present. */
1339 vmsvgaGMRFree(pThis, idGMR);
1340
1341 /* Just undefine the GMR? */
1342 if (GCPhys == 0)
1343 break;
1344
1345 pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));
1346 AssertReturn(pSVGAState->aGMR[idGMR].paDesc, VERR_NO_MEMORY);
1347
1348 /* Never cross a page boundary automatically. */
1349 while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1350 {
1351 /* Read descriptor. */
1352 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
1353 AssertRCBreak(rc);
1354
1355 if ( desc.ppn == 0
1356 && desc.numPages == 0)
1357 break; /* terminator */
1358
1359 if ( desc.ppn != 0
1360 && desc.numPages == 0)
1361 {
1362 /* Pointer to the next physical page of descriptors. */
1363 GCPhys = GCPhysBase = desc.ppn << PAGE_SHIFT;
1364 }
1365 else
1366 {
1367 if (iDescriptor == cDescriptorsAllocated)
1368 {
1369 cDescriptorsAllocated += 16;
1370 pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemRealloc(pSVGAState->aGMR[idGMR].paDesc, cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));
1371 AssertReturn(pSVGAState->aGMR[idGMR].paDesc, VERR_NO_MEMORY);
1372 }
1373
1374 pSVGAState->aGMR[idGMR].paDesc[iDescriptor].GCPhys = desc.ppn << PAGE_SHIFT;
1375 pSVGAState->aGMR[idGMR].paDesc[iDescriptor++].numPages = desc.numPages;
1376 pSVGAState->aGMR[idGMR].cbTotal += desc.numPages * PAGE_SIZE;
1377
1378 /* Continue with the next descriptor. */
1379 GCPhys += sizeof(desc);
1380 }
1381 }
1382 pSVGAState->aGMR[idGMR].numDescriptors = iDescriptor;
1383 Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x\n", idGMR, iDescriptor, pSVGAState->aGMR[idGMR].cbTotal));
1384
1385 if (!pSVGAState->aGMR[idGMR].numDescriptors)
1386 {
1387 AssertFailed();
1388 RTMemFree(pSVGAState->aGMR[idGMR].paDesc);
1389 pSVGAState->aGMR[idGMR].paDesc = NULL;
1390 }
1391 AssertRC(rc);
1392 break;
1393 }
1394# endif /* IN_RING3 */
1395#endif // VBOX_WITH_VMSVGA3D
1396
1397 case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1398 if (pThis->svga.fTraces == u32)
1399 break; /* nothing to do */
1400
1401#ifdef IN_RING3
1402 vmsvgaSetTraces(pThis, !!u32);
1403#else
1404 rc = VINF_IOM_R3_IOPORT_WRITE;
1405#endif
1406 break;
1407
1408 case SVGA_REG_TOP: /* Must be 1 more than the last register */
1409 break;
1410
1411 case SVGA_PALETTE_BASE: /* Base of SVGA color map */
1412 break;
1413 /* Next 768 (== 256*3) registers exist for colormap */
1414
1415 case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1416 Log(("Write to deprecated register %x - val %x ignored\n", pThis->svga.u32IndexReg, u32));
1417 break;
1418
1419 case SVGA_REG_FB_START:
1420 case SVGA_REG_MEM_START:
1421 case SVGA_REG_HOST_BITS_PER_PIXEL:
1422 case SVGA_REG_MAX_WIDTH:
1423 case SVGA_REG_MAX_HEIGHT:
1424 case SVGA_REG_VRAM_SIZE:
1425 case SVGA_REG_FB_SIZE:
1426 case SVGA_REG_CAPABILITIES:
1427 case SVGA_REG_MEM_SIZE:
1428 case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1429 case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1430 case SVGA_REG_BYTES_PER_LINE:
1431 case SVGA_REG_FB_OFFSET:
1432 case SVGA_REG_RED_MASK:
1433 case SVGA_REG_GREEN_MASK:
1434 case SVGA_REG_BLUE_MASK:
1435 case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1436 case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1437 case SVGA_REG_GMR_MAX_IDS:
1438 case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1439 /* Read only - ignore. */
1440 Log(("Write to R/O register %x - val %x ignored\n", pThis->svga.u32IndexReg, u32));
1441 break;
1442
1443 default:
1444 if ( pThis->svga.u32IndexReg >= SVGA_SCRATCH_BASE
1445 && pThis->svga.u32IndexReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion)
1446 {
1447 pThis->svga.au32ScratchRegion[pThis->svga.u32IndexReg - SVGA_SCRATCH_BASE] = u32;
1448 }
1449 break;
1450 }
1451 return rc;
1452}
1453
1454/**
1455 * Port I/O Handler for IN operations.
1456 *
1457 * @returns VINF_SUCCESS or VINF_EM_*.
1458 * @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
1459 *
1460 * @param pDevIns The device instance.
1461 * @param pvUser User argument.
1462 * @param uPort Port number used for the IN operation.
1463 * @param pu32 Where to store the result. This is always a 32-bit
1464 * variable regardless of what @a cb might say.
1465 * @param cb Number of bytes read.
1466 */
1467PDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1468{
1469 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1470 int rc = VINF_SUCCESS;
1471
1472 /* Ignore non-dword accesses. */
1473 if (cb != 4)
1474 {
1475 Log(("Ignoring non-dword read at %x cb=%d\n", Port, cb));
1476 *pu32 = ~0;
1477 return VINF_SUCCESS;
1478 }
1479
1480 switch (Port - pThis->svga.BasePort)
1481 {
1482 case SVGA_INDEX_PORT:
1483 *pu32 = pThis->svga.u32IndexReg;
1484 break;
1485
1486 case SVGA_VALUE_PORT:
1487 return vmsvgaReadPort(pThis, pu32);
1488
1489 case SVGA_BIOS_PORT:
1490 Log(("Ignoring BIOS port read\n"));
1491 *pu32 = 0;
1492 break;
1493
1494 case SVGA_IRQSTATUS_PORT:
1495 LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1496 *pu32 = pThis->svga.u32IrqStatus;
1497 break;
1498 }
1499 return rc;
1500}
1501
1502/**
1503 * Port I/O Handler for OUT operations.
1504 *
1505 * @returns VINF_SUCCESS or VINF_EM_*.
1506 *
1507 * @param pDevIns The device instance.
1508 * @param pvUser User argument.
1509 * @param uPort Port number used for the OUT operation.
1510 * @param u32 The value to output.
1511 * @param cb The value size in bytes.
1512 */
1513PDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1514{
1515 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1516 int rc = VINF_SUCCESS;
1517
1518 /* Ignore non-dword accesses. */
1519 if (cb != 4)
1520 {
1521 Log(("Ignoring non-dword write at %x val=%x cb=%d\n", Port, u32, cb));
1522 return VINF_SUCCESS;
1523 }
1524
1525 switch (Port - pThis->svga.BasePort)
1526 {
1527 case SVGA_INDEX_PORT:
1528 pThis->svga.u32IndexReg = u32;
1529 break;
1530
1531 case SVGA_VALUE_PORT:
1532 return vmsvgaWritePort(pThis, u32);
1533
1534 case SVGA_BIOS_PORT:
1535 Log(("Ignoring BIOS port write (val=%x)\n", u32));
1536 break;
1537
1538 case SVGA_IRQSTATUS_PORT:
1539 Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
1540 ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
1541 /* Clear the irq in case all events have been cleared. */
1542 if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
1543 {
1544 Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
1545 PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1546 }
1547 break;
1548 }
1549 return rc;
1550}
1551
1552#ifdef DEBUG_FIFO_ACCESS
1553
1554# ifdef IN_RING3
1555/**
1556 * Handle LFB access.
1557 * @returns VBox status code.
1558 * @param pVM VM handle.
1559 * @param pThis VGA device instance data.
1560 * @param GCPhys The access physical address.
1561 * @param fWriteAccess Read or write access
1562 */
1563static int vmsvgaFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
1564{
1565 RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
1566 uint32_t *pFIFO = pThis->svga.pFIFOR3;
1567
1568 switch (GCPhysOffset >> 2)
1569 {
1570 case SVGA_FIFO_MIN:
1571 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1572 break;
1573 case SVGA_FIFO_MAX:
1574 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1575 break;
1576 case SVGA_FIFO_NEXT_CMD:
1577 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1578 break;
1579 case SVGA_FIFO_STOP:
1580 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1581 break;
1582 case SVGA_FIFO_CAPABILITIES:
1583 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1584 break;
1585 case SVGA_FIFO_FLAGS:
1586 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1587 break;
1588 case SVGA_FIFO_FENCE:
1589 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1590 break;
1591 case SVGA_FIFO_3D_HWVERSION:
1592 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1593 break;
1594 case SVGA_FIFO_PITCHLOCK:
1595 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1596 break;
1597 case SVGA_FIFO_CURSOR_ON:
1598 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1599 break;
1600 case SVGA_FIFO_CURSOR_X:
1601 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1602 break;
1603 case SVGA_FIFO_CURSOR_Y:
1604 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1605 break;
1606 case SVGA_FIFO_CURSOR_COUNT:
1607 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1608 break;
1609 case SVGA_FIFO_CURSOR_LAST_UPDATED:
1610 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1611 break;
1612 case SVGA_FIFO_RESERVED:
1613 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1614 break;
1615 case SVGA_FIFO_CURSOR_SCREEN_ID:
1616 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1617 break;
1618 case SVGA_FIFO_DEAD:
1619 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1620 break;
1621 case SVGA_FIFO_3D_HWVERSION_REVISED:
1622 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1623 break;
1624 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
1625 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1626 break;
1627 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
1628 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1629 break;
1630 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
1631 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1632 break;
1633 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
1634 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1635 break;
1636 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
1637 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1638 break;
1639 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
1640 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1641 break;
1642 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
1643 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1644 break;
1645 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
1646 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1647 break;
1648 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
1649 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1650 break;
1651 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
1652 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1653 break;
1654 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
1655 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1656 break;
1657 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
1658 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1659 break;
1660 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
1661 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1662 break;
1663 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
1664 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1665 break;
1666 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
1667 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1668 break;
1669 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
1670 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1671 break;
1672 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
1673 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1674 break;
1675 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
1676 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1677 break;
1678 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
1679 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1680 break;
1681 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
1682 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1683 break;
1684 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
1685 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1686 break;
1687 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
1688 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1689 break;
1690 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
1691 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1692 break;
1693 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
1694 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1695 break;
1696 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
1697 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1698 break;
1699 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
1700 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1701 break;
1702 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
1703 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1704 break;
1705 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
1706 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1707 break;
1708 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
1709 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1710 break;
1711 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
1712 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1713 break;
1714 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
1715 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1716 break;
1717 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
1718 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1719 break;
1720 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
1721 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1722 break;
1723 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
1724 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1725 break;
1726 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
1727 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1728 break;
1729 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
1730 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1731 break;
1732 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
1733 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1734 break;
1735 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
1736 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1737 break;
1738 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
1739 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1740 break;
1741 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
1742 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1743 break;
1744 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
1745 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1746 break;
1747 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
1748 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1749 break;
1750 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
1751 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1752 break;
1753 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
1754 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1755 break;
1756 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
1757 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1758 break;
1759 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
1760 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1761 break;
1762 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
1763 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1764 break;
1765 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
1766 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1767 break;
1768 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
1769 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1770 break;
1771 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
1772 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1773 break;
1774 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
1775 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1776 break;
1777 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
1778 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1779 break;
1780 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
1781 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1782 break;
1783 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
1784 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1785 break;
1786 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
1787 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1788 break;
1789 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
1790 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1791 break;
1792 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
1793 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1794 break;
1795 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
1796 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1797 break;
1798 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
1799 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1800 break;
1801 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
1802 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1803 break;
1804 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
1805 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1806 break;
1807 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
1808 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1809 break;
1810 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
1811 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1812 break;
1813 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
1814 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1815 break;
1816 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
1817 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1818 break;
1819 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
1820 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1821 break;
1822 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
1823 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1824 break;
1825 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
1826 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1827 break;
1828 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
1829 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1830 break;
1831 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
1832 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1833 break;
1834 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
1835 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1836 break;
1837 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
1838 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1839 break;
1840 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
1841 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1842 break;
1843 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
1844 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1845 break;
1846 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
1847 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1848 break;
1849 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
1850 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1851 break;
1852 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
1853 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1854 break;
1855 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
1856 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1857 break;
1858 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
1859 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1860 break;
1861 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
1862 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1863 break;
1864 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
1865 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1866 break;
1867 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
1868 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1869 break;
1870 case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
1871 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1872 break;
1873 case SVGA_FIFO_3D_CAPS_LAST:
1874 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1875 break;
1876 case SVGA_FIFO_GUEST_3D_HWVERSION:
1877 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1878 break;
1879 case SVGA_FIFO_FENCE_GOAL:
1880 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1881 break;
1882 case SVGA_FIFO_BUSY:
1883 Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
1884 break;
1885 default:
1886 Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
1887 break;
1888 }
1889
1890 return VINF_EM_RAW_EMULATE_INSTR;
1891}
1892
1893/**
1894 * HC access handler for the FIFO.
1895 *
1896 * @returns VINF_SUCCESS if the handler have carried out the operation.
1897 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1898 * @param pVM VM Handle.
1899 * @param pVCpu The cross context CPU structure for the calling EMT.
1900 * @param GCPhys The physical address the guest is writing to.
1901 * @param pvPhys The HC mapping of that address.
1902 * @param pvBuf What the guest is reading/writing.
1903 * @param cbBuf How much it's reading/writing.
1904 * @param enmAccessType The access type.
1905 * @param enmOrigin Who is making the access.
1906 * @param pvUser User argument.
1907 */
1908static DECLCALLBACK(VBOXSTRICTRC)
1909vmsvgaR3FIFOAccessHandler(PVM pVM, PVMCPU pVCpu RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
1910 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
1911{
1912 PVGASTATE pThis = (PVGASTATE)pvUser;
1913 int rc;
1914 Assert(pThis);
1915 Assert(GCPhys >= pThis->GCPhysVRAM);
1916 NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin);
1917
1918 rc = vmsvgaFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
1919 if (RT_SUCCESS(rc))
1920 return VINF_PGM_HANDLER_DO_DEFAULT;
1921 AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
1922 return rc;
1923}
1924
1925# endif /* IN_RING3 */
1926#endif /* DEBUG_FIFO_ACCESS */
1927
1928#ifdef DEBUG_GMR_ACCESS
1929/**
1930 * HC access handler for the FIFO.
1931 *
1932 * @returns VINF_SUCCESS if the handler have carried out the operation.
1933 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
1934 * @param pVM VM Handle.
1935 * @param pVCpu The cross context CPU structure for the calling EMT.
1936 * @param GCPhys The physical address the guest is writing to.
1937 * @param pvPhys The HC mapping of that address.
1938 * @param pvBuf What the guest is reading/writing.
1939 * @param cbBuf How much it's reading/writing.
1940 * @param enmAccessType The access type.
1941 * @param enmOrigin Who is making the access.
1942 * @param pvUser User argument.
1943 */
1944static DECLCALLBACK(VBOXSTRICTRC)
1945vmsvgaR3GMRAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
1946 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
1947{
1948 PVGASTATE pThis = (PVGASTATE)pvUser;
1949 Assert(pThis);
1950 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1951 NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin);
1952
1953 Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
1954
1955 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
1956 {
1957 PGMR pGMR = &pSVGAState->aGMR[i];
1958
1959 if (pGMR->numDescriptors)
1960 {
1961 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
1962 {
1963 if ( GCPhys >= pGMR->paDesc[j].GCPhys
1964 && GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
1965 {
1966 /*
1967 * Turn off the write handler for this particular page and make it R/W.
1968 * Then return telling the caller to restart the guest instruction.
1969 */
1970 int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
1971 goto end;
1972 }
1973 }
1974 }
1975 }
1976end:
1977 return VINF_PGM_HANDLER_DO_DEFAULT;
1978}
1979
1980# ifdef IN_RING3
1981
1982/* Callback handler for VMR3ReqCallWait */
1983static DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
1984{
1985 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
1986 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
1987 PGMR pGMR = &pSVGAState->aGMR[gmrId];
1988 int rc;
1989
1990 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
1991 {
1992 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
1993 pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
1994 pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
1995 AssertRC(rc);
1996 }
1997 return VINF_SUCCESS;
1998}
1999
2000/* Callback handler for VMR3ReqCallWait */
2001static DECLCALLBACK(int) vmsvgaDeregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
2002{
2003 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
2004 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2005 PGMR pGMR = &pSVGAState->aGMR[gmrId];
2006
2007 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2008 {
2009 int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
2010 AssertRC(rc);
2011 }
2012 return VINF_SUCCESS;
2013}
2014
2015/* Callback handler for VMR3ReqCallWait */
2016static DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
2017{
2018 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2019
2020 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
2021 {
2022 PGMR pGMR = &pSVGAState->aGMR[i];
2023
2024 if (pGMR->numDescriptors)
2025 {
2026 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2027 {
2028 int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
2029 AssertRC(rc);
2030 }
2031 }
2032 }
2033 return VINF_SUCCESS;
2034}
2035
2036# endif /* IN_RING3 */
2037#endif /* DEBUG_GMR_ACCESS */
2038
2039/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2040
2041#ifdef IN_RING3
2042
2043/**
2044 * Worker for vmsvgaR3FifoThread that handles an external command.
2045 *
2046 * @param pThis VGA device instance data.
2047 */
2048static void vmsvgaR3FifoHandleExtCmd(PVGASTATE pThis)
2049{
2050 uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2051 switch (pThis->svga.u8FIFOExtCommand)
2052 {
2053 case VMSVGA_FIFO_EXTCMD_RESET:
2054 Log(("vmsvgaFIFOLoop: reset the fifo thread.\n"));
2055 Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2056# ifdef VBOX_WITH_VMSVGA3D
2057 if (pThis->svga.f3DEnabled)
2058 {
2059 /* The 3d subsystem must be reset from the fifo thread. */
2060 vmsvga3dReset(pThis);
2061 }
2062# endif
2063 break;
2064
2065 case VMSVGA_FIFO_EXTCMD_TERMINATE:
2066 Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
2067 Assert(pThis->svga.pvFIFOExtCmdParam == NULL);
2068# ifdef VBOX_WITH_VMSVGA3D
2069 if (pThis->svga.f3DEnabled)
2070 {
2071 /* The 3d subsystem must be shut down from the fifo thread. */
2072 vmsvga3dTerminate(pThis);
2073 }
2074# endif
2075 break;
2076
2077 case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2078 {
2079 Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2080# ifdef VBOX_WITH_VMSVGA3D
2081 PSSMHANDLE pSSM = (PSSMHANDLE)pThis->svga.pvFIFOExtCmdParam;
2082 AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2083 vmsvga3dSaveExec(pThis, pSSM);
2084# endif
2085 break;
2086 }
2087
2088 case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2089 {
2090 Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2091# ifdef VBOX_WITH_VMSVGA3D
2092 PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pvFIFOExtCmdParam;
2093 AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2094 vmsvga3dLoadExec(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2095# endif
2096 break;
2097 }
2098
2099 case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2100 {
2101# ifdef VBOX_WITH_VMSVGA3D
2102 uint32_t sid = (uint32_t)(uintptr_t)pThis->svga.pvFIFOExtCmdParam;
2103 Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2104 vmsvga3dUpdateHeapBuffersForSurfaces(pThis, sid);
2105# endif
2106 break;
2107 }
2108
2109
2110 default:
2111 AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThis->svga.pvFIFOExtCmdParam));
2112 break;
2113 }
2114
2115 /*
2116 * Signal the end of the external command.
2117 */
2118 pThis->svga.pvFIFOExtCmdParam = NULL;
2119 pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2120 ASMMemoryFence(); /* paranoia^2 */
2121 int rc = RTSemEventSignal(pThis->svga.FIFOExtCmdSem);
2122 AssertLogRelRC(rc);
2123}
2124
2125/**
2126 * Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2127 * doing a job on the FIFO thread (even when it's officially suspended).
2128 *
2129 * @returns VBox status code (fully asserted).
2130 * @param pThis VGA device instance data.
2131 * @param uExtCmd The command to execute on the FIFO thread.
2132 * @param pvParam Pointer to command parameters.
2133 * @param cMsWait The time to wait for the command, given in
2134 * milliseconds.
2135 */
2136static int vmsvgaR3RunExtCmdOnFifoThread(PVGASTATE pThis, uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2137{
2138 Assert(cMsWait >= RT_MS_1SEC * 5);
2139 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2140 ("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2141
2142 int rc;
2143 PPDMTHREAD pThread = pThis->svga.pFIFOIOThread;
2144 PDMTHREADSTATE enmState = pThread->enmState;
2145 if (enmState == PDMTHREADSTATE_SUSPENDED)
2146 {
2147 /*
2148 * The thread is suspended, we have to temporarily wake it up so it can
2149 * perform the task.
2150 * (We ASSUME not racing code here, both wrt thread state and ext commands.)
2151 */
2152 Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
2153 /* Post the request. */
2154 pThis->svga.fFifoExtCommandWakeup = true;
2155 pThis->svga.pvFIFOExtCmdParam = pvParam;
2156 pThis->svga.u8FIFOExtCommand = uExtCmd;
2157 ASMMemoryFence(); /* paranoia^3 */
2158
2159 /* Resume the thread. */
2160 rc = PDMR3ThreadResume(pThread);
2161 AssertLogRelRC(rc);
2162 if (RT_SUCCESS(rc))
2163 {
2164 /* Wait. Take care in case the semaphore was already posted (same as below). */
2165 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2166 if ( rc == VINF_SUCCESS
2167 && pThis->svga.u8FIFOExtCommand == uExtCmd)
2168 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2169 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd || RT_FAILURE_NP(rc),
2170 ("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2171
2172 /* suspend the thread */
2173 pThis->svga.fFifoExtCommandWakeup = false;
2174 int rc2 = PDMR3ThreadSuspend(pThread);
2175 AssertLogRelRC(rc2);
2176 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
2177 rc = rc2;
2178 }
2179 pThis->svga.fFifoExtCommandWakeup = false;
2180 pThis->svga.pvFIFOExtCmdParam = NULL;
2181 }
2182 else if (enmState == PDMTHREADSTATE_RUNNING)
2183 {
2184 /*
2185 * The thread is running, should only happen during reset and vmsvga3dsfc.
2186 * We ASSUME not racing code here, both wrt thread state and ext commands.
2187 */
2188 Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
2189 Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET || uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
2190
2191 /* Post the request. */
2192 pThis->svga.pvFIFOExtCmdParam = pvParam;
2193 pThis->svga.u8FIFOExtCommand = uExtCmd;
2194 ASMMemoryFence(); /* paranoia^2 */
2195 rc = SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2196 AssertLogRelRC(rc);
2197
2198 /* Wait. Take care in case the semaphore was already posted (same as above). */
2199 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait);
2200 if ( rc == VINF_SUCCESS
2201 && pThis->svga.u8FIFOExtCommand == uExtCmd)
2202 rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
2203 AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd || RT_FAILURE_NP(rc),
2204 ("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
2205
2206 pThis->svga.pvFIFOExtCmdParam = NULL;
2207 }
2208 else
2209 {
2210 /*
2211 * Something is wrong with the thread!
2212 */
2213 AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
2214 rc = VERR_INVALID_STATE;
2215 }
2216 return rc;
2217}
2218
2219
2220/**
2221 * Marks the FIFO non-busy, notifying any waiting EMTs.
2222 *
2223 * @param pThis The VGA state.
2224 * @param pSVGAState Pointer to the ring-3 only SVGA state data.
2225 * @param offFifoMin The start byte offset of the command FIFO.
2226 */
2227static void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
2228{
2229 ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
2230 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
2231 vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
2232
2233 /* Wake up any waiting EMTs. */
2234 if (pSVGAState->cBusyDelayedEmts > 0)
2235 {
2236#ifdef VMSVGA_USE_EMT_HALT_CODE
2237 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
2238 VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
2239 if (idCpu != NIL_VMCPUID)
2240 {
2241 VMR3NotifyCpuDeviceReady(pVM, idCpu);
2242 while (idCpu-- > 0)
2243 if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
2244 VMR3NotifyCpuDeviceReady(pVM, idCpu);
2245 }
2246#else
2247 int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
2248 AssertRC(rc2);
2249#endif
2250 }
2251}
2252
2253/**
2254 * Reads (more) payload into the command buffer.
2255 *
2256 * @returns pbBounceBuf on success
2257 * @retval (void *)1 if the thread was requested to stop.
2258 * @retval NULL on FIFO error.
2259 *
2260 * @param cbPayloadReq The number of bytes of payload requested.
2261 * @param pFIFO The FIFO.
2262 * @param offCurrentCmd The FIFO byte offset of the current command.
2263 * @param offFifoMin The start byte offset of the command FIFO.
2264 * @param offFifoMax The end byte offset of the command FIFO.
2265 * @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
2266 * always sufficient size.
2267 * @param pcbAlreadyRead How much payload we've already read into the bounce
2268 * buffer. (We will NEVER re-read anything.)
2269 * @param pThread The calling PDM thread handle.
2270 * @param pThis The VGA state.
2271 * @param pSVGAState Pointer to the ring-3 only SVGA state data. For
2272 * statistics collection.
2273 */
2274static void *vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t volatile *pFIFO,
2275 uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
2276 uint8_t *pbBounceBuf, uint32_t *pcbAlreadyRead,
2277 PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
2278{
2279 Assert(pbBounceBuf);
2280 Assert(pcbAlreadyRead);
2281 Assert(offFifoMin < offFifoMax);
2282 Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
2283 Assert(offFifoMax <= VMSVGA_FIFO_SIZE);
2284
2285 /*
2286 * Check if the requested payload size has already been satisfied .
2287 * .
2288 * When called to read more, the caller is responsible for making sure the .
2289 * new command size (cbRequsted) never is smaller than what has already .
2290 * been read.
2291 */
2292 uint32_t cbAlreadyRead = *pcbAlreadyRead;
2293 if (cbPayloadReq <= cbAlreadyRead)
2294 {
2295 AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
2296 return pbBounceBuf;
2297 }
2298
2299 /*
2300 * Commands bigger than the fifo buffer are invalid.
2301 */
2302 uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
2303 AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
2304 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
2305 NULL);
2306
2307 /*
2308 * Move offCurrentCmd past the command dword.
2309 */
2310 offCurrentCmd += sizeof(uint32_t);
2311 if (offCurrentCmd >= offFifoMax)
2312 offCurrentCmd = offFifoMin;
2313
2314 /*
2315 * Do we have sufficient payload data available already?
2316 */
2317 uint32_t cbAfter, cbBefore;
2318 uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
2319 if (offNextCmd > offCurrentCmd)
2320 {
2321 if (RT_LIKELY(offNextCmd < offFifoMax))
2322 cbAfter = offNextCmd - offCurrentCmd;
2323 else
2324 {
2325 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2326 LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2327 offNextCmd, offFifoMin, offFifoMax));
2328 cbAfter = offFifoMax - offCurrentCmd;
2329 }
2330 cbBefore = 0;
2331 }
2332 else
2333 {
2334 cbAfter = offFifoMax - offCurrentCmd;
2335 if (offNextCmd >= offFifoMin)
2336 cbBefore = offNextCmd - offFifoMin;
2337 else
2338 {
2339 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2340 LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
2341 offNextCmd, offFifoMin, offFifoMax));
2342 cbBefore = 0;
2343 }
2344 }
2345 if (cbAfter + cbBefore < cbPayloadReq)
2346 {
2347 /*
2348 * Insufficient, must wait for it to arrive.
2349 */
2350 STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
2351 for (uint32_t i = 0;; i++)
2352 {
2353 if (pThread->enmState != PDMTHREADSTATE_RUNNING)
2354 {
2355 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2356 return (void *)(uintptr_t)1;
2357 }
2358 Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
2359 cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
2360
2361 SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
2362
2363 offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
2364 if (offNextCmd > offCurrentCmd)
2365 {
2366 cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
2367 cbBefore = 0;
2368 }
2369 else
2370 {
2371 cbAfter = offFifoMax - offCurrentCmd;
2372 cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
2373 }
2374
2375 if (cbAfter + cbBefore >= cbPayloadReq)
2376 break;
2377 }
2378 STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
2379 }
2380
2381 /*
2382 * Copy out the memory and update what pcbAlreadyRead points to.
2383 */
2384 if (cbAfter >= cbPayloadReq)
2385 memcpy(pbBounceBuf + cbAlreadyRead,
2386 (uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
2387 cbPayloadReq - cbAlreadyRead);
2388 else
2389 {
2390 LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
2391 if (cbAlreadyRead < cbAfter)
2392 {
2393 memcpy(pbBounceBuf + cbAlreadyRead,
2394 (uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
2395 cbAfter - cbAlreadyRead);
2396 cbAlreadyRead = cbAfter;
2397 }
2398 memcpy(pbBounceBuf + cbAlreadyRead,
2399 (uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
2400 cbPayloadReq - cbAlreadyRead);
2401 }
2402 *pcbAlreadyRead = cbPayloadReq;
2403 return pbBounceBuf;
2404}
2405
2406/* The async FIFO handling thread. */
2407static DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2408{
2409 PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
2410 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
2411 int rc;
2412
2413 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
2414 return VINF_SUCCESS;
2415
2416 /*
2417 * Special mode where we only execute an external command and the go back
2418 * to being suspended. Currently, all ext cmds ends up here, with the reset
2419 * one also being eligble for runtime execution further down as well.
2420 */
2421 if (pThis->svga.fFifoExtCommandWakeup)
2422 {
2423 vmsvgaR3FifoHandleExtCmd(pThis);
2424 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2425 if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
2426 SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, RT_MS_1MIN);
2427 else
2428 vmsvgaR3FifoHandleExtCmd(pThis);
2429 return VINF_SUCCESS;
2430 }
2431
2432
2433 /*
2434 * Signal the semaphore to make sure we don't wait for 250 after a
2435 * suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
2436 */
2437 SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
2438
2439 /*
2440 * Allocate a bounce buffer for command we get from the FIFO.
2441 * (All code must return via the end of the function to free this buffer.)
2442 */
2443 uint8_t *pbBounceBuf = (uint8_t *)RTMemAllocZ(VMSVGA_FIFO_SIZE);
2444 AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
2445
2446 LogFlow(("vmsvgaFIFOLoop: started loop\n"));
2447 uint32_t volatile * const pFIFO = pThis->svga.pFIFOR3;
2448 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2449 {
2450# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
2451 /*
2452 * Should service the run loop every so often.
2453 */
2454 if (pThis->svga.f3DEnabled)
2455 vmsvga3dCocoaServiceRunLoop();
2456# endif
2457
2458 /*
2459 * Wait for at most 250 ms to start polling.
2460 */
2461 rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, 250);
2462 AssertBreak(RT_SUCCESS(rc) || rc == VERR_TIMEOUT || rc == VERR_INTERRUPTED);
2463 if (pThread->enmState != PDMTHREADSTATE_RUNNING)
2464 {
2465 LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
2466 break;
2467 }
2468 if (rc == VERR_TIMEOUT)
2469 {
2470 if (pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
2471 continue;
2472 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
2473
2474 Log(("vmsvgaFIFOLoop: timeout\n"));
2475 }
2476 else if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
2477 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
2478
2479 Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
2480 Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
2481 Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
2482
2483 /*
2484 * Handle external commands (currently only reset).
2485 */
2486 if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
2487 {
2488 vmsvgaR3FifoHandleExtCmd(pThis);
2489 continue;
2490 }
2491
2492 /*
2493 * The device must be enabled and configured.
2494 */
2495 if ( !pThis->svga.fEnabled
2496 || !pThis->svga.fConfigured)
2497 {
2498 vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
2499 continue;
2500 }
2501
2502 /*
2503 * Get and check the min/max values. We ASSUME that they will remain
2504 * unchanged while we process requests. A further ASSUMPTION is that
2505 * the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
2506 * we don't read it back while in the loop.
2507 */
2508 uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
2509 uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
2510 uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
2511 if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
2512 || offFifoMax <= offFifoMin
2513 || offFifoMax > VMSVGA_FIFO_SIZE
2514 || (offFifoMax & 3) != 0
2515 || (offFifoMin & 3) != 0
2516 || offCurrentCmd < offFifoMin
2517 || offCurrentCmd > offFifoMax))
2518 {
2519 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2520 LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
2521 vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
2522 continue;
2523 }
2524 if (RT_UNLIKELY(offCurrentCmd & 3))
2525 {
2526 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
2527 LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
2528 offCurrentCmd = ~UINT32_C(3);
2529 }
2530
2531/**
2532 * Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
2533 *
2534 * Will break out of the switch on failure.
2535 * Will restart and quit the loop if the thread was requested to stop.
2536 *
2537 * @param a_cbPayloadReq How much payload to fetch.
2538 * @remarks Access a bunch of variables in the current scope!
2539 */
2540# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
2541 if (1) { \
2542 (a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
2543 pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
2544 if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
2545 } else do {} while (0)
2546/**
2547 * Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
2548 * buffer after figuring out the actual command size.
2549 * Will break out of the switch on failure.
2550 * @param a_cbPayloadReq How much payload to fetch.
2551 * @remarks Access a bunch of variables in the current scope!
2552 */
2553# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
2554 if (1) { \
2555 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
2556 } else do {} while (0)
2557
2558 /*
2559 * Mark the FIFO as busy.
2560 */
2561 ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
2562 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
2563 ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
2564
2565 /*
2566 * Execute all queued FIFO commands.
2567 * Quit if pending external command or changes in the thread state.
2568 */
2569 bool fDone = false;
2570 while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
2571 && pThread->enmState == PDMTHREADSTATE_RUNNING)
2572 {
2573 uint32_t cbPayload = 0;
2574 uint32_t u32IrqStatus = 0;
2575 bool fTriggerIrq = false;
2576
2577 Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
2578
2579 /* First check any pending actions. */
2580 if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
2581# ifdef VBOX_WITH_VMSVGA3D
2582 vmsvga3dChangeMode(pThis);
2583# else
2584 {/*nothing*/}
2585# endif
2586 /* Check for pending external commands (reset). */
2587 if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
2588 break;
2589
2590 /*
2591 * Process the command.
2592 */
2593 SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
2594 LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
2595 offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
2596 switch (enmCmdId)
2597 {
2598 case SVGA_CMD_INVALID_CMD:
2599 /* Nothing to do. */
2600 break;
2601
2602 case SVGA_CMD_FENCE:
2603 {
2604 SVGAFifoCmdFence *pCmdFence;
2605 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
2606 if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
2607 {
2608 Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
2609 pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
2610
2611 if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
2612 {
2613 Log(("vmsvgaFIFOLoop: any fence irq\n"));
2614 u32IrqStatus |= SVGA_IRQFLAG_ANY_FENCE;
2615 }
2616 else
2617 if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
2618 && (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
2619 && pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
2620 {
2621 Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
2622 u32IrqStatus |= SVGA_IRQFLAG_FENCE_GOAL;
2623 }
2624 }
2625 else
2626 Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
2627 break;
2628 }
2629 case SVGA_CMD_UPDATE:
2630 case SVGA_CMD_UPDATE_VERBOSE:
2631 {
2632 SVGAFifoCmdUpdate *pUpdate;
2633 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
2634 Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
2635 vgaR3UpdateDisplay(pThis, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
2636 break;
2637 }
2638
2639 case SVGA_CMD_DEFINE_CURSOR:
2640 {
2641 /* Followed by bitmap data. */
2642 SVGAFifoCmdDefineCursor *pCursor;
2643 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
2644 AssertFailed(); /** @todo implement when necessary. */
2645 break;
2646 }
2647
2648 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
2649 {
2650 /* Followed by bitmap data. */
2651 uint32_t cbCursorShape, cbAndMask;
2652 uint8_t *pCursorCopy;
2653 uint32_t cbCmd;
2654
2655 SVGAFifoCmdDefineAlphaCursor *pCursor;
2656 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
2657
2658 Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
2659
2660 /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
2661 AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
2662
2663 /* Refetch the bitmap data as well. */
2664 cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
2665 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
2666 /** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
2667
2668 /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
2669 cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
2670 cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
2671 cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
2672
2673 pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
2674 AssertBreak(pCursorCopy);
2675
2676 Log2(("Cursor data:\n%.*Rhxd\n", pCursor->width * pCursor->height * sizeof(uint32_t), pCursor+1));
2677
2678 /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
2679 memset(pCursorCopy, 0xff, cbAndMask);
2680 /* Colour data */
2681 memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
2682
2683 rc = pThis->pDrv->pfnVBVAMousePointerShape (pThis->pDrv,
2684 true,
2685 true,
2686 pCursor->hotspotX,
2687 pCursor->hotspotY,
2688 pCursor->width,
2689 pCursor->height,
2690 pCursorCopy);
2691 AssertRC(rc);
2692
2693 if (pSVGAState->Cursor.fActive)
2694 RTMemFree(pSVGAState->Cursor.pData);
2695
2696 pSVGAState->Cursor.fActive = true;
2697 pSVGAState->Cursor.xHotspot = pCursor->hotspotX;
2698 pSVGAState->Cursor.yHotspot = pCursor->hotspotY;
2699 pSVGAState->Cursor.width = pCursor->width;
2700 pSVGAState->Cursor.height = pCursor->height;
2701 pSVGAState->Cursor.cbData = cbCursorShape;
2702 pSVGAState->Cursor.pData = pCursorCopy;
2703 break;
2704 }
2705
2706 case SVGA_CMD_ESCAPE:
2707 {
2708 /* Followed by nsize bytes of data. */
2709 SVGAFifoCmdEscape *pEscape;
2710 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
2711
2712 /* Refetch the command buffer with the variable data; undo size increase (ugly) */
2713 AssertBreak(pEscape->size < VMSVGA_FIFO_SIZE);
2714 uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
2715 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
2716
2717 if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
2718 {
2719 AssertBreak(pEscape->size >= sizeof(uint32_t));
2720 uint32_t cmd = *(uint32_t *)(pEscape + 1);
2721 Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
2722
2723 switch (cmd)
2724 {
2725 case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
2726 {
2727 SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pEscape + 1);
2728 AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
2729 uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
2730
2731 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
2732 for (uint32_t iReg = 0; iReg < cRegs; iReg++)
2733 {
2734 Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
2735 }
2736 break;
2737 }
2738
2739 case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
2740 SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pEscape + 1);
2741 AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
2742 Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
2743 break;
2744 }
2745 }
2746 else
2747 Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
2748
2749 break;
2750 }
2751# ifdef VBOX_WITH_VMSVGA3D
2752 case SVGA_CMD_DEFINE_GMR2:
2753 {
2754 SVGAFifoCmdDefineGMR2 *pCmd;
2755 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
2756 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
2757
2758 /* Validate current GMR id. */
2759 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2760 AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
2761
2762 if (!pCmd->numPages)
2763 {
2764 vmsvgaGMRFree(pThis, pCmd->gmrId);
2765 }
2766 else
2767 {
2768 PGMR pGMR = &pSVGAState->aGMR[pCmd->gmrId];
2769 pGMR->cMaxPages = pCmd->numPages;
2770 }
2771 /* everything done in remap */
2772 break;
2773 }
2774
2775 case SVGA_CMD_REMAP_GMR2:
2776 {
2777 /* Followed by page descriptors or guest ptr. */
2778 SVGAFifoCmdRemapGMR2 *pCmd;
2779 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
2780 uint32_t cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
2781 uint32_t cbCmd;
2782 uint64_t *paNewPage64 = NULL;
2783
2784 Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
2785 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2786
2787 /* Calculate the size of what comes after next and fetch it. */
2788 cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
2789 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
2790 cbCmd += sizeof(SVGAGuestPtr);
2791 else
2792 if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
2793 {
2794 cbCmd += cbPageDesc;
2795 pCmd->numPages = 1;
2796 }
2797 else
2798 {
2799 AssertBreak(pCmd->numPages <= VMSVGA_FIFO_SIZE);
2800 cbCmd += cbPageDesc * pCmd->numPages;
2801 }
2802 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
2803
2804 /* Validate current GMR id. */
2805 AssertBreak(pCmd->gmrId < VMSVGA_MAX_GMR_IDS);
2806 PGMR pGMR = &pSVGAState->aGMR[pCmd->gmrId];
2807 AssertBreak(pCmd->offsetPages + pCmd->numPages <= pGMR->cMaxPages);
2808 AssertBreak(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
2809
2810 /* Save the old page descriptors as an array of page addresses (>> PAGE_SHIFT) */
2811 if (pGMR->paDesc)
2812 {
2813 uint32_t idxPage = 0;
2814 paNewPage64 = (uint64_t *)RTMemAllocZ(pGMR->cMaxPages * sizeof(uint64_t));
2815 AssertBreak(paNewPage64);
2816
2817 for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2818 {
2819 for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
2820 {
2821 paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * PAGE_SIZE) >> PAGE_SHIFT;
2822 }
2823 }
2824 AssertBreak(idxPage == pGMR->cbTotal >> PAGE_SHIFT);
2825 }
2826
2827 /* Free the old GMR if present. */
2828 if (pGMR->paDesc)
2829 RTMemFree(pGMR->paDesc);
2830
2831 /* Allocate the maximum amount possible (everything non-continuous) */
2832 pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->cMaxPages * sizeof(VMSVGAGMRDESCRIPTOR));
2833 AssertBreak(pGMR->paDesc);
2834
2835 if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
2836 {
2837 /** @todo */
2838 AssertFailed();
2839 }
2840 else
2841 {
2842 uint32_t *pPage32 = (uint32_t *)(pCmd + 1);
2843 uint64_t *pPage64 = (uint64_t *)(pCmd + 1);
2844 uint32_t iDescriptor = 0;
2845 RTGCPHYS GCPhys;
2846 PVMSVGAGMRDESCRIPTOR paDescOld = NULL;
2847 bool fGCPhys64 = !!(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
2848
2849 if (paNewPage64)
2850 {
2851 /* Overwrite the old page array with the new page values. */
2852 for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
2853 {
2854 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
2855 paNewPage64[i] = pPage64[i - pCmd->offsetPages];
2856 else
2857 paNewPage64[i] = pPage32[i - pCmd->offsetPages];
2858 }
2859 /* Use the updated page array instead of the command data. */
2860 fGCPhys64 = true;
2861 pPage64 = paNewPage64;
2862 pCmd->numPages = pGMR->cbTotal >> PAGE_SHIFT;
2863 }
2864
2865 if (fGCPhys64)
2866 GCPhys = (pPage64[0] << PAGE_SHIFT) & 0x00000FFFFFFFFFFFULL; /* seeing rubbish in the top bits with certain linux guests*/
2867 else
2868 GCPhys = pPage32[0] << PAGE_SHIFT;
2869
2870 pGMR->paDesc[0].GCPhys = GCPhys;
2871 pGMR->paDesc[0].numPages = 1;
2872 pGMR->cbTotal = PAGE_SIZE;
2873
2874 for (uint32_t i = 1; i < pCmd->numPages; i++)
2875 {
2876 if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
2877 GCPhys = (pPage64[i] << PAGE_SHIFT) & 0x00000FFFFFFFFFFFULL; /* seeing rubbish in the top bits with certain linux guests*/
2878 else
2879 GCPhys = pPage32[i] << PAGE_SHIFT;
2880
2881 /* Continuous physical memory? */
2882 if (GCPhys == pGMR->paDesc[iDescriptor].GCPhys + pGMR->paDesc[iDescriptor].numPages * PAGE_SIZE)
2883 {
2884 Assert(pGMR->paDesc[iDescriptor].numPages);
2885 pGMR->paDesc[iDescriptor].numPages++;
2886 LogFlow(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
2887 }
2888 else
2889 {
2890 iDescriptor++;
2891 pGMR->paDesc[iDescriptor].GCPhys = GCPhys;
2892 pGMR->paDesc[iDescriptor].numPages = 1;
2893 LogFlow(("Page %x GCPhys=%RGp\n", i, pGMR->paDesc[iDescriptor].GCPhys));
2894 }
2895
2896 pGMR->cbTotal += PAGE_SIZE;
2897 }
2898 LogFlow(("Nr of descriptors %x\n", iDescriptor + 1));
2899 pGMR->numDescriptors = iDescriptor + 1;
2900 }
2901
2902 if (paNewPage64)
2903 RTMemFree(paNewPage64);
2904
2905# ifdef DEBUG_GMR_ACCESS
2906 VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
2907# endif
2908 break;
2909 }
2910# endif // VBOX_WITH_VMSVGA3D
2911 case SVGA_CMD_DEFINE_SCREEN:
2912 {
2913 /* Note! The size of this command is specified by the guest and depends on capabilities. */
2914 Assert(!(pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT));
2915 SVGAFifoCmdDefineScreen *pCmd;
2916 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
2917 RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.structSize));
2918 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
2919
2920 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d)\n", pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y));
2921 if (pCmd->screen.flags & SVGA_SCREEN_HAS_ROOT)
2922 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_HAS_ROOT\n"));
2923 if (pCmd->screen.flags & SVGA_SCREEN_IS_PRIMARY)
2924 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_IS_PRIMARY\n"));
2925 if (pCmd->screen.flags & SVGA_SCREEN_FULLSCREEN_HINT)
2926 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_FULLSCREEN_HINT\n"));
2927 if (pCmd->screen.flags & SVGA_SCREEN_DEACTIVATE )
2928 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_DEACTIVATE \n"));
2929 if (pCmd->screen.flags & SVGA_SCREEN_BLANKING)
2930 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_BLANKING\n"));
2931
2932 /** @todo multi monitor support and screen object capabilities. */
2933 pThis->svga.uWidth = pCmd->screen.size.width;
2934 pThis->svga.uHeight = pCmd->screen.size.height;
2935 vmsvgaChangeMode(pThis);
2936 break;
2937 }
2938
2939 case SVGA_CMD_DESTROY_SCREEN:
2940 {
2941 SVGAFifoCmdDestroyScreen *pCmd;
2942 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
2943
2944 Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
2945 break;
2946 }
2947# ifdef VBOX_WITH_VMSVGA3D
2948 case SVGA_CMD_DEFINE_GMRFB:
2949 {
2950 SVGAFifoCmdDefineGMRFB *pCmd;
2951 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
2952
2953 Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
2954 pSVGAState->GMRFB.ptr = pCmd->ptr;
2955 pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
2956 pSVGAState->GMRFB.format = pCmd->format;
2957 break;
2958 }
2959
2960 case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
2961 {
2962 uint32_t width, height;
2963 SVGAFifoCmdBlitGMRFBToScreen *pCmd;
2964 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
2965
2966 Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
2967
2968 /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
2969 AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pThis->svga.uBpp);
2970 AssertBreak(pCmd->destScreenId == 0);
2971
2972 if (pCmd->destRect.left < 0)
2973 pCmd->destRect.left = 0;
2974 if (pCmd->destRect.top < 0)
2975 pCmd->destRect.top = 0;
2976 if (pCmd->destRect.right < 0)
2977 pCmd->destRect.right = 0;
2978 if (pCmd->destRect.bottom < 0)
2979 pCmd->destRect.bottom = 0;
2980
2981 width = pCmd->destRect.right - pCmd->destRect.left;
2982 height = pCmd->destRect.bottom - pCmd->destRect.top;
2983
2984 if ( width == 0
2985 || height == 0)
2986 break; /* Nothing to do. */
2987
2988 /* Clip to screen dimensions. */
2989 if (width > pThis->svga.uWidth)
2990 width = pThis->svga.uWidth;
2991 if (height > pThis->svga.uHeight)
2992 height = pThis->svga.uHeight;
2993
2994 unsigned offsetSource = (pCmd->srcOrigin.x * pSVGAState->GMRFB.format.s.bitsPerPixel) / 8 + pSVGAState->GMRFB.bytesPerLine * pCmd->srcOrigin.y;
2995 unsigned offsetDest = (pCmd->destRect.left * RT_ALIGN(pThis->svga.uBpp, 8)) / 8 + pThis->svga.cbScanline * pCmd->destRect.top;
2996 unsigned cbCopyWidth = (width * RT_ALIGN(pThis->svga.uBpp, 8)) / 8;
2997
2998 AssertBreak(offsetDest < pThis->vram_size);
2999
3000 rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM, pThis->CTX_SUFF(vram_ptr) + offsetDest, pThis->svga.cbScanline, pSVGAState->GMRFB.ptr, offsetSource, pSVGAState->GMRFB.bytesPerLine, cbCopyWidth, height);
3001 AssertRC(rc);
3002 vgaR3UpdateDisplay(pThis, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right - pCmd->destRect.left, pCmd->destRect.bottom - pCmd->destRect.top);
3003 break;
3004 }
3005
3006 case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
3007 {
3008 SVGAFifoCmdBlitScreenToGMRFB *pCmd;
3009 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
3010
3011 /* Note! This can fetch 3d render results as well!! */
3012 Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n", pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
3013 AssertFailed();
3014 break;
3015 }
3016# endif // VBOX_WITH_VMSVGA3D
3017 case SVGA_CMD_ANNOTATION_FILL:
3018 {
3019 SVGAFifoCmdAnnotationFill *pCmd;
3020 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
3021
3022 Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
3023 pSVGAState->colorAnnotation = pCmd->color;
3024 break;
3025 }
3026
3027 case SVGA_CMD_ANNOTATION_COPY:
3028 {
3029 SVGAFifoCmdAnnotationCopy *pCmd;
3030 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
3031
3032 Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
3033 AssertFailed();
3034 break;
3035 }
3036
3037 /** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
3038
3039 default:
3040# ifdef VBOX_WITH_VMSVGA3D
3041 if ( enmCmdId >= SVGA_3D_CMD_BASE
3042 && enmCmdId < SVGA_3D_CMD_MAX)
3043 {
3044 /* All 3d commands start with a common header, which defines the size of the command. */
3045 SVGA3dCmdHeader *pHdr;
3046 VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
3047 AssertBreak(pHdr->size < VMSVGA_FIFO_SIZE);
3048 uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
3049 VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
3050
3051/**
3052 * Check that the 3D command has at least a_cbMin of payload bytes after the
3053 * header. Will break out of the switch if it doesn't.
3054 */
3055# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
3056 AssertMsgBreak((a_cbMin) <= pHdr->size, ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin)))
3057 switch ((int)enmCmdId)
3058 {
3059 case SVGA_3D_CMD_SURFACE_DEFINE:
3060 {
3061 uint32_t cMipLevels;
3062 SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)(pHdr + 1);
3063 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3064
3065 cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3066 rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
3067 SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
3068# ifdef DEBUG_GMR_ACCESS
3069 VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
3070# endif
3071 break;
3072 }
3073
3074 case SVGA_3D_CMD_SURFACE_DEFINE_V2:
3075 {
3076 uint32_t cMipLevels;
3077 SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)(pHdr + 1);
3078 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3079
3080 cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
3081 rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
3082 pCmd->multisampleCount, pCmd->autogenFilter,
3083 cMipLevels, (SVGA3dSize *)(pCmd + 1));
3084 break;
3085 }
3086
3087 case SVGA_3D_CMD_SURFACE_DESTROY:
3088 {
3089 SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)(pHdr + 1);
3090 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3091 rc = vmsvga3dSurfaceDestroy(pThis, pCmd->sid);
3092 break;
3093 }
3094
3095 case SVGA_3D_CMD_SURFACE_COPY:
3096 {
3097 uint32_t cCopyBoxes;
3098 SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)(pHdr + 1);
3099 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3100
3101 cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
3102 rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3103 break;
3104 }
3105
3106 case SVGA_3D_CMD_SURFACE_STRETCHBLT:
3107 {
3108 SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)(pHdr + 1);
3109 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3110
3111 rc = vmsvga3dSurfaceStretchBlt(pThis, &pCmd->dest, &pCmd->boxDest, &pCmd->src, &pCmd->boxSrc, pCmd->mode);
3112 break;
3113 }
3114
3115 case SVGA_3D_CMD_SURFACE_DMA:
3116 {
3117 uint32_t cCopyBoxes;
3118 SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)(pHdr + 1);
3119 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3120
3121 cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
3122 STAM_PROFILE_START(&pSVGAState->StatR3CmdSurfaceDMA, a);
3123 rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
3124 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdSurfaceDMA, a);
3125 break;
3126 }
3127
3128 case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
3129 {
3130 uint32_t cRects;
3131 SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)(pHdr + 1);
3132 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3133
3134 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
3135 rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
3136 break;
3137 }
3138
3139 case SVGA_3D_CMD_CONTEXT_DEFINE:
3140 {
3141 SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)(pHdr + 1);
3142 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3143
3144 rc = vmsvga3dContextDefine(pThis, pCmd->cid);
3145 break;
3146 }
3147
3148 case SVGA_3D_CMD_CONTEXT_DESTROY:
3149 {
3150 SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)(pHdr + 1);
3151 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3152
3153 rc = vmsvga3dContextDestroy(pThis, pCmd->cid);
3154 break;
3155 }
3156
3157 case SVGA_3D_CMD_SETTRANSFORM:
3158 {
3159 SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)(pHdr + 1);
3160 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3161
3162 rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
3163 break;
3164 }
3165
3166 case SVGA_3D_CMD_SETZRANGE:
3167 {
3168 SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)(pHdr + 1);
3169 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3170
3171 rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
3172 break;
3173 }
3174
3175 case SVGA_3D_CMD_SETRENDERSTATE:
3176 {
3177 uint32_t cRenderStates;
3178 SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)(pHdr + 1);
3179 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3180
3181 cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
3182 rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
3183 break;
3184 }
3185
3186 case SVGA_3D_CMD_SETRENDERTARGET:
3187 {
3188 SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)(pHdr + 1);
3189 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3190
3191 rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
3192 break;
3193 }
3194
3195 case SVGA_3D_CMD_SETTEXTURESTATE:
3196 {
3197 uint32_t cTextureStates;
3198 SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)(pHdr + 1);
3199 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3200
3201 cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
3202 rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
3203 break;
3204 }
3205
3206 case SVGA_3D_CMD_SETMATERIAL:
3207 {
3208 SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)(pHdr + 1);
3209 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3210
3211 rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
3212 break;
3213 }
3214
3215 case SVGA_3D_CMD_SETLIGHTDATA:
3216 {
3217 SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)(pHdr + 1);
3218 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3219
3220 rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
3221 break;
3222 }
3223
3224 case SVGA_3D_CMD_SETLIGHTENABLED:
3225 {
3226 SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)(pHdr + 1);
3227 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3228
3229 rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
3230 break;
3231 }
3232
3233 case SVGA_3D_CMD_SETVIEWPORT:
3234 {
3235 SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)(pHdr + 1);
3236 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3237
3238 rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
3239 break;
3240 }
3241
3242 case SVGA_3D_CMD_SETCLIPPLANE:
3243 {
3244 SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)(pHdr + 1);
3245 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3246
3247 rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
3248 break;
3249 }
3250
3251 case SVGA_3D_CMD_CLEAR:
3252 {
3253 SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)(pHdr + 1);
3254 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3255 uint32_t cRects;
3256
3257 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
3258 rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
3259 break;
3260 }
3261
3262 case SVGA_3D_CMD_PRESENT:
3263 case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
3264 {
3265 SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)(pHdr + 1);
3266 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3267 uint32_t cRects;
3268
3269 cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
3270
3271 STAM_PROFILE_START(&pSVGAState->StatR3CmdPresent, a);
3272 rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
3273 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdPresent, a);
3274 break;
3275 }
3276
3277 case SVGA_3D_CMD_SHADER_DEFINE:
3278 {
3279 SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)(pHdr + 1);
3280 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3281 uint32_t cbData;
3282
3283 cbData = (pHdr->size - sizeof(*pCmd));
3284 rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
3285 break;
3286 }
3287
3288 case SVGA_3D_CMD_SHADER_DESTROY:
3289 {
3290 SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)(pHdr + 1);
3291 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3292
3293 rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
3294 break;
3295 }
3296
3297 case SVGA_3D_CMD_SET_SHADER:
3298 {
3299 SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)(pHdr + 1);
3300 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3301
3302 rc = vmsvga3dShaderSet(pThis, NULL, pCmd->cid, pCmd->type, pCmd->shid);
3303 break;
3304 }
3305
3306 case SVGA_3D_CMD_SET_SHADER_CONST:
3307 {
3308 SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)(pHdr + 1);
3309 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3310
3311 uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
3312 rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
3313 break;
3314 }
3315
3316 case SVGA_3D_CMD_DRAW_PRIMITIVES:
3317 {
3318 SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)(pHdr + 1);
3319 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3320 uint32_t cVertexDivisor;
3321
3322 cVertexDivisor = (pHdr->size - sizeof(*pCmd) - sizeof(SVGA3dVertexDecl) * pCmd->numVertexDecls - sizeof(SVGA3dPrimitiveRange) * pCmd->numRanges);
3323 Assert(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
3324 Assert(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
3325 Assert(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls);
3326
3327 SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
3328 SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *) (&pVertexDecl[pCmd->numVertexDecls]);
3329 SVGA3dVertexDivisor *pVertexDivisor = (cVertexDivisor) ? (SVGA3dVertexDivisor *)(&pNumRange[pCmd->numRanges]) : NULL;
3330
3331 STAM_PROFILE_START(&pSVGAState->StatR3CmdDrawPrimitive, a);
3332 rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges, pNumRange, cVertexDivisor, pVertexDivisor);
3333 STAM_PROFILE_STOP(&pSVGAState->StatR3CmdDrawPrimitive, a);
3334 break;
3335 }
3336
3337 case SVGA_3D_CMD_SETSCISSORRECT:
3338 {
3339 SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)(pHdr + 1);
3340 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3341
3342 rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
3343 break;
3344 }
3345
3346 case SVGA_3D_CMD_BEGIN_QUERY:
3347 {
3348 SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)(pHdr + 1);
3349 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3350
3351 rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
3352 break;
3353 }
3354
3355 case SVGA_3D_CMD_END_QUERY:
3356 {
3357 SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)(pHdr + 1);
3358 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3359
3360 rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
3361 break;
3362 }
3363
3364 case SVGA_3D_CMD_WAIT_FOR_QUERY:
3365 {
3366 SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)(pHdr + 1);
3367 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3368
3369 rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
3370 break;
3371 }
3372
3373 case SVGA_3D_CMD_GENERATE_MIPMAPS:
3374 {
3375 SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)(pHdr + 1);
3376 VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
3377
3378 rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
3379 break;
3380 }
3381
3382 case SVGA_3D_CMD_ACTIVATE_SURFACE:
3383 case SVGA_3D_CMD_DEACTIVATE_SURFACE:
3384 /* context id + surface id? */
3385 break;
3386
3387 default:
3388 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
3389 AssertFailed();
3390 break;
3391 }
3392 }
3393 else
3394# endif // VBOX_WITH_VMSVGA3D
3395 {
3396 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
3397 AssertFailed();
3398 }
3399 }
3400
3401 /* Go to the next slot */
3402 Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
3403 offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
3404 if (offCurrentCmd >= offFifoMax)
3405 {
3406 offCurrentCmd -= offFifoMax - offFifoMin;
3407 Assert(offCurrentCmd >= offFifoMin);
3408 Assert(offCurrentCmd < offFifoMax);
3409 }
3410 ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
3411 STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
3412
3413 /*
3414 * Raise IRQ if required. Must enter the critical section here
3415 * before making final decisions here, otherwise cubebench and
3416 * others may end up waiting forever.
3417 */
3418 if ( u32IrqStatus
3419 || (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
3420 {
3421 PDMCritSectEnter(&pThis->CritSect, VERR_IGNORED);
3422
3423 /* FIFO progress might trigger an interrupt. */
3424 if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
3425 {
3426 Log(("vmsvgaFIFOLoop: fifo progress irq\n"));
3427 u32IrqStatus |= SVGA_IRQFLAG_FIFO_PROGRESS;
3428 }
3429
3430 /* Unmasked IRQ pending? */
3431 if (pThis->svga.u32IrqMask & u32IrqStatus)
3432 {
3433 Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
3434 ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
3435 PDMDevHlpPCISetIrq(pDevIns, 0, 1);
3436 }
3437
3438 PDMCritSectLeave(&pThis->CritSect);
3439 }
3440 }
3441
3442 /* If really done, clear the busy flag. */
3443 if (fDone)
3444 {
3445 Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
3446 vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
3447 }
3448 }
3449
3450 /*
3451 * Free the bounce buffer. (There are no returns above!)
3452 */
3453 RTMemFree(pbBounceBuf);
3454
3455 return VINF_SUCCESS;
3456}
3457
3458/**
3459 * Free the specified GMR
3460 *
3461 * @param pThis VGA device instance data.
3462 * @param idGMR GMR id
3463 */
3464void vmsvgaGMRFree(PVGASTATE pThis, uint32_t idGMR)
3465{
3466 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3467
3468 /* Free the old descriptor if present. */
3469 if (pSVGAState->aGMR[idGMR].numDescriptors)
3470 {
3471 PGMR pGMR = &pSVGAState->aGMR[idGMR];
3472# ifdef DEBUG_GMR_ACCESS
3473 VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaDeregisterGMR, 2, pThis->pDevInsR3, idGMR);
3474# endif
3475
3476 Assert(pGMR->paDesc);
3477 RTMemFree(pGMR->paDesc);
3478 pGMR->paDesc = NULL;
3479 pGMR->numDescriptors = 0;
3480 pGMR->cbTotal = 0;
3481 pGMR->cMaxPages = 0;
3482 }
3483 Assert(!pSVGAState->aGMR[idGMR].cbTotal);
3484}
3485
3486/**
3487 * Copy from a GMR to host memory or vice versa
3488 *
3489 * @returns VBox status code.
3490 * @param pThis VGA device instance data.
3491 * @param enmTransferType Transfer type (read/write)
3492 * @param pbDst Host destination pointer
3493 * @param cbDestPitch Destination buffer pitch
3494 * @param src GMR description
3495 * @param offSrc Source buffer offset
3496 * @param cbSrcPitch Source buffer pitch
3497 * @param cbWidth Source width in bytes
3498 * @param cHeight Source height
3499 */
3500int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType, uint8_t *pbDst, int32_t cbDestPitch,
3501 SVGAGuestPtr src, uint32_t offSrc, int32_t cbSrcPitch, uint32_t cbWidth, uint32_t cHeight)
3502{
3503 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3504 PGMR pGMR;
3505 int rc;
3506 PVMSVGAGMRDESCRIPTOR pDesc;
3507 unsigned offDesc = 0;
3508
3509 Log(("vmsvgaGMRTransfer: gmr=%x offset=%x pitch=%d cbWidth=%d cHeight=%d; src offset=%d src pitch=%d\n",
3510 src.gmrId, src.offset, cbDestPitch, cbWidth, cHeight, offSrc, cbSrcPitch));
3511 Assert(cbWidth && cHeight);
3512
3513 /* Shortcut for the framebuffer. */
3514 if (src.gmrId == SVGA_GMR_FRAMEBUFFER)
3515 {
3516 offSrc += src.offset;
3517 AssertMsgReturn(src.offset < pThis->vram_size,
3518 ("src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x vram_size=%#x\n",
3519 src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pThis->vram_size),
3520 VERR_INVALID_PARAMETER);
3521 AssertMsgReturn(offSrc + cbSrcPitch * (cHeight - 1) + cbWidth <= pThis->vram_size,
3522 ("src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x vram_size=%#x\n",
3523 src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pThis->vram_size),
3524 VERR_INVALID_PARAMETER);
3525
3526 uint8_t *pSrc = pThis->CTX_SUFF(vram_ptr) + offSrc;
3527
3528 if (enmTransferType == SVGA3D_READ_HOST_VRAM)
3529 {
3530 /* switch src & dest */
3531 uint8_t *pTemp = pbDst;
3532 int32_t cbTempPitch = cbDestPitch;
3533
3534 pbDst = pSrc;
3535 pSrc = pTemp;
3536
3537 cbDestPitch = cbSrcPitch;
3538 cbSrcPitch = cbTempPitch;
3539 }
3540
3541 if ( pThis->svga.cbScanline == (uint32_t)cbDestPitch
3542 && cbWidth == (uint32_t)cbDestPitch
3543 && cbSrcPitch == cbDestPitch)
3544 {
3545 memcpy(pbDst, pSrc, cbWidth * cHeight);
3546 }
3547 else
3548 {
3549 for(uint32_t i = 0; i < cHeight; i++)
3550 {
3551 memcpy(pbDst, pSrc, cbWidth);
3552
3553 pbDst += cbDestPitch;
3554 pSrc += cbSrcPitch;
3555 }
3556 }
3557 return VINF_SUCCESS;
3558 }
3559
3560 AssertReturn(src.gmrId < VMSVGA_MAX_GMR_IDS, VERR_INVALID_PARAMETER);
3561 pGMR = &pSVGAState->aGMR[src.gmrId];
3562 pDesc = pGMR->paDesc;
3563
3564 offSrc += src.offset;
3565 AssertMsgReturn(src.offset < pGMR->cbTotal,
3566 ("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x\n",
3567 src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pGMR->cbTotal),
3568 VERR_INVALID_PARAMETER);
3569 AssertMsgReturn(offSrc + cbSrcPitch * (cHeight - 1) + cbWidth <= pGMR->cbTotal,
3570 ("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x\n",
3571 src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pGMR->cbTotal),
3572 VERR_INVALID_PARAMETER);
3573
3574 for (uint32_t i = 0; i < cHeight; i++)
3575 {
3576 uint32_t cbCurrentWidth = cbWidth;
3577 uint32_t offCurrent = offSrc;
3578 uint8_t *pCurrentDest = pbDst;
3579
3580 /* Find the right descriptor */
3581 while (offDesc + pDesc->numPages * PAGE_SIZE <= offCurrent)
3582 {
3583 offDesc += pDesc->numPages * PAGE_SIZE;
3584 AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
3585 pDesc++;
3586 }
3587
3588 while (cbCurrentWidth)
3589 {
3590 uint32_t cbToCopy;
3591
3592 if (offCurrent + cbCurrentWidth <= offDesc + pDesc->numPages * PAGE_SIZE)
3593 {
3594 cbToCopy = cbCurrentWidth;
3595 }
3596 else
3597 {
3598 cbToCopy = (offDesc + pDesc->numPages * PAGE_SIZE - offCurrent);
3599 AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
3600 }
3601
3602 LogFlow(("vmsvgaGMRTransfer: %s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", pDesc->GCPhys + offCurrent - offDesc));
3603
3604 if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
3605 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
3606 else
3607 rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
3608 AssertRCBreak(rc);
3609
3610 cbCurrentWidth -= cbToCopy;
3611 offCurrent += cbToCopy;
3612 pCurrentDest += cbToCopy;
3613
3614 /* Go to the next descriptor if there's anything left. */
3615 if (cbCurrentWidth)
3616 {
3617 offDesc += pDesc->numPages * PAGE_SIZE;
3618 pDesc++;
3619 }
3620 }
3621
3622 offSrc += cbSrcPitch;
3623 pbDst += cbDestPitch;
3624 }
3625
3626 return VINF_SUCCESS;
3627}
3628
3629/**
3630 * Unblock the FIFO I/O thread so it can respond to a state change.
3631 *
3632 * @returns VBox status code.
3633 * @param pDevIns The VGA device instance.
3634 * @param pThread The send thread.
3635 */
3636static DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3637{
3638 PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
3639 Log(("vmsvgaFIFOLoopWakeUp\n"));
3640 return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3641}
3642
3643/**
3644 * Enables or disables dirty page tracking for the framebuffer
3645 *
3646 * @param pThis VGA device instance data.
3647 * @param fTraces Enable/disable traces
3648 */
3649static void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
3650{
3651 if ( (!pThis->svga.fConfigured || !pThis->svga.fEnabled)
3652 && !fTraces)
3653 {
3654 //Assert(pThis->svga.fTraces);
3655 Log(("vmsvgaSetTraces: *not* allowed to disable dirty page tracking when the device is in legacy mode.\n"));
3656 return;
3657 }
3658
3659 pThis->svga.fTraces = fTraces;
3660 if (pThis->svga.fTraces)
3661 {
3662 unsigned cbFrameBuffer = pThis->vram_size;
3663
3664 Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
3665 if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
3666 {
3667#ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
3668 Assert(pThis->svga.cbScanline);
3669#endif
3670 /* Hardware enabled; return real framebuffer size .*/
3671 cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
3672 cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
3673 }
3674
3675 if (!pThis->svga.fVRAMTracking)
3676 {
3677 Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
3678 vgaR3RegisterVRAMHandler(pThis, cbFrameBuffer);
3679 pThis->svga.fVRAMTracking = true;
3680 }
3681 }
3682 else
3683 {
3684 if (pThis->svga.fVRAMTracking)
3685 {
3686 Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
3687 vgaR3UnregisterVRAMHandler(pThis);
3688 pThis->svga.fVRAMTracking = false;
3689 }
3690 }
3691}
3692
3693/**
3694 * Callback function for mapping a PCI I/O region.
3695 *
3696 * @return VBox status code.
3697 * @param pPciDev Pointer to PCI device.
3698 * Use pPciDev->pDevIns to get the device instance.
3699 * @param iRegion The region number.
3700 * @param GCPhysAddress Physical address of the region.
3701 * If iType is PCI_ADDRESS_SPACE_IO, this is an
3702 * I/O port, else it's a physical address.
3703 * This address is *NOT* relative
3704 * to pci_mem_base like earlier!
3705 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
3706 */
3707DECLCALLBACK(int) vmsvgaR3IORegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
3708{
3709 int rc;
3710 PPDMDEVINS pDevIns = pPciDev->pDevIns;
3711 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3712
3713 Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%#x enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
3714 if (enmType == PCI_ADDRESS_SPACE_IO)
3715 {
3716 AssertReturn(iRegion == 0, VERR_INTERNAL_ERROR);
3717 rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3718 vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr */, NULL /* InStr */, "VMSVGA");
3719 if (RT_FAILURE(rc))
3720 return rc;
3721 if (pThis->fR0Enabled)
3722 {
3723 rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3724 "vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
3725 if (RT_FAILURE(rc))
3726 return rc;
3727 }
3728 if (pThis->fGCEnabled)
3729 {
3730 rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
3731 "vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
3732 if (RT_FAILURE(rc))
3733 return rc;
3734 }
3735
3736 pThis->svga.BasePort = GCPhysAddress;
3737 Log(("vmsvgaR3IORegionMap: base port = %x\n", pThis->svga.BasePort));
3738 }
3739 else
3740 {
3741 AssertReturn(iRegion == 2 && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);
3742 if (GCPhysAddress != NIL_RTGCPHYS)
3743 {
3744 /*
3745 * Mapping the FIFO RAM.
3746 */
3747 rc = PDMDevHlpMMIO2Map(pDevIns, iRegion, GCPhysAddress);
3748 AssertRC(rc);
3749
3750# ifdef DEBUG_FIFO_ACCESS
3751 if (RT_SUCCESS(rc))
3752 {
3753 rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress, GCPhysAddress + (VMSVGA_FIFO_SIZE - 1),
3754 pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
3755 "VMSVGA FIFO");
3756 AssertRC(rc);
3757 }
3758# endif
3759 if (RT_SUCCESS(rc))
3760 {
3761 pThis->svga.GCPhysFIFO = GCPhysAddress;
3762 Log(("vmsvgaR3IORegionMap: FIFO address = %RGp\n", GCPhysAddress));
3763 }
3764 }
3765 else
3766 {
3767 Assert(pThis->svga.GCPhysFIFO);
3768# ifdef DEBUG_FIFO_ACCESS
3769 rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3770 AssertRC(rc);
3771# endif
3772 pThis->svga.GCPhysFIFO = 0;
3773 }
3774
3775 }
3776 return VINF_SUCCESS;
3777}
3778
3779# ifdef VBOX_WITH_VMSVGA3D
3780
3781/**
3782 * Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
3783 * surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
3784 *
3785 * @param pThis The VGA device instance data.
3786 * @param sid Either UINT32_MAX or the ID of a specific
3787 * surface. If UINT32_MAX is used, all surfaces
3788 * are processed.
3789 */
3790void vmsvga3dSurfaceUpdateHeapBuffersOnFifoThread(PVGASTATE pThis, uint32_t sid)
3791{
3792 vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
3793 sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
3794}
3795
3796
3797/**
3798 * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
3799 */
3800DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3801{
3802 /* There might be a specific context ID at the start of the
3803 arguments, if not show all contexts. */
3804 uint32_t cid = UINT32_MAX;
3805 if (pszArgs)
3806 pszArgs = RTStrStripL(pszArgs);
3807 if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
3808 cid = RTStrToUInt32(pszArgs);
3809
3810 /* Verbose or terse display, we default to verbose. */
3811 bool fVerbose = true;
3812 if (RTStrIStr(pszArgs, "terse"))
3813 fVerbose = false;
3814
3815 /* The size of the ascii art (x direction, y is 3/4 of x). */
3816 uint32_t cxAscii = 80;
3817 if (RTStrIStr(pszArgs, "gigantic"))
3818 cxAscii = 300;
3819 else if (RTStrIStr(pszArgs, "huge"))
3820 cxAscii = 180;
3821 else if (RTStrIStr(pszArgs, "big"))
3822 cxAscii = 132;
3823 else if (RTStrIStr(pszArgs, "normal"))
3824 cxAscii = 80;
3825 else if (RTStrIStr(pszArgs, "medium"))
3826 cxAscii = 64;
3827 else if (RTStrIStr(pszArgs, "small"))
3828 cxAscii = 48;
3829 else if (RTStrIStr(pszArgs, "tiny"))
3830 cxAscii = 24;
3831
3832 /* Y invert the image when producing the ASCII art. */
3833 bool fInvY = false;
3834 if (RTStrIStr(pszArgs, "invy"))
3835 fInvY = true;
3836
3837 vmsvga3dInfoSurfaceWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, cid, fVerbose, cxAscii, fInvY);
3838}
3839
3840
3841/**
3842 * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
3843 */
3844DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3845{
3846 /* There might be a specific surface ID at the start of the
3847 arguments, if not show all contexts. */
3848 uint32_t sid = UINT32_MAX;
3849 if (pszArgs)
3850 pszArgs = RTStrStripL(pszArgs);
3851 if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
3852 sid = RTStrToUInt32(pszArgs);
3853
3854 /* Verbose or terse display, we default to verbose. */
3855 bool fVerbose = true;
3856 if (RTStrIStr(pszArgs, "terse"))
3857 fVerbose = false;
3858
3859 vmsvga3dInfoContextWorker(PDMINS_2_DATA(pDevIns, PVGASTATE), pHlp, sid, fVerbose);
3860}
3861
3862# endif /* VBOX_WITH_VMSVGA3D */
3863
3864/**
3865 * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
3866 */
3867static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3868{
3869 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3870 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3871
3872 pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
3873 pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
3874 pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n", pThis->svga.BasePort);
3875 pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
3876 pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
3877 pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
3878 pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
3879 pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
3880 pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
3881 pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
3882 pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
3883 pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
3884 pHlp->pfnPrintf(pHlp, "Pitch lock: %#x\n", pThis->svga.u32PitchLock);
3885 pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
3886 pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
3887 pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
3888 pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
3889 pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
3890 pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
3891 pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
3892 pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
3893 pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
3894
3895 pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
3896 pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
3897 pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
3898 pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
3899
3900# ifdef VBOX_WITH_VMSVGA3D
3901 pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
3902 pHlp->pfnPrintf(pHlp, "Host windows ID: %#RX64\n", pThis->svga.u64HostWindowId);
3903 if (pThis->svga.u64HostWindowId != 0)
3904 vmsvga3dInfoHostWindow(pHlp, pThis->svga.u64HostWindowId);
3905# endif
3906}
3907
3908
3909/**
3910 * @copydoc FNSSMDEVLOADEXEC
3911 */
3912int vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3913{
3914 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3915 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3916 int rc;
3917
3918 /* Load our part of the VGAState */
3919 rc = SSMR3GetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
3920 AssertRCReturn(rc, rc);
3921
3922 /* Load the framebuffer backup. */
3923 rc = SSMR3GetMem(pSSM, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
3924 AssertRCReturn(rc, rc);
3925
3926 /* Load the VMSVGA state. */
3927 rc = SSMR3GetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
3928 AssertRCReturn(rc, rc);
3929
3930 /* Load the active cursor bitmaps. */
3931 if (pSVGAState->Cursor.fActive)
3932 {
3933 pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
3934 AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
3935
3936 rc = SSMR3GetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
3937 AssertRCReturn(rc, rc);
3938 }
3939
3940 /* Load the GMR state */
3941 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
3942 {
3943 PGMR pGMR = &pSVGAState->aGMR[i];
3944
3945 rc = SSMR3GetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
3946 AssertRCReturn(rc, rc);
3947
3948 if (pGMR->numDescriptors)
3949 {
3950 /* Allocate the maximum amount possible (everything non-continuous) */
3951 Assert(pGMR->cMaxPages || pGMR->cbTotal);
3952 pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ((pGMR->cMaxPages) ? pGMR->cMaxPages : (pGMR->cbTotal >> PAGE_SHIFT) * sizeof(VMSVGAGMRDESCRIPTOR));
3953 AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
3954
3955 for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
3956 {
3957 rc = SSMR3GetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
3958 AssertRCReturn(rc, rc);
3959 }
3960 }
3961 }
3962
3963# ifdef VBOX_WITH_VMSVGA3D
3964 if (pThis->svga.f3DEnabled)
3965 {
3966# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
3967 vmsvga3dPowerOn(pThis);
3968# endif
3969
3970 VMSVGA_STATE_LOAD LoadState;
3971 LoadState.pSSM = pSSM;
3972 LoadState.uVersion = uVersion;
3973 LoadState.uPass = uPass;
3974 rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
3975 AssertLogRelRCReturn(rc, rc);
3976 }
3977# endif
3978
3979 return VINF_SUCCESS;
3980}
3981
3982/**
3983 * Reinit the video mode after the state has been loaded.
3984 */
3985int vmsvgaLoadDone(PPDMDEVINS pDevIns)
3986{
3987 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3988 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
3989
3990 pThis->last_bpp = VMSVGA_VAL_UNINITIALIZED; /* force mode reset */
3991 vmsvgaChangeMode(pThis);
3992
3993 /* Set the active cursor. */
3994 if (pSVGAState->Cursor.fActive)
3995 {
3996 int rc;
3997
3998 rc = pThis->pDrv->pfnVBVAMousePointerShape(pThis->pDrv,
3999 true,
4000 true,
4001 pSVGAState->Cursor.xHotspot,
4002 pSVGAState->Cursor.yHotspot,
4003 pSVGAState->Cursor.width,
4004 pSVGAState->Cursor.height,
4005 pSVGAState->Cursor.pData);
4006 AssertRC(rc);
4007 }
4008 return VINF_SUCCESS;
4009}
4010
4011/**
4012 * @copydoc FNSSMDEVSAVEEXEC
4013 */
4014int vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4015{
4016 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4017 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4018 int rc;
4019
4020 /* Save our part of the VGAState */
4021 rc = SSMR3PutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
4022 AssertLogRelRCReturn(rc, rc);
4023
4024 /* Save the framebuffer backup. */
4025 rc = SSMR3PutMem(pSSM, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
4026 AssertLogRelRCReturn(rc, rc);
4027
4028 /* Save the VMSVGA state. */
4029 rc = SSMR3PutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
4030 AssertLogRelRCReturn(rc, rc);
4031
4032 /* Save the active cursor bitmaps. */
4033 if (pSVGAState->Cursor.fActive)
4034 {
4035 rc = SSMR3PutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
4036 AssertLogRelRCReturn(rc, rc);
4037 }
4038
4039 /* Save the GMR state */
4040 for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
4041 {
4042 rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i], sizeof(pSVGAState->aGMR[i]), 0, g_aGMRFields, NULL);
4043 AssertLogRelRCReturn(rc, rc);
4044
4045 for (uint32_t j = 0; j < pSVGAState->aGMR[i].numDescriptors; j++)
4046 {
4047 rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i].paDesc[j], sizeof(pSVGAState->aGMR[i].paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
4048 AssertLogRelRCReturn(rc, rc);
4049 }
4050 }
4051
4052# ifdef VBOX_WITH_VMSVGA3D
4053 /*
4054 * Must save the 3d state in the FIFO thread.
4055 */
4056 if (pThis->svga.f3DEnabled)
4057 {
4058 rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
4059 AssertLogRelRCReturn(rc, rc);
4060 }
4061# endif
4062 return VINF_SUCCESS;
4063}
4064
4065/**
4066 * Resets the SVGA hardware state
4067 *
4068 * @returns VBox status code.
4069 * @param pDevIns The device instance.
4070 */
4071int vmsvgaReset(PPDMDEVINS pDevIns)
4072{
4073 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4074 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4075
4076 /* Reset before init? */
4077 if (!pSVGAState)
4078 return VINF_SUCCESS;
4079
4080 Log(("vmsvgaReset\n"));
4081
4082
4083 /* Reset the FIFO processing as well as the 3d state (if we have one). */
4084 pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
4085 int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_RESET, NULL /*pvParam*/, 10000 /*ms*/);
4086
4087 /* Reset other stuff. */
4088 pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
4089 RT_ZERO(pThis->svga.au32ScratchRegion);
4090 RT_ZERO(*pThis->svga.pSvgaR3State);
4091 RT_BZERO(pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
4092
4093 /* Register caps. */
4094 pThis->svga.u32RegCaps = SVGA_CAP_GMR | SVGA_CAP_GMR2 | SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | SVGA_CAP_EXTENDED_FIFO | SVGA_CAP_IRQMASK | SVGA_CAP_PITCHLOCK | SVGA_CAP_TRACES | SVGA_CAP_SCREEN_OBJECT_2 | SVGA_CAP_ALPHA_CURSOR;
4095# ifdef VBOX_WITH_VMSVGA3D
4096 pThis->svga.u32RegCaps |= SVGA_CAP_3D;
4097# endif
4098
4099 /* Setup FIFO capabilities. */
4100 pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE | SVGA_FIFO_CAP_CURSOR_BYPASS_3 | SVGA_FIFO_CAP_GMR2 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED | SVGA_FIFO_CAP_SCREEN_OBJECT_2;
4101
4102 /* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
4103 pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
4104
4105 /* VRAM tracking is enabled by default during bootup. */
4106 pThis->svga.fVRAMTracking = true;
4107 pThis->svga.fEnabled = false;
4108
4109 /* Invalidate current settings. */
4110 pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
4111 pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
4112 pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
4113 pThis->svga.cbScanline = 0;
4114
4115 return rc;
4116}
4117
4118/**
4119 * Cleans up the SVGA hardware state
4120 *
4121 * @returns VBox status code.
4122 * @param pDevIns The device instance.
4123 */
4124int vmsvgaDestruct(PPDMDEVINS pDevIns)
4125{
4126 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4127
4128 /*
4129 * Ask the FIFO thread to terminate the 3d state and then terminate it.
4130 */
4131 if (pThis->svga.pFIFOIOThread)
4132 {
4133 int rc = vmsvgaR3RunExtCmdOnFifoThread(pThis, VMSVGA_FIFO_EXTCMD_TERMINATE, NULL /*pvParam*/, 30000 /*ms*/);
4134 AssertLogRelRC(rc);
4135
4136 rc = PDMR3ThreadDestroy(pThis->svga.pFIFOIOThread, NULL);
4137 AssertLogRelRC(rc);
4138 pThis->svga.pFIFOIOThread = NULL;
4139 }
4140
4141 /*
4142 * Destroy the special SVGA state.
4143 */
4144 PVMSVGAR3STATE pSVGAState = pThis->svga.pSvgaR3State;
4145 if (pSVGAState)
4146 {
4147# ifndef VMSVGA_USE_EMT_HALT_CODE
4148 if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
4149 {
4150 RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
4151 pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
4152 }
4153# endif
4154 if (pSVGAState->Cursor.fActive)
4155 RTMemFree(pSVGAState->Cursor.pData);
4156
4157 for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
4158 if (pSVGAState->aGMR[i].paDesc)
4159 RTMemFree(pSVGAState->aGMR[i].paDesc);
4160
4161 RTMemFree(pSVGAState);
4162 pThis->svga.pSvgaR3State = NULL;
4163 }
4164
4165 /*
4166 * Free our resources residing in the VGA state.
4167 */
4168 if (pThis->svga.pFrameBufferBackup)
4169 RTMemFree(pThis->svga.pFrameBufferBackup);
4170 if (pThis->svga.FIFOExtCmdSem != NIL_RTSEMEVENT)
4171 {
4172 RTSemEventDestroy(pThis->svga.FIFOExtCmdSem);
4173 pThis->svga.FIFOExtCmdSem = NIL_RTSEMEVENT;
4174 }
4175 if (pThis->svga.FIFORequestSem != NIL_SUPSEMEVENT)
4176 {
4177 SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
4178 pThis->svga.FIFORequestSem = NIL_SUPSEMEVENT;
4179 }
4180
4181 return VINF_SUCCESS;
4182}
4183
4184/**
4185 * Initialize the SVGA hardware state
4186 *
4187 * @returns VBox status code.
4188 * @param pDevIns The device instance.
4189 */
4190int vmsvgaInit(PPDMDEVINS pDevIns)
4191{
4192 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4193 PVMSVGAR3STATE pSVGAState;
4194 PVM pVM = PDMDevHlpGetVM(pDevIns);
4195 int rc;
4196
4197 pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
4198 memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
4199
4200 pThis->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAllocZ(sizeof(VMSVGAR3STATE));
4201 AssertReturn(pThis->svga.pSvgaR3State, VERR_NO_MEMORY);
4202 pSVGAState = pThis->svga.pSvgaR3State;
4203
4204 /* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
4205 pThis->svga.pFrameBufferBackup = RTMemAllocZ(VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
4206 AssertReturn(pThis->svga.pFrameBufferBackup, VERR_NO_MEMORY);
4207
4208 /* Create event semaphore. */
4209 pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
4210
4211 rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
4212 if (RT_FAILURE(rc))
4213 {
4214 Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
4215 return rc;
4216 }
4217
4218 /* Create event semaphore. */
4219 rc = RTSemEventCreate(&pThis->svga.FIFOExtCmdSem);
4220 if (RT_FAILURE(rc))
4221 {
4222 Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
4223 return rc;
4224 }
4225
4226# ifndef VMSVGA_USE_EMT_HALT_CODE
4227 /* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
4228 rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
4229 AssertRCReturn(rc, rc);
4230# endif
4231
4232 /* Register caps. */
4233 pThis->svga.u32RegCaps = SVGA_CAP_GMR | SVGA_CAP_GMR2 | SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | SVGA_CAP_EXTENDED_FIFO | SVGA_CAP_IRQMASK | SVGA_CAP_PITCHLOCK | SVGA_CAP_TRACES | SVGA_CAP_SCREEN_OBJECT_2 | SVGA_CAP_ALPHA_CURSOR;
4234# ifdef VBOX_WITH_VMSVGA3D
4235 pThis->svga.u32RegCaps |= SVGA_CAP_3D;
4236# endif
4237
4238 /* Setup FIFO capabilities. */
4239 pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE | SVGA_FIFO_CAP_CURSOR_BYPASS_3 | SVGA_FIFO_CAP_GMR2 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED | SVGA_FIFO_CAP_SCREEN_OBJECT_2;
4240
4241 /* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
4242 pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
4243
4244 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = 0; /* no 3d available. */
4245# ifdef VBOX_WITH_VMSVGA3D
4246 if (pThis->svga.f3DEnabled)
4247 {
4248 rc = vmsvga3dInit(pThis);
4249 if (RT_FAILURE(rc))
4250 {
4251 LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
4252 pThis->svga.f3DEnabled = false;
4253 }
4254 }
4255# endif
4256 /* VRAM tracking is enabled by default during bootup. */
4257 pThis->svga.fVRAMTracking = true;
4258
4259 /* Invalidate current settings. */
4260 pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
4261 pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
4262 pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
4263 pThis->svga.cbScanline = 0;
4264
4265 pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
4266 pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
4267 while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
4268 {
4269 pThis->svga.u32MaxWidth -= 256;
4270 pThis->svga.u32MaxHeight -= 256;
4271 }
4272 Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
4273
4274# ifdef DEBUG_GMR_ACCESS
4275 /* Register the GMR access handler type. */
4276 rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
4277 vmsvgaR3GMRAccessHandler,
4278 NULL, NULL, NULL,
4279 NULL, NULL, NULL,
4280 "VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
4281 AssertRCReturn(rc, rc);
4282# endif
4283# ifdef DEBUG_FIFO_ACCESS
4284 rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pThis->pDevInsR3), PGMPHYSHANDLERKIND_ALL,
4285 vmsvgaR3FIFOAccessHandler,
4286 NULL, NULL, NULL,
4287 NULL, NULL, NULL,
4288 "VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
4289 AssertRCReturn(rc, rc);
4290#endif
4291
4292 /* Create the async IO thread. */
4293 rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
4294 RTTHREADTYPE_IO, "VMSVGA FIFO");
4295 if (RT_FAILURE(rc))
4296 {
4297 AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
4298 return rc;
4299 }
4300
4301 /*
4302 * Statistics.
4303 */
4304 STAM_REG(pVM, &pSVGAState->StatR3CmdPresent, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/Present", STAMUNIT_TICKS_PER_CALL, "Profiling of Present.");
4305 STAM_REG(pVM, &pSVGAState->StatR3CmdDrawPrimitive, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/DrawPrimitive", STAMUNIT_TICKS_PER_CALL, "Profiling of DrawPrimitive.");
4306 STAM_REG(pVM, &pSVGAState->StatR3CmdSurfaceDMA, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/SurfaceDMA", STAMUNIT_TICKS_PER_CALL, "Profiling of SurfaceDMA.");
4307 STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
4308 STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
4309 STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
4310 STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
4311 STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
4312 STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
4313 STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");
4314
4315 /*
4316 * Info handlers.
4317 */
4318 PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
4319# ifdef VBOX_WITH_VMSVGA3D
4320 PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
4321 PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
4322 "VMSVGA 3d surface details. "
4323 "Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
4324 vmsvgaR3Info3dSurface);
4325# endif
4326
4327 return VINF_SUCCESS;
4328}
4329
4330# ifdef VBOX_WITH_VMSVGA3D
4331/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
4332static const char * const g_apszVmSvgaDevCapNames[] =
4333{
4334 "x3D", /* = 0 */
4335 "xMAX_LIGHTS",
4336 "xMAX_TEXTURES",
4337 "xMAX_CLIP_PLANES",
4338 "xVERTEX_SHADER_VERSION",
4339 "xVERTEX_SHADER",
4340 "xFRAGMENT_SHADER_VERSION",
4341 "xFRAGMENT_SHADER",
4342 "xMAX_RENDER_TARGETS",
4343 "xS23E8_TEXTURES",
4344 "xS10E5_TEXTURES",
4345 "xMAX_FIXED_VERTEXBLEND",
4346 "xD16_BUFFER_FORMAT",
4347 "xD24S8_BUFFER_FORMAT",
4348 "xD24X8_BUFFER_FORMAT",
4349 "xQUERY_TYPES",
4350 "xTEXTURE_GRADIENT_SAMPLING",
4351 "rMAX_POINT_SIZE",
4352 "xMAX_SHADER_TEXTURES",
4353 "xMAX_TEXTURE_WIDTH",
4354 "xMAX_TEXTURE_HEIGHT",
4355 "xMAX_VOLUME_EXTENT",
4356 "xMAX_TEXTURE_REPEAT",
4357 "xMAX_TEXTURE_ASPECT_RATIO",
4358 "xMAX_TEXTURE_ANISOTROPY",
4359 "xMAX_PRIMITIVE_COUNT",
4360 "xMAX_VERTEX_INDEX",
4361 "xMAX_VERTEX_SHADER_INSTRUCTIONS",
4362 "xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
4363 "xMAX_VERTEX_SHADER_TEMPS",
4364 "xMAX_FRAGMENT_SHADER_TEMPS",
4365 "xTEXTURE_OPS",
4366 "xSURFACEFMT_X8R8G8B8",
4367 "xSURFACEFMT_A8R8G8B8",
4368 "xSURFACEFMT_A2R10G10B10",
4369 "xSURFACEFMT_X1R5G5B5",
4370 "xSURFACEFMT_A1R5G5B5",
4371 "xSURFACEFMT_A4R4G4B4",
4372 "xSURFACEFMT_R5G6B5",
4373 "xSURFACEFMT_LUMINANCE16",
4374 "xSURFACEFMT_LUMINANCE8_ALPHA8",
4375 "xSURFACEFMT_ALPHA8",
4376 "xSURFACEFMT_LUMINANCE8",
4377 "xSURFACEFMT_Z_D16",
4378 "xSURFACEFMT_Z_D24S8",
4379 "xSURFACEFMT_Z_D24X8",
4380 "xSURFACEFMT_DXT1",
4381 "xSURFACEFMT_DXT2",
4382 "xSURFACEFMT_DXT3",
4383 "xSURFACEFMT_DXT4",
4384 "xSURFACEFMT_DXT5",
4385 "xSURFACEFMT_BUMPX8L8V8U8",
4386 "xSURFACEFMT_A2W10V10U10",
4387 "xSURFACEFMT_BUMPU8V8",
4388 "xSURFACEFMT_Q8W8V8U8",
4389 "xSURFACEFMT_CxV8U8",
4390 "xSURFACEFMT_R_S10E5",
4391 "xSURFACEFMT_R_S23E8",
4392 "xSURFACEFMT_RG_S10E5",
4393 "xSURFACEFMT_RG_S23E8",
4394 "xSURFACEFMT_ARGB_S10E5",
4395 "xSURFACEFMT_ARGB_S23E8",
4396 "xMISSING62",
4397 "xMAX_VERTEX_SHADER_TEXTURES",
4398 "xMAX_SIMULTANEOUS_RENDER_TARGETS",
4399 "xSURFACEFMT_V16U16",
4400 "xSURFACEFMT_G16R16",
4401 "xSURFACEFMT_A16B16G16R16",
4402 "xSURFACEFMT_UYVY",
4403 "xSURFACEFMT_YUY2",
4404 "xMULTISAMPLE_NONMASKABLESAMPLES",
4405 "xMULTISAMPLE_MASKABLESAMPLES",
4406 "xALPHATOCOVERAGE",
4407 "xSUPERSAMPLE",
4408 "xAUTOGENMIPMAPS",
4409 "xSURFACEFMT_NV12",
4410 "xSURFACEFMT_AYUV",
4411 "xMAX_CONTEXT_IDS",
4412 "xMAX_SURFACE_IDS",
4413 "xSURFACEFMT_Z_DF16",
4414 "xSURFACEFMT_Z_DF24",
4415 "xSURFACEFMT_Z_D24S8_INT",
4416 "xSURFACEFMT_BC4_UNORM",
4417 "xSURFACEFMT_BC5_UNORM", /* 83 */
4418};
4419# endif
4420
4421
4422/**
4423 * Power On notification.
4424 *
4425 * @returns VBox status.
4426 * @param pDevIns The device instance data.
4427 *
4428 * @remarks Caller enters the device critical section.
4429 */
4430DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
4431{
4432 PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
4433 int rc;
4434
4435# ifdef VBOX_WITH_VMSVGA3D
4436 if (pThis->svga.f3DEnabled)
4437 {
4438 rc = vmsvga3dPowerOn(pThis);
4439
4440 if (RT_SUCCESS(rc))
4441 {
4442 bool fSavedBuffering = RTLogRelSetBuffering(true);
4443 SVGA3dCapsRecord *pCaps;
4444 SVGA3dCapPair *pData;
4445 uint32_t idxCap = 0;
4446
4447 /* 3d hardware version; latest and greatest */
4448 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
4449 pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
4450
4451 pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
4452 pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
4453 pData = (SVGA3dCapPair *)&pCaps->data;
4454
4455 /* Fill out all 3d capabilities. */
4456 for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
4457 {
4458 uint32_t val = 0;
4459
4460 rc = vmsvga3dQueryCaps(pThis, i, &val);
4461 if (RT_SUCCESS(rc))
4462 {
4463 pData[idxCap][0] = i;
4464 pData[idxCap][1] = val;
4465 idxCap++;
4466 if (g_apszVmSvgaDevCapNames[i][0] == 'x')
4467 LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
4468 else
4469 LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)*(float *)&val, (unsigned)(*(float *)&val * 10000) % 10000,
4470 &g_apszVmSvgaDevCapNames[i][1]));
4471 }
4472 else
4473 LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
4474 }
4475 pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
4476 pCaps = (SVGA3dCapsRecord *)((uint32_t *)pCaps + pCaps->header.length);
4477
4478 /* Mark end of record array. */
4479 pCaps->header.length = 0;
4480
4481 RTLogRelSetBuffering(fSavedBuffering);
4482 }
4483 }
4484# endif // VBOX_WITH_VMSVGA3D
4485}
4486
4487#endif /* IN_RING3 */
4488
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