VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevPCI.cpp@ 41816

Last change on this file since 41816 was 41816, checked in by vboxsync, 13 years ago

DevPCI: Changed return values of PCIDevPhysRead/Write to VINF_NOT_SUPPORTED.
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1/* $Id: DevPCI.cpp 41816 2012-06-18 14:07:17Z vboxsync $ */
2/** @file
3 * DevPCI - PCI BUS Device.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.215389.xyz. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 * --------------------------------------------------------------------
17 *
18 * This code is based on:
19 *
20 * QEMU PCI bus manager
21 *
22 * Copyright (c) 2004 Fabrice Bellard
23 *
24 * Permission is hereby granted, free of charge, to any person obtaining a copy
25 * of this software and associated documentation files (the "Software"), to deal
26 * in the Software without restriction, including without limitation the rights
27 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28 * copies of the Software, and to permit persons to whom the Software is
29 * furnished to do so, subject to the following conditions:
30 *
31 * The above copyright notice and this permission notice shall be included in
32 * all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40 * THE SOFTWARE.
41 */
42
43/*******************************************************************************
44* Header Files *
45*******************************************************************************/
46#define LOG_GROUP LOG_GROUP_DEV_PCI
47/* Hack to get PCIDEVICEINT declare at the right point - include "PCIInternal.h". */
48#define PCI_INCLUDE_PRIVATE
49#include <VBox/pci.h>
50#include <VBox/vmm/pdmdev.h>
51#include <iprt/asm.h>
52#include <iprt/assert.h>
53#include <iprt/string.h>
54
55#include "VBoxDD.h"
56
57
58/*******************************************************************************
59* Structures and Typedefs *
60*******************************************************************************/
61/**
62 * PIIX3 ISA Bridge state.
63 */
64typedef struct PIIX3State
65{
66 /** The PCI device of the bridge. */
67 PCIDEVICE dev;
68} PIIX3State, PIIX3, *PPIIX3;
69
70/**
71 * PCI Bus instance.
72 */
73typedef struct PCIBus
74{
75 /** Bus number. */
76 int32_t iBus;
77 /** Start device number. */
78 int32_t iDevSearch;
79 /** Number of bridges attached to the bus. */
80 uint32_t cBridges;
81
82 uint32_t Alignment0;
83
84 /** Array of PCI devices. */
85 R3PTRTYPE(PPCIDEVICE) devices[256];
86 /** Array of bridges attached to the bus. */
87 R3PTRTYPE(PPCIDEVICE *) papBridgesR3;
88
89 /** R3 pointer to the device instance. */
90 PPDMDEVINSR3 pDevInsR3;
91 /** Pointer to the PCI R3 helpers. */
92 PCPDMPCIHLPR3 pPciHlpR3;
93
94 /** R0 pointer to the device instance. */
95 PPDMDEVINSR0 pDevInsR0;
96 /** Pointer to the PCI R0 helpers. */
97 PCPDMPCIHLPR0 pPciHlpR0;
98
99 /** RC pointer to the device instance. */
100 PPDMDEVINSRC pDevInsRC;
101 /** Pointer to the PCI RC helpers. */
102 PCPDMPCIHLPRC pPciHlpRC;
103
104 /** The PCI device for the PCI bridge. */
105 PCIDEVICE PciDev;
106
107} PCIBUS;
108/** Pointer to a PCIBUS instance. */
109typedef PCIBUS *PPCIBUS;
110typedef PCIBUS PCIBus;
111
112/** @def PCI_IRQ_PINS
113 * Number of pins for interrupts (PIRQ#0...PIRQ#3)
114 */
115#define PCI_IRQ_PINS 4
116
117/** @def PCI_APIC_IRQ_PINS
118 * Number of pins for interrupts if the APIC is used.
119 */
120#define PCI_APIC_IRQ_PINS 8
121
122/**
123 * PCI Globals - This is the host-to-pci bridge and the root bus.
124 */
125typedef struct PCIGLOBALS
126{
127 /** Irq levels for the four PCI Irqs.
128 * These count how many devices asserted
129 * the IRQ line. If greater 0 an IRQ is sent to the guest.
130 * If it drops to 0 the IRQ is deasserted.
131 */
132 volatile uint32_t pci_irq_levels[PCI_IRQ_PINS];
133
134#if 1 /* Will be moved into the BIOS soon. */
135 /** The next I/O port address which the PCI BIOS will use. */
136 uint32_t pci_bios_io_addr;
137 /** The next MMIO address which the PCI BIOS will use. */
138 uint32_t pci_bios_mem_addr;
139 /** Actual bus number. */
140 uint8_t uBus;
141#endif
142
143 /** I/O APIC usage flag */
144 bool fUseIoApic;
145 /** I/O APIC irq levels */
146 volatile uint32_t pci_apic_irq_levels[PCI_APIC_IRQ_PINS];
147 /** ACPI IRQ level */
148 uint32_t acpi_irq_level;
149 /** ACPI PIC IRQ */
150 int acpi_irq;
151 /** Config register. */
152 uint32_t uConfigReg;
153
154 /** R3 pointer to the device instance. */
155 PPDMDEVINSR3 pDevInsR3;
156 /** R0 pointer to the device instance. */
157 PPDMDEVINSR0 pDevInsR0;
158 /** RC pointer to the device instance. */
159 PPDMDEVINSRC pDevInsRC;
160
161#if HC_ARCH_BITS == 64
162 uint32_t Alignment0;
163#endif
164
165 /** ISA bridge state. */
166 PIIX3 PIIX3State;
167 /** PCI bus which is attached to the host-to-PCI bridge. */
168 PCIBUS PciBus;
169
170} PCIGLOBALS;
171/** Pointer to per VM data. */
172typedef PCIGLOBALS *PPCIGLOBALS;
173
174
175/*******************************************************************************
176* Defined Constants And Macros *
177*******************************************************************************/
178
179/** Converts a bus instance pointer to a device instance pointer. */
180#define PCIBUS_2_DEVINS(pPciBus) ((pPciBus)->CTX_SUFF(pDevIns))
181/** Converts a device instance pointer to a PCIGLOBALS pointer. */
182#define DEVINS_2_PCIGLOBALS(pDevIns) ((PPCIGLOBALS)(PDMINS_2_DATA(pDevIns, PPCIGLOBALS)))
183/** Converts a device instance pointer to a PCIBUS pointer. */
184#define DEVINS_2_PCIBUS(pDevIns) ((PPCIBUS)(&PDMINS_2_DATA(pDevIns, PPCIGLOBALS)->PciBus))
185
186/** Converts a pointer to a PCI bus instance to a PCIGLOBALS pointer.
187 * @note This works only if the bus number is 0!!!
188 */
189#define PCIBUS_2_PCIGLOBALS(pPciBus) ( (PPCIGLOBALS)((uintptr_t)(pPciBus) - RT_OFFSETOF(PCIGLOBALS, PciBus)) )
190
191/** @def PCI_LOCK
192 * Acquires the PDM lock. This is a NOP if locking is disabled. */
193/** @def PCI_UNLOCK
194 * Releases the PDM lock. This is a NOP if locking is disabled. */
195#define PCI_LOCK(pDevIns, rc) \
196 do { \
197 int rc2 = DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnLock((pDevIns), rc); \
198 if (rc2 != VINF_SUCCESS) \
199 return rc2; \
200 } while (0)
201#define PCI_UNLOCK(pDevIns) \
202 DEVINS_2_PCIBUS(pDevIns)->CTX_SUFF(pPciHlp)->pfnUnlock(pDevIns)
203
204/** @def VBOX_PCI_SAVED_STATE_VERSION
205 * Saved state version of the PCI bus device.
206 */
207#define VBOX_PCI_SAVED_STATE_VERSION 3
208
209
210#ifndef VBOX_DEVICE_STRUCT_TESTCASE
211/*******************************************************************************
212* Internal Functions *
213*******************************************************************************/
214RT_C_DECLS_BEGIN
215
216PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTag);
217PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTag);
218PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
219PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
220PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
221PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
222
223#ifdef IN_RING3
224DECLINLINE(PPCIDEVICE) pciFindBridge(PPCIBUS pBus, uint8_t iBus);
225#endif
226
227RT_C_DECLS_END
228
229#define DEBUG_PCI
230
231#define PCI_VENDOR_ID 0x00 /* 16 bits */
232#define PCI_DEVICE_ID 0x02 /* 16 bits */
233#define PCI_COMMAND 0x04 /* 16 bits */
234#define PCI_COMMAND_IO 0x01 /* Enable response in I/O space */
235#define PCI_COMMAND_MEMORY 0x02 /* Enable response in Memory space */
236#define PCI_CLASS_DEVICE 0x0a /* Device class */
237#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
238#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
239#define PCI_MIN_GNT 0x3e /* 8 bits */
240#define PCI_MAX_LAT 0x3f /* 8 bits */
241
242
243#ifdef IN_RING3
244/**
245 * Reads data via bus mastering, if enabled. If no bus mastering is available,
246 * this function does nothing and returns VINF_NOT_SUPPORTED.
247 *
248 * @return IPRT status code.
249 */
250int PCIDevPhysRead(PPCIDEVICE pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
251{
252 AssertPtrReturn(pPciDev, VERR_INVALID_POINTER);
253 AssertPtrReturn(pvBuf, VERR_INVALID_POINTER);
254 AssertReturn(cbRead, VERR_INVALID_PARAMETER);
255
256 if (!PCIDevIsBusmaster(pPciDev))
257 {
258#ifdef DEBUG
259 Log2(("%s: %RU16:%RU16: No bus master (anymore), skipping read %p (%z)\n", __FUNCTION__,
260 PCIDevGetVendorId(pPciDev), PCIDevGetDeviceId(pPciDev), pvBuf, cbRead));
261#endif
262 return VINF_NOT_SUPPORTED;
263 }
264
265 return PDMDevHlpPhysRead(pPciDev->pDevIns, GCPhys, pvBuf, cbRead);
266}
267
268/**
269 * Writes data via bus mastering, if enabled. If no bus mastering is available,
270 * this function does nothing and returns VINF_NOT_SUPPORTED.
271 *
272 * @return IPRT status code.
273 */
274int PCIDevPhysWrite(PPCIDEVICE pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
275{
276 AssertPtrReturn(pPciDev, VERR_INVALID_POINTER);
277 AssertPtrReturn(pvBuf, VERR_INVALID_POINTER);
278 AssertReturn(cbWrite, VERR_INVALID_PARAMETER);
279
280 if (!PCIDevIsBusmaster(pPciDev))
281 {
282#ifdef DEBUG
283 Log2(("%s: %RU16:%RU16: No bus master (anymore), skipping write %p (%z)\n", __FUNCTION__,
284 PCIDevGetVendorId(pPciDev), PCIDevGetDeviceId(pPciDev), pvBuf, cbWrite));
285#endif
286 return VINF_NOT_SUPPORTED;
287 }
288
289 return PDMDevHlpPhysWrite(pPciDev->pDevIns, GCPhys, pvBuf, cbWrite);
290}
291
292static void pci_update_mappings(PCIDevice *d)
293{
294 PPCIBUS pBus = d->Int.s.CTX_SUFF(pBus);
295 PCIIORegion *r;
296 int cmd, i;
297 uint32_t last_addr, new_addr, config_ofs;
298
299 cmd = RT_LE2H_U16(*(uint16_t *)(d->config + PCI_COMMAND));
300 for(i = 0; i < PCI_NUM_REGIONS; i++) {
301 r = &d->Int.s.aIORegions[i];
302 if (i == PCI_ROM_SLOT) {
303 config_ofs = 0x30;
304 } else {
305 config_ofs = 0x10 + i * 4;
306 }
307 if (r->size != 0) {
308 if (r->type & PCI_ADDRESS_SPACE_IO) {
309 if (cmd & PCI_COMMAND_IO) {
310 new_addr = RT_LE2H_U32(*(uint32_t *)(d->config +
311 config_ofs));
312 new_addr = new_addr & ~(r->size - 1);
313 last_addr = new_addr + r->size - 1;
314 /* NOTE: we have only 64K ioports on PC */
315 if (last_addr <= new_addr || new_addr == 0 ||
316 last_addr >= 0x10000) {
317 new_addr = ~0U;
318 }
319 } else {
320 new_addr = ~0U;
321 }
322 } else {
323 if (cmd & PCI_COMMAND_MEMORY) {
324 new_addr = RT_LE2H_U32(*(uint32_t *)(d->config +
325 config_ofs));
326 /* the ROM slot has a specific enable bit */
327 if (i == PCI_ROM_SLOT && !(new_addr & 1))
328 goto no_mem_map;
329 new_addr = new_addr & ~(r->size - 1);
330 last_addr = new_addr + r->size - 1;
331 /* NOTE: we do not support wrapping */
332 /* XXX: as we cannot support really dynamic
333 mappings, we handle specific values as invalid
334 mappings. */
335 if (last_addr <= new_addr || new_addr == 0 ||
336 last_addr == ~0U) {
337 new_addr = ~0U;
338 }
339 } else {
340 no_mem_map:
341 new_addr = ~0U;
342 }
343 }
344 /* now do the real mapping */
345 if (new_addr != r->addr) {
346 if (r->addr != ~0U) {
347 if (r->type & PCI_ADDRESS_SPACE_IO) {
348 int devclass;
349 /* NOTE: specific hack for IDE in PC case:
350 only one byte must be mapped. */
351 devclass = d->config[0x0a] | (d->config[0x0b] << 8);
352 if (devclass == 0x0101 && r->size == 4) {
353 int rc = PDMDevHlpIOPortDeregister(d->pDevIns, r->addr + 2, 1);
354 AssertRC(rc);
355 } else {
356 int rc = PDMDevHlpIOPortDeregister(d->pDevIns, r->addr, r->size);
357 AssertRC(rc);
358 }
359 } else {
360 RTGCPHYS GCPhysBase = r->addr;
361 int rc;
362 if (pBus->pPciHlpR3->pfnIsMMIO2Base(pBus->pDevInsR3, d->pDevIns, GCPhysBase))
363 {
364 /* unmap it. */
365 rc = r->map_func(d, i, NIL_RTGCPHYS, r->size, (PCIADDRESSSPACE)(r->type));
366 AssertRC(rc);
367 rc = PDMDevHlpMMIO2Unmap(d->pDevIns, i, GCPhysBase);
368 }
369 else
370 rc = PDMDevHlpMMIODeregister(d->pDevIns, GCPhysBase, r->size);
371 AssertMsgRC(rc, ("rc=%Rrc d=%s i=%d GCPhysBase=%RGp size=%#x\n", rc, d->name, i, GCPhysBase, r->size));
372 }
373 }
374 r->addr = new_addr;
375 if (r->addr != ~0U) {
376 int rc = r->map_func(d, i,
377 r->addr + (r->type & PCI_ADDRESS_SPACE_IO ? 0 : 0),
378 r->size, (PCIADDRESSSPACE)(r->type));
379 AssertRC(rc);
380 }
381 }
382 }
383 }
384}
385
386
387static DECLCALLBACK(uint32_t) pci_default_read_config(PCIDevice *d, uint32_t address, unsigned len)
388{
389 uint32_t val;
390 switch(len) {
391 case 1:
392 val = d->config[address];
393 break;
394 case 2:
395 val = RT_LE2H_U16(*(uint16_t *)(d->config + address));
396 break;
397 default:
398 case 4:
399 val = RT_LE2H_U32(*(uint32_t *)(d->config + address));
400 break;
401 }
402 return val;
403}
404
405static DECLCALLBACK(void) pci_default_write_config(PCIDevice *d, uint32_t address, uint32_t val, unsigned len)
406{
407 int can_write;
408 unsigned i;
409 uint32_t end, addr;
410
411 if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
412 (address >= 0x30 && address < 0x34))) {
413 PCIIORegion *r;
414 int reg;
415
416 if ( address >= 0x30 ) {
417 reg = PCI_ROM_SLOT;
418 }else{
419 reg = (address - 0x10) >> 2;
420 }
421 r = &d->Int.s.aIORegions[reg];
422 if (r->size == 0)
423 goto default_config;
424 /* compute the stored value */
425 if (reg == PCI_ROM_SLOT) {
426 /* keep ROM enable bit */
427 val &= (~(r->size - 1)) | 1;
428 } else {
429 val &= ~(r->size - 1);
430 val |= r->type;
431 }
432 *(uint32_t *)(d->config + address) = RT_H2LE_U32(val);
433 pci_update_mappings(d);
434 return;
435 }
436 default_config:
437 /* not efficient, but simple */
438 addr = address;
439 for(i = 0; i < len; i++) {
440 /* default read/write accesses */
441 switch(d->config[0x0e]) {
442 case 0x00: /* normal device */
443 case 0x80: /* multi-function device */
444 switch(addr) {
445 case 0x00:
446 case 0x01:
447 case 0x02:
448 case 0x03:
449 case 0x08:
450 case 0x09:
451 case 0x0a:
452 case 0x0b:
453 case 0x0e:
454 case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: /* base */
455 case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
456 case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
457 case 0x2c: case 0x2d: /* subsystem ID */
458 case 0x2e: case 0x2f: /* vendor ID */
459 case 0x30: case 0x31: case 0x32: case 0x33: /* rom */
460 case 0x34: /* Capabilities pointer. */
461 case 0x3d: /* Interrupt pin. */
462 can_write = 0;
463 break;
464 default:
465 can_write = 1;
466 break;
467 }
468 break;
469 default:
470 case 0x01: /* bridge */
471 switch(addr) {
472 case 0x00:
473 case 0x01:
474 case 0x02:
475 case 0x03:
476 case 0x08:
477 case 0x09:
478 case 0x0a:
479 case 0x0b:
480 case 0x0e:
481 case 0x38: case 0x39: case 0x3a: case 0x3b: /* rom */
482 case 0x3d:
483 can_write = 0;
484 break;
485 default:
486 can_write = 1;
487 break;
488 }
489 break;
490 }
491#ifdef VBOX
492 if (addr == 0x05) /* Command register, bits 8-15. */
493 {
494 /* don't change reserved bits (11-15) */
495 val &= UINT32_C(~0xf8);
496 d->config[addr] = val;
497 }
498 else if (addr == 0x06) /* Status register, bits 0-7. */
499 {
500 /* don't change read-only bits => actually all lower bits are read-only */
501 val &= UINT32_C(~0xff);
502 /* status register, low part: clear bits by writing a '1' to the corresponding bit */
503 d->config[addr] &= ~val;
504 }
505 else if (addr == 0x07) /* Status register, bits 8-15. */
506 {
507 /* don't change read-only bits */
508 val &= UINT32_C(~0x06);
509 /* status register, high part: clear bits by writing a '1' to the corresponding bit */
510 d->config[addr] &= ~val;
511 }
512 else
513#endif
514 if (can_write) {
515 d->config[addr] = val;
516 }
517 addr++;
518 val >>= 8;
519 }
520
521 end = address + len;
522 if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
523 /* if the command register is modified, we must modify the mappings */
524 pci_update_mappings(d);
525 }
526}
527
528#endif /* IN_RING3 */
529
530static int pci_data_write(PPCIGLOBALS pGlobals, uint32_t addr, uint32_t val, int len)
531{
532 uint8_t iBus, iDevice;
533 uint32_t config_addr;
534
535 Log(("pci_data_write: addr=%08x val=%08x len=%d\n", pGlobals->uConfigReg, val, len));
536
537 if (!(pGlobals->uConfigReg & (1 << 31))) {
538 return VINF_SUCCESS;
539 }
540 if ((pGlobals->uConfigReg & 0x3) != 0) {
541 return VINF_SUCCESS;
542 }
543 iBus = (pGlobals->uConfigReg >> 16) & 0xff;
544 iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
545 config_addr = (pGlobals->uConfigReg & 0xfc) | (addr & 3);
546 if (iBus != 0)
547 {
548 if (pGlobals->PciBus.cBridges)
549 {
550#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
551 PPCIDEVICE pBridgeDevice = pciFindBridge(&pGlobals->PciBus, iBus);
552 if (pBridgeDevice)
553 {
554 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
555 pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, val, len);
556 }
557#else
558 return VINF_IOM_R3_IOPORT_WRITE;
559#endif
560 }
561 }
562 else
563 {
564 R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
565 if (pci_dev)
566 {
567#ifdef IN_RING3
568 Log(("pci_config_write: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, val, len));
569 pci_dev->Int.s.pfnConfigWrite(pci_dev, config_addr, val, len);
570#else
571 return VINF_IOM_R3_IOPORT_WRITE;
572#endif
573 }
574 }
575 return VINF_SUCCESS;
576}
577
578static int pci_data_read(PPCIGLOBALS pGlobals, uint32_t addr, int len, uint32_t *pu32)
579{
580 uint8_t iBus, iDevice;
581 uint32_t config_addr;
582
583 *pu32 = 0xffffffff;
584
585 if (!(pGlobals->uConfigReg & (1 << 31)))
586 return VINF_SUCCESS;
587 if ((pGlobals->uConfigReg & 0x3) != 0)
588 return VINF_SUCCESS;
589 iBus = (pGlobals->uConfigReg >> 16) & 0xff;
590 iDevice = (pGlobals->uConfigReg >> 8) & 0xff;
591 config_addr = (pGlobals->uConfigReg & 0xfc) | (addr & 3);
592 if (iBus != 0)
593 {
594 if (pGlobals->PciBus.cBridges)
595 {
596#ifdef IN_RING3 /** @todo do lookup in R0/RC too! */
597 PPCIDEVICE pBridgeDevice = pciFindBridge(&pGlobals->PciBus, iBus);
598 if (pBridgeDevice)
599 {
600 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigRead);
601 *pu32 = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, config_addr, len);
602 }
603#else
604 NOREF(len);
605 return VINF_IOM_R3_IOPORT_READ;
606#endif
607 }
608 }
609 else
610 {
611 R3PTRTYPE(PCIDevice *) pci_dev = pGlobals->PciBus.devices[iDevice];
612 if (pci_dev)
613 {
614#ifdef IN_RING3
615 *pu32 = pci_dev->Int.s.pfnConfigRead(pci_dev, config_addr, len);
616 Log(("pci_config_read: %s: addr=%02x val=%08x len=%d\n", pci_dev->name, config_addr, *pu32, len));
617#else
618 NOREF(len);
619 return VINF_IOM_R3_IOPORT_READ;
620#endif
621 }
622 }
623
624 return VINF_SUCCESS;
625}
626
627
628
629/* return the global irq number corresponding to a given device irq
630 pin. We could also use the bus number to have a more precise
631 mapping.
632 This is the implementation note described in the PCI spec chapter 2.2.6 */
633static inline int pci_slot_get_pirq(uint8_t uDevFn, int irq_num)
634{
635 int slot_addend;
636 slot_addend = (uDevFn >> 3) - 1;
637 return (irq_num + slot_addend) & 3;
638}
639
640static inline int pci_slot_get_apic_pirq(uint8_t uDevFn, int irq_num)
641{
642 return (irq_num + (uDevFn >> 3)) & 7;
643}
644
645static inline int get_pci_irq_apic_level(PPCIGLOBALS pGlobals, int irq_num)
646{
647 return (pGlobals->pci_apic_irq_levels[irq_num] != 0);
648}
649
650static void apic_set_irq(PPCIBUS pBus, uint8_t uDevFn, PCIDevice *pPciDev, int irq_num1, int iLevel, int acpi_irq, uint32_t uTagSrc)
651{
652 /* This is only allowed to be called with a pointer to the host bus. */
653 AssertMsg(pBus->iBus == 0, ("iBus=%u\n", pBus->iBus));
654
655 if (acpi_irq == -1) {
656 int apic_irq, apic_level;
657 PPCIGLOBALS pGlobals = PCIBUS_2_PCIGLOBALS(pBus);
658 int irq_num = pci_slot_get_apic_pirq(uDevFn, irq_num1);
659
660 if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
661 ASMAtomicIncU32(&pGlobals->pci_apic_irq_levels[irq_num]);
662 else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
663 ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
664
665 apic_irq = irq_num + 0x10;
666 apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
667 Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d\n",
668 R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
669 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
670
671 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
672 ASMAtomicDecU32(&pGlobals->pci_apic_irq_levels[irq_num]);
673 pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
674 apic_level = get_pci_irq_apic_level(pGlobals, irq_num);
675 Log3(("apic_set_irq: %s: irq_num1=%d level=%d apic_irq=%d apic_level=%d irq_num1=%d (flop)\n",
676 R3STRING(pPciDev->name), irq_num1, iLevel, apic_irq, apic_level, irq_num));
677 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), apic_irq, apic_level, uTagSrc);
678 }
679 } else {
680 Log3(("apic_set_irq: %s: irq_num1=%d level=%d acpi_irq=%d\n",
681 R3STRING(pPciDev->name), irq_num1, iLevel, acpi_irq));
682 pBus->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pBus->CTX_SUFF(pDevIns), acpi_irq, iLevel, uTagSrc);
683 }
684}
685
686DECLINLINE(int) get_pci_irq_level(PPCIGLOBALS pGlobals, int irq_num)
687{
688 return (pGlobals->pci_irq_levels[irq_num] != 0);
689}
690
691/**
692 * Set the IRQ for a PCI device on the host bus - shared by host bus and bridge.
693 *
694 * @param pDevIns Device instance of the host PCI Bus.
695 * @param uDevFn The device number on the host bus which will raise the IRQ
696 * @param pPciDev The PCI device structure which raised the interrupt.
697 * @param iIrq IRQ number to set.
698 * @param iLevel IRQ level.
699 * @param uTagSrc The IRQ tag and source ID (for tracing).
700 * @remark uDevFn and pPciDev->devfn are not the same if the device is behind a bridge.
701 * In that case uDevFn will be the slot of the bridge which is needed to calculate the
702 * PIRQ value.
703 */
704static void pciSetIrqInternal(PPCIGLOBALS pGlobals, uint8_t uDevFn, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
705{
706 PPCIBUS pBus = &pGlobals->PciBus;
707 uint8_t *pbCfg = pGlobals->PIIX3State.dev.config;
708 const bool fIsAcpiDevice = pPciDev->config[2] == 0x13 && pPciDev->config[3] == 0x71;
709 /* If the two configuration space bytes at 0xde, 0xad are set to 0xbe, 0xef, a back door
710 * is opened to route PCI interrupts directly to the I/O APIC and bypass the PIC.
711 * See the \_SB_.PCI0._PRT method in vbox.dsl.
712 */
713 const bool fIsApicEnabled = pGlobals->fUseIoApic && pbCfg[0xde] == 0xbe && pbCfg[0xad] == 0xef;
714 int pic_irq, pic_level;
715
716 /* Check if the state changed. */
717 if (pPciDev->Int.s.uIrqPinState != iLevel)
718 {
719 pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
720
721 /* Send interrupt to I/O APIC only. */
722 if (fIsApicEnabled)
723 {
724 if (fIsAcpiDevice)
725 /*
726 * ACPI needs special treatment since SCI is hardwired and
727 * should not be affected by PCI IRQ routing tables at the
728 * same time SCI IRQ is shared in PCI sense hence this
729 * kludge (i.e. we fetch the hardwired value from ACPIs
730 * PCI device configuration space).
731 */
732 apic_set_irq(pBus, uDevFn, pPciDev, -1, iLevel, pPciDev->config[PCI_INTERRUPT_LINE], uTagSrc);
733 else
734 apic_set_irq(pBus, uDevFn, pPciDev, iIrq, iLevel, -1, uTagSrc);
735 return;
736 }
737
738 if (fIsAcpiDevice)
739 {
740 /* As per above treat ACPI in a special way */
741 pic_irq = pPciDev->config[PCI_INTERRUPT_LINE];
742 pGlobals->acpi_irq = pic_irq;
743 pGlobals->acpi_irq_level = iLevel & PDM_IRQ_LEVEL_HIGH;
744 }
745 else
746 {
747 int irq_num;
748 irq_num = pci_slot_get_pirq(uDevFn, iIrq);
749
750 if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
751 ASMAtomicIncU32(&pGlobals->pci_irq_levels[irq_num]);
752 else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
753 ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
754
755 /* now we change the pic irq level according to the piix irq mappings */
756 pic_irq = pbCfg[0x60 + irq_num];
757 if (pic_irq >= 16)
758 {
759 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
760 {
761 ASMAtomicDecU32(&pGlobals->pci_irq_levels[irq_num]);
762 pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
763 }
764
765 return;
766 }
767 }
768
769 /* the pic level is the logical OR of all the PCI irqs mapped to it */
770 pic_level = 0;
771 if (pic_irq == pbCfg[0x60])
772 pic_level |= get_pci_irq_level(pGlobals, 0);
773 if (pic_irq == pbCfg[0x61])
774 pic_level |= get_pci_irq_level(pGlobals, 1);
775 if (pic_irq == pbCfg[0x62])
776 pic_level |= get_pci_irq_level(pGlobals, 2);
777 if (pic_irq == pbCfg[0x63])
778 pic_level |= get_pci_irq_level(pGlobals, 3);
779 if (pic_irq == pGlobals->acpi_irq)
780 pic_level |= pGlobals->acpi_irq_level;
781
782 Log3(("pciSetIrq: %s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d uTagSrc=%#x\n",
783 R3STRING(pPciDev->name), iLevel, iIrq, pic_irq, pic_level, uTagSrc));
784 pBus->CTX_SUFF(pPciHlp)->pfnIsaSetIrq(pBus->CTX_SUFF(pDevIns), pic_irq, pic_level, uTagSrc);
785
786 /** @todo optimize pci irq flip-flop some rainy day. */
787 if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
788 pciSetIrqInternal(pGlobals, uDevFn, pPciDev, iIrq, PDM_IRQ_LEVEL_LOW, uTagSrc);
789 }
790}
791
792/**
793 * Set the IRQ for a PCI device on the host bus.
794 *
795 * @param pDevIns Device instance of the PCI Bus.
796 * @param pPciDev The PCI device structure.
797 * @param iIrq IRQ number to set.
798 * @param iLevel IRQ level.
799 * @param uTagSrc The IRQ tag and source ID (for tracing).
800 */
801PDMBOTHCBDECL(void) pciSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
802{
803 pciSetIrqInternal(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), pPciDev->devfn, pPciDev, iIrq, iLevel, uTagSrc);
804}
805
806#ifdef IN_RING3
807/**
808 * Finds a bridge on the bus which contains the destination bus.
809 *
810 * @return Pointer to the device instance data of the bus or
811 * NULL if no bridge was found.
812 * @param pBus Pointer to the bus to search on.
813 * @param iBus Destination bus number.
814 */
815DECLINLINE(PPCIDEVICE) pciFindBridge(PPCIBUS pBus, uint8_t iBus)
816{
817 /* Search for a fitting bridge. */
818 for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
819 {
820 /*
821 * Examine secondary and subordinate bus number.
822 * If the target bus is in the range we pass the request on to the bridge.
823 */
824 PPCIDEVICE pBridgeTemp = pBus->papBridgesR3[iBridge];
825 AssertMsg(pBridgeTemp && pciDevIsPci2PciBridge(pBridgeTemp),
826 ("Device is not a PCI bridge but on the list of PCI bridges\n"));
827
828 if ( iBus >= pBridgeTemp->config[VBOX_PCI_SECONDARY_BUS]
829 && iBus <= pBridgeTemp->config[VBOX_PCI_SUBORDINATE_BUS])
830 return pBridgeTemp;
831 }
832
833 /* Nothing found. */
834 return NULL;
835}
836
837static void piix3_reset(PIIX3State *d)
838{
839 uint8_t *pci_conf = d->dev.config;
840
841 pci_conf[0x04] = 0x07; /* master, memory and I/O */
842 pci_conf[0x05] = 0x00;
843 pci_conf[0x06] = 0x00;
844 pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
845 pci_conf[0x4c] = 0x4d;
846 pci_conf[0x4e] = 0x03;
847 pci_conf[0x4f] = 0x00;
848 pci_conf[0x60] = 0x80;
849 pci_conf[0x69] = 0x02;
850 pci_conf[0x70] = 0x80;
851 pci_conf[0x76] = 0x0c;
852 pci_conf[0x77] = 0x0c;
853 pci_conf[0x78] = 0x02;
854 pci_conf[0x79] = 0x00;
855 pci_conf[0x80] = 0x00;
856 pci_conf[0x82] = 0x02; /* Get rid of the Linux guest "Enabling Passive Release" PCI quirk warning. */
857 pci_conf[0xa0] = 0x08;
858 pci_conf[0xa0] = 0x08;
859 pci_conf[0xa2] = 0x00;
860 pci_conf[0xa3] = 0x00;
861 pci_conf[0xa4] = 0x00;
862 pci_conf[0xa5] = 0x00;
863 pci_conf[0xa6] = 0x00;
864 pci_conf[0xa7] = 0x00;
865 pci_conf[0xa8] = 0x0f;
866 pci_conf[0xaa] = 0x00;
867 pci_conf[0xab] = 0x00;
868 pci_conf[0xac] = 0x00;
869 pci_conf[0xae] = 0x00;
870}
871
872static void pci_config_writel(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
873{
874 pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
875 (uDevFn << 8) | addr;
876 pci_data_write(pGlobals, 0, val, 4);
877}
878
879static void pci_config_writew(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
880{
881 pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
882 (uDevFn << 8) | (addr & ~3);
883 pci_data_write(pGlobals, addr & 3, val, 2);
884}
885
886static void pci_config_writeb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr, uint32_t val)
887{
888 pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
889 (uDevFn << 8) | (addr & ~3);
890 pci_data_write(pGlobals, addr & 3, val, 1);
891}
892
893static uint32_t pci_config_readl(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
894{
895 pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
896 (uDevFn << 8) | addr;
897 uint32_t u32Val;
898 int rc = pci_data_read(pGlobals, 0, 4, &u32Val);
899 AssertRC(rc);
900 return u32Val;
901}
902
903static uint32_t pci_config_readw(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
904{
905 pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
906 (uDevFn << 8) | (addr & ~3);
907 uint32_t u32Val;
908 int rc = pci_data_read(pGlobals, addr & 3, 2, &u32Val);
909 AssertRC(rc);
910 return u32Val;
911}
912
913static uint32_t pci_config_readb(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint32_t addr)
914{
915 pGlobals->uConfigReg = 0x80000000 | (uBus << 16) |
916 (uDevFn << 8) | (addr & ~3);
917 uint32_t u32Val;
918 int rc = pci_data_read(pGlobals, addr & 3, 1, &u32Val);
919 AssertRC(rc);
920 return u32Val;
921}
922
923/* host irqs corresponding to PCI irqs A-D */
924static const uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; /* bird: added const */
925
926static void pci_set_io_region_addr(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, int region_num, uint32_t addr)
927{
928 uint16_t cmd;
929 uint32_t ofs;
930
931 if ( region_num == PCI_ROM_SLOT )
932 ofs = 0x30;
933 else
934 ofs = 0x10 + region_num * 4;
935
936 /* Read memory type first. */
937 uint8_t uRessourceType = pci_config_readb(pGlobals, uBus, uDevFn, ofs);
938
939 /* Read command register. */
940 cmd = pci_config_readw(pGlobals, uBus, uDevFn, PCI_COMMAND);
941 if ( region_num == PCI_ROM_SLOT )
942 cmd |= 2;
943 else if ((uRessourceType & 0x01) == 1) /* Test if region is I/O space. */
944 cmd |= 1; /* Enable I/O space access. */
945 else /* The region is MMIO. */
946 cmd |= 2; /* Enable MMIO access. */
947
948 /* Write address of the device. */
949 pci_config_writel(pGlobals, uBus, uDevFn, ofs, addr);
950
951 /* enable memory mappings */
952 pci_config_writew(pGlobals, uBus, uDevFn, PCI_COMMAND, cmd);
953}
954
955static void pci_bios_init_device(PPCIGLOBALS pGlobals, uint8_t uBus, uint8_t uDevFn, uint8_t cBridgeDepth, uint8_t *paBridgePositions)
956{
957 uint32_t *paddr;
958 int i, pin, pic_irq;
959 uint16_t devclass, vendor_id, device_id;
960
961 devclass = pci_config_readw(pGlobals, uBus, uDevFn, PCI_CLASS_DEVICE);
962 vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
963 device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
964
965 /* Check if device is present. */
966 if (vendor_id != 0xffff)
967 {
968 switch(devclass)
969 {
970 case 0x0101:
971 if ( (vendor_id == 0x8086)
972 && (device_id == 0x7010 || device_id == 0x7111 || device_id == 0x269e))
973 {
974 /* PIIX3, PIIX4 or ICH6 IDE */
975 pci_config_writew(pGlobals, uBus, uDevFn, 0x40, 0x8000); /* enable IDE0 */
976 pci_config_writew(pGlobals, uBus, uDevFn, 0x42, 0x8000); /* enable IDE1 */
977 goto default_map;
978 }
979 else
980 {
981 /* IDE: we map it as in ISA mode */
982 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x1f0);
983 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 1, 0x3f4);
984 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 2, 0x170);
985 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 3, 0x374);
986 }
987 break;
988 case 0x0300:
989 if (vendor_id != 0x80ee)
990 goto default_map;
991 /* VGA: map frame buffer to default Bochs VBE address */
992 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0xE0000000);
993 /*
994 * Legacy VGA I/O ports are implicitly decoded by a VGA class device. But
995 * only the framebuffer (i.e., a memory region) is explicitly registered via
996 * pci_set_io_region_addr, so I/O decoding must be enabled manually.
997 */
998 pci_config_writeb(pGlobals, uBus, uDevFn, PCI_COMMAND,
999 pci_config_readb(pGlobals, uBus, uDevFn, PCI_COMMAND)
1000 | 1 /* Enable I/O space access. */);
1001 break;
1002 case 0x0800:
1003 /* PIC */
1004 vendor_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_VENDOR_ID);
1005 device_id = pci_config_readw(pGlobals, uBus, uDevFn, PCI_DEVICE_ID);
1006 if (vendor_id == 0x1014)
1007 {
1008 /* IBM */
1009 if (device_id == 0x0046 || device_id == 0xFFFF)
1010 {
1011 /* MPIC & MPIC2 */
1012 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000 + 0x00040000);
1013 }
1014 }
1015 break;
1016 case 0xff00:
1017 if ( (vendor_id == 0x0106b)
1018 && (device_id == 0x0017 || device_id == 0x0022))
1019 {
1020 /* macio bridge */
1021 pci_set_io_region_addr(pGlobals, uBus, uDevFn, 0, 0x80800000);
1022 }
1023 break;
1024 case 0x0604:
1025 {
1026 /* Init PCI-to-PCI bridge. */
1027 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_PRIMARY_BUS, uBus);
1028
1029 AssertMsg(pGlobals->uBus < 255, ("Too many bridges on the bus\n"));
1030 pGlobals->uBus++;
1031 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SECONDARY_BUS, pGlobals->uBus);
1032 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, 0xff); /* Temporary until we know how many other bridges are behind this one. */
1033
1034 /* Add position of this bridge into the array. */
1035 paBridgePositions[cBridgeDepth+1] = (uDevFn >> 3);
1036
1037 /*
1038 * The I/O range for the bridge must be aligned to a 4KB boundary.
1039 * This does not change anything really as the access to the device is not going
1040 * through the bridge but we want to be compliant to the spec.
1041 */
1042 if ((pGlobals->pci_bios_io_addr % 4096) != 0)
1043 pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
1044 Log(("%s: Aligned I/O start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_io_addr));
1045 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_BASE, (pGlobals->pci_bios_io_addr >> 8) & 0xf0);
1046
1047 /* The MMIO range for the bridge must be aligned to a 1MB boundary. */
1048 if ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0)
1049 pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
1050 Log(("%s: Aligned MMIO start address. New address %#x\n", __FUNCTION__, pGlobals->pci_bios_mem_addr));
1051 pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_BASE, (pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xffff0));
1052
1053 /* Save values to compare later to. */
1054 uint32_t u32IoAddressBase = pGlobals->pci_bios_io_addr;
1055 uint32_t u32MMIOAddressBase = pGlobals->pci_bios_mem_addr;
1056
1057 /* Init devices behind the bridge and possibly other bridges as well. */
1058 for (int iDev = 0; iDev <= 255; iDev++)
1059 pci_bios_init_device(pGlobals, uBus + 1, iDev, cBridgeDepth + 1, paBridgePositions);
1060
1061 /* The number of bridges behind the this one is now available. */
1062 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_SUBORDINATE_BUS, pGlobals->uBus);
1063
1064 /*
1065 * Set I/O limit register. If there is no device with I/O space behind the bridge
1066 * we set a lower value than in the base register.
1067 * The result with a real bridge is that no I/O transactions are passed to the secondary
1068 * interface. Again this doesn't really matter here but we want to be compliant to the spec.
1069 */
1070 if ((u32IoAddressBase != pGlobals->pci_bios_io_addr) && ((pGlobals->pci_bios_io_addr % 4096) != 0))
1071 {
1072 /* The upper boundary must be one byte less than a 4KB boundary. */
1073 pGlobals->pci_bios_io_addr = RT_ALIGN_32(pGlobals->pci_bios_io_addr, 4*1024);
1074 }
1075 pci_config_writeb(pGlobals, uBus, uDevFn, VBOX_PCI_IO_LIMIT, ((pGlobals->pci_bios_io_addr >> 8) & 0xf0) - 1);
1076
1077 /* Same with the MMIO limit register but with 1MB boundary here. */
1078 if ((u32MMIOAddressBase != pGlobals->pci_bios_mem_addr) && ((pGlobals->pci_bios_mem_addr % (1024 * 1024)) != 0))
1079 {
1080 /* The upper boundary must be one byte less than a 1MB boundary. */
1081 pGlobals->pci_bios_mem_addr = RT_ALIGN_32(pGlobals->pci_bios_mem_addr, 1024*1024);
1082 }
1083 pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_MEMORY_LIMIT, ((pGlobals->pci_bios_mem_addr >> 16) & UINT32_C(0xfff0)) - 1);
1084
1085 /*
1086 * Set the prefetch base and limit registers. We currently have no device with a prefetchable region
1087 * which may be behind a bridge. That's why it is unconditionally disabled here atm by writing a higher value into
1088 * the base register than in the limit register.
1089 */
1090 pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_BASE, 0xfff0);
1091 pci_config_writew(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_MEMORY_LIMIT, 0x0);
1092 pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_BASE_UPPER32, 0x00);
1093 pci_config_writel(pGlobals, uBus, uDevFn, VBOX_PCI_PREF_LIMIT_UPPER32, 0x00);
1094 break;
1095 }
1096 default:
1097 default_map:
1098 {
1099 /* default memory mappings */
1100 /*
1101 * PCI_NUM_REGIONS is 7 because of the rom region but there are only 6 base address register defined by the PCI spec.
1102 * Leaving only PCI_NUM_REGIONS would cause reading another and enabling a memory region which does not exist.
1103 */
1104 for(i = 0; i < (PCI_NUM_REGIONS-1); i++)
1105 {
1106 uint32_t u32Size;
1107 uint8_t u8RessourceType;
1108 uint32_t u32Address = 0x10 + i * 4;
1109
1110 /* Calculate size. */
1111 u8RessourceType = pci_config_readb(pGlobals, uBus, uDevFn, u32Address);
1112 pci_config_writel(pGlobals, uBus, uDevFn, u32Address, UINT32_C(0xffffffff));
1113 u32Size = pci_config_readl(pGlobals, uBus, uDevFn, u32Address);
1114 /* Clear resource information depending on resource type. */
1115 if ((u8RessourceType & 0x01) == 1) /* I/O */
1116 u32Size &= ~(0x01);
1117 else /* MMIO */
1118 u32Size &= ~(0x0f);
1119
1120 /*
1121 * Invert all bits and add 1 to get size of the region.
1122 * (From PCI implementation note)
1123 */
1124 if (((u8RessourceType & 0x01) == 1) && (u32Size & UINT32_C(0xffff0000)) == 0)
1125 u32Size = (~(u32Size | UINT32_C(0xffff0000))) + 1;
1126 else
1127 u32Size = (~u32Size) + 1;
1128
1129 Log(("%s: Size of region %u for device %d on bus %d is %u\n", __FUNCTION__, i, uDevFn, uBus, u32Size));
1130
1131 if (u32Size)
1132 {
1133 if ((u8RessourceType & 0x01) == 1)
1134 paddr = &pGlobals->pci_bios_io_addr;
1135 else
1136 paddr = &pGlobals->pci_bios_mem_addr;
1137 *paddr = (*paddr + u32Size - 1) & ~(u32Size - 1);
1138 Log(("%s: Start address of %s region %u is %#x\n", __FUNCTION__, ((u8RessourceType & 0x01) == 1 ? "I/O" : "MMIO"), i, *paddr));
1139 pci_set_io_region_addr(pGlobals, uBus, uDevFn, i, *paddr);
1140 *paddr += u32Size;
1141 Log(("%s: New address is %#x\n", __FUNCTION__, *paddr));
1142 }
1143 }
1144 break;
1145 }
1146 }
1147
1148 /* map the interrupt */
1149 pin = pci_config_readb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_PIN);
1150 if (pin != 0)
1151 {
1152 uint8_t uBridgeDevFn = uDevFn;
1153 pin--;
1154
1155 /* We need to go up to the host bus to see which irq this device will assert there. */
1156 while (cBridgeDepth != 0)
1157 {
1158 /* Get the pin the device would assert on the bridge. */
1159 pin = ((uBridgeDevFn >> 3) + pin) & 3;
1160 uBridgeDevFn = paBridgePositions[cBridgeDepth];
1161 cBridgeDepth--;
1162 }
1163
1164 pin = pci_slot_get_pirq(uDevFn, pin);
1165 pic_irq = pci_irqs[pin];
1166 pci_config_writeb(pGlobals, uBus, uDevFn, PCI_INTERRUPT_LINE, pic_irq);
1167 }
1168 }
1169}
1170
1171#endif /* IN_RING3 */
1172
1173/* -=-=-=-=-=- wrappers -=-=-=-=-=- */
1174
1175/**
1176 * Port I/O Handler for PCI address OUT operations.
1177 *
1178 * @returns VBox status code.
1179 *
1180 * @param pDevIns The device instance.
1181 * @param pvUser User argument - ignored.
1182 * @param uPort Port number used for the IN operation.
1183 * @param u32 The value to output.
1184 * @param cb The value size in bytes.
1185 */
1186PDMBOTHCBDECL(int) pciIOPortAddressWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1187{
1188 Log(("pciIOPortAddressWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1189 NOREF(pvUser);
1190 if (cb == 4)
1191 {
1192 PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1193 PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
1194 pThis->uConfigReg = u32 & ~3; /* Bits 0-1 are reserved and we silently clear them */
1195 PCI_UNLOCK(pDevIns);
1196 }
1197 /* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1198 * Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1199 return VINF_SUCCESS;
1200}
1201
1202
1203/**
1204 * Port I/O Handler for PCI address IN operations.
1205 *
1206 * @returns VBox status code.
1207 *
1208 * @param pDevIns The device instance.
1209 * @param pvUser User argument - ignored.
1210 * @param uPort Port number used for the IN operation.
1211 * @param pu32 Where to store the result.
1212 * @param cb Number of bytes read.
1213 */
1214PDMBOTHCBDECL(int) pciIOPortAddressRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1215{
1216 NOREF(pvUser);
1217 if (cb == 4)
1218 {
1219 PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1220 PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
1221 *pu32 = pThis->uConfigReg;
1222 PCI_UNLOCK(pDevIns);
1223 Log(("pciIOPortAddressRead: Port=%#x cb=%d -> %#x\n", Port, cb, *pu32));
1224 return VINF_SUCCESS;
1225 }
1226 /* else: 440FX does "pass through to the bus" for other writes, what ever that means.
1227 * Linux probes for cmd640 using byte writes/reads during ide init. We'll just ignore it. */
1228 Log(("pciIOPortAddressRead: Port=%#x cb=%d VERR_IOM_IOPORT_UNUSED\n", Port, cb));
1229 return VERR_IOM_IOPORT_UNUSED;
1230}
1231
1232
1233/**
1234 * Port I/O Handler for PCI data OUT operations.
1235 *
1236 * @returns VBox status code.
1237 *
1238 * @param pDevIns The device instance.
1239 * @param pvUser User argument - ignored.
1240 * @param uPort Port number used for the IN operation.
1241 * @param u32 The value to output.
1242 * @param cb The value size in bytes.
1243 */
1244PDMBOTHCBDECL(int) pciIOPortDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1245{
1246 Log(("pciIOPortDataWrite: Port=%#x u32=%#x cb=%d\n", Port, u32, cb));
1247 NOREF(pvUser);
1248 int rc = VINF_SUCCESS;
1249 if (!(Port % cb))
1250 {
1251 PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_WRITE);
1252 rc = pci_data_write(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, u32, cb);
1253 PCI_UNLOCK(pDevIns);
1254 }
1255 else
1256 AssertMsgFailed(("Write to port %#x u32=%#x cb=%d\n", Port, u32, cb));
1257 return rc;
1258}
1259
1260
1261/**
1262 * Port I/O Handler for PCI data IN operations.
1263 *
1264 * @returns VBox status code.
1265 *
1266 * @param pDevIns The device instance.
1267 * @param pvUser User argument - ignored.
1268 * @param uPort Port number used for the IN operation.
1269 * @param pu32 Where to store the result.
1270 * @param cb Number of bytes read.
1271 */
1272PDMBOTHCBDECL(int) pciIOPortDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1273{
1274 NOREF(pvUser);
1275 if (!(Port % cb))
1276 {
1277 PCI_LOCK(pDevIns, VINF_IOM_R3_IOPORT_READ);
1278 int rc = pci_data_read(PDMINS_2_DATA(pDevIns, PPCIGLOBALS), Port, cb, pu32);
1279 PCI_UNLOCK(pDevIns);
1280 Log(("pciIOPortDataRead: Port=%#x cb=%#x -> %#x (%Rrc)\n", Port, cb, *pu32, rc));
1281 return rc;
1282 }
1283 AssertMsgFailed(("Read from port %#x cb=%d\n", Port, cb));
1284 return VERR_IOM_IOPORT_UNUSED;
1285}
1286
1287#ifdef IN_RING3
1288
1289/**
1290 * Saves a state of the PCI device.
1291 *
1292 * @returns VBox status code.
1293 * @param pDevIns Device instance of the PCI Bus.
1294 * @param pPciDev Pointer to PCI device.
1295 * @param pSSM The handle to save the state to.
1296 */
1297static DECLCALLBACK(int) pciGenericSaveExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
1298{
1299 NOREF(pDevIns);
1300 return SSMR3PutMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
1301}
1302
1303
1304/**
1305 * Loads a saved PCI device state.
1306 *
1307 * @returns VBox status code.
1308 * @param pDevIns Device instance of the PCI Bus.
1309 * @param pPciDev Pointer to PCI device.
1310 * @param pSSM The handle to the saved state.
1311 */
1312static DECLCALLBACK(int) pciGenericLoadExec(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PSSMHANDLE pSSM)
1313{
1314 NOREF(pDevIns);
1315 return SSMR3GetMem(pSSM, &pPciDev->config[0], sizeof(pPciDev->config));
1316}
1317
1318
1319/**
1320 * Common worker for pciR3SaveExec and pcibridgeR3SaveExec.
1321 *
1322 * @returns VBox status code.
1323 * @param pBus The bus to save.
1324 * @param pSSM The saved state handle.
1325 */
1326static int pciR3CommonSaveExec(PPCIBUS pBus, PSSMHANDLE pSSM)
1327{
1328 /*
1329 * Iterate thru all the devices.
1330 */
1331 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1332 {
1333 PPCIDEVICE pDev = pBus->devices[i];
1334 if (pDev)
1335 {
1336 SSMR3PutU32(pSSM, i);
1337 SSMR3PutMem(pSSM, pDev->config, sizeof(pDev->config));
1338
1339 int rc = SSMR3PutS32(pSSM, pDev->Int.s.uIrqPinState);
1340 if (RT_FAILURE(rc))
1341 return rc;
1342 }
1343 }
1344 return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
1345}
1346
1347
1348/**
1349 * Saves a state of the PCI device.
1350 *
1351 * @returns VBox status code.
1352 * @param pDevIns The device instance.
1353 * @param pPciDev Pointer to PCI device.
1354 * @param pSSM The handle to save the state to.
1355 */
1356static DECLCALLBACK(int) pciR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1357{
1358 uint32_t i;
1359 PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1360
1361 /*
1362 * Bus state data.
1363 */
1364 SSMR3PutU32(pSSM, pThis->uConfigReg);
1365 SSMR3PutBool(pSSM, pThis->fUseIoApic);
1366
1367 /*
1368 * Save IRQ states.
1369 */
1370 for (i = 0; i < PCI_IRQ_PINS; i++)
1371 SSMR3PutU32(pSSM, pThis->pci_irq_levels[i]);
1372 for (i = 0; i < PCI_APIC_IRQ_PINS; i++)
1373 SSMR3PutU32(pSSM, pThis->pci_apic_irq_levels[i]);
1374
1375 SSMR3PutU32(pSSM, pThis->acpi_irq_level);
1376 SSMR3PutS32(pSSM, pThis->acpi_irq);
1377
1378 SSMR3PutU32(pSSM, ~0); /* separator */
1379
1380 /*
1381 * Join paths with pcibridgeR3SaveExec.
1382 */
1383 return pciR3CommonSaveExec(&pThis->PciBus, pSSM);
1384}
1385
1386
1387/**
1388 * Common routine for restoring the config registers of a PCI device.
1389 *
1390 * @param pDev The PCI device.
1391 * @param pbSrcConfig The configuration register values to be loaded.
1392 * @param fIsBridge Whether this is a bridge device or not.
1393 */
1394static void pciR3CommonRestoreConfig(PPCIDEVICE pDev, uint8_t const *pbSrcConfig, bool fIsBridge)
1395{
1396 /*
1397 * This table defines the fields for normal devices and bridge devices, and
1398 * the order in which they need to be restored.
1399 */
1400 static const struct PciField
1401 {
1402 uint8_t off;
1403 uint8_t cb;
1404 uint8_t fWritable;
1405 uint8_t fBridge;
1406 const char *pszName;
1407 } s_aFields[] =
1408 {
1409 /* off,cb,fW,fB, pszName */
1410 { 0x00, 2, 0, 3, "VENDOR_ID" },
1411 { 0x02, 2, 0, 3, "DEVICE_ID" },
1412 { 0x06, 2, 1, 3, "STATUS" },
1413 { 0x08, 1, 0, 3, "REVISION_ID" },
1414 { 0x09, 1, 0, 3, "CLASS_PROG" },
1415 { 0x0a, 1, 0, 3, "CLASS_SUB" },
1416 { 0x0b, 1, 0, 3, "CLASS_BASE" },
1417 { 0x0c, 1, 0, 3, "CACHE_LINE_SIZE" }, // fWritable = ??
1418 { 0x0d, 1, 0, 3, "LATENCY_TIMER" }, // fWritable = ??
1419 { 0x0e, 1, 0, 3, "HEADER_TYPE" }, // fWritable = ??
1420 { 0x0f, 1, 0, 3, "BIST" }, // fWritable = ??
1421 { 0x10, 4, 1, 3, "BASE_ADDRESS_0" },
1422 { 0x14, 4, 1, 3, "BASE_ADDRESS_1" },
1423 { 0x18, 4, 1, 1, "BASE_ADDRESS_2" },
1424 { 0x18, 1, 1, 2, "PRIMARY_BUS" }, // fWritable = ??
1425 { 0x19, 1, 1, 2, "SECONDARY_BUS" }, // fWritable = ??
1426 { 0x1a, 1, 1, 2, "SUBORDINATE_BUS" }, // fWritable = ??
1427 { 0x1b, 1, 1, 2, "SEC_LATENCY_TIMER" }, // fWritable = ??
1428 { 0x1c, 4, 1, 1, "BASE_ADDRESS_3" },
1429 { 0x1c, 1, 1, 2, "IO_BASE" }, // fWritable = ??
1430 { 0x1d, 1, 1, 2, "IO_LIMIT" }, // fWritable = ??
1431 { 0x1e, 2, 1, 2, "SEC_STATUS" }, // fWritable = ??
1432 { 0x20, 4, 1, 1, "BASE_ADDRESS_4" },
1433 { 0x20, 2, 1, 2, "MEMORY_BASE" }, // fWritable = ??
1434 { 0x22, 2, 1, 2, "MEMORY_LIMIT" }, // fWritable = ??
1435 { 0x24, 4, 1, 1, "BASE_ADDRESS_5" },
1436 { 0x24, 2, 1, 2, "PREF_MEMORY_BASE" }, // fWritable = ??
1437 { 0x26, 2, 1, 2, "PREF_MEMORY_LIMIT" }, // fWritable = ??
1438 { 0x28, 4, 1, 1, "CARDBUS_CIS" }, // fWritable = ??
1439 { 0x28, 4, 1, 2, "PREF_BASE_UPPER32" }, // fWritable = ??
1440 { 0x2c, 2, 0, 1, "SUBSYSTEM_VENDOR_ID" },// fWritable = !?
1441 { 0x2c, 4, 1, 2, "PREF_LIMIT_UPPER32" },// fWritable = ??
1442 { 0x2e, 2, 0, 1, "SUBSYSTEM_ID" }, // fWritable = !?
1443 { 0x30, 4, 1, 1, "ROM_ADDRESS" }, // fWritable = ?!
1444 { 0x30, 2, 1, 2, "IO_BASE_UPPER16" }, // fWritable = ?!
1445 { 0x32, 2, 1, 2, "IO_LIMIT_UPPER16" }, // fWritable = ?!
1446 { 0x34, 4, 0, 3, "CAPABILITY_LIST" }, // fWritable = !? cb=!?
1447 { 0x38, 4, 1, 1, "???" }, // ???
1448 { 0x38, 4, 1, 2, "ROM_ADDRESS_BR" }, // fWritable = !? cb=!? fBridge=!?
1449 { 0x3c, 1, 1, 3, "INTERRUPT_LINE" }, // fBridge=??
1450 { 0x3d, 1, 0, 3, "INTERRUPT_PIN" }, // fBridge=??
1451 { 0x3e, 1, 0, 1, "MIN_GNT" }, // fWritable = !?
1452 { 0x3e, 1, 1, 2, "BRIDGE_CONTROL" }, // fWritable = !? cb=!?
1453 { 0x3f, 1, 1, 3, "MAX_LAT" }, // fWritable = !? fBridge=!?
1454 /* The COMMAND register must come last as it requires the *ADDRESS*
1455 registers to be restored before we pretent to change it from 0 to
1456 whatever value the guest assigned it. */
1457 { 0x04, 2, 1, 3, "COMMAND" },
1458 };
1459
1460#ifdef RT_STRICT
1461 /* Check that we've got full register coverage. */
1462 uint32_t bmDevice[0x40 / 32];
1463 uint32_t bmBridge[0x40 / 32];
1464 RT_ZERO(bmDevice);
1465 RT_ZERO(bmBridge);
1466 for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1467 {
1468 uint8_t off = s_aFields[i].off;
1469 uint8_t cb = s_aFields[i].cb;
1470 uint8_t f = s_aFields[i].fBridge;
1471 while (cb-- > 0)
1472 {
1473 if (f & 1) AssertMsg(!ASMBitTest(bmDevice, off), ("%#x\n", off));
1474 if (f & 2) AssertMsg(!ASMBitTest(bmBridge, off), ("%#x\n", off));
1475 if (f & 1) ASMBitSet(bmDevice, off);
1476 if (f & 2) ASMBitSet(bmBridge, off);
1477 off++;
1478 }
1479 }
1480 for (uint32_t off = 0; off < 0x40; off++)
1481 {
1482 AssertMsg(ASMBitTest(bmDevice, off), ("%#x\n", off));
1483 AssertMsg(ASMBitTest(bmBridge, off), ("%#x\n", off));
1484 }
1485#endif
1486
1487 /*
1488 * Loop thru the fields covering the 64 bytes of standard registers.
1489 */
1490 uint8_t const fBridge = fIsBridge ? 2 : 1;
1491 uint8_t *pbDstConfig = &pDev->config[0];
1492 for (uint32_t i = 0; i < RT_ELEMENTS(s_aFields); i++)
1493 if (s_aFields[i].fBridge & fBridge)
1494 {
1495 uint8_t const off = s_aFields[i].off;
1496 uint8_t const cb = s_aFields[i].cb;
1497 uint32_t u32Src;
1498 uint32_t u32Dst;
1499 switch (cb)
1500 {
1501 case 1:
1502 u32Src = pbSrcConfig[off];
1503 u32Dst = pbDstConfig[off];
1504 break;
1505 case 2:
1506 u32Src = *(uint16_t const *)&pbSrcConfig[off];
1507 u32Dst = *(uint16_t const *)&pbDstConfig[off];
1508 break;
1509 case 4:
1510 u32Src = *(uint32_t const *)&pbSrcConfig[off];
1511 u32Dst = *(uint32_t const *)&pbDstConfig[off];
1512 break;
1513 default:
1514 AssertFailed();
1515 continue;
1516 }
1517
1518 if ( u32Src != u32Dst
1519 || off == VBOX_PCI_COMMAND)
1520 {
1521 if (u32Src != u32Dst)
1522 {
1523 if (!s_aFields[i].fWritable)
1524 LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x - !READ ONLY!\n",
1525 pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1526 else
1527 LogRel(("PCI: %8s/%u: %2u-bit field %s: %x -> %x\n",
1528 pDev->name, pDev->pDevIns->iInstance, cb*8, s_aFields[i].pszName, u32Dst, u32Src));
1529 }
1530 if (off == VBOX_PCI_COMMAND)
1531 PCIDevSetCommand(pDev, 0); /* For remapping, see pciR3CommonLoadExec. */
1532 pDev->Int.s.pfnConfigWrite(pDev, off, u32Src, cb);
1533 }
1534 }
1535
1536 /*
1537 * The device dependent registers.
1538 *
1539 * We will not use ConfigWrite here as we have no clue about the size
1540 * of the registers, so the device is responsible for correctly
1541 * restoring functionality governed by these registers.
1542 */
1543 for (uint32_t off = 0x40; off < sizeof(pDev->config); off++)
1544 if (pbDstConfig[off] != pbSrcConfig[off])
1545 {
1546 LogRel(("PCI: %8s/%u: register %02x: %02x -> %02x\n",
1547 pDev->name, pDev->pDevIns->iInstance, off, pbDstConfig[off], pbSrcConfig[off])); /** @todo make this Log() later. */
1548 pbDstConfig[off] = pbSrcConfig[off];
1549 }
1550}
1551
1552
1553/**
1554 * Common worker for pciR3LoadExec and pcibridgeR3LoadExec.
1555 *
1556 * @returns VBox status code.
1557 * @param pBus The bus which data is being loaded.
1558 * @param pSSM The saved state handle.
1559 * @param uVersion The data version.
1560 * @param uPass The pass.
1561 */
1562static DECLCALLBACK(int) pciR3CommonLoadExec(PPCIBUS pBus, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1563{
1564 uint32_t u32;
1565 uint32_t i;
1566 int rc;
1567
1568 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1569
1570 /*
1571 * Iterate thru all the devices and write 0 to the COMMAND register so
1572 * that all the memory is unmapped before we start restoring the saved
1573 * mapping locations.
1574 *
1575 * The register value is restored afterwards so we can do proper
1576 * LogRels in pciR3CommonRestoreConfig.
1577 */
1578 for (i = 0; i < RT_ELEMENTS(pBus->devices); i++)
1579 {
1580 PPCIDEVICE pDev = pBus->devices[i];
1581 if (pDev)
1582 {
1583 uint16_t u16 = PCIDevGetCommand(pDev);
1584 pDev->Int.s.pfnConfigWrite(pDev, VBOX_PCI_COMMAND, 0, 2);
1585 PCIDevSetCommand(pDev, u16);
1586 Assert(PCIDevGetCommand(pDev) == u16);
1587 }
1588 }
1589
1590 /*
1591 * Iterate all the devices.
1592 */
1593 for (i = 0;; i++)
1594 {
1595 PCIDEVICE DevTmp;
1596 PPCIDEVICE pDev;
1597
1598 /* index / terminator */
1599 rc = SSMR3GetU32(pSSM, &u32);
1600 if (RT_FAILURE(rc))
1601 return rc;
1602 if (u32 == (uint32_t)~0)
1603 break;
1604 if ( u32 >= RT_ELEMENTS(pBus->devices)
1605 || u32 < i)
1606 {
1607 AssertMsgFailed(("u32=%#x i=%#x\n", u32, i));
1608 return rc;
1609 }
1610
1611 /* skip forward to the device checking that no new devices are present. */
1612 for (; i < u32; i++)
1613 {
1614 if (pBus->devices[i])
1615 {
1616 LogRel(("New device in slot %#x, %s (vendor=%#06x device=%#06x)\n", i, pBus->devices[i]->name,
1617 PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i])));
1618 if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1619 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("New device in slot %#x, %s (vendor=%#06x device=%#06x)"),
1620 i, pBus->devices[i]->name, PCIDevGetVendorId(pBus->devices[i]), PCIDevGetDeviceId(pBus->devices[i]));
1621 }
1622 }
1623
1624 /* get the data */
1625 DevTmp.Int.s.uIrqPinState = ~0; /* Invalid value in case we have an older saved state to force a state change in pciSetIrq. */
1626 SSMR3GetMem(pSSM, DevTmp.config, sizeof(DevTmp.config));
1627 if (uVersion < 3)
1628 {
1629 int32_t i32Temp;
1630 /* Irq value not needed anymore. */
1631 rc = SSMR3GetS32(pSSM, &i32Temp);
1632 if (RT_FAILURE(rc))
1633 return rc;
1634 }
1635 else
1636 {
1637 rc = SSMR3GetS32(pSSM, &DevTmp.Int.s.uIrqPinState);
1638 if (RT_FAILURE(rc))
1639 return rc;
1640 }
1641
1642 /* check that it's still around. */
1643 pDev = pBus->devices[i];
1644 if (!pDev)
1645 {
1646 LogRel(("Device in slot %#x has been removed! vendor=%#06x device=%#06x\n", i,
1647 PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp)));
1648 if (SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT)
1649 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x has been removed! vendor=%#06x device=%#06x"),
1650 i, PCIDevGetVendorId(&DevTmp), PCIDevGetDeviceId(&DevTmp));
1651 continue;
1652 }
1653
1654 /* match the vendor id assuming that this will never be changed. */
1655 if ( DevTmp.config[0] != pDev->config[0]
1656 || DevTmp.config[1] != pDev->config[1])
1657 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Device in slot %#x (%s) vendor id mismatch! saved=%.4Rhxs current=%.4Rhxs"),
1658 i, pDev->name, DevTmp.config, pDev->config);
1659
1660 /* commit the loaded device config. */
1661 pciR3CommonRestoreConfig(pDev, &DevTmp.config[0], false ); /** @todo fix bridge fun! */
1662
1663 pDev->Int.s.uIrqPinState = DevTmp.Int.s.uIrqPinState;
1664 }
1665
1666 return VINF_SUCCESS;
1667}
1668
1669
1670/**
1671 * Loads a saved PCI device state.
1672 *
1673 * @returns VBox status code.
1674 * @param pDevIns The device instance.
1675 * @param pSSM The handle to the saved state.
1676 * @param uVersion The data unit version number.
1677 * @param uPass The data pass.
1678 */
1679static DECLCALLBACK(int) pciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1680{
1681 PPCIGLOBALS pThis = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1682 PPCIBUS pBus = &pThis->PciBus;
1683 uint32_t u32;
1684 int rc;
1685
1686 /*
1687 * Check the version.
1688 */
1689 if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
1690 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1691 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
1692
1693 /*
1694 * Bus state data.
1695 */
1696 SSMR3GetU32(pSSM, &pThis->uConfigReg);
1697 if (uVersion > 1)
1698 SSMR3GetBool(pSSM, &pThis->fUseIoApic);
1699
1700 /* Load IRQ states. */
1701 if (uVersion > 2)
1702 {
1703 for (uint8_t i = 0; i < PCI_IRQ_PINS; i++)
1704 SSMR3GetU32(pSSM, (uint32_t *)&pThis->pci_irq_levels[i]);
1705 for (uint8_t i = 0; i < PCI_APIC_IRQ_PINS; i++)
1706 SSMR3GetU32(pSSM, (uint32_t *)&pThis->pci_apic_irq_levels[i]);
1707
1708 SSMR3GetU32(pSSM, &pThis->acpi_irq_level);
1709 SSMR3GetS32(pSSM, &pThis->acpi_irq);
1710 }
1711
1712 /* separator */
1713 rc = SSMR3GetU32(pSSM, &u32);
1714 if (RT_FAILURE(rc))
1715 return rc;
1716 if (u32 != (uint32_t)~0)
1717 AssertMsgFailedReturn(("u32=%#x\n", u32), rc);
1718
1719 /*
1720 * The devices.
1721 */
1722 return pciR3CommonLoadExec(pBus, pSSM, uVersion, uPass);
1723}
1724
1725
1726/* -=-=-=-=-=- real code -=-=-=-=-=- */
1727
1728/**
1729 * Registers the device with the specified PCI bus.
1730 *
1731 * @returns VBox status code.
1732 * @param pBus The bus to register with.
1733 * @param iDev The PCI device ordinal.
1734 * @param pPciDev The PCI device structure.
1735 * @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
1736 */
1737static int pciRegisterInternal(PPCIBUS pBus, int iDev, PPCIDEVICE pPciDev, const char *pszName)
1738{
1739 /*
1740 * Find device slot.
1741 */
1742 if (iDev < 0)
1743 {
1744 /*
1745 * Special check for the IDE controller which is our function 1 device
1746 * before searching.
1747 */
1748 if ( !strcmp(pszName, "piix3ide")
1749 && !pBus->devices[9])
1750 iDev = 9;
1751 /* LPC bus expected to be there by some guests, better make an additional argument to PDM
1752 device helpers, but requires significant rewrite */
1753 else if (!strcmp(pszName, "lpc")
1754 && !pBus->devices[0xf8])
1755 iDev = 0xf8;
1756 else
1757 {
1758 Assert(!(pBus->iDevSearch % 8));
1759 for (iDev = pBus->iDevSearch; iDev < (int)RT_ELEMENTS(pBus->devices); iDev += 8)
1760 if ( !pBus->devices[iDev]
1761 && !pBus->devices[iDev + 1]
1762 && !pBus->devices[iDev + 2]
1763 && !pBus->devices[iDev + 3]
1764 && !pBus->devices[iDev + 4]
1765 && !pBus->devices[iDev + 5]
1766 && !pBus->devices[iDev + 6]
1767 && !pBus->devices[iDev + 7])
1768 break;
1769 if (iDev >= (int)RT_ELEMENTS(pBus->devices))
1770 {
1771 AssertMsgFailed(("Couldn't find free spot!\n"));
1772 return VERR_PDM_TOO_PCI_MANY_DEVICES;
1773 }
1774 }
1775 pciDevClearRequestedDevfunc(pPciDev);
1776 }
1777 else
1778 {
1779 /*
1780 * An explicit request.
1781 *
1782 * If the slot is occupied we'll have to relocate the device
1783 * currently occupying it first. This can only be done if the
1784 * existing device wasn't explicitly assigned. Also we limit
1785 * ourselves to function 0 devices.
1786 *
1787 * If you start setting devices + function in the
1788 * config, do it for all pci devices!
1789 */
1790 //AssertReleaseMsg(iDev > 8 || pBus->iBus != 0, ("iDev=%d pszName=%s\n", iDev, pszName));
1791 if (pBus->devices[iDev])
1792 {
1793 int iDevRel;
1794 AssertReleaseMsg(!(iDev % 8), ("PCI Configuration Conflict! iDev=%d pszName=%s clashes with %s\n",
1795 iDev, pszName, pBus->devices[iDev]->name));
1796 if ( pciDevIsRequestedDevfunc(pBus->devices[iDev])
1797 || (pBus->devices[iDev + 1] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 1]))
1798 || (pBus->devices[iDev + 2] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 2]))
1799 || (pBus->devices[iDev + 3] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 3]))
1800 || (pBus->devices[iDev + 4] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 4]))
1801 || (pBus->devices[iDev + 5] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 5]))
1802 || (pBus->devices[iDev + 6] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 6]))
1803 || (pBus->devices[iDev + 7] && pciDevIsRequestedDevfunc(pBus->devices[iDev + 7])))
1804 {
1805 AssertReleaseMsgFailed(("Configuration error:'%s' and '%s' are both configured as device %d\n",
1806 pszName, pBus->devices[iDev]->name, iDev));
1807 return VERR_INTERNAL_ERROR;
1808 }
1809
1810 /* Find free slot for the device(s) we're moving and move them. */
1811 for (iDevRel = pBus->iDevSearch; iDevRel < (int)RT_ELEMENTS(pBus->devices); iDevRel += 8)
1812 {
1813 if ( !pBus->devices[iDevRel]
1814 && !pBus->devices[iDevRel + 1]
1815 && !pBus->devices[iDevRel + 2]
1816 && !pBus->devices[iDevRel + 3]
1817 && !pBus->devices[iDevRel + 4]
1818 && !pBus->devices[iDevRel + 5]
1819 && !pBus->devices[iDevRel + 6]
1820 && !pBus->devices[iDevRel + 7])
1821 {
1822 int i = 0;
1823 for (i = 0; i < 8; i++)
1824 {
1825 if (!pBus->devices[iDev + i])
1826 continue;
1827 Log(("PCI: relocating '%s' from slot %#x to %#x\n", pBus->devices[iDev + i]->name, iDev + i, iDevRel + i));
1828 pBus->devices[iDevRel + i] = pBus->devices[iDev + i];
1829 pBus->devices[iDevRel + i]->devfn = iDevRel + i;
1830 pBus->devices[iDev + i] = NULL;
1831 }
1832 }
1833 }
1834 if (pBus->devices[iDev])
1835 {
1836 AssertMsgFailed(("Couldn't find free spot!\n"));
1837 return VERR_PDM_TOO_PCI_MANY_DEVICES;
1838 }
1839 } /* if conflict */
1840 pciDevSetRequestedDevfunc(pPciDev);
1841 }
1842
1843 Assert(!pBus->devices[iDev]);
1844 pPciDev->devfn = iDev;
1845 pPciDev->name = pszName;
1846 pPciDev->Int.s.pBusR3 = pBus;
1847 pPciDev->Int.s.pBusR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1848 pPciDev->Int.s.pBusRC = MMHyperR3ToRC(PDMDevHlpGetVM(pBus->CTX_SUFF(pDevIns)), pBus);
1849 pPciDev->Int.s.pfnConfigRead = pci_default_read_config;
1850 pPciDev->Int.s.pfnConfigWrite = pci_default_write_config;
1851 pBus->devices[iDev] = pPciDev;
1852 if (pciDevIsPci2PciBridge(pPciDev))
1853 {
1854 AssertMsg(pBus->cBridges < RT_ELEMENTS(pBus->devices), ("Number of bridges exceeds the number of possible devices on the bus\n"));
1855 AssertMsg(pPciDev->Int.s.pfnBridgeConfigRead && pPciDev->Int.s.pfnBridgeConfigWrite,
1856 ("device is a bridge but does not implement read/write functions\n"));
1857 pBus->papBridgesR3[pBus->cBridges] = pPciDev;
1858 pBus->cBridges++;
1859 }
1860
1861 Log(("PCI: Registered device %d function %d (%#x) '%s'.\n",
1862 iDev >> 3, iDev & 7, 0x80000000 | (iDev << 8), pszName));
1863
1864 return VINF_SUCCESS;
1865}
1866
1867
1868/**
1869 * Registers the device with the default PCI bus.
1870 *
1871 * @returns VBox status code.
1872 * @param pDevIns Device instance of the PCI Bus.
1873 * @param pPciDev The PCI device structure.
1874 * Any PCI enabled device must keep this in it's instance data!
1875 * Fill in the PCI data config before registration, please.
1876 * @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
1877 * @param iDev The PCI device number. Use a negative value for auto assigning one.
1878 */
1879static DECLCALLBACK(int) pciRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
1880{
1881 PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
1882
1883 /*
1884 * Check input.
1885 */
1886 if ( !pszName
1887 || !pPciDev
1888 || iDev >= (int)RT_ELEMENTS(pBus->devices)
1889 || (iDev >= 0 && iDev <= 8))
1890 {
1891 AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
1892 return VERR_INVALID_PARAMETER;
1893 }
1894
1895 /*
1896 * Register the device.
1897 */
1898 return pciRegisterInternal(pBus, iDev, pPciDev, pszName);
1899}
1900
1901
1902static DECLCALLBACK(int) pciIORegionRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1903{
1904 NOREF(pDevIns);
1905
1906 /*
1907 * Validate.
1908 */
1909 AssertMsgReturn( enmType == PCI_ADDRESS_SPACE_MEM
1910 || enmType == PCI_ADDRESS_SPACE_IO
1911 || enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH,
1912 ("Invalid enmType=%#x? Or was this a bitmask after all...\n", enmType),
1913 VERR_INVALID_PARAMETER);
1914 AssertMsgReturn((unsigned)iRegion < PCI_NUM_REGIONS,
1915 ("Invalid iRegion=%d PCI_NUM_REGIONS=%d\n", iRegion, PCI_NUM_REGIONS),
1916 VERR_INVALID_PARAMETER);
1917 int iLastSet = ASMBitLastSetU32(cbRegion);
1918 AssertMsgReturn( iLastSet != 0
1919 && RT_BIT_32(iLastSet - 1) == cbRegion,
1920 ("Invalid cbRegion=%#x iLastSet=%#x (not a power of 2 or 0)\n", cbRegion, iLastSet),
1921 VERR_INVALID_PARAMETER);
1922
1923 /*
1924 * Register the I/O region.
1925 */
1926 PPCIIOREGION pRegion = &pPciDev->Int.s.aIORegions[iRegion];
1927 pRegion->addr = ~0U;
1928 pRegion->size = cbRegion;
1929 pRegion->type = enmType;
1930 pRegion->map_func = pfnCallback;
1931
1932 /* Set type in the config space. */
1933 uint32_t u32Address = 0x10 + iRegion * 4;
1934 uint32_t u32Value = (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH ? (1 << 3) : 0)
1935 | (enmType == PCI_ADDRESS_SPACE_IO ? 1 : 0);
1936 *(uint32_t *)(pPciDev->config + u32Address) = RT_H2LE_U32(u32Value);
1937
1938 return VINF_SUCCESS;
1939}
1940
1941
1942/**
1943 * @copydoc PDMPCIBUSREG::pfnSetConfigCallbacksR3
1944 */
1945static DECLCALLBACK(void) pciSetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1946 PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1947{
1948 NOREF(pDevIns);
1949
1950 if (ppfnReadOld)
1951 *ppfnReadOld = pPciDev->Int.s.pfnConfigRead;
1952 pPciDev->Int.s.pfnConfigRead = pfnRead;
1953
1954 if (ppfnWriteOld)
1955 *ppfnWriteOld = pPciDev->Int.s.pfnConfigWrite;
1956 pPciDev->Int.s.pfnConfigWrite = pfnWrite;
1957}
1958
1959
1960/**
1961 * Called to perform the job of the bios.
1962 *
1963 * @returns VBox status.
1964 * @param pDevIns Device instance of the first bus.
1965 */
1966static DECLCALLBACK(int) pciFakePCIBIOS(PPDMDEVINS pDevIns)
1967{
1968 unsigned i;
1969 uint8_t elcr[2] = {0, 0};
1970 PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
1971 PVM pVM = PDMDevHlpGetVM(pDevIns);
1972 Assert(pVM);
1973
1974 /*
1975 * Set the start addresses.
1976 */
1977 pGlobals->pci_bios_io_addr = 0xd000;
1978 pGlobals->pci_bios_mem_addr = UINT32_C(0xf0000000);
1979 pGlobals->uBus = 0;
1980
1981 /*
1982 * Activate IRQ mappings.
1983 */
1984 for (i = 0; i < 4; i++)
1985 {
1986 uint8_t irq = pci_irqs[i];
1987 /* Set to trigger level. */
1988 elcr[irq >> 3] |= (1 << (irq & 7));
1989 /* Activate irq remapping in PIIX3. */
1990 pci_config_writeb(pGlobals, 0, pGlobals->PIIX3State.dev.devfn, 0x60 + i, irq);
1991 }
1992
1993 /* Tell to the PIC. */
1994 VBOXSTRICTRC rcStrict = IOMIOPortWrite(pVM, 0x4d0, elcr[0], sizeof(uint8_t));
1995 if (rcStrict == VINF_SUCCESS)
1996 rcStrict = IOMIOPortWrite(pVM, 0x4d1, elcr[1], sizeof(uint8_t));
1997 if (rcStrict != VINF_SUCCESS)
1998 {
1999 AssertMsgFailed(("Writing to PIC failed! rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
2000 return RT_SUCCESS(rcStrict) ? VERR_INTERNAL_ERROR : VBOXSTRICTRC_VAL(rcStrict);
2001 }
2002
2003 /*
2004 * Init the devices.
2005 */
2006 for (i = 0; i < 256; i++)
2007 {
2008 uint8_t aBridgePositions[256];
2009
2010 memset(aBridgePositions, 0, sizeof(aBridgePositions));
2011 Log2(("PCI: Initializing device %d (%#x)\n",
2012 i, 0x80000000 | (i << 8)));
2013 pci_bios_init_device(pGlobals, 0, i, 0, aBridgePositions);
2014 }
2015
2016 return VINF_SUCCESS;
2017}
2018
2019/**
2020 * Info handler, device version.
2021 *
2022 * @param pDevIns Device instance which registered the info.
2023 * @param pHlp Callback functions for doing output.
2024 * @param pszArgs Argument string. Optional and specific to the handler.
2025 */
2026static DECLCALLBACK(void) pciIrqInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2027{
2028 PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2029 uint16_t router;
2030 uint8_t irq_map;
2031 int i;
2032 NOREF(pszArgs);
2033
2034 router = pGlobals->PIIX3State.dev.devfn;
2035 pHlp->pfnPrintf(pHlp, "PCI interrupt router at: %02X:%02X:%X\n",
2036 router >> 8, (router >> 3) & 0x1f, router & 0x7);
2037
2038 for (i = 0; i < 4; ++i)
2039 {
2040 irq_map = pci_config_readb(pGlobals, 0, router, 0x60 + i);
2041 if (irq_map & 0x80)
2042 pHlp->pfnPrintf(pHlp, "PIRQ%c disabled\n", 'A' + i);
2043 else
2044 pHlp->pfnPrintf(pHlp, "PIRQ%c -> IRQ%d\n", 'A' + i, irq_map & 0xf);
2045 }
2046}
2047
2048static void printIndent(PCDBGFINFOHLP pHlp, int iIndent)
2049{
2050 for (int i = 0; i < iIndent; i++)
2051 {
2052 pHlp->pfnPrintf(pHlp, " ");
2053 }
2054}
2055
2056static void pciBusInfo(PPCIBUS pBus, PCDBGFINFOHLP pHlp, int iIndent, bool fRegisters)
2057{
2058 for (uint32_t iDev = 0; iDev < RT_ELEMENTS(pBus->devices); iDev++)
2059 {
2060 PPCIDEVICE pPciDev = pBus->devices[iDev];
2061 if (pPciDev != NULL)
2062 {
2063 printIndent(pHlp, iIndent);
2064
2065 /*
2066 * For passthrough devices MSI/MSI-X mostly reflects the way interrupts delivered to the guest,
2067 * as host driver handles real devices interrupts.
2068 */
2069 pHlp->pfnPrintf(pHlp, "%02x:%02x:%02x %s%s: %04x-%04x%s%s",
2070 pBus->iBus, (iDev >> 3) & 0xff, iDev & 0x7,
2071 pPciDev->name,
2072 pciDevIsPassthrough(pPciDev) ? " (PASSTHROUGH)" : "",
2073 PCIDevGetWord(pPciDev, VBOX_PCI_VENDOR_ID), PCIDevGetWord(pPciDev, VBOX_PCI_DEVICE_ID),
2074 pciDevIsMsiCapable(pPciDev) ? " MSI" : "",
2075 pciDevIsMsixCapable(pPciDev) ? " MSI-X" : ""
2076 );
2077 if (PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN) != 0)
2078 pHlp->pfnPrintf(pHlp, " IRQ%d", PCIDevGetByte(pPciDev, VBOX_PCI_INTERRUPT_LINE));
2079
2080 pHlp->pfnPrintf(pHlp, "\n");
2081
2082 uint16_t iCmd = PCIDevGetWord(pPciDev, VBOX_PCI_COMMAND);
2083 if ((iCmd & (VBOX_PCI_COMMAND_IO | VBOX_PCI_COMMAND_MEMORY)) != 0)
2084 {
2085 for (int iRegion = 0; iRegion < PCI_NUM_REGIONS; iRegion++)
2086 {
2087 PCIIORegion* pRegion = &pPciDev->Int.s.aIORegions[iRegion];
2088 uint64_t iRegionSize = pRegion->size;
2089
2090 if (iRegionSize == 0)
2091 continue;
2092
2093 uint32_t u32Addr = PCIDevGetDWord(pPciDev, PCIDevGetRegionReg(iRegion));
2094 const char * pszDesc;
2095 char szDescBuf[128];
2096
2097 bool f64Bit = !!(pRegion->type & PCI_ADDRESS_SPACE_BAR64);
2098 if (pRegion->type & PCI_ADDRESS_SPACE_IO)
2099 {
2100 pszDesc = "IO";
2101 u32Addr &= ~0x3;
2102 }
2103 else
2104 {
2105 RTStrPrintf(szDescBuf, sizeof(szDescBuf), "MMIO%s%s",
2106 f64Bit ? "64" : "32",
2107 (pRegion->type & PCI_ADDRESS_SPACE_MEM_PREFETCH) ? " PREFETCH" : "");
2108 pszDesc = szDescBuf;
2109 u32Addr &= ~0xf;
2110 }
2111
2112 printIndent(pHlp, iIndent + 2);
2113 pHlp->pfnPrintf(pHlp, "%s region #%d: %x..%x\n",
2114 pszDesc, iRegion, u32Addr, u32Addr+iRegionSize);
2115 if (f64Bit)
2116 iRegion++;
2117 }
2118 }
2119
2120 printIndent(pHlp, iIndent + 2);
2121 uint16_t iStatus = PCIDevGetWord(pPciDev, VBOX_PCI_STATUS);
2122 pHlp->pfnPrintf(pHlp, "Command: %.*Rhxs, Status: %.*Rhxs\n",
2123 sizeof(uint16_t), &iCmd, sizeof(uint16_t), &iStatus);
2124 printIndent(pHlp, iIndent + 2);
2125 pHlp->pfnPrintf(pHlp, "Bus master: %s\n",
2126 iCmd & VBOX_PCI_COMMAND_MASTER ? "Yes" : "No");
2127
2128 if (fRegisters)
2129 {
2130 printIndent(pHlp, iIndent + 2);
2131 pHlp->pfnPrintf(pHlp, "PCI registers:\n");
2132 for (int iReg = 0; iReg < 0x100; )
2133 {
2134 int iPerLine = 0x10;
2135 Assert (0x100 % iPerLine == 0);
2136 printIndent(pHlp, iIndent + 3);
2137
2138 while (iPerLine-- > 0)
2139 {
2140 pHlp->pfnPrintf(pHlp, "%02x ", PCIDevGetByte(pPciDev, iReg++));
2141 }
2142 pHlp->pfnPrintf(pHlp, "\n");
2143 }
2144 }
2145 }
2146 }
2147
2148 if (pBus->cBridges > 0)
2149 {
2150 printIndent(pHlp, iIndent);
2151 pHlp->pfnPrintf(pHlp, "Registered %d bridges, subordinate buses info follows\n", pBus->cBridges);
2152 for (uint32_t iBridge = 0; iBridge < pBus->cBridges; iBridge++)
2153 {
2154 PPCIBUS pBusSub = PDMINS_2_DATA(pBus->papBridgesR3[iBridge]->pDevIns, PPCIBUS);
2155 pciBusInfo(pBusSub, pHlp, iIndent + 1, fRegisters);
2156 }
2157 }
2158}
2159
2160/**
2161 * Info handler, device version.
2162 *
2163 * @param pDevIns Device instance which registered the info.
2164 * @param pHlp Callback functions for doing output.
2165 * @param pszArgs Argument string. Optional and specific to the handler.
2166 */
2167static DECLCALLBACK(void) pciInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2168{
2169 PPCIBUS pBus = DEVINS_2_PCIBUS(pDevIns);
2170
2171 if (pszArgs == NULL || !strcmp(pszArgs, "basic"))
2172 {
2173 pciBusInfo(pBus, pHlp, 0, false);
2174 }
2175 else if (!strcmp(pszArgs, "verbose"))
2176 {
2177 pciBusInfo(pBus, pHlp, 0, true);
2178 }
2179 else
2180 {
2181 pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'verbose'.\n");
2182 }
2183}
2184
2185/**
2186 * @copydoc FNPDMDEVRELOCATE
2187 */
2188static DECLCALLBACK(void) pciRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2189{
2190 PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2191 PPCIBUS pBus = &pGlobals->PciBus;
2192 pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2193
2194 pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2195 pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2196
2197 /* Relocate RC pointers for the attached pci devices. */
2198 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
2199 {
2200 if (pBus->devices[i])
2201 pBus->devices[i]->Int.s.pBusRC += offDelta;
2202 }
2203}
2204
2205
2206/**
2207 * @copydoc FNPDMDEVRESET
2208 */
2209static DECLCALLBACK(void) pciReset(PPDMDEVINS pDevIns)
2210{
2211 pciFakePCIBIOS(pDevIns);
2212}
2213
2214/**
2215 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2216 */
2217static DECLCALLBACK(int) pciConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2218{
2219 Assert(iInstance == 0);
2220 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2221
2222 /*
2223 * Validate and read configuration.
2224 */
2225 if (!CFGMR3AreValuesValid(pCfg, "IOAPIC\0" "GCEnabled\0" "R0Enabled\0"))
2226 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2227
2228 /* query whether we got an IOAPIC */
2229 bool fUseIoApic;
2230 int rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &fUseIoApic, false);
2231 if (RT_FAILURE(rc))
2232 return PDMDEV_SET_ERROR(pDevIns, rc,
2233 N_("Configuration error: Failed to query boolean value \"IOAPIC\""));
2234
2235 /* check if RC code is enabled. */
2236 bool fGCEnabled;
2237 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2238 if (RT_FAILURE(rc))
2239 return PDMDEV_SET_ERROR(pDevIns, rc,
2240 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2241
2242 /* check if R0 code is enabled. */
2243 bool fR0Enabled;
2244 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2245 if (RT_FAILURE(rc))
2246 return PDMDEV_SET_ERROR(pDevIns, rc,
2247 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2248 Log(("PCI: fUseIoApic=%RTbool fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fUseIoApic, fGCEnabled, fR0Enabled));
2249
2250 /*
2251 * Init data and register the PCI bus.
2252 */
2253 PPCIGLOBALS pGlobals = PDMINS_2_DATA(pDevIns, PPCIGLOBALS);
2254 pGlobals->pci_bios_io_addr = 0xc000;
2255 pGlobals->pci_bios_mem_addr = 0xf0000000;
2256 memset((void *)&pGlobals->pci_irq_levels, 0, sizeof(pGlobals->pci_irq_levels));
2257 pGlobals->fUseIoApic = fUseIoApic;
2258 memset((void *)&pGlobals->pci_apic_irq_levels, 0, sizeof(pGlobals->pci_apic_irq_levels));
2259
2260 pGlobals->pDevInsR3 = pDevIns;
2261 pGlobals->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2262 pGlobals->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2263
2264 pGlobals->PciBus.pDevInsR3 = pDevIns;
2265 pGlobals->PciBus.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2266 pGlobals->PciBus.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2267 pGlobals->PciBus.papBridgesR3 = (PPCIDEVICE *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) * RT_ELEMENTS(pGlobals->PciBus.devices));
2268
2269 PDMPCIBUSREG PciBusReg;
2270 PPCIBUS pBus = &pGlobals->PciBus;
2271 PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2272 PciBusReg.pfnRegisterR3 = pciRegister;
2273 PciBusReg.pfnRegisterMsiR3 = NULL;
2274 PciBusReg.pfnIORegionRegisterR3 = pciIORegionRegister;
2275 PciBusReg.pfnSetConfigCallbacksR3 = pciSetConfigCallbacks;
2276 PciBusReg.pfnSetIrqR3 = pciSetIrq;
2277 PciBusReg.pfnSaveExecR3 = pciGenericSaveExec;
2278 PciBusReg.pfnLoadExecR3 = pciGenericLoadExec;
2279 PciBusReg.pfnFakePCIBIOSR3 = pciFakePCIBIOS;
2280 PciBusReg.pszSetIrqRC = fGCEnabled ? "pciSetIrq" : NULL;
2281 PciBusReg.pszSetIrqR0 = fR0Enabled ? "pciSetIrq" : NULL;
2282 rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2283 if (RT_FAILURE(rc))
2284 return PDMDEV_SET_ERROR(pDevIns, rc,
2285 N_("Failed to register ourselves as a PCI Bus"));
2286 if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2287 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2288 N_("PCI helper version mismatch; got %#x expected %#x"),
2289 pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION);
2290
2291 pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2292 pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2293
2294 /* Disable default device locking. */
2295 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2296 AssertRCReturn(rc, rc);
2297
2298 /*
2299 * Fill in PCI configs and add them to the bus.
2300 */
2301 /* i440FX */
2302 PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2303 PCIDevSetDeviceId( &pBus->PciDev, 0x1237);
2304 PCIDevSetRevisionId(&pBus->PciDev, 0x02);
2305 PCIDevSetClassSub( &pBus->PciDev, 0x00); /* host2pci */
2306 PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2307 PCIDevSetHeaderType(&pBus->PciDev, 0x00);
2308
2309 pBus->PciDev.pDevIns = pDevIns;
2310 pciDevSetRequestedDevfunc(&pBus->PciDev);
2311 pciRegisterInternal(pBus, 0, &pBus->PciDev, "i440FX");
2312
2313 /* PIIX3 */
2314 PCIDevSetVendorId( &pGlobals->PIIX3State.dev, 0x8086); /* Intel */
2315 PCIDevSetDeviceId( &pGlobals->PIIX3State.dev, 0x7000); /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
2316 PCIDevSetClassSub( &pGlobals->PIIX3State.dev, 0x01); /* PCI_ISA */
2317 PCIDevSetClassBase( &pGlobals->PIIX3State.dev, 0x06); /* PCI_bridge */
2318 PCIDevSetHeaderType(&pGlobals->PIIX3State.dev, 0x80); /* PCI_multifunction, generic */
2319
2320 pGlobals->PIIX3State.dev.pDevIns = pDevIns;
2321 pciDevSetRequestedDevfunc(&pGlobals->PIIX3State.dev);
2322 pciRegisterInternal(pBus, 8, &pGlobals->PIIX3State.dev, "PIIX3");
2323 piix3_reset(&pGlobals->PIIX3State);
2324
2325 pBus->iDevSearch = 16;
2326
2327 /*
2328 * Register I/O ports and save state.
2329 */
2330 rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cf8, 1, NULL, pciIOPortAddressWrite, pciIOPortAddressRead, NULL, NULL, "i440FX (PCI)");
2331 if (RT_FAILURE(rc))
2332 return rc;
2333 rc = PDMDevHlpIOPortRegister(pDevIns, 0x0cfc, 4, NULL, pciIOPortDataWrite, pciIOPortDataRead, NULL, NULL, "i440FX (PCI)");
2334 if (RT_FAILURE(rc))
2335 return rc;
2336 if (fGCEnabled)
2337 {
2338 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cf8, 1, NIL_RTGCPTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
2339 if (RT_FAILURE(rc))
2340 return rc;
2341 rc = PDMDevHlpIOPortRegisterRC(pDevIns, 0x0cfc, 4, NIL_RTGCPTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
2342 if (RT_FAILURE(rc))
2343 return rc;
2344 }
2345 if (fR0Enabled)
2346 {
2347 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cf8, 1, NIL_RTR0PTR, "pciIOPortAddressWrite", "pciIOPortAddressRead", NULL, NULL, "i440FX (PCI)");
2348 if (RT_FAILURE(rc))
2349 return rc;
2350 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x0cfc, 4, NIL_RTR0PTR, "pciIOPortDataWrite", "pciIOPortDataRead", NULL, NULL, "i440FX (PCI)");
2351 if (RT_FAILURE(rc))
2352 return rc;
2353 }
2354
2355 rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(*pBus) + 16*128, "pgm",
2356 NULL, NULL, NULL,
2357 NULL, pciR3SaveExec, NULL,
2358 NULL, pciR3LoadExec, NULL);
2359 if (RT_FAILURE(rc))
2360 return rc;
2361
2362 PDMDevHlpDBGFInfoRegister(pDevIns, "pci", "Display PCI bus status. Recognizes 'basic' or 'verbose' "
2363 "as arguments, defaults to 'basic'.", pciInfo);
2364
2365 PDMDevHlpDBGFInfoRegister(pDevIns, "pciirq", "Display PCI IRQ routing state. (no arguments)", pciIrqInfo);
2366
2367 return VINF_SUCCESS;
2368}
2369
2370
2371/**
2372 * The device registration structure.
2373 */
2374const PDMDEVREG g_DevicePCI =
2375{
2376 /* u32Version */
2377 PDM_DEVREG_VERSION,
2378 /* szName */
2379 "pci",
2380 /* szRCMod */
2381 "VBoxDDGC.gc",
2382 /* szR0Mod */
2383 "VBoxDDR0.r0",
2384 /* pszDescription */
2385 "i440FX PCI bridge and PIIX3 ISA bridge.",
2386 /* fFlags */
2387 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
2388 /* fClass */
2389 PDM_DEVREG_CLASS_BUS_PCI | PDM_DEVREG_CLASS_BUS_ISA,
2390 /* cMaxInstances */
2391 1,
2392 /* cbInstance */
2393 sizeof(PCIGLOBALS),
2394 /* pfnConstruct */
2395 pciConstruct,
2396 /* pfnDestruct */
2397 NULL,
2398 /* pfnRelocate */
2399 pciRelocate,
2400 /* pfnIOCtl */
2401 NULL,
2402 /* pfnPowerOn */
2403 NULL,
2404 /* pfnReset */
2405 pciReset,
2406 /* pfnSuspend */
2407 NULL,
2408 /* pfnResume */
2409 NULL,
2410 /* pfnAttach */
2411 NULL,
2412 /* pfnDetach */
2413 NULL,
2414 /* pfnQueryInterface */
2415 NULL,
2416 /* pfnInitComplete */
2417 NULL,
2418 /* pfnPowerOff */
2419 NULL,
2420 /* pfnSoftReset */
2421 NULL,
2422 /* u32VersionEnd */
2423 PDM_DEVREG_VERSION
2424
2425};
2426#endif /* IN_RING3 */
2427
2428
2429/**
2430 * Set the IRQ for a PCI device on a secondary bus.
2431 *
2432 * @param pDevIns Device instance of the PCI Bus.
2433 * @param pPciDev The PCI device structure.
2434 * @param iIrq IRQ number to set.
2435 * @param iLevel IRQ level.
2436 * @param uTagSrc The IRQ tag and source ID (for tracing).
2437 */
2438PDMBOTHCBDECL(void) pcibridgeSetIrq(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
2439{
2440 /*
2441 * The PCI-to-PCI bridge specification defines how the interrupt pins
2442 * are routed from the secondary to the primary bus (see chapter 9).
2443 * iIrq gives the interrupt pin the pci device asserted.
2444 * We change iIrq here according to the spec and call the SetIrq function
2445 * of our parent passing the device which asserted the interrupt instead of the device of the bridge.
2446 */
2447 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2448 PPCIDEVICE pPciDevBus = pPciDev;
2449 int iIrqPinBridge = iIrq;
2450 uint8_t uDevFnBridge = 0;
2451
2452 /* Walk the chain until we reach the host bus. */
2453 do
2454 {
2455 uDevFnBridge = pBus->PciDev.devfn;
2456 iIrqPinBridge = ((pPciDevBus->devfn >> 3) + iIrqPinBridge) & 3;
2457
2458 /* Get the parent. */
2459 pBus = pBus->PciDev.Int.s.CTX_SUFF(pBus);
2460 pPciDevBus = &pBus->PciDev;
2461 } while (pBus->iBus != 0);
2462
2463 AssertMsg(pBus->iBus == 0, ("This is not the host pci bus iBus=%d\n", pBus->iBus));
2464 pciSetIrqInternal(PCIBUS_2_PCIGLOBALS(pBus), uDevFnBridge, pPciDev, iIrqPinBridge, iLevel, uTagSrc);
2465}
2466
2467#ifdef IN_RING3
2468
2469static void pcibridgeConfigWrite(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, uint32_t u32Value, unsigned cb)
2470{
2471 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2472
2473 LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u u32Value=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, u32Value, cb));
2474
2475 /* If the current bus is not the target bus search for the bus which contains the device. */
2476 if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2477 {
2478 PPCIDEVICE pBridgeDevice = pciFindBridge(pBus, iBus);
2479 if (pBridgeDevice)
2480 {
2481 AssertPtr(pBridgeDevice->Int.s.pfnBridgeConfigWrite);
2482 pBridgeDevice->Int.s.pfnBridgeConfigWrite(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, u32Value, cb);
2483 }
2484 }
2485 else
2486 {
2487 /* This is the target bus, pass the write to the device. */
2488 PPCIDEVICE pPciDev = pBus->devices[iDevice];
2489 if (pPciDev)
2490 {
2491 Log(("%s: %s: addr=%02x val=%08x len=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2492 pPciDev->Int.s.pfnConfigWrite(pPciDev, u32Address, u32Value, cb);
2493 }
2494 }
2495}
2496
2497static uint32_t pcibridgeConfigRead(PPDMDEVINSR3 pDevIns, uint8_t iBus, uint8_t iDevice, uint32_t u32Address, unsigned cb)
2498{
2499 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2500 uint32_t u32Value = 0xffffffff; /* Return value in case there is no device. */
2501
2502 LogFlowFunc((": pDevIns=%p iBus=%d iDevice=%d u32Address=%u cb=%d\n", pDevIns, iBus, iDevice, u32Address, cb));
2503
2504 /* If the current bus is not the target bus search for the bus which contains the device. */
2505 if (iBus != pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS])
2506 {
2507 PPCIDEVICE pBridgeDevice = pciFindBridge(pBus, iBus);
2508 if (pBridgeDevice)
2509 {
2510 AssertPtr( pBridgeDevice->Int.s.pfnBridgeConfigRead);
2511 u32Value = pBridgeDevice->Int.s.pfnBridgeConfigRead(pBridgeDevice->pDevIns, iBus, iDevice, u32Address, cb);
2512 }
2513 }
2514 else
2515 {
2516 /* This is the target bus, pass the read to the device. */
2517 PPCIDEVICE pPciDev = pBus->devices[iDevice];
2518 if (pPciDev)
2519 {
2520 u32Value = pPciDev->Int.s.pfnConfigRead(pPciDev, u32Address, cb);
2521 Log(("%s: %s: u32Address=%02x u32Value=%08x cb=%d\n", __FUNCTION__, pPciDev->name, u32Address, u32Value, cb));
2522 }
2523 }
2524
2525 return u32Value;
2526}
2527
2528
2529/**
2530 * @copydoc FNSSMDEVSAVEEXEC
2531 */
2532static DECLCALLBACK(int) pcibridgeR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
2533{
2534 PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2535 return pciR3CommonSaveExec(pThis, pSSM);
2536}
2537
2538
2539/**
2540 * @copydoc FNSSMDEVLOADEXEC
2541 */
2542static DECLCALLBACK(int) pcibridgeR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2543{
2544 PPCIBUS pThis = PDMINS_2_DATA(pDevIns, PPCIBUS);
2545 if (uVersion > VBOX_PCI_SAVED_STATE_VERSION)
2546 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2547 return pciR3CommonLoadExec(pThis, pSSM, uVersion, uPass);
2548}
2549
2550
2551/**
2552 * Registers the device with the default PCI bus.
2553 *
2554 * @returns VBox status code.
2555 * @param pDevIns Device instance of the PCI Bus.
2556 * @param pPciDev The PCI device structure.
2557 * Any PCI enabled device must keep this in it's instance data!
2558 * Fill in the PCI data config before registration, please.
2559 * @param pszName Pointer to device name (permanent, readonly). For debugging, not unique.
2560 * @param iDev The PCI device number. Use a negative value for auto assigning one.
2561 */
2562static DECLCALLBACK(int) pcibridgeRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, const char *pszName, int iDev)
2563{
2564 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2565
2566 /*
2567 * Check input.
2568 */
2569 if ( !pszName
2570 || !pPciDev
2571 || iDev >= (int)RT_ELEMENTS(pBus->devices))
2572 {
2573 AssertMsgFailed(("Invalid argument! pszName=%s pPciDev=%p iDev=%d\n", pszName, pPciDev, iDev));
2574 return VERR_INVALID_PARAMETER;
2575 }
2576
2577 /*
2578 * Register the device.
2579 */
2580 return pciRegisterInternal(pBus, iDev, pPciDev, pszName);
2581}
2582
2583
2584/**
2585 * @copydoc FNPDMDEVRESET
2586 */
2587static DECLCALLBACK(void) pcibridgeReset(PPDMDEVINS pDevIns)
2588{
2589 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2590
2591 /* Reset config space to default values. */
2592 pBus->PciDev.config[VBOX_PCI_PRIMARY_BUS] = 0;
2593 pBus->PciDev.config[VBOX_PCI_SECONDARY_BUS] = 0;
2594 pBus->PciDev.config[VBOX_PCI_SUBORDINATE_BUS] = 0;
2595}
2596
2597
2598/**
2599 * @copydoc FNPDMDEVRELOCATE
2600 */
2601static DECLCALLBACK(void) pcibridgeRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2602{
2603 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2604 pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2605
2606 /* Relocate RC pointers for the attached pci devices. */
2607 for (uint32_t i = 0; i < RT_ELEMENTS(pBus->devices); i++)
2608 {
2609 if (pBus->devices[i])
2610 pBus->devices[i]->Int.s.pBusRC += offDelta;
2611 }
2612}
2613
2614
2615/**
2616 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2617 */
2618static DECLCALLBACK(int) pcibridgeConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2619{
2620 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2621
2622 /*
2623 * Validate and read configuration.
2624 */
2625 if (!CFGMR3AreValuesValid(pCfg, "GCEnabled\0" "R0Enabled\0"))
2626 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
2627
2628 /* check if RC code is enabled. */
2629 bool fGCEnabled;
2630 int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fGCEnabled, true);
2631 if (RT_FAILURE(rc))
2632 return PDMDEV_SET_ERROR(pDevIns, rc,
2633 N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
2634
2635 /* check if R0 code is enabled. */
2636 bool fR0Enabled;
2637 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
2638 if (RT_FAILURE(rc))
2639 return PDMDEV_SET_ERROR(pDevIns, rc,
2640 N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
2641 Log(("PCI: fGCEnabled=%RTbool fR0Enabled=%RTbool\n", fGCEnabled, fR0Enabled));
2642
2643 /*
2644 * Init data and register the PCI bus.
2645 */
2646 PPCIBUS pBus = PDMINS_2_DATA(pDevIns, PPCIBUS);
2647 pBus->pDevInsR3 = pDevIns;
2648 pBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2649 pBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2650 pBus->papBridgesR3 = (PPCIDEVICE *)PDMDevHlpMMHeapAllocZ(pDevIns, sizeof(PPCIDEVICE) * RT_ELEMENTS(pBus->devices));
2651
2652 PDMPCIBUSREG PciBusReg;
2653 PciBusReg.u32Version = PDM_PCIBUSREG_VERSION;
2654 PciBusReg.pfnRegisterR3 = pcibridgeRegister;
2655 PciBusReg.pfnRegisterMsiR3 = NULL;
2656 PciBusReg.pfnIORegionRegisterR3 = pciIORegionRegister;
2657 PciBusReg.pfnSetConfigCallbacksR3 = pciSetConfigCallbacks;
2658 PciBusReg.pfnSetIrqR3 = pcibridgeSetIrq;
2659 PciBusReg.pfnSaveExecR3 = pciGenericSaveExec;
2660 PciBusReg.pfnLoadExecR3 = pciGenericLoadExec;
2661 PciBusReg.pfnFakePCIBIOSR3 = NULL; /* Only needed for the first bus. */
2662 PciBusReg.pszSetIrqRC = fGCEnabled ? "pcibridgeSetIrq" : NULL;
2663 PciBusReg.pszSetIrqR0 = fR0Enabled ? "pcibridgeSetIrq" : NULL;
2664 rc = PDMDevHlpPCIBusRegister(pDevIns, &PciBusReg, &pBus->pPciHlpR3);
2665 if (RT_FAILURE(rc))
2666 return PDMDEV_SET_ERROR(pDevIns, rc,
2667 N_("Failed to register ourselves as a PCI Bus"));
2668 if (pBus->pPciHlpR3->u32Version != PDM_PCIHLPR3_VERSION)
2669 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2670 N_("PCI helper version mismatch; got %#x expected %#x"),
2671 pBus->pPciHlpR3->u32Version, PDM_PCIHLPR3_VERSION);
2672
2673 pBus->pPciHlpRC = pBus->pPciHlpR3->pfnGetRCHelpers(pDevIns);
2674 pBus->pPciHlpR0 = pBus->pPciHlpR3->pfnGetR0Helpers(pDevIns);
2675
2676 /*
2677 * Fill in PCI configs and add them to the bus.
2678 */
2679 PCIDevSetVendorId( &pBus->PciDev, 0x8086); /* Intel */
2680 PCIDevSetDeviceId( &pBus->PciDev, 0x2448); /* 82801 Mobile PCI bridge. */
2681 PCIDevSetRevisionId(&pBus->PciDev, 0xf2);
2682 PCIDevSetClassSub( &pBus->PciDev, 0x04); /* pci2pci */
2683 PCIDevSetClassBase( &pBus->PciDev, 0x06); /* PCI_bridge */
2684 PCIDevSetClassProg( &pBus->PciDev, 0x01); /* Supports subtractive decoding. */
2685 PCIDevSetHeaderType(&pBus->PciDev, 0x01); /* Single function device which adheres to the PCI-to-PCI bridge spec. */
2686 PCIDevSetCommand( &pBus->PciDev, 0x00);
2687 PCIDevSetStatus( &pBus->PciDev, 0x20); /* 66MHz Capable. */
2688 PCIDevSetInterruptLine(&pBus->PciDev, 0x00); /* This device does not assert interrupts. */
2689
2690 /*
2691 * This device does not generate interrupts. Interrupt delivery from
2692 * devices attached to the bus is unaffected.
2693 */
2694 PCIDevSetInterruptPin (&pBus->PciDev, 0x00);
2695
2696 pBus->PciDev.pDevIns = pDevIns;
2697
2698 /* Bridge-specific data */
2699 pciDevSetPci2PciBridge(&pBus->PciDev);
2700 pBus->PciDev.Int.s.pfnBridgeConfigRead = pcibridgeConfigRead;
2701 pBus->PciDev.Int.s.pfnBridgeConfigWrite = pcibridgeConfigWrite;
2702
2703 /*
2704 * Register this PCI bridge. The called function will take care on which bus we will get registered.
2705 */
2706 rc = PDMDevHlpPCIRegister (pDevIns, &pBus->PciDev);
2707 if (RT_FAILURE(rc))
2708 return rc;
2709
2710 pBus->iDevSearch = 0;
2711 /*
2712 * The iBus property doesn't really represent the bus number
2713 * because the guest and the BIOS can choose different bus numbers
2714 * for them.
2715 * The bus number is mainly for the setIrq function to indicate
2716 * when the host bus is reached which will have iBus = 0.
2717 * That's why the + 1.
2718 */
2719 pBus->iBus = iInstance + 1;
2720
2721 /*
2722 * Register SSM handlers. We use the same saved state version as for the host bridge
2723 * to make changes easier.
2724 */
2725 rc = PDMDevHlpSSMRegisterEx(pDevIns, VBOX_PCI_SAVED_STATE_VERSION, sizeof(*pBus) + 16*128, "pgm",
2726 NULL, NULL, NULL,
2727 NULL, pcibridgeR3SaveExec, NULL,
2728 NULL, pcibridgeR3LoadExec, NULL);
2729 if (RT_FAILURE(rc))
2730 return rc;
2731
2732 return VINF_SUCCESS;
2733}
2734
2735
2736/**
2737 * The device registration structure
2738 * for the PCI-to-PCI bridge.
2739 */
2740const PDMDEVREG g_DevicePCIBridge =
2741{
2742 /* u32Version */
2743 PDM_DEVREG_VERSION,
2744 /* szName */
2745 "pcibridge",
2746 /* szRCMod */
2747 "VBoxDDGC.gc",
2748 /* szR0Mod */
2749 "VBoxDDR0.r0",
2750 /* pszDescription */
2751 "82801 Mobile PCI to PCI bridge",
2752 /* fFlags */
2753 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
2754 /* fClass */
2755 PDM_DEVREG_CLASS_BUS_PCI,
2756 /* cMaxInstances */
2757 ~0U,
2758 /* cbInstance */
2759 sizeof(PCIBUS),
2760 /* pfnConstruct */
2761 pcibridgeConstruct,
2762 /* pfnDestruct */
2763 NULL,
2764 /* pfnRelocate */
2765 pcibridgeRelocate,
2766 /* pfnIOCtl */
2767 NULL,
2768 /* pfnPowerOn */
2769 NULL,
2770 /* pfnReset */
2771 pcibridgeReset,
2772 /* pfnSuspend */
2773 NULL,
2774 /* pfnResume */
2775 NULL,
2776 /* pfnAttach */
2777 NULL,
2778 /* pfnDetach */
2779 NULL,
2780 /* pfnQueryInterface */
2781 NULL,
2782 /* pfnInitComplete */
2783 NULL,
2784 /* pfnPowerOff */
2785 NULL,
2786 /* pfnSoftReset */
2787 NULL,
2788 /* u32VersionEnd */
2789 PDM_DEVREG_VERSION
2790};
2791
2792#endif /* IN_RING3 */
2793#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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