hm_vmx.h@ 96601

Last change on this file since 96601 was 96601, checked in by vboxsync, 3 years ago
hm_vmx.h: Nested EPT: bugref:10092 Added newer EPT paging entry defines and comment nits.
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1	/** @file
2	* HM - VMX Structures and Definitions. (VMM)
3	*/
4
5	/*
6	* Copyright (C) 2006-2022 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.215389.xyz.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_vmm_hm_vmx_h
37	#define VBOX_INCLUDED_vmm_hm_vmx_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#include <VBox/types.h>
43	#include <iprt/x86.h>
44	#include <iprt/assertcompile.h>
45
46
47	/** @defgroup grp_hm_vmx VMX Types and Definitions
48	* @ingroup grp_hm
49	* @{
50	*/
51
52	/** @name Host-state MSR lazy-restoration flags.
53	* @{
54	*/
55	/** The host MSRs have been saved. */
56	#define VMX_LAZY_MSRS_SAVED_HOST RT_BIT(0)
57	/** The guest MSRs are loaded and in effect. */
58	#define VMX_LAZY_MSRS_LOADED_GUEST RT_BIT(1)
59	/** @} */
60
61	/** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
62	* UFC = Unsupported Feature Combination.
63	* @{
64	*/
65	/** Unsupported pin-based VM-execution controls combo. */
66	#define VMX_UFC_CTRL_PIN_EXEC 1
67	/** Unsupported processor-based VM-execution controls combo. */
68	#define VMX_UFC_CTRL_PROC_EXEC 2
69	/** Unsupported move debug register VM-exit combo. */
70	#define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT 3
71	/** Unsupported VM-entry controls combo. */
72	#define VMX_UFC_CTRL_ENTRY 4
73	/** Unsupported VM-exit controls combo. */
74	#define VMX_UFC_CTRL_EXIT 5
75	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
76	* for storing host MSRs. */
77	#define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE 6
78	/** MSR storage capacity of the VMCS autoload/store area is not sufficient
79	* for storing guest MSRs. */
80	#define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE 7
81	/** Invalid VMCS size. */
82	#define VMX_UFC_INVALID_VMCS_SIZE 8
83	/** Unsupported secondary processor-based VM-execution controls combo. */
84	#define VMX_UFC_CTRL_PROC_EXEC2 9
85	/** Invalid unrestricted-guest execution controls combo. */
86	#define VMX_UFC_INVALID_UX_COMBO 10
87	/** EPT flush type not supported. */
88	#define VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED 11
89	/** EPT paging structure memory type is not write-back. */
90	#define VMX_UFC_EPT_MEM_TYPE_NOT_WB 12
91	/** EPT requires INVEPT instr. support but it's not available. */
92	#define VMX_UFC_EPT_INVEPT_UNAVAILABLE 13
93	/** EPT requires page-walk length of 4. */
94	#define VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED 14
95	/** VMX VMWRITE all feature exposed to the guest but not supported on host. */
96	#define VMX_UFC_GST_HOST_VMWRITE_ALL 15
97	/** LBR stack size cannot be determined for the current CPU. */
98	#define VMX_UFC_LBR_STACK_SIZE_UNKNOWN 16
99	/** LBR stack size of the CPU exceeds our buffer size. */
100	#define VMX_UFC_LBR_STACK_SIZE_OVERFLOW 17
101	/** @} */
102
103	/** @name VMX HM-error codes for VERR_VMX_VMCS_FIELD_CACHE_INVALID.
104	* VCI = VMCS-field Cache Invalid.
105	* @{
106	*/
107	/** Cache of VM-entry controls invalid. */
108	#define VMX_VCI_CTRL_ENTRY 300
109	/** Cache of VM-exit controls invalid. */
110	#define VMX_VCI_CTRL_EXIT 301
111	/** Cache of pin-based VM-execution controls invalid. */
112	#define VMX_VCI_CTRL_PIN_EXEC 302
113	/** Cache of processor-based VM-execution controls invalid. */
114	#define VMX_VCI_CTRL_PROC_EXEC 303
115	/** Cache of secondary processor-based VM-execution controls invalid. */
116	#define VMX_VCI_CTRL_PROC_EXEC2 304
117	/** Cache of exception bitmap invalid. */
118	#define VMX_VCI_CTRL_XCPT_BITMAP 305
119	/** Cache of TSC offset invalid. */
120	#define VMX_VCI_CTRL_TSC_OFFSET 306
121	/** Cache of tertiary processor-based VM-execution controls invalid. */
122	#define VMX_VCI_CTRL_PROC_EXEC3 307
123	/** @} */
124
125	/** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
126	* IGS = Invalid Guest State.
127	* @{
128	*/
129	/** An error occurred while checking invalid-guest-state. */
130	#define VMX_IGS_ERROR 500
131	/** The invalid guest-state checks did not find any reason why. */
132	#define VMX_IGS_REASON_NOT_FOUND 501
133	/** CR0 fixed1 bits invalid. */
134	#define VMX_IGS_CR0_FIXED1 502
135	/** CR0 fixed0 bits invalid. */
136	#define VMX_IGS_CR0_FIXED0 503
137	/** CR0.PE and CR0.PE invalid VT-x/host combination. */
138	#define VMX_IGS_CR0_PG_PE_COMBO 504
139	/** CR4 fixed1 bits invalid. */
140	#define VMX_IGS_CR4_FIXED1 505
141	/** CR4 fixed0 bits invalid. */
142	#define VMX_IGS_CR4_FIXED0 506
143	/** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
144	* VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
145	#define VMX_IGS_DEBUGCTL_MSR_RESERVED 507
146	/** CR0.PG not set for long-mode when not using unrestricted guest. */
147	#define VMX_IGS_CR0_PG_LONGMODE 508
148	/** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
149	#define VMX_IGS_CR4_PAE_LONGMODE 509
150	/** CR4.PCIDE set for 32-bit guest. */
151	#define VMX_IGS_CR4_PCIDE 510
152	/** VMCS' DR7 reserved bits not set to 0. */
153	#define VMX_IGS_DR7_RESERVED 511
154	/** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
155	#define VMX_IGS_PERF_GLOBAL_MSR_RESERVED 512
156	/** VMCS' EFER MSR reserved bits not set to 0. */
157	#define VMX_IGS_EFER_MSR_RESERVED 513
158	/** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
159	#define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH 514
160	/** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging
161	* without unrestricted guest. */
162	#define VMX_IGS_EFER_LMA_LME_MISMATCH 515
163	/** CS.Attr.P bit invalid. */
164	#define VMX_IGS_CS_ATTR_P_INVALID 516
165	/** CS.Attr reserved bits not set to 0. */
166	#define VMX_IGS_CS_ATTR_RESERVED 517
167	/** CS.Attr.G bit invalid. */
168	#define VMX_IGS_CS_ATTR_G_INVALID 518
169	/** CS is unusable. */
170	#define VMX_IGS_CS_ATTR_UNUSABLE 519
171	/** CS and SS DPL unequal. */
172	#define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL 520
173	/** CS and SS DPL mismatch. */
174	#define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH 521
175	/** CS Attr.Type invalid. */
176	#define VMX_IGS_CS_ATTR_TYPE_INVALID 522
177	/** CS and SS RPL unequal. */
178	#define VMX_IGS_SS_CS_RPL_UNEQUAL 523
179	/** SS.Attr.DPL and SS RPL unequal. */
180	#define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL 524
181	/** SS.Attr.DPL invalid for segment type. */
182	#define VMX_IGS_SS_ATTR_DPL_INVALID 525
183	/** SS.Attr.Type invalid. */
184	#define VMX_IGS_SS_ATTR_TYPE_INVALID 526
185	/** SS.Attr.P bit invalid. */
186	#define VMX_IGS_SS_ATTR_P_INVALID 527
187	/** SS.Attr reserved bits not set to 0. */
188	#define VMX_IGS_SS_ATTR_RESERVED 528
189	/** SS.Attr.G bit invalid. */
190	#define VMX_IGS_SS_ATTR_G_INVALID 529
191	/** DS.Attr.A bit invalid. */
192	#define VMX_IGS_DS_ATTR_A_INVALID 530
193	/** DS.Attr.P bit invalid. */
194	#define VMX_IGS_DS_ATTR_P_INVALID 531
195	/** DS.Attr.DPL and DS RPL unequal. */
196	#define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL 532
197	/** DS.Attr reserved bits not set to 0. */
198	#define VMX_IGS_DS_ATTR_RESERVED 533
199	/** DS.Attr.G bit invalid. */
200	#define VMX_IGS_DS_ATTR_G_INVALID 534
201	/** DS.Attr.Type invalid. */
202	#define VMX_IGS_DS_ATTR_TYPE_INVALID 535
203	/** ES.Attr.A bit invalid. */
204	#define VMX_IGS_ES_ATTR_A_INVALID 536
205	/** ES.Attr.P bit invalid. */
206	#define VMX_IGS_ES_ATTR_P_INVALID 537
207	/** ES.Attr.DPL and DS RPL unequal. */
208	#define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL 538
209	/** ES.Attr reserved bits not set to 0. */
210	#define VMX_IGS_ES_ATTR_RESERVED 539
211	/** ES.Attr.G bit invalid. */
212	#define VMX_IGS_ES_ATTR_G_INVALID 540
213	/** ES.Attr.Type invalid. */
214	#define VMX_IGS_ES_ATTR_TYPE_INVALID 541
215	/** FS.Attr.A bit invalid. */
216	#define VMX_IGS_FS_ATTR_A_INVALID 542
217	/** FS.Attr.P bit invalid. */
218	#define VMX_IGS_FS_ATTR_P_INVALID 543
219	/** FS.Attr.DPL and DS RPL unequal. */
220	#define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL 544
221	/** FS.Attr reserved bits not set to 0. */
222	#define VMX_IGS_FS_ATTR_RESERVED 545
223	/** FS.Attr.G bit invalid. */
224	#define VMX_IGS_FS_ATTR_G_INVALID 546
225	/** FS.Attr.Type invalid. */
226	#define VMX_IGS_FS_ATTR_TYPE_INVALID 547
227	/** GS.Attr.A bit invalid. */
228	#define VMX_IGS_GS_ATTR_A_INVALID 548
229	/** GS.Attr.P bit invalid. */
230	#define VMX_IGS_GS_ATTR_P_INVALID 549
231	/** GS.Attr.DPL and DS RPL unequal. */
232	#define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL 550
233	/** GS.Attr reserved bits not set to 0. */
234	#define VMX_IGS_GS_ATTR_RESERVED 551
235	/** GS.Attr.G bit invalid. */
236	#define VMX_IGS_GS_ATTR_G_INVALID 552
237	/** GS.Attr.Type invalid. */
238	#define VMX_IGS_GS_ATTR_TYPE_INVALID 553
239	/** V86 mode CS.Base invalid. */
240	#define VMX_IGS_V86_CS_BASE_INVALID 554
241	/** V86 mode CS.Limit invalid. */
242	#define VMX_IGS_V86_CS_LIMIT_INVALID 555
243	/** V86 mode CS.Attr invalid. */
244	#define VMX_IGS_V86_CS_ATTR_INVALID 556
245	/** V86 mode SS.Base invalid. */
246	#define VMX_IGS_V86_SS_BASE_INVALID 557
247	/** V86 mode SS.Limit invalid. */
248	#define VMX_IGS_V86_SS_LIMIT_INVALID 558
249	/** V86 mode SS.Attr invalid. */
250	#define VMX_IGS_V86_SS_ATTR_INVALID 559
251	/** V86 mode DS.Base invalid. */
252	#define VMX_IGS_V86_DS_BASE_INVALID 560
253	/** V86 mode DS.Limit invalid. */
254	#define VMX_IGS_V86_DS_LIMIT_INVALID 561
255	/** V86 mode DS.Attr invalid. */
256	#define VMX_IGS_V86_DS_ATTR_INVALID 562
257	/** V86 mode ES.Base invalid. */
258	#define VMX_IGS_V86_ES_BASE_INVALID 563
259	/** V86 mode ES.Limit invalid. */
260	#define VMX_IGS_V86_ES_LIMIT_INVALID 564
261	/** V86 mode ES.Attr invalid. */
262	#define VMX_IGS_V86_ES_ATTR_INVALID 565
263	/** V86 mode FS.Base invalid. */
264	#define VMX_IGS_V86_FS_BASE_INVALID 566
265	/** V86 mode FS.Limit invalid. */
266	#define VMX_IGS_V86_FS_LIMIT_INVALID 567
267	/** V86 mode FS.Attr invalid. */
268	#define VMX_IGS_V86_FS_ATTR_INVALID 568
269	/** V86 mode GS.Base invalid. */
270	#define VMX_IGS_V86_GS_BASE_INVALID 569
271	/** V86 mode GS.Limit invalid. */
272	#define VMX_IGS_V86_GS_LIMIT_INVALID 570
273	/** V86 mode GS.Attr invalid. */
274	#define VMX_IGS_V86_GS_ATTR_INVALID 571
275	/** Longmode CS.Base invalid. */
276	#define VMX_IGS_LONGMODE_CS_BASE_INVALID 572
277	/** Longmode SS.Base invalid. */
278	#define VMX_IGS_LONGMODE_SS_BASE_INVALID 573
279	/** Longmode DS.Base invalid. */
280	#define VMX_IGS_LONGMODE_DS_BASE_INVALID 574
281	/** Longmode ES.Base invalid. */
282	#define VMX_IGS_LONGMODE_ES_BASE_INVALID 575
283	/** SYSENTER ESP is not canonical. */
284	#define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL 576
285	/** SYSENTER EIP is not canonical. */
286	#define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL 577
287	/** PAT MSR invalid. */
288	#define VMX_IGS_PAT_MSR_INVALID 578
289	/** PAT MSR reserved bits not set to 0. */
290	#define VMX_IGS_PAT_MSR_RESERVED 579
291	/** GDTR.Base is not canonical. */
292	#define VMX_IGS_GDTR_BASE_NOT_CANONICAL 580
293	/** IDTR.Base is not canonical. */
294	#define VMX_IGS_IDTR_BASE_NOT_CANONICAL 581
295	/** GDTR.Limit invalid. */
296	#define VMX_IGS_GDTR_LIMIT_INVALID 582
297	/** IDTR.Limit invalid. */
298	#define VMX_IGS_IDTR_LIMIT_INVALID 583
299	/** Longmode RIP is invalid. */
300	#define VMX_IGS_LONGMODE_RIP_INVALID 584
301	/** RFLAGS reserved bits not set to 0. */
302	#define VMX_IGS_RFLAGS_RESERVED 585
303	/** RFLAGS RA1 reserved bits not set to 1. */
304	#define VMX_IGS_RFLAGS_RESERVED1 586
305	/** RFLAGS.VM (V86 mode) invalid. */
306	#define VMX_IGS_RFLAGS_VM_INVALID 587
307	/** RFLAGS.IF invalid. */
308	#define VMX_IGS_RFLAGS_IF_INVALID 588
309	/** Activity state invalid. */
310	#define VMX_IGS_ACTIVITY_STATE_INVALID 589
311	/** Activity state HLT invalid when SS.Attr.DPL is not zero. */
312	#define VMX_IGS_ACTIVITY_STATE_HLT_INVALID 590
313	/** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
314	#define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID 591
315	/** Activity state SIPI WAIT invalid. */
316	#define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID 592
317	/** Interruptibility state reserved bits not set to 0. */
318	#define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED 593
319	/** Interruptibility state cannot be block-by-STI -and- MOV SS. */
320	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID 594
321	/** Interruptibility state block-by-STI invalid for EFLAGS. */
322	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID 595
323	/** Interruptibility state invalid while trying to deliver external
324	* interrupt. */
325	#define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID 596
326	/** Interruptibility state block-by-MOVSS invalid while trying to deliver an
327	* NMI. */
328	#define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID 597
329	/** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
330	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID 598
331	/** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
332	#define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID 599
333	/** Interruptibility state block-by-STI (maybe) invalid when trying to
334	* deliver an NMI. */
335	#define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID 600
336	/** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
337	* active. */
338	#define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID 601
339	/** Pending debug exceptions reserved bits not set to 0. */
340	#define VMX_IGS_PENDING_DEBUG_RESERVED 602
341	/** Longmode pending debug exceptions reserved bits not set to 0. */
342	#define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED 603
343	/** Pending debug exceptions.BS bit is not set when it should be. */
344	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET 604
345	/** Pending debug exceptions.BS bit is not clear when it should be. */
346	#define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR 605
347	/** VMCS link pointer reserved bits not set to 0. */
348	#define VMX_IGS_VMCS_LINK_PTR_RESERVED 606
349	/** TR cannot index into LDT, TI bit MBZ. */
350	#define VMX_IGS_TR_TI_INVALID 607
351	/** LDTR cannot index into LDT. TI bit MBZ. */
352	#define VMX_IGS_LDTR_TI_INVALID 608
353	/** TR.Base is not canonical. */
354	#define VMX_IGS_TR_BASE_NOT_CANONICAL 609
355	/** FS.Base is not canonical. */
356	#define VMX_IGS_FS_BASE_NOT_CANONICAL 610
357	/** GS.Base is not canonical. */
358	#define VMX_IGS_GS_BASE_NOT_CANONICAL 611
359	/** LDTR.Base is not canonical. */
360	#define VMX_IGS_LDTR_BASE_NOT_CANONICAL 612
361	/** TR is unusable. */
362	#define VMX_IGS_TR_ATTR_UNUSABLE 613
363	/** TR.Attr.S bit invalid. */
364	#define VMX_IGS_TR_ATTR_S_INVALID 614
365	/** TR is not present. */
366	#define VMX_IGS_TR_ATTR_P_INVALID 615
367	/** TR.Attr reserved bits not set to 0. */
368	#define VMX_IGS_TR_ATTR_RESERVED 616
369	/** TR.Attr.G bit invalid. */
370	#define VMX_IGS_TR_ATTR_G_INVALID 617
371	/** Longmode TR.Attr.Type invalid. */
372	#define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID 618
373	/** TR.Attr.Type invalid. */
374	#define VMX_IGS_TR_ATTR_TYPE_INVALID 619
375	/** CS.Attr.S invalid. */
376	#define VMX_IGS_CS_ATTR_S_INVALID 620
377	/** CS.Attr.DPL invalid. */
378	#define VMX_IGS_CS_ATTR_DPL_INVALID 621
379	/** PAE PDPTE reserved bits not set to 0. */
380	#define VMX_IGS_PAE_PDPTE_RESERVED 623
381	/** VMCS link pointer does not point to a shadow VMCS. */
382	#define VMX_IGS_VMCS_LINK_PTR_NOT_SHADOW 624
383	/** VMCS link pointer to a shadow VMCS with invalid VMCS revision identifer. */
384	#define VMX_IGS_VMCS_LINK_PTR_SHADOW_VMCS_ID_INVALID 625
385	/** @} */
386
387	/** @name VMX VMCS-Read cache indices.
388	* @{
389	*/
390	#define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX 0
391	#define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX 1
392	#define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX 2
393	#define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX 3
394	#define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX 4
395	#define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX 5
396	#define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX 6
397	#define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX 7
398	#define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX 8
399	#define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX 9
400	#define VMX_VMCS_GUEST_RSP_CACHE_IDX 10
401	#define VMX_VMCS_GUEST_RIP_CACHE_IDX 11
402	#define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX 12
403	#define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX 13
404	#define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 14
405	#define VMX_VMCS_RO_GUEST_LINEAR_ADDR_CACHE_IDX 15
406	#define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS_RO_GUEST_LINEAR_ADDR_CACHE_IDX + 1)
407	#define VMX_VMCS_GUEST_CR3_CACHE_IDX 16
408	#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
409	/** @} */
410
411	/** @name VMX Extended Page Tables (EPT) Common Bits
412	* @{ */
413	/** Bit 0 - Readable (we often think of it as present). */
414	#define EPT_E_BIT_READ 0
415	#define EPT_E_READ RT_BIT_64(EPT_E_BIT_READ) /*< @see EPT_E_BIT_READ /
416	/** Bit 1 - Writable. */
417	#define EPT_E_BIT_WRITE 1
418	#define EPT_E_WRITE RT_BIT_64(EPT_E_BIT_WRITE) /*< @see EPT_E_BIT_WRITE /
419	/** Bit 2 - Executable.
420	* @note This controls supervisor instruction fetching if mode-based
421	* execution control is enabled. */
422	#define EPT_E_BIT_EXECUTE 2
423	#define EPT_E_EXECUTE RT_BIT_64(EPT_E_BIT_EXECUTE) /*< @see EPT_E_BIT_EXECUTE /
424	/** Bits 3-5 - Memory type mask (leaf only, MBZ).
425	* The memory type is only applicable for leaf entries and MBZ for
426	* non-leaf (causes miconfiguration exit). */
427	#define EPT_E_MEMTYPE_MASK UINT64_C(0x0038)
428	/** Bits 3-5 - Memory type shifted mask. */
429	#define EPT_E_MEMTYPE_SMASK UINT64_C(0x0007)
430	/** Bits 3-5 - Memory type shift count. */
431	#define EPT_E_MEMTYPE_SHIFT 3
432	/** Bits 3-5 - Memory type: UC (Uncacheable). */
433	#define EPT_E_MEMTYPE_UC (UINT64_C(0) << EPT_E_MEMTYPE_SHIFT)
434	/** Bits 3-5 - Memory type: WC (Write Combining). */
435	#define EPT_E_MEMTYPE_WC (UINT64_C(1) << EPT_E_MEMTYPE_SHIFT)
436	/** Bits 3-5 - Memory type: Invalid (2). */
437	#define EPT_E_MEMTYPE_INVALID_2 (UINT64_C(2) << EPT_E_MEMTYPE_SHIFT)
438	/** Bits 3-5 - Memory type: Invalid (3). */
439	#define EPT_E_MEMTYPE_INVALID_3 (UINT64_C(3) << EPT_E_MEMTYPE_SHIFT)
440	/** Bits 3-5 - Memory type: WT (Write Through). */
441	#define EPT_E_MEMTYPE_WT (UINT64_C(4) << EPT_E_MEMTYPE_SHIFT)
442	/** Bits 3-5 - Memory type: WP (Write Protected). */
443	#define EPT_E_MEMTYPE_WP (UINT64_C(5) << EPT_E_MEMTYPE_SHIFT)
444	/** Bits 3-5 - Memory type: WB (Write Back). */
445	#define EPT_E_MEMTYPE_WB (UINT64_C(6) << EPT_E_MEMTYPE_SHIFT)
446	/** Bits 3-5 - Memory type: Invalid (7). */
447	#define EPT_E_MEMTYPE_INVALID_7 (UINT64_C(7) << EPT_E_MEMTYPE_SHIFT)
448
449	/** Bit 6 - Ignore page attribute table (leaf, MBZ). */
450	#define EPT_E_BIT_IGNORE_PAT 6
451	#define EPT_E_IGNORE_PAT RT_BIT_64(EPT_E_BIT_IGNORE_PAT) /*< @see EPT_E_BIT_IGNORE_PAT /
452	/** Bit 7 - Leaf entry (MBZ in PML4, ignored in PT). */
453	#define EPT_E_BIT_LEAF 7
454	#define EPT_E_LEAF RT_BIT_64(EPT_E_BIT_LEAF) /*< @see EPT_E_BIT_LEAF /
455	/** Bit 8 - Accessed (all levels).
456	* @note Ignored and not written when EPTP bit 6 is 0. */
457	#define EPT_E_BIT_ACCESSED 8
458	#define EPT_E_ACCESSED RT_BIT_64(EPT_E_BIT_ACCESSED) /*< @see EPT_E_BIT_ACCESSED /
459	/** Bit 9 - Dirty (leaf only).
460	* @note Ignored and not written when EPTP bit 6 is 0. */
461	#define EPT_E_BIT_DIRTY 9
462	#define EPT_E_DIRTY RT_BIT_64(EPT_E_BIT_DIRTY) /*< @see EPT_E_BIT_DIRTY /
463	/** Bit 10 - Executable for usermode.
464	* @note This ignored if mode-based execution control is disabled. */
465	#define EPT_E_BIT_USER_EXECUTE 10
466	#define EPT_E_USER_EXECUTE RT_BIT_64(EPT_E_BIT_USER_EXECUTE) /*< @see EPT_E_BIT_USER_EXECUTE /
467
468	/* 11 is always ignored (at time of writing) */
469
470	/** Bits 12-51 - Physical Page number of the next level. */
471	#define EPT_E_PG_MASK UINT64_C(0x000ffffffffff000)
472
473	/** Bit 58 - Page-write access (leaf only, ignored).
474	* @note Ignored if EPT page-write control is disabled. */
475	#define EPT_E_BIT_PAGING_WRITE 58
476	#define EPT_E_PAGING_WRITE RT_BIT_64(EPT_E_BIT_PAGING_WRITE) /*< @see EPT_E_BIT_PAGING_WRITE/
477
478	/* Bit 59 is always ignored. */
479
480	/** Bit 60 - Supervisor shadow stack (leaf only, ignored).
481	* @note Ignored if EPT bit 7 is 0. */
482	#define EPT_E_BIT_SUPER_SHW_STACK 60
483	#define EPT_E_SUPER_SHW_STACK RT_BIT_64(EPT_E_BIT_SUPER_SHW_STACK) /*< @see EPT_E_BIT_SUPER_SHW_STACK /
484
485	/** Bit 61 - Sub-page write permission (leaf only, ignored).
486	* @note Ignored if sub-page write permission for EPT is disabled. */
487	#define EPT_E_BIT_SUBPAGE_WRITE_PERM 61
488	#define EPT_E_SUBPAGE_WRITE_PERM RT_BIT_64(EPT_E_BIT_SUBPAGE_WRITE_PERM) /*< @see EPT_E_BIT_SUBPAGE_WRITE_PERM/
489
490	/* Bit 62 is always ignored. */
491
492	/** Bit 63 - Suppress \#VE (leaf only, ignored).
493	* @note Ignored if EPT violation to \#VE conversion is disabled. */
494	#define EPT_E_BIT_SUPPRESS_VE 63
495	#define EPT_E_SUPPRESS_VE RT_BIT_64(EPT_E_BIT_SUPPRESS_VE) /*< @see EPT_E_BIT_SUPPRESS_VE /
496	/** @} */
497
498
499	/**@name Bit fields for common EPT attributes.
500	@{ */
501	/** Read access. */
502	#define VMX_BF_EPT_PT_READ_SHIFT 0
503	#define VMX_BF_EPT_PT_READ_MASK UINT64_C(0x0000000000000001)
504	/** Write access. */
505	#define VMX_BF_EPT_PT_WRITE_SHIFT 1
506	#define VMX_BF_EPT_PT_WRITE_MASK UINT64_C(0x0000000000000002)
507	/** Execute access or execute access for supervisor-mode linear-addresses. */
508	#define VMX_BF_EPT_PT_EXECUTE_SHIFT 2
509	#define VMX_BF_EPT_PT_EXECUTE_MASK UINT64_C(0x0000000000000004)
510	/** EPT memory type. */
511	#define VMX_BF_EPT_PT_MEMTYPE_SHIFT 3
512	#define VMX_BF_EPT_PT_MEMTYPE_MASK UINT64_C(0x0000000000000038)
513	/** Ignore PAT. */
514	#define VMX_BF_EPT_PT_IGNORE_PAT_SHIFT 6
515	#define VMX_BF_EPT_PT_IGNORE_PAT_MASK UINT64_C(0x0000000000000040)
516	/** Ignored (bit 7). */
517	#define VMX_BF_EPT_PT_IGN_7_SHIFT 7
518	#define VMX_BF_EPT_PT_IGN_7_MASK UINT64_C(0x0000000000000080)
519	/** Accessed flag. */
520	#define VMX_BF_EPT_PT_ACCESSED_SHIFT 8
521	#define VMX_BF_EPT_PT_ACCESSED_MASK UINT64_C(0x0000000000000100)
522	/** Dirty flag. */
523	#define VMX_BF_EPT_PT_DIRTY_SHIFT 9
524	#define VMX_BF_EPT_PT_DIRTY_MASK UINT64_C(0x0000000000000200)
525	/** Execute access for user-mode linear addresses. */
526	#define VMX_BF_EPT_PT_EXECUTE_USER_SHIFT 10
527	#define VMX_BF_EPT_PT_EXECUTE_USER_MASK UINT64_C(0x0000000000000400)
528	/** Ignored (bit 59:11). */
529	#define VMX_BF_EPT_PT_IGN_59_11_SHIFT 11
530	#define VMX_BF_EPT_PT_IGN_59_11_MASK UINT64_C(0x0ffffffffffff800)
531	/** Supervisor shadow stack. */
532	#define VMX_BF_EPT_PT_SUPER_SHW_STACK_SHIFT 60
533	#define VMX_BF_EPT_PT_SUPER_SHW_STACK_MASK UINT64_C(0x1000000000000000)
534	/** Ignored (bits 62:61). */
535	#define VMX_BF_EPT_PT_IGN_62_61_SHIFT 61
536	#define VMX_BF_EPT_PT_IGN_62_61_MASK UINT64_C(0x6000000000000000)
537	/** Suppress \#VE. */
538	#define VMX_BF_EPT_PT_SUPPRESS_VE_SHIFT 63
539	#define VMX_BF_EPT_PT_SUPPRESS_VE_MASK UINT64_C(0x8000000000000000)
540	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EPT_PT_, UINT64_C(0), UINT64_MAX,
541	(READ, WRITE, EXECUTE, MEMTYPE, IGNORE_PAT, IGN_7, ACCESSED, DIRTY, EXECUTE_USER, IGN_59_11,
542	SUPER_SHW_STACK, IGN_62_61, SUPPRESS_VE));
543	/** @} */
544
545
546	/** @name VMX Extended Page Tables (EPT) Structures
547	* @{
548	*/
549
550	/**
551	* Number of page table entries in the EPT. (PDPTE/PDE/PTE)
552	*/
553	#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
554
555	/**
556	* EPT present mask.
557	* These are ONLY the common bits in all EPT page-table entries which does
558	* not rely on any CPU feature. It isn't necessarily the complete mask (e.g. when
559	* mode-based excute control is active).
560	*/
561	#define EPT_PRESENT_MASK (EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE)
562
563	/**
564	* EPT Page Directory Pointer Entry. Bit view.
565	* In accordance with the VT-x spec.
566	*
567	* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
568	* this did cause trouble with one compiler/version).
569	*/
570	typedef struct EPTPML4EBITS
571	{
572	/** Present bit. */
573	RT_GCC_EXTENSION uint64_t u1Present : 1;
574	/** Writable bit. */
575	RT_GCC_EXTENSION uint64_t u1Write : 1;
576	/** Executable bit. */
577	RT_GCC_EXTENSION uint64_t u1Execute : 1;
578	/** Reserved (must be 0). */
579	RT_GCC_EXTENSION uint64_t u5Reserved : 5;
580	/** Available for software. */
581	RT_GCC_EXTENSION uint64_t u4Available : 4;
582	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
583	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
584	/** Available for software. */
585	RT_GCC_EXTENSION uint64_t u12Available : 12;
586	} EPTPML4EBITS;
587	AssertCompileSize(EPTPML4EBITS, 8);
588
589	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
590	#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
591	/** The page shift to get the PML4 index. */
592	#define EPT_PML4_SHIFT X86_PML4_SHIFT
593	/** The PML4 index mask (apply to a shifted page address). */
594	#define EPT_PML4_MASK X86_PML4_MASK
595	/** Bits - - EPT - PML4 MBZ mask. */
596	#define EPT_PML4E_MBZ_MASK UINT64_C(0x00000000000000f8)
597	/** Mask of all possible EPT PML4E attribute bits. */
598	#define EPT_PML4E_ATTR_MASK (EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_ACCESSED \| EPT_E_USER_EXECUTE)
599
600	/**
601	* EPT PML4E.
602	* In accordance with the VT-x spec.
603	*/
604	typedef union EPTPML4E
605	{
606	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
607	/** Normal view. */
608	EPTPML4EBITS n;
609	#endif
610	/** Unsigned integer view. */
611	X86PGPAEUINT u;
612	/** 64 bit unsigned integer view. */
613	uint64_t au64[1];
614	/** 32 bit unsigned integer view. */
615	uint32_t au32[2];
616	} EPTPML4E;
617	AssertCompileSize(EPTPML4E, 8);
618	/** Pointer to a PML4 table entry. */
619	typedef EPTPML4E *PEPTPML4E;
620	/** Pointer to a const PML4 table entry. */
621	typedef const EPTPML4E *PCEPTPML4E;
622
623	/**
624	* EPT PML4 Table.
625	* In accordance with the VT-x spec.
626	*/
627	typedef struct EPTPML4
628	{
629	EPTPML4E a[EPT_PG_ENTRIES];
630	} EPTPML4;
631	AssertCompileSize(EPTPML4, 0x1000);
632	/** Pointer to an EPT PML4 Table. */
633	typedef EPTPML4 *PEPTPML4;
634	/** Pointer to a const EPT PML4 Table. */
635	typedef const EPTPML4 *PCEPTPML4;
636
637
638	/**
639	* EPT Page Directory Pointer Entry. Bit view.
640	* In accordance with the VT-x spec.
641	*/
642	typedef struct EPTPDPTEBITS
643	{
644	/** Present bit. */
645	RT_GCC_EXTENSION uint64_t u1Present : 1;
646	/** Writable bit. */
647	RT_GCC_EXTENSION uint64_t u1Write : 1;
648	/** Executable bit. */
649	RT_GCC_EXTENSION uint64_t u1Execute : 1;
650	/** Reserved (must be 0). */
651	RT_GCC_EXTENSION uint64_t u5Reserved : 5;
652	/** Available for software. */
653	RT_GCC_EXTENSION uint64_t u4Available : 4;
654	/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
655	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
656	/** Available for software. */
657	RT_GCC_EXTENSION uint64_t u12Available : 12;
658	} EPTPDPTEBITS;
659	AssertCompileSize(EPTPDPTEBITS, 8);
660
661	/** Bit 7 - - EPT - PDPTE maps a 1GB page. */
662	#define EPT_PDPTE1G_SIZE_MASK RT_BIT_64(7)
663	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
664	#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
665	/** Bits 30-51 - - EPT - Physical Page number of the 1G large page. */
666	#define EPT_PDPTE1G_PG_MASK X86_PDPE1G_PG_MASK
667
668	/** The page shift to get the PDPT index. */
669	#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
670	/** The PDPT index mask (apply to a shifted page address). */
671	#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
672	/** Bits 3-7 - - EPT - PDPTE MBZ Mask. */
673	#define EPT_PDPTE_MBZ_MASK UINT64_C(0x00000000000000f8)
674	/** Bits 12-29 - - EPT - 1GB PDPTE MBZ Mask. */
675	#define EPT_PDPTE1G_MBZ_MASK UINT64_C(0x000000003ffff000)
676	/** Mask of all possible EPT PDPTE (1GB) attribute bits. */
677	#define EPT_PDPTE1G_ATTR_MASK ( EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_MEMTYPE_MASK \| EPT_E_IGNORE_PAT \
678	\| EPT_E_ACCESSED \| EPT_E_DIRTY \| EPT_E_USER_EXECUTE)
679	/** Mask of all possible EPT PDPTE attribute bits. */
680	#define EPT_PDPTE_ATTR_MASK (EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_ACCESSED \| EPT_E_USER_EXECUTE)
681	/** */
682
683	/**
684	* EPT Page Directory Pointer.
685	* In accordance with the VT-x spec.
686	*/
687	typedef union EPTPDPTE
688	{
689	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
690	/** Normal view. */
691	EPTPDPTEBITS n;
692	#endif
693	/** Unsigned integer view. */
694	X86PGPAEUINT u;
695	/** 64 bit unsigned integer view. */
696	uint64_t au64[1];
697	/** 32 bit unsigned integer view. */
698	uint32_t au32[2];
699	} EPTPDPTE;
700	AssertCompileSize(EPTPDPTE, 8);
701	/** Pointer to an EPT Page Directory Pointer Entry. */
702	typedef EPTPDPTE *PEPTPDPTE;
703	/** Pointer to a const EPT Page Directory Pointer Entry. */
704	typedef const EPTPDPTE *PCEPTPDPTE;
705
706	/**
707	* EPT Page Directory Pointer Table.
708	* In accordance with the VT-x spec.
709	*/
710	typedef struct EPTPDPT
711	{
712	EPTPDPTE a[EPT_PG_ENTRIES];
713	} EPTPDPT;
714	AssertCompileSize(EPTPDPT, 0x1000);
715	/** Pointer to an EPT Page Directory Pointer Table. */
716	typedef EPTPDPT *PEPTPDPT;
717	/** Pointer to a const EPT Page Directory Pointer Table. */
718	typedef const EPTPDPT *PCEPTPDPT;
719
720
721	/**
722	* EPT Page Directory Table Entry. Bit view.
723	* In accordance with the VT-x spec.
724	*/
725	typedef struct EPTPDEBITS
726	{
727	/** Present bit. */
728	RT_GCC_EXTENSION uint64_t u1Present : 1;
729	/** Writable bit. */
730	RT_GCC_EXTENSION uint64_t u1Write : 1;
731	/** Executable bit. */
732	RT_GCC_EXTENSION uint64_t u1Execute : 1;
733	/** Reserved (must be 0). */
734	RT_GCC_EXTENSION uint64_t u4Reserved : 4;
735	/** Big page (must be 0 here). */
736	RT_GCC_EXTENSION uint64_t u1Size : 1;
737	/** Available for software. */
738	RT_GCC_EXTENSION uint64_t u4Available : 4;
739	/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
740	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
741	/** Available for software. */
742	RT_GCC_EXTENSION uint64_t u12Available : 12;
743	} EPTPDEBITS;
744	AssertCompileSize(EPTPDEBITS, 8);
745
746	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
747	#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
748	/** The page shift to get the PD index. */
749	#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
750	/** The PD index mask (apply to a shifted page address). */
751	#define EPT_PD_MASK X86_PD_PAE_MASK
752	/** Bits 3-7 - EPT - PDE MBZ Mask. */
753	#define EPT_PDE_MBZ_MASK UINT64_C(0x00000000000000f8)
754	/** Mask of all possible EPT PDE (2M) attribute bits. */
755	#define EPT_PDE2M_ATTR_MASK ( EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_MEMTYPE_MASK \| EPT_E_IGNORE_PAT \
756	\| EPT_E_ACCESSED \| EPT_E_DIRTY \| EPT_E_USER_EXECUTE)
757	/** Mask of all possible EPT PDE attribute bits. */
758	#define EPT_PDE_ATTR_MASK (EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_ACCESSED \| EPT_E_USER_EXECUTE)
759
760
761	/**
762	* EPT 2MB Page Directory Table Entry. Bit view.
763	* In accordance with the VT-x spec.
764	*/
765	typedef struct EPTPDE2MBITS
766	{
767	/** Present bit. */
768	RT_GCC_EXTENSION uint64_t u1Present : 1;
769	/** Writable bit. */
770	RT_GCC_EXTENSION uint64_t u1Write : 1;
771	/** Executable bit. */
772	RT_GCC_EXTENSION uint64_t u1Execute : 1;
773	/** EPT Table Memory Type. MBZ for non-leaf nodes. */
774	RT_GCC_EXTENSION uint64_t u3EMT : 3;
775	/** Ignore PAT memory type */
776	RT_GCC_EXTENSION uint64_t u1IgnorePAT : 1;
777	/** Big page (must be 1 here). */
778	RT_GCC_EXTENSION uint64_t u1Size : 1;
779	/** Available for software. */
780	RT_GCC_EXTENSION uint64_t u4Available : 4;
781	/** Reserved (must be 0). */
782	RT_GCC_EXTENSION uint64_t u9Reserved : 9;
783	/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
784	RT_GCC_EXTENSION uint64_t u31PhysAddr : 31;
785	/** Available for software. */
786	RT_GCC_EXTENSION uint64_t u12Available : 12;
787	} EPTPDE2MBITS;
788	AssertCompileSize(EPTPDE2MBITS, 8);
789
790	/** Bits 21-51 - - EPT - Physical Page number of the next level. */
791	#define EPT_PDE2M_PG_MASK X86_PDE2M_PAE_PG_MASK
792	/** Bits 20-12 - - EPT - PDE 2M MBZ Mask. */
793	#define EPT_PDE2M_MBZ_MASK UINT64_C(0x00000000001ff000)
794
795
796	/**
797	* EPT Page Directory Table Entry.
798	* In accordance with the VT-x spec.
799	*/
800	typedef union EPTPDE
801	{
802	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
803	/** Normal view. */
804	EPTPDEBITS n;
805	/** 2MB view (big). */
806	EPTPDE2MBITS b;
807	#endif
808	/** Unsigned integer view. */
809	X86PGPAEUINT u;
810	/** 64 bit unsigned integer view. */
811	uint64_t au64[1];
812	/** 32 bit unsigned integer view. */
813	uint32_t au32[2];
814	} EPTPDE;
815	AssertCompileSize(EPTPDE, 8);
816	/** Pointer to an EPT Page Directory Table Entry. */
817	typedef EPTPDE *PEPTPDE;
818	/** Pointer to a const EPT Page Directory Table Entry. */
819	typedef const EPTPDE *PCEPTPDE;
820
821	/**
822	* EPT Page Directory Table.
823	* In accordance with the VT-x spec.
824	*/
825	typedef struct EPTPD
826	{
827	EPTPDE a[EPT_PG_ENTRIES];
828	} EPTPD;
829	AssertCompileSize(EPTPD, 0x1000);
830	/** Pointer to an EPT Page Directory Table. */
831	typedef EPTPD *PEPTPD;
832	/** Pointer to a const EPT Page Directory Table. */
833	typedef const EPTPD *PCEPTPD;
834
835	/**
836	* EPT Page Table Entry. Bit view.
837	* In accordance with the VT-x spec.
838	*/
839	typedef struct EPTPTEBITS
840	{
841	/** 0 - Present bit.
842	* @remarks This is a convenience "misnomer". The bit actually indicates read access
843	* and the CPU will consider an entry with any of the first three bits set
844	* as present. Since all our valid entries will have this bit set, it can
845	* be used as a present indicator and allow some code sharing. */
846	RT_GCC_EXTENSION uint64_t u1Present : 1;
847	/** 1 - Writable bit. */
848	RT_GCC_EXTENSION uint64_t u1Write : 1;
849	/** 2 - Executable bit. */
850	RT_GCC_EXTENSION uint64_t u1Execute : 1;
851	/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
852	RT_GCC_EXTENSION uint64_t u3EMT : 3;
853	/** 6 - Ignore PAT memory type */
854	RT_GCC_EXTENSION uint64_t u1IgnorePAT : 1;
855	/** 11:7 - Available for software. */
856	RT_GCC_EXTENSION uint64_t u5Available : 5;
857	/** 51:12 - Physical address of page. Restricted by maximum physical
858	* address width of the cpu. */
859	RT_GCC_EXTENSION uint64_t u40PhysAddr : 40;
860	/** 63:52 - Available for software. */
861	RT_GCC_EXTENSION uint64_t u12Available : 12;
862	} EPTPTEBITS;
863	AssertCompileSize(EPTPTEBITS, 8);
864
865	/** Bits 12-51 - - EPT - Physical Page number of the next level. */
866	#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
867	/** The page shift to get the EPT PTE index. */
868	#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
869	/** The EPT PT index mask (apply to a shifted page address). */
870	#define EPT_PT_MASK X86_PT_PAE_MASK
871	/** No bits - - EPT - PTE MBZ bits. */
872	#define EPT_PTE_MBZ_MASK UINT64_C(0x0000000000000000)
873	/** Mask of all possible EPT PTE attribute bits. */
874	#define EPT_PTE_ATTR_MASK ( EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_MEMTYPE_MASK \| EPT_E_IGNORE_PAT \
875	\| EPT_E_ACCESSED \| EPT_E_USER_EXECUTE)
876
877
878	/**
879	* EPT Page Table Entry.
880	* In accordance with the VT-x spec.
881	*/
882	typedef union EPTPTE
883	{
884	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
885	/** Normal view. */
886	EPTPTEBITS n;
887	#endif
888	/** Unsigned integer view. */
889	X86PGPAEUINT u;
890	/** 64 bit unsigned integer view. */
891	uint64_t au64[1];
892	/** 32 bit unsigned integer view. */
893	uint32_t au32[2];
894	} EPTPTE;
895	AssertCompileSize(EPTPTE, 8);
896	/** Pointer to an EPT Page Directory Table Entry. */
897	typedef EPTPTE *PEPTPTE;
898	/** Pointer to a const EPT Page Directory Table Entry. */
899	typedef const EPTPTE *PCEPTPTE;
900
901	/**
902	* EPT Page Table.
903	* In accordance with the VT-x spec.
904	*/
905	typedef struct EPTPT
906	{
907	EPTPTE a[EPT_PG_ENTRIES];
908	} EPTPT;
909	AssertCompileSize(EPTPT, 0x1000);
910	/** Pointer to an extended page table. */
911	typedef EPTPT *PEPTPT;
912	/** Pointer to a const extended table. */
913	typedef const EPTPT *PCEPTPT;
914
915	/** EPTP page mask for the EPT PML4 table. */
916	#define EPT_EPTP_PG_MASK X86_CR3_AMD64_PAGE_MASK
917	/** @} */
918
919	/**
920	* VMX VPID flush types.
921	* Valid enum members are in accordance with the VT-x spec.
922	*/
923	typedef enum
924	{
925	/** Invalidate a specific page. */
926	VMXTLBFLUSHVPID_INDIV_ADDR = 0,
927	/** Invalidate one context (specific VPID). */
928	VMXTLBFLUSHVPID_SINGLE_CONTEXT = 1,
929	/** Invalidate all contexts (all VPIDs). */
930	VMXTLBFLUSHVPID_ALL_CONTEXTS = 2,
931	/** Invalidate a single VPID context retaining global mappings. */
932	VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
933	/** Unsupported by VirtualBox. */
934	VMXTLBFLUSHVPID_NOT_SUPPORTED = 0xbad0,
935	/** Unsupported by CPU. */
936	VMXTLBFLUSHVPID_NONE = 0xbad1
937	} VMXTLBFLUSHVPID;
938	AssertCompileSize(VMXTLBFLUSHVPID, 4);
939	/** Mask of all valid INVVPID flush types. */
940	#define VMX_INVVPID_VALID_MASK ( VMXTLBFLUSHVPID_INDIV_ADDR \
941	\| VMXTLBFLUSHVPID_SINGLE_CONTEXT \
942	\| VMXTLBFLUSHVPID_ALL_CONTEXTS \
943	\| VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
944
945	/**
946	* VMX EPT flush types.
947	* @note Valid enums values are in accordance with the VT-x spec.
948	*/
949	typedef enum
950	{
951	/** Invalidate one context (specific EPT). */
952	VMXTLBFLUSHEPT_SINGLE_CONTEXT = 1,
953	/* Invalidate all contexts (all EPTs) */
954	VMXTLBFLUSHEPT_ALL_CONTEXTS = 2,
955	/** Unsupported by VirtualBox. */
956	VMXTLBFLUSHEPT_NOT_SUPPORTED = 0xbad0,
957	/** Unsupported by CPU. */
958	VMXTLBFLUSHEPT_NONE = 0xbad1
959	} VMXTLBFLUSHEPT;
960	AssertCompileSize(VMXTLBFLUSHEPT, 4);
961	/** Mask of all valid INVEPT flush types. */
962	#define VMX_INVEPT_VALID_MASK ( VMXTLBFLUSHEPT_SINGLE_CONTEXT \
963	\| VMXTLBFLUSHEPT_ALL_CONTEXTS)
964
965	/**
966	* VMX Posted Interrupt Descriptor.
967	* In accordance with the VT-x spec.
968	*/
969	typedef struct VMXPOSTEDINTRDESC
970	{
971	uint32_t aVectorBitmap[8];
972	uint32_t fOutstandingNotification : 1;
973	uint32_t uReserved0 : 31;
974	uint8_t au8Reserved0[28];
975	} VMXPOSTEDINTRDESC;
976	AssertCompileMemberSize(VMXPOSTEDINTRDESC, aVectorBitmap, 32);
977	AssertCompileSize(VMXPOSTEDINTRDESC, 64);
978	/** Pointer to a posted interrupt descriptor. */
979	typedef VMXPOSTEDINTRDESC *PVMXPOSTEDINTRDESC;
980	/** Pointer to a const posted interrupt descriptor. */
981	typedef const VMXPOSTEDINTRDESC *PCVMXPOSTEDINTRDESC;
982
983	/**
984	* VMX VMCS revision identifier.
985	* In accordance with the VT-x spec.
986	*/
987	typedef union
988	{
989	struct
990	{
991	/** Revision identifier. */
992	uint32_t u31RevisionId : 31;
993	/** Whether this is a shadow VMCS. */
994	uint32_t fIsShadowVmcs : 1;
995	} n;
996	/* The unsigned integer view. */
997	uint32_t u;
998	} VMXVMCSREVID;
999	AssertCompileSize(VMXVMCSREVID, 4);
1000	/** Pointer to the VMXVMCSREVID union. */
1001	typedef VMXVMCSREVID *PVMXVMCSREVID;
1002	/** Pointer to a const VMXVMCSREVID union. */
1003	typedef const VMXVMCSREVID *PCVMXVMCSREVID;
1004
1005	/**
1006	* VMX VM-exit instruction information.
1007	* In accordance with the VT-x spec.
1008	*/
1009	typedef union
1010	{
1011	/** Plain unsigned int representation. */
1012	uint32_t u;
1013
1014	/** INS and OUTS information. */
1015	struct
1016	{
1017	uint32_t u7Reserved0 : 7;
1018	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1019	uint32_t u3AddrSize : 3;
1020	uint32_t u5Reserved1 : 5;
1021	/** The segment register (X86_SREG_XXX). */
1022	uint32_t iSegReg : 3;
1023	uint32_t uReserved2 : 14;
1024	} StrIo;
1025
1026	/** INVEPT, INVPCID, INVVPID information. */
1027	struct
1028	{
1029	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1030	uint32_t u2Scaling : 2;
1031	uint32_t u5Undef0 : 5;
1032	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1033	uint32_t u3AddrSize : 3;
1034	/** Cleared to 0. */
1035	uint32_t u1Cleared0 : 1;
1036	uint32_t u4Undef0 : 4;
1037	/** The segment register (X86_SREG_XXX). */
1038	uint32_t iSegReg : 3;
1039	/** The index register (X86_GREG_XXX). */
1040	uint32_t iIdxReg : 4;
1041	/** Set if index register is invalid. */
1042	uint32_t fIdxRegInvalid : 1;
1043	/** The base register (X86_GREG_XXX). */
1044	uint32_t iBaseReg : 4;
1045	/** Set if base register is invalid. */
1046	uint32_t fBaseRegInvalid : 1;
1047	/** Register 2 (X86_GREG_XXX). */
1048	uint32_t iReg2 : 4;
1049	} Inv;
1050
1051	/** VMCLEAR, VMPTRLD, VMPTRST, VMXON, XRSTORS, XSAVES information. */
1052	struct
1053	{
1054	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1055	uint32_t u2Scaling : 2;
1056	uint32_t u5Reserved0 : 5;
1057	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1058	uint32_t u3AddrSize : 3;
1059	/** Cleared to 0. */
1060	uint32_t u1Cleared0 : 1;
1061	uint32_t u4Reserved0 : 4;
1062	/** The segment register (X86_SREG_XXX). */
1063	uint32_t iSegReg : 3;
1064	/** The index register (X86_GREG_XXX). */
1065	uint32_t iIdxReg : 4;
1066	/** Set if index register is invalid. */
1067	uint32_t fIdxRegInvalid : 1;
1068	/** The base register (X86_GREG_XXX). */
1069	uint32_t iBaseReg : 4;
1070	/** Set if base register is invalid. */
1071	uint32_t fBaseRegInvalid : 1;
1072	/** Register 2 (X86_GREG_XXX). */
1073	uint32_t iReg2 : 4;
1074	} VmxXsave;
1075
1076	/** LIDT, LGDT, SIDT, SGDT information. */
1077	struct
1078	{
1079	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1080	uint32_t u2Scaling : 2;
1081	uint32_t u5Undef0 : 5;
1082	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1083	uint32_t u3AddrSize : 3;
1084	/** Always cleared to 0. */
1085	uint32_t u1Cleared0 : 1;
1086	/** Operand size; 0=16-bit, 1=32-bit, undefined for 64-bit. */
1087	uint32_t uOperandSize : 1;
1088	uint32_t u3Undef0 : 3;
1089	/** The segment register (X86_SREG_XXX). */
1090	uint32_t iSegReg : 3;
1091	/** The index register (X86_GREG_XXX). */
1092	uint32_t iIdxReg : 4;
1093	/** Set if index register is invalid. */
1094	uint32_t fIdxRegInvalid : 1;
1095	/** The base register (X86_GREG_XXX). */
1096	uint32_t iBaseReg : 4;
1097	/** Set if base register is invalid. */
1098	uint32_t fBaseRegInvalid : 1;
1099	/** Instruction identity (VMX_INSTR_ID_XXX). */
1100	uint32_t u2InstrId : 2;
1101	uint32_t u2Undef0 : 2;
1102	} GdtIdt;
1103
1104	/** LLDT, LTR, SLDT, STR information. */
1105	struct
1106	{
1107	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1108	uint32_t u2Scaling : 2;
1109	uint32_t u1Undef0 : 1;
1110	/** Register 1 (X86_GREG_XXX). */
1111	uint32_t iReg1 : 4;
1112	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1113	uint32_t u3AddrSize : 3;
1114	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
1115	uint32_t fIsRegOperand : 1;
1116	uint32_t u4Undef0 : 4;
1117	/** The segment register (X86_SREG_XXX). */
1118	uint32_t iSegReg : 3;
1119	/** The index register (X86_GREG_XXX). */
1120	uint32_t iIdxReg : 4;
1121	/** Set if index register is invalid. */
1122	uint32_t fIdxRegInvalid : 1;
1123	/** The base register (X86_GREG_XXX). */
1124	uint32_t iBaseReg : 4;
1125	/** Set if base register is invalid. */
1126	uint32_t fBaseRegInvalid : 1;
1127	/** Instruction identity (VMX_INSTR_ID_XXX). */
1128	uint32_t u2InstrId : 2;
1129	uint32_t u2Undef0 : 2;
1130	} LdtTr;
1131
1132	/** RDRAND, RDSEED information. */
1133	struct
1134	{
1135	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1136	uint32_t u2Undef0 : 2;
1137	/** Destination register (X86_GREG_XXX). */
1138	uint32_t iReg1 : 4;
1139	uint32_t u4Undef0 : 4;
1140	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1141	uint32_t u2OperandSize : 2;
1142	uint32_t u19Def0 : 20;
1143	} RdrandRdseed;
1144
1145	/** VMREAD, VMWRITE information. */
1146	struct
1147	{
1148	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1149	uint32_t u2Scaling : 2;
1150	uint32_t u1Undef0 : 1;
1151	/** Register 1 (X86_GREG_XXX). */
1152	uint32_t iReg1 : 4;
1153	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1154	uint32_t u3AddrSize : 3;
1155	/** Memory or register operand. */
1156	uint32_t fIsRegOperand : 1;
1157	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1158	uint32_t u4Undef0 : 4;
1159	/** The segment register (X86_SREG_XXX). */
1160	uint32_t iSegReg : 3;
1161	/** The index register (X86_GREG_XXX). */
1162	uint32_t iIdxReg : 4;
1163	/** Set if index register is invalid. */
1164	uint32_t fIdxRegInvalid : 1;
1165	/** The base register (X86_GREG_XXX). */
1166	uint32_t iBaseReg : 4;
1167	/** Set if base register is invalid. */
1168	uint32_t fBaseRegInvalid : 1;
1169	/** Register 2 (X86_GREG_XXX). */
1170	uint32_t iReg2 : 4;
1171	} VmreadVmwrite;
1172
1173	struct
1174	{
1175	uint32_t u2Undef0 : 3;
1176	/** First XMM register operand. */
1177	uint32_t u4XmmReg1 : 4;
1178	uint32_t u23Undef1 : 21;
1179	/** Second XMM register operand. */
1180	uint32_t u4XmmReg2 : 4;
1181	} LoadIwkey;
1182
1183	/** This is a combination field of all instruction information. Note! Not all field
1184	* combinations are valid (e.g., iReg1 is undefined for memory operands) and
1185	* specialized fields are overwritten by their generic counterparts (e.g. no
1186	* instruction identity field). */
1187	struct
1188	{
1189	/** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
1190	uint32_t u2Scaling : 2;
1191	uint32_t u1Undef0 : 1;
1192	/** Register 1 (X86_GREG_XXX). */
1193	uint32_t iReg1 : 4;
1194	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
1195	uint32_t u3AddrSize : 3;
1196	/** Memory/Register - Always cleared to 0 to indicate memory operand. */
1197	uint32_t fIsRegOperand : 1;
1198	/** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused. */
1199	uint32_t uOperandSize : 2;
1200	uint32_t u2Undef0 : 2;
1201	/** The segment register (X86_SREG_XXX). */
1202	uint32_t iSegReg : 3;
1203	/** The index register (X86_GREG_XXX). */
1204	uint32_t iIdxReg : 4;
1205	/** Set if index register is invalid. */
1206	uint32_t fIdxRegInvalid : 1;
1207	/** The base register (X86_GREG_XXX). */
1208	uint32_t iBaseReg : 4;
1209	/** Set if base register is invalid. */
1210	uint32_t fBaseRegInvalid : 1;
1211	/** Register 2 (X86_GREG_XXX) or instruction identity. */
1212	uint32_t iReg2 : 4;
1213	} All;
1214	} VMXEXITINSTRINFO;
1215	AssertCompileSize(VMXEXITINSTRINFO, 4);
1216	/** Pointer to a VMX VM-exit instruction info. struct. */
1217	typedef VMXEXITINSTRINFO *PVMXEXITINSTRINFO;
1218	/** Pointer to a const VMX VM-exit instruction info. struct. */
1219	typedef const VMXEXITINSTRINFO *PCVMXEXITINSTRINFO;
1220
1221
1222	/** @name VM-entry failure reported in Exit qualification.
1223	* See Intel spec. 26.7 "VM-entry failures during or after loading guest-state".
1224	* @{
1225	*/
1226	/** No errors during VM-entry. */
1227	#define VMX_ENTRY_FAIL_QUAL_NO_ERROR (0)
1228	/** Not used. */
1229	#define VMX_ENTRY_FAIL_QUAL_NOT_USED (1)
1230	/** Error while loading PDPTEs. */
1231	#define VMX_ENTRY_FAIL_QUAL_PDPTE (2)
1232	/** NMI injection when blocking-by-STI is set. */
1233	#define VMX_ENTRY_FAIL_QUAL_NMI_INJECT (3)
1234	/** Invalid VMCS link pointer. */
1235	#define VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR (4)
1236	/** @} */
1237
1238
1239	/** @name VMXMSRPM_XXX - VMX MSR-bitmap permissions.
1240	* These are -not- specified by Intel but used internally by VirtualBox.
1241	* @{ */
1242	/** Guest software reads of this MSR must not cause a VM-exit. */
1243	#define VMXMSRPM_ALLOW_RD RT_BIT(0)
1244	/** Guest software reads of this MSR must cause a VM-exit. */
1245	#define VMXMSRPM_EXIT_RD RT_BIT(1)
1246	/** Guest software writes to this MSR must not cause a VM-exit. */
1247	#define VMXMSRPM_ALLOW_WR RT_BIT(2)
1248	/** Guest software writes to this MSR must cause a VM-exit. */
1249	#define VMXMSRPM_EXIT_WR RT_BIT(3)
1250	/** Guest software reads or writes of this MSR must not cause a VM-exit. */
1251	#define VMXMSRPM_ALLOW_RD_WR (VMXMSRPM_ALLOW_RD \| VMXMSRPM_ALLOW_WR)
1252	/** Guest software reads or writes of this MSR must cause a VM-exit. */
1253	#define VMXMSRPM_EXIT_RD_WR (VMXMSRPM_EXIT_RD \| VMXMSRPM_EXIT_WR)
1254	/** Mask of valid MSR read permissions. */
1255	#define VMXMSRPM_RD_MASK (VMXMSRPM_ALLOW_RD \| VMXMSRPM_EXIT_RD)
1256	/** Mask of valid MSR write permissions. */
1257	#define VMXMSRPM_WR_MASK (VMXMSRPM_ALLOW_WR \| VMXMSRPM_EXIT_WR)
1258	/** Mask of valid MSR permissions. */
1259	#define VMXMSRPM_MASK (VMXMSRPM_RD_MASK \| VMXMSRPM_WR_MASK)
1260	/** */
1261	/** Gets whether the MSR permission is valid or not. */
1262	#define VMXMSRPM_IS_FLAG_VALID(a_Msrpm) ( (a_Msrpm) != 0 \
1263	&& ((a_Msrpm) & ~VMXMSRPM_MASK) == 0 \
1264	&& ((a_Msrpm) & VMXMSRPM_RD_MASK) != VMXMSRPM_RD_MASK \
1265	&& ((a_Msrpm) & VMXMSRPM_WR_MASK) != VMXMSRPM_WR_MASK)
1266	/** @} */
1267
1268	/**
1269	* VMX MSR autoload/store slot.
1270	* In accordance with the VT-x spec.
1271	*/
1272	typedef struct VMXAUTOMSR
1273	{
1274	/** The MSR Id. */
1275	uint32_t u32Msr;
1276	/** Reserved (MBZ). */
1277	uint32_t u32Reserved;
1278	/** The MSR value. */
1279	uint64_t u64Value;
1280	} VMXAUTOMSR;
1281	AssertCompileSize(VMXAUTOMSR, 16);
1282	/** Pointer to an MSR load/store element. */
1283	typedef VMXAUTOMSR *PVMXAUTOMSR;
1284	/** Pointer to a const MSR load/store element. */
1285	typedef const VMXAUTOMSR *PCVMXAUTOMSR;
1286
1287	/** VMX auto load-store MSR (VMXAUTOMSR) offset mask. */
1288	#define VMX_AUTOMSR_OFFSET_MASK 0xf
1289
1290	/**
1291	* VMX tagged-TLB flush types.
1292	*/
1293	typedef enum
1294	{
1295	VMXTLBFLUSHTYPE_EPT,
1296	VMXTLBFLUSHTYPE_VPID,
1297	VMXTLBFLUSHTYPE_EPT_VPID,
1298	VMXTLBFLUSHTYPE_NONE
1299	} VMXTLBFLUSHTYPE;
1300	/** Pointer to a VMXTLBFLUSHTYPE enum. */
1301	typedef VMXTLBFLUSHTYPE *PVMXTLBFLUSHTYPE;
1302	/** Pointer to a const VMXTLBFLUSHTYPE enum. */
1303	typedef const VMXTLBFLUSHTYPE *PCVMXTLBFLUSHTYPE;
1304
1305	/**
1306	* VMX controls MSR.
1307	* In accordance with the VT-x spec.
1308	*/
1309	typedef union
1310	{
1311	struct
1312	{
1313	/** Bits set here -must- be set in the corresponding VM-execution controls. */
1314	uint32_t allowed0;
1315	/** Bits cleared here -must- be cleared in the corresponding VM-execution
1316	* controls. */
1317	uint32_t allowed1;
1318	} n;
1319	uint64_t u;
1320	} VMXCTLSMSR;
1321	AssertCompileSize(VMXCTLSMSR, 8);
1322	/** Pointer to a VMXCTLSMSR union. */
1323	typedef VMXCTLSMSR *PVMXCTLSMSR;
1324	/** Pointer to a const VMXCTLSMSR union. */
1325	typedef const VMXCTLSMSR *PCVMXCTLSMSR;
1326
1327	/**
1328	* VMX MSRs.
1329	*/
1330	typedef struct VMXMSRS
1331	{
1332	/** Basic information. */
1333	uint64_t u64Basic;
1334	/** Pin-based VM-execution controls. */
1335	VMXCTLSMSR PinCtls;
1336	/** Processor-based VM-execution controls. */
1337	VMXCTLSMSR ProcCtls;
1338	/** Secondary processor-based VM-execution controls. */
1339	VMXCTLSMSR ProcCtls2;
1340	/** VM-exit controls. */
1341	VMXCTLSMSR ExitCtls;
1342	/** VM-entry controls. */
1343	VMXCTLSMSR EntryCtls;
1344	/** True pin-based VM-execution controls. */
1345	VMXCTLSMSR TruePinCtls;
1346	/** True processor-based VM-execution controls. */
1347	VMXCTLSMSR TrueProcCtls;
1348	/** True VM-entry controls. */
1349	VMXCTLSMSR TrueEntryCtls;
1350	/** True VM-exit controls. */
1351	VMXCTLSMSR TrueExitCtls;
1352	/** Miscellaneous data. */
1353	uint64_t u64Misc;
1354	/** CR0 fixed-0 - bits set here must be set in VMX operation. */
1355	uint64_t u64Cr0Fixed0;
1356	/** CR0 fixed-1 - bits clear here must be clear in VMX operation. */
1357	uint64_t u64Cr0Fixed1;
1358	/** CR4 fixed-0 - bits set here must be set in VMX operation. */
1359	uint64_t u64Cr4Fixed0;
1360	/** CR4 fixed-1 - bits clear here must be clear in VMX operation. */
1361	uint64_t u64Cr4Fixed1;
1362	/** VMCS enumeration. */
1363	uint64_t u64VmcsEnum;
1364	/** VM Functions. */
1365	uint64_t u64VmFunc;
1366	/** EPT, VPID capabilities. */
1367	uint64_t u64EptVpidCaps;
1368	/** Tertiary processor-based VM-execution controls. */
1369	uint64_t u64ProcCtls3;
1370	/** Reserved for future. */
1371	uint64_t a_u64Reserved[9];
1372	} VMXMSRS;
1373	AssertCompileSizeAlignment(VMXMSRS, 8);
1374	AssertCompileSize(VMXMSRS, 224);
1375	/** Pointer to a VMXMSRS struct. */
1376	typedef VMXMSRS *PVMXMSRS;
1377	/** Pointer to a const VMXMSRS struct. */
1378	typedef const VMXMSRS *PCVMXMSRS;
1379
1380
1381	/**
1382	* LBR MSRs.
1383	*/
1384	typedef struct LBRMSRS
1385	{
1386	/** List of LastBranch-From-IP MSRs. */
1387	uint64_t au64BranchFromIpMsr[32];
1388	/** List of LastBranch-To-IP MSRs. */
1389	uint64_t au64BranchToIpMsr[32];
1390	/** The MSR containing the index to the most recent branch record. */
1391	uint64_t uBranchTosMsr;
1392	} LBRMSRS;
1393	AssertCompileSizeAlignment(LBRMSRS, 8);
1394	/** Pointer to a VMXMSRS struct. */
1395	typedef LBRMSRS *PLBRMSRS;
1396	/** Pointer to a const VMXMSRS struct. */
1397	typedef const LBRMSRS *PCLBRMSRS;
1398
1399
1400	/** @name VMX Basic Exit Reasons.
1401	* In accordance with the VT-x spec.
1402	* Update g_aVMExitHandlers if new VM-exit reasons are added.
1403	* @{
1404	*/
1405	/** Invalid exit code */
1406	#define VMX_EXIT_INVALID (-1)
1407	/** Exception or non-maskable interrupt (NMI). */
1408	#define VMX_EXIT_XCPT_OR_NMI 0
1409	/** External interrupt. */
1410	#define VMX_EXIT_EXT_INT 1
1411	/** Triple fault. */
1412	#define VMX_EXIT_TRIPLE_FAULT 2
1413	/** INIT signal. */
1414	#define VMX_EXIT_INIT_SIGNAL 3
1415	/** Start-up IPI (SIPI). */
1416	#define VMX_EXIT_SIPI 4
1417	/** I/O system-management interrupt (SMI). */
1418	#define VMX_EXIT_IO_SMI 5
1419	/** Other SMI. */
1420	#define VMX_EXIT_SMI 6
1421	/** Interrupt window exiting. */
1422	#define VMX_EXIT_INT_WINDOW 7
1423	/** NMI window exiting. */
1424	#define VMX_EXIT_NMI_WINDOW 8
1425	/** Task switch. */
1426	#define VMX_EXIT_TASK_SWITCH 9
1427	/** CPUID. */
1428	#define VMX_EXIT_CPUID 10
1429	/** GETSEC. */
1430	#define VMX_EXIT_GETSEC 11
1431	/** HLT. */
1432	#define VMX_EXIT_HLT 12
1433	/** INVD. */
1434	#define VMX_EXIT_INVD 13
1435	/** INVLPG. */
1436	#define VMX_EXIT_INVLPG 14
1437	/** RDPMC. */
1438	#define VMX_EXIT_RDPMC 15
1439	/** RDTSC. */
1440	#define VMX_EXIT_RDTSC 16
1441	/** RSM in SMM. */
1442	#define VMX_EXIT_RSM 17
1443	/** VMCALL. */
1444	#define VMX_EXIT_VMCALL 18
1445	/** VMCLEAR. */
1446	#define VMX_EXIT_VMCLEAR 19
1447	/** VMLAUNCH. */
1448	#define VMX_EXIT_VMLAUNCH 20
1449	/** VMPTRLD. */
1450	#define VMX_EXIT_VMPTRLD 21
1451	/** VMPTRST. */
1452	#define VMX_EXIT_VMPTRST 22
1453	/** VMREAD. */
1454	#define VMX_EXIT_VMREAD 23
1455	/** VMRESUME. */
1456	#define VMX_EXIT_VMRESUME 24
1457	/** VMWRITE. */
1458	#define VMX_EXIT_VMWRITE 25
1459	/** VMXOFF. */
1460	#define VMX_EXIT_VMXOFF 26
1461	/** VMXON. */
1462	#define VMX_EXIT_VMXON 27
1463	/** Control-register accesses. */
1464	#define VMX_EXIT_MOV_CRX 28
1465	/** Debug-register accesses. */
1466	#define VMX_EXIT_MOV_DRX 29
1467	/** I/O instruction. */
1468	#define VMX_EXIT_IO_INSTR 30
1469	/** RDMSR. */
1470	#define VMX_EXIT_RDMSR 31
1471	/** WRMSR. */
1472	#define VMX_EXIT_WRMSR 32
1473	/** VM-entry failure due to invalid guest state. */
1474	#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
1475	/** VM-entry failure due to MSR loading. */
1476	#define VMX_EXIT_ERR_MSR_LOAD 34
1477	/** MWAIT. */
1478	#define VMX_EXIT_MWAIT 36
1479	/** VM-exit due to monitor trap flag. */
1480	#define VMX_EXIT_MTF 37
1481	/** MONITOR. */
1482	#define VMX_EXIT_MONITOR 39
1483	/** PAUSE. */
1484	#define VMX_EXIT_PAUSE 40
1485	/** VM-entry failure due to machine-check. */
1486	#define VMX_EXIT_ERR_MACHINE_CHECK 41
1487	/** TPR below threshold. Guest software executed MOV to CR8. */
1488	#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
1489	/** VM-exit due to guest accessing physical address in the APIC-access page. */
1490	#define VMX_EXIT_APIC_ACCESS 44
1491	/** VM-exit due to EOI virtualization. */
1492	#define VMX_EXIT_VIRTUALIZED_EOI 45
1493	/** Access to GDTR/IDTR using LGDT, LIDT, SGDT or SIDT. */
1494	#define VMX_EXIT_GDTR_IDTR_ACCESS 46
1495	/** Access to LDTR/TR due to LLDT, LTR, SLDT, or STR. */
1496	#define VMX_EXIT_LDTR_TR_ACCESS 47
1497	/** EPT violation. */
1498	#define VMX_EXIT_EPT_VIOLATION 48
1499	/** EPT misconfiguration. */
1500	#define VMX_EXIT_EPT_MISCONFIG 49
1501	/** INVEPT. */
1502	#define VMX_EXIT_INVEPT 50
1503	/** RDTSCP. */
1504	#define VMX_EXIT_RDTSCP 51
1505	/** VMX-preemption timer expired. */
1506	#define VMX_EXIT_PREEMPT_TIMER 52
1507	/** INVVPID. */
1508	#define VMX_EXIT_INVVPID 53
1509	/** WBINVD. */
1510	#define VMX_EXIT_WBINVD 54
1511	/** XSETBV. */
1512	#define VMX_EXIT_XSETBV 55
1513	/** Guest completed write to virtual-APIC. */
1514	#define VMX_EXIT_APIC_WRITE 56
1515	/** RDRAND. */
1516	#define VMX_EXIT_RDRAND 57
1517	/** INVPCID. */
1518	#define VMX_EXIT_INVPCID 58
1519	/** VMFUNC. */
1520	#define VMX_EXIT_VMFUNC 59
1521	/** ENCLS. */
1522	#define VMX_EXIT_ENCLS 60
1523	/** RDSEED. */
1524	#define VMX_EXIT_RDSEED 61
1525	/** Page-modification log full. */
1526	#define VMX_EXIT_PML_FULL 62
1527	/** XSAVES. */
1528	#define VMX_EXIT_XSAVES 63
1529	/** XRSTORS. */
1530	#define VMX_EXIT_XRSTORS 64
1531	/** SPP-related event (SPP miss or misconfiguration). */
1532	#define VMX_EXIT_SPP_EVENT 66
1533	/* UMWAIT. */
1534	#define VMX_EXIT_UMWAIT 67
1535	/** TPAUSE. */
1536	#define VMX_EXIT_TPAUSE 68
1537	/** LOADIWKEY. */
1538	#define VMX_EXIT_LOADIWKEY 69
1539	/** The maximum VM-exit value (inclusive). */
1540	#define VMX_EXIT_MAX (VMX_EXIT_LOADIWKEY)
1541	/** @} */
1542
1543
1544	/** @name VM Instruction Errors.
1545	* In accordance with the VT-x spec.
1546	* See Intel spec. "30.4 VM Instruction Error Numbers"
1547	* @{
1548	*/
1549	typedef enum
1550	{
1551	/** VMCALL executed in VMX root operation. */
1552	VMXINSTRERR_VMCALL_VMXROOTMODE = 1,
1553	/** VMCLEAR with invalid physical address. */
1554	VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR = 2,
1555	/** VMCLEAR with VMXON pointer. */
1556	VMXINSTRERR_VMCLEAR_VMXON_PTR = 3,
1557	/** VMLAUNCH with non-clear VMCS. */
1558	VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS = 4,
1559	/** VMRESUME with non-launched VMCS. */
1560	VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS = 5,
1561	/** VMRESUME after VMXOFF (VMXOFF and VMXON between VMLAUNCH and VMRESUME). */
1562	VMXINSTRERR_VMRESUME_AFTER_VMXOFF = 6,
1563	/** VM-entry with invalid control field(s). */
1564	VMXINSTRERR_VMENTRY_INVALID_CTLS = 7,
1565	/** VM-entry with invalid host-state field(s). */
1566	VMXINSTRERR_VMENTRY_INVALID_HOST_STATE = 8,
1567	/** VMPTRLD with invalid physical address. */
1568	VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR = 9,
1569	/** VMPTRLD with VMXON pointer. */
1570	VMXINSTRERR_VMPTRLD_VMXON_PTR = 10,
1571	/** VMPTRLD with incorrect VMCS revision identifier. */
1572	VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV = 11,
1573	/** VMREAD from unsupported VMCS component. */
1574	VMXINSTRERR_VMREAD_INVALID_COMPONENT = 12,
1575	/** VMWRITE to unsupported VMCS component. */
1576	VMXINSTRERR_VMWRITE_INVALID_COMPONENT = 12,
1577	/** VMWRITE to read-only VMCS component. */
1578	VMXINSTRERR_VMWRITE_RO_COMPONENT = 13,
1579	/** VMXON executed in VMX root operation. */
1580	VMXINSTRERR_VMXON_IN_VMXROOTMODE = 15,
1581	/** VM-entry with invalid executive-VMCS pointer. */
1582	VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_PTR = 16,
1583	/** VM-entry with non-launched executive VMCS. */
1584	VMXINSTRERR_VMENTRY_EXEC_VMCS_NON_LAUNCHED = 17,
1585	/** VM-entry with executive-VMCS pointer not VMXON pointer. */
1586	VMXINSTRERR_VMENTRY_EXEC_VMCS_PTR = 18,
1587	/** VMCALL with non-clear VMCS. */
1588	VMXINSTRERR_VMCALL_NON_CLEAR_VMCS = 19,
1589	/** VMCALL with invalid VM-exit control fields. */
1590	VMXINSTRERR_VMCALL_INVALID_EXITCTLS = 20,
1591	/** VMCALL with incorrect MSEG revision identifier. */
1592	VMXINSTRERR_VMCALL_INVALID_MSEG_ID = 22,
1593	/** VMXOFF under dual-monitor treatment of SMIs and SMM. */
1594	VMXINSTRERR_VMXOFF_DUAL_MON = 23,
1595	/** VMCALL with invalid SMM-monitor features. */
1596	VMXINSTRERR_VMCALL_INVALID_SMMCTLS = 24,
1597	/** VM-entry with invalid VM-execution control fields in executive VMCS. */
1598	VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_CTLS = 25,
1599	/** VM-entry with events blocked by MOV SS. */
1600	VMXINSTRERR_VMENTRY_BLOCK_MOVSS = 26,
1601	/** Invalid operand to INVEPT/INVVPID. */
1602	VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND = 28
1603	} VMXINSTRERR;
1604	/** @} */
1605
1606
1607	/** @name VMX abort reasons.
1608	* In accordance with the VT-x spec.
1609	* See Intel spec. "27.7 VMX Aborts".
1610	* Update HMGetVmxAbortDesc() if new reasons are added.
1611	* @{
1612	*/
1613	typedef enum
1614	{
1615	/** None - don't use this / uninitialized value. */
1616	VMXABORT_NONE = 0,
1617	/** VMX abort caused during saving of guest MSRs. */
1618	VMXABORT_SAVE_GUEST_MSRS = 1,
1619	/** VMX abort caused during host PDPTE checks. */
1620	VMXBOART_HOST_PDPTE = 2,
1621	/** VMX abort caused due to current VMCS being corrupted. */
1622	VMXABORT_CURRENT_VMCS_CORRUPT = 3,
1623	/** VMX abort caused during loading of host MSRs. */
1624	VMXABORT_LOAD_HOST_MSR = 4,
1625	/** VMX abort caused due to a machine-check exception during VM-exit. */
1626	VMXABORT_MACHINE_CHECK_XCPT = 5,
1627	/** VMX abort caused due to invalid return from long mode. */
1628	VMXABORT_HOST_NOT_IN_LONG_MODE = 6,
1629	/* Type size hack. */
1630	VMXABORT_32BIT_HACK = 0x7fffffff
1631	} VMXABORT;
1632	AssertCompileSize(VMXABORT, 4);
1633	/** @} */
1634
1635
1636	/** @name VMX MSR - Basic VMX information.
1637	* @{
1638	*/
1639	/** VMCS (and related regions) memory type - Uncacheable. */
1640	#define VMX_BASIC_MEM_TYPE_UC 0
1641	/** VMCS (and related regions) memory type - Write back. */
1642	#define VMX_BASIC_MEM_TYPE_WB 6
1643	/** Width of physical addresses used for VMCS and associated memory regions
1644	* (1=32-bit, 0=processor's physical address width). */
1645	#define VMX_BASIC_PHYSADDR_WIDTH_32BIT RT_BIT_64(48)
1646
1647	/** Bit fields for MSR_IA32_VMX_BASIC. */
1648	/** VMCS revision identifier used by the processor. */
1649	#define VMX_BF_BASIC_VMCS_ID_SHIFT 0
1650	#define VMX_BF_BASIC_VMCS_ID_MASK UINT64_C(0x000000007fffffff)
1651	/** Bit 31 is reserved and RAZ. */
1652	#define VMX_BF_BASIC_RSVD_32_SHIFT 31
1653	#define VMX_BF_BASIC_RSVD_32_MASK UINT64_C(0x0000000080000000)
1654	/** VMCS size in bytes. */
1655	#define VMX_BF_BASIC_VMCS_SIZE_SHIFT 32
1656	#define VMX_BF_BASIC_VMCS_SIZE_MASK UINT64_C(0x00001fff00000000)
1657	/** Bits 45:47 are reserved. */
1658	#define VMX_BF_BASIC_RSVD_45_47_SHIFT 45
1659	#define VMX_BF_BASIC_RSVD_45_47_MASK UINT64_C(0x0000e00000000000)
1660	/** Width of physical addresses used for the VMCS and associated memory regions
1661	* (always 0 on CPUs that support Intel 64 architecture). */
1662	#define VMX_BF_BASIC_PHYSADDR_WIDTH_SHIFT 48
1663	#define VMX_BF_BASIC_PHYSADDR_WIDTH_MASK UINT64_C(0x0001000000000000)
1664	/** Dual-monitor treatment of SMI and SMM supported. */
1665	#define VMX_BF_BASIC_DUAL_MON_SHIFT 49
1666	#define VMX_BF_BASIC_DUAL_MON_MASK UINT64_C(0x0002000000000000)
1667	/** Memory type that must be used for the VMCS and associated memory regions. */
1668	#define VMX_BF_BASIC_VMCS_MEM_TYPE_SHIFT 50
1669	#define VMX_BF_BASIC_VMCS_MEM_TYPE_MASK UINT64_C(0x003c000000000000)
1670	/** VM-exit instruction information for INS/OUTS. */
1671	#define VMX_BF_BASIC_VMCS_INS_OUTS_SHIFT 54
1672	#define VMX_BF_BASIC_VMCS_INS_OUTS_MASK UINT64_C(0x0040000000000000)
1673	/** Whether 'true' VMX controls MSRs are supported for handling of default1 class
1674	* bits in VMX control MSRs. */
1675	#define VMX_BF_BASIC_TRUE_CTLS_SHIFT 55
1676	#define VMX_BF_BASIC_TRUE_CTLS_MASK UINT64_C(0x0080000000000000)
1677	/** Whether VM-entry can delivery error code for all hardware exception vectors. */
1678	#define VMX_BF_BASIC_XCPT_ERRCODE_SHIFT 56
1679	#define VMX_BF_BASIC_XCPT_ERRCODE_MASK UINT64_C(0x0100000000000000)
1680	/** Bits 57:63 are reserved and RAZ. */
1681	#define VMX_BF_BASIC_RSVD_56_63_SHIFT 57
1682	#define VMX_BF_BASIC_RSVD_56_63_MASK UINT64_C(0xfe00000000000000)
1683	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_BASIC_, UINT64_C(0), UINT64_MAX,
1684	(VMCS_ID, RSVD_32, VMCS_SIZE, RSVD_45_47, PHYSADDR_WIDTH, DUAL_MON, VMCS_MEM_TYPE,
1685	VMCS_INS_OUTS, TRUE_CTLS, XCPT_ERRCODE, RSVD_56_63));
1686	/** @} */
1687
1688
1689	/** @name VMX MSR - Miscellaneous data.
1690	* @{
1691	*/
1692	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1693	#define VMX_MISC_EXIT_SAVE_EFER_LMA RT_BIT(5)
1694	/** Whether Intel PT is supported in VMX operation. */
1695	#define VMX_MISC_INTEL_PT RT_BIT(14)
1696	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1697	* VMWRITE cannot modify read-only VM-exit information fields. */
1698	#define VMX_MISC_VMWRITE_ALL RT_BIT(29)
1699	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1700	* instructions. */
1701	#define VMX_MISC_ENTRY_INJECT_SOFT_INT RT_BIT(30)
1702	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
1703	#define VMX_MISC_MAX_MSRS(a_MiscMsr) (512 * (RT_BF_GET((a_MiscMsr), VMX_BF_MISC_MAX_MSRS) + 1))
1704	/** Maximum CR3-target count supported by the CPU. */
1705	#define VMX_MISC_CR3_TARGET_COUNT(a_MiscMsr) (((a) >> 16) & 0xff)
1706
1707	/** Bit fields for MSR_IA32_VMX_MISC. */
1708	/** Relationship between the preemption timer and tsc. */
1709	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_SHIFT 0
1710	#define VMX_BF_MISC_PREEMPT_TIMER_TSC_MASK UINT64_C(0x000000000000001f)
1711	/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
1712	#define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_SHIFT 5
1713	#define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_MASK UINT64_C(0x0000000000000020)
1714	/** Activity states supported by the implementation. */
1715	#define VMX_BF_MISC_ACTIVITY_STATES_SHIFT 6
1716	#define VMX_BF_MISC_ACTIVITY_STATES_MASK UINT64_C(0x00000000000001c0)
1717	/** Bits 9:13 is reserved and RAZ. */
1718	#define VMX_BF_MISC_RSVD_9_13_SHIFT 9
1719	#define VMX_BF_MISC_RSVD_9_13_MASK UINT64_C(0x0000000000003e00)
1720	/** Whether Intel PT (Processor Trace) can be used in VMX operation. */
1721	#define VMX_BF_MISC_INTEL_PT_SHIFT 14
1722	#define VMX_BF_MISC_INTEL_PT_MASK UINT64_C(0x0000000000004000)
1723	/** Whether RDMSR can be used to read IA32_SMBASE MSR in SMM. */
1724	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_SHIFT 15
1725	#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_MASK UINT64_C(0x0000000000008000)
1726	/** Number of CR3 target values supported by the processor. (0-256) */
1727	#define VMX_BF_MISC_CR3_TARGET_SHIFT 16
1728	#define VMX_BF_MISC_CR3_TARGET_MASK UINT64_C(0x0000000001ff0000)
1729	/** Maximum number of MSRs in the VMCS. */
1730	#define VMX_BF_MISC_MAX_MSRS_SHIFT 25
1731	#define VMX_BF_MISC_MAX_MSRS_MASK UINT64_C(0x000000000e000000)
1732	/** Whether IA32_SMM_MONITOR_CTL MSR can be modified to allow VMXOFF to block
1733	* SMIs. */
1734	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_SHIFT 28
1735	#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_MASK UINT64_C(0x0000000010000000)
1736	/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
1737	* VMWRITE cannot modify read-only VM-exit information fields. */
1738	#define VMX_BF_MISC_VMWRITE_ALL_SHIFT 29
1739	#define VMX_BF_MISC_VMWRITE_ALL_MASK UINT64_C(0x0000000020000000)
1740	/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
1741	* instructions. */
1742	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_SHIFT 30
1743	#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_MASK UINT64_C(0x0000000040000000)
1744	/** Bit 31 is reserved and RAZ. */
1745	#define VMX_BF_MISC_RSVD_31_SHIFT 31
1746	#define VMX_BF_MISC_RSVD_31_MASK UINT64_C(0x0000000080000000)
1747	/** 32-bit MSEG revision ID used by the processor. */
1748	#define VMX_BF_MISC_MSEG_ID_SHIFT 32
1749	#define VMX_BF_MISC_MSEG_ID_MASK UINT64_C(0xffffffff00000000)
1750	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_MISC_, UINT64_C(0), UINT64_MAX,
1751	(PREEMPT_TIMER_TSC, EXIT_SAVE_EFER_LMA, ACTIVITY_STATES, RSVD_9_13, INTEL_PT, SMM_READ_SMBASE_MSR,
1752	CR3_TARGET, MAX_MSRS, VMXOFF_BLOCK_SMI, VMWRITE_ALL, ENTRY_INJECT_SOFT_INT, RSVD_31, MSEG_ID));
1753	/** @} */
1754
1755	/** @name VMX MSR - VMCS enumeration.
1756	* Bit fields for MSR_IA32_VMX_VMCS_ENUM.
1757	* @{
1758	*/
1759	/** Bit 0 is reserved and RAZ. */
1760	#define VMX_BF_VMCS_ENUM_RSVD_0_SHIFT 0
1761	#define VMX_BF_VMCS_ENUM_RSVD_0_MASK UINT64_C(0x0000000000000001)
1762	/** Highest index value used in VMCS field encoding. */
1763	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT 1
1764	#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_MASK UINT64_C(0x00000000000003fe)
1765	/** Bit 10:63 is reserved and RAZ. */
1766	#define VMX_BF_VMCS_ENUM_RSVD_10_63_SHIFT 10
1767	#define VMX_BF_VMCS_ENUM_RSVD_10_63_MASK UINT64_C(0xfffffffffffffc00)
1768	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_ENUM_, UINT64_C(0), UINT64_MAX,
1769	(RSVD_0, HIGHEST_IDX, RSVD_10_63));
1770	/** @} */
1771
1772
1773	/** @name VMX MSR - VM Functions.
1774	* Bit fields for MSR_IA32_VMX_VMFUNC.
1775	* @{
1776	*/
1777	/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
1778	#define VMX_BF_VMFUNC_EPTP_SWITCHING_SHIFT 0
1779	#define VMX_BF_VMFUNC_EPTP_SWITCHING_MASK UINT64_C(0x0000000000000001)
1780	/** Bits 1:63 are reserved and RAZ. */
1781	#define VMX_BF_VMFUNC_RSVD_1_63_SHIFT 1
1782	#define VMX_BF_VMFUNC_RSVD_1_63_MASK UINT64_C(0xfffffffffffffffe)
1783	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMFUNC_, UINT64_C(0), UINT64_MAX,
1784	(EPTP_SWITCHING, RSVD_1_63));
1785	/** @} */
1786
1787
1788	/** @name VMX MSR - EPT/VPID capabilities.
1789	* @{
1790	*/
1791	/** Supports execute-only translations by EPT. */
1792	#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
1793	/** Supports page-walk length of 4. */
1794	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4 RT_BIT_64(6)
1795	/** Supports page-walk length of 5. */
1796	#define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5 RT_BIT_64(7)
1797	/** Supports EPT paging-structure memory type to be uncacheable. */
1798	#define MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_UC RT_BIT_64(8)
1799	/** Supports EPT paging structure memory type to be write-back. */
1800	#define MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_WB RT_BIT_64(14)
1801	/** Supports EPT PDE to map a 2 MB page. */
1802	#define MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M RT_BIT_64(16)
1803	/** Supports EPT PDPTE to map a 1 GB page. */
1804	#define MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G RT_BIT_64(17)
1805	/** Supports INVEPT instruction. */
1806	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20)
1807	/** Supports accessed and dirty flags for EPT. */
1808	#define MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY RT_BIT_64(21)
1809	/** Supports advanced VM-exit info. for EPT violations. */
1810	#define MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION RT_BIT_64(22)
1811	/** Supports supervisor shadow-stack control. */
1812	#define MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK RT_BIT_64(23)
1813	/** Supports single-context INVEPT type. */
1814	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25)
1815	/** Supports all-context INVEPT type. */
1816	#define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26)
1817	/** Supports INVVPID instruction. */
1818	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32)
1819	/** Supports individual-address INVVPID type. */
1820	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40)
1821	/** Supports single-context INVVPID type. */
1822	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41)
1823	/** Supports all-context INVVPID type. */
1824	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42)
1825	/** Supports singe-context-retaining-globals INVVPID type. */
1826	#define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43)
1827
1828	/** Bit fields for MSR_IA32_VMX_EPT_VPID_CAP. */
1829	#define VMX_BF_EPT_VPID_CAP_EXEC_ONLY_SHIFT 0
1830	#define VMX_BF_EPT_VPID_CAP_EXEC_ONLY_MASK UINT64_C(0x0000000000000001)
1831	#define VMX_BF_EPT_VPID_CAP_RSVD_1_5_SHIFT 1
1832	#define VMX_BF_EPT_VPID_CAP_RSVD_1_5_MASK UINT64_C(0x000000000000003e)
1833	#define VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4_SHIFT 6
1834	#define VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4_MASK UINT64_C(0x0000000000000040)
1835	#define VMX_BF_EPT_VPID_CAP_RSVD_7_SHIFT 7
1836	#define VMX_BF_EPT_VPID_CAP_RSVD_7_MASK UINT64_C(0x0000000000000080)
1837	#define VMX_BF_EPT_VPID_CAP_MEMTYPE_UC_SHIFT 8
1838	#define VMX_BF_EPT_VPID_CAP_MEMTYPE_UC_MASK UINT64_C(0x0000000000000100)
1839	#define VMX_BF_EPT_VPID_CAP_RSVD_9_13_SHIFT 9
1840	#define VMX_BF_EPT_VPID_CAP_RSVD_9_13_MASK UINT64_C(0x0000000000003e00)
1841	#define VMX_BF_EPT_VPID_CAP_MEMTYPE_WB_SHIFT 14
1842	#define VMX_BF_EPT_VPID_CAP_MEMTYPE_WB_MASK UINT64_C(0x0000000000004000)
1843	#define VMX_BF_EPT_VPID_CAP_RSVD_15_SHIFT 15
1844	#define VMX_BF_EPT_VPID_CAP_RSVD_15_MASK UINT64_C(0x0000000000008000)
1845	#define VMX_BF_EPT_VPID_CAP_PDE_2M_SHIFT 16
1846	#define VMX_BF_EPT_VPID_CAP_PDE_2M_MASK UINT64_C(0x0000000000010000)
1847	#define VMX_BF_EPT_VPID_CAP_PDPTE_1G_SHIFT 17
1848	#define VMX_BF_EPT_VPID_CAP_PDPTE_1G_MASK UINT64_C(0x0000000000020000)
1849	#define VMX_BF_EPT_VPID_CAP_RSVD_18_19_SHIFT 18
1850	#define VMX_BF_EPT_VPID_CAP_RSVD_18_19_MASK UINT64_C(0x00000000000c0000)
1851	#define VMX_BF_EPT_VPID_CAP_INVEPT_SHIFT 20
1852	#define VMX_BF_EPT_VPID_CAP_INVEPT_MASK UINT64_C(0x0000000000100000)
1853	#define VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY_SHIFT 21
1854	#define VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY_MASK UINT64_C(0x0000000000200000)
1855	#define VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION_SHIFT 22
1856	#define VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION_MASK UINT64_C(0x0000000000400000)
1857	#define VMX_BF_EPT_VPID_CAP_SUPER_SHW_STACK_SHIFT 23
1858	#define VMX_BF_EPT_VPID_CAP_SUPER_SHW_STACK_MASK UINT64_C(0x0000000000800000)
1859	#define VMX_BF_EPT_VPID_CAP_RSVD_24_SHIFT 24
1860	#define VMX_BF_EPT_VPID_CAP_RSVD_24_MASK UINT64_C(0x0000000001000000)
1861	#define VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX_SHIFT 25
1862	#define VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX_MASK UINT64_C(0x0000000002000000)
1863	#define VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX_SHIFT 26
1864	#define VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX_MASK UINT64_C(0x0000000004000000)
1865	#define VMX_BF_EPT_VPID_CAP_RSVD_27_31_SHIFT 27
1866	#define VMX_BF_EPT_VPID_CAP_RSVD_27_31_MASK UINT64_C(0x00000000f8000000)
1867	#define VMX_BF_EPT_VPID_CAP_INVVPID_SHIFT 32
1868	#define VMX_BF_EPT_VPID_CAP_INVVPID_MASK UINT64_C(0x0000000100000000)
1869	#define VMX_BF_EPT_VPID_CAP_RSVD_33_39_SHIFT 33
1870	#define VMX_BF_EPT_VPID_CAP_RSVD_33_39_MASK UINT64_C(0x000000fe00000000)
1871	#define VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR_SHIFT 40
1872	#define VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR_MASK UINT64_C(0x0000010000000000)
1873	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_SHIFT 41
1874	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_MASK UINT64_C(0x0000020000000000)
1875	#define VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX_SHIFT 42
1876	#define VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX_MASK UINT64_C(0x0000040000000000)
1877	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS_SHIFT 43
1878	#define VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS_MASK UINT64_C(0x0000080000000000)
1879	#define VMX_BF_EPT_VPID_CAP_RSVD_44_63_SHIFT 44
1880	#define VMX_BF_EPT_VPID_CAP_RSVD_44_63_MASK UINT64_C(0xfffff00000000000)
1881	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EPT_VPID_CAP_, UINT64_C(0), UINT64_MAX,
1882	(EXEC_ONLY, RSVD_1_5, PAGE_WALK_LENGTH_4, RSVD_7, MEMTYPE_UC, RSVD_9_13, MEMTYPE_WB, RSVD_15, PDE_2M,
1883	PDPTE_1G, RSVD_18_19, INVEPT, ACCESS_DIRTY, ADVEXITINFO_EPT_VIOLATION, SUPER_SHW_STACK, RSVD_24,
1884	INVEPT_SINGLE_CTX, INVEPT_ALL_CTX, RSVD_27_31, INVVPID, RSVD_33_39, INVVPID_INDIV_ADDR,
1885	INVVPID_SINGLE_CTX, INVVPID_ALL_CTX, INVVPID_SINGLE_CTX_RETAIN_GLOBALS, RSVD_44_63));
1886	/** @} */
1887
1888
1889	/** @name Extended Page Table Pointer (EPTP)
1890	* In accordance with the VT-x spec.
1891	* See Intel spec. 23.6.11 "Extended-Page-Table Pointer (EPTP)".
1892	* @{
1893	*/
1894	/** EPTP memory type: Uncachable. */
1895	#define VMX_EPTP_MEMTYPE_UC 0
1896	/** EPTP memory type: Write Back. */
1897	#define VMX_EPTP_MEMTYPE_WB 6
1898	/** Page-walk length for PML4 (4-level paging). */
1899	#define VMX_EPTP_PAGE_WALK_LENGTH_4 3
1900
1901	/** Bit fields for EPTP. */
1902	#define VMX_BF_EPTP_MEMTYPE_SHIFT 0
1903	#define VMX_BF_EPTP_MEMTYPE_MASK UINT64_C(0x0000000000000007)
1904	#define VMX_BF_EPTP_PAGE_WALK_LENGTH_SHIFT 3
1905	#define VMX_BF_EPTP_PAGE_WALK_LENGTH_MASK UINT64_C(0x0000000000000038)
1906	#define VMX_BF_EPTP_ACCESS_DIRTY_SHIFT 6
1907	#define VMX_BF_EPTP_ACCESS_DIRTY_MASK UINT64_C(0x0000000000000040)
1908	#define VMX_BF_EPTP_SUPER_SHW_STACK_SHIFT 7
1909	#define VMX_BF_EPTP_SUPER_SHW_STACK_MASK UINT64_C(0x0000000000000080)
1910	#define VMX_BF_EPTP_RSVD_8_11_SHIFT 8
1911	#define VMX_BF_EPTP_RSVD_8_11_MASK UINT64_C(0x0000000000000f00)
1912	#define VMX_BF_EPTP_PML4_TABLE_ADDR_SHIFT 12
1913	#define VMX_BF_EPTP_PML4_TABLE_ADDR_MASK UINT64_C(0xfffffffffffff000)
1914	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EPTP_, UINT64_C(0), UINT64_MAX,
1915	(MEMTYPE, PAGE_WALK_LENGTH, ACCESS_DIRTY, SUPER_SHW_STACK, RSVD_8_11, PML4_TABLE_ADDR));
1916
1917	/* Mask of valid EPTP bits sans physically non-addressable bits. */
1918	#define VMX_EPTP_VALID_MASK ( VMX_BF_EPTP_MEMTYPE_MASK \
1919	\| VMX_BF_EPTP_PAGE_WALK_LENGTH_MASK \
1920	\| VMX_BF_EPTP_ACCESS_DIRTY_MASK \
1921	\| VMX_BF_EPTP_SUPER_SHW_STACK_MASK \
1922	\| VMX_BF_EPTP_PML4_TABLE_ADDR_MASK)
1923	/** @} */
1924
1925
1926	/** @name VMCS fields and encoding.
1927	*
1928	* When adding a new field:
1929	* - Always add it to g_aVmcsFields.
1930	* - Consider if it needs to be added to VMXVVMCS.
1931	* @{
1932	*/
1933	/** 16-bit control fields. */
1934	#define VMX_VMCS16_VPID 0x0000
1935	#define VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR 0x0002
1936	#define VMX_VMCS16_EPTP_INDEX 0x0004
1937
1938	/** 16-bit guest-state fields. */
1939	#define VMX_VMCS16_GUEST_ES_SEL 0x0800
1940	#define VMX_VMCS16_GUEST_CS_SEL 0x0802
1941	#define VMX_VMCS16_GUEST_SS_SEL 0x0804
1942	#define VMX_VMCS16_GUEST_DS_SEL 0x0806
1943	#define VMX_VMCS16_GUEST_FS_SEL 0x0808
1944	#define VMX_VMCS16_GUEST_GS_SEL 0x080a
1945	#define VMX_VMCS16_GUEST_LDTR_SEL 0x080c
1946	#define VMX_VMCS16_GUEST_TR_SEL 0x080e
1947	#define VMX_VMCS16_GUEST_INTR_STATUS 0x0810
1948	#define VMX_VMCS16_GUEST_PML_INDEX 0x0812
1949
1950	/** 16-bits host-state fields. */
1951	#define VMX_VMCS16_HOST_ES_SEL 0x0c00
1952	#define VMX_VMCS16_HOST_CS_SEL 0x0c02
1953	#define VMX_VMCS16_HOST_SS_SEL 0x0c04
1954	#define VMX_VMCS16_HOST_DS_SEL 0x0c06
1955	#define VMX_VMCS16_HOST_FS_SEL 0x0c08
1956	#define VMX_VMCS16_HOST_GS_SEL 0x0c0a
1957	#define VMX_VMCS16_HOST_TR_SEL 0x0c0c
1958
1959	/** 64-bit control fields. */
1960	#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
1961	#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
1962	#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
1963	#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
1964	#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
1965	#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
1966	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
1967	#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
1968	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
1969	#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
1970	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200a
1971	#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200b
1972	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200c
1973	#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200d
1974	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL 0x200e
1975	#define VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH 0x200f
1976	#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
1977	#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
1978	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL 0x2012
1979	#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH 0x2013
1980	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
1981	#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
1982	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL 0x2016
1983	#define VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH 0x2017
1984	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
1985	#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
1986	#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
1987	#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
1988	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL 0x201c
1989	#define VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH 0x201d
1990	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL 0x201e
1991	#define VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH 0x201f
1992	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL 0x2020
1993	#define VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH 0x2021
1994	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL 0x2022
1995	#define VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH 0x2023
1996	#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
1997	#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
1998	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL 0x2026
1999	#define VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH 0x2027
2000	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL 0x2028
2001	#define VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH 0x2029
2002	#define VMX_VMCS64_CTRL_VE_XCPT_INFO_ADDR_FULL 0x202a
2003	#define VMX_VMCS64_CTRL_VE_XCPT_INFO_ADDR_HIGH 0x202b
2004	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL 0x202c
2005	#define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH 0x202d
2006	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL 0x202e
2007	#define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH 0x202f
2008	#define VMX_VMCS64_CTRL_SPPTP_FULL 0x2030
2009	#define VMX_VMCS64_CTRL_SPPTP_HIGH 0x2031
2010	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL 0x2032
2011	#define VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH 0x2033
2012	#define VMX_VMCS64_CTRL_PROC_EXEC3_FULL 0x2034
2013	#define VMX_VMCS64_CTRL_PROC_EXEC3_HIGH 0x2035
2014	#define VMX_VMCS64_CTRL_ENCLV_EXITING_BITMAP_FULL 0x2036
2015	#define VMX_VMCS64_CTRL_ENCLV_EXITING_BITMAP_HIGH 0x2037
2016
2017	/** 64-bit read-only data fields. */
2018	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL 0x2400
2019	#define VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH 0x2401
2020
2021	/** 64-bit guest-state fields. */
2022	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
2023	#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
2024	#define VMX_VMCS64_GUEST_DEBUGCTL_FULL 0x2802
2025	#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH 0x2803
2026	#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
2027	#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
2028	#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
2029	#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
2030	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL 0x2808
2031	#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH 0x2809
2032	#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280a
2033	#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280b
2034	#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280c
2035	#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280d
2036	#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280e
2037	#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280f
2038	#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
2039	#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
2040	#define VMX_VMCS64_GUEST_BNDCFGS_FULL 0x2812
2041	#define VMX_VMCS64_GUEST_BNDCFGS_HIGH 0x2813
2042	#define VMX_VMCS64_GUEST_RTIT_CTL_FULL 0x2814
2043	#define VMX_VMCS64_GUEST_RTIT_CTL_HIGH 0x2815
2044	#define VMX_VMCS64_GUEST_PKRS_FULL 0x2818
2045	#define VMX_VMCS64_GUEST_PKRS_HIGH 0x2819
2046
2047	/** 64-bit host-state fields. */
2048	#define VMX_VMCS64_HOST_PAT_FULL 0x2c00
2049	#define VMX_VMCS64_HOST_PAT_HIGH 0x2c01
2050	#define VMX_VMCS64_HOST_EFER_FULL 0x2c02
2051	#define VMX_VMCS64_HOST_EFER_HIGH 0x2c03
2052	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2c04
2053	#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2c05
2054	#define VMX_VMCS64_HOST_PKRS_FULL 0x2c06
2055	#define VMX_VMCS64_HOST_PKRS_HIGH 0x2c07
2056
2057	/** 32-bit control fields. */
2058	#define VMX_VMCS32_CTRL_PIN_EXEC 0x4000
2059	#define VMX_VMCS32_CTRL_PROC_EXEC 0x4002
2060	#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
2061	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
2062	#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
2063	#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400a
2064	#define VMX_VMCS32_CTRL_EXIT 0x400c
2065	#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400e
2066	#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
2067	#define VMX_VMCS32_CTRL_ENTRY 0x4012
2068	#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
2069	#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
2070	#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
2071	#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401a
2072	#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401c
2073	#define VMX_VMCS32_CTRL_PROC_EXEC2 0x401e
2074	#define VMX_VMCS32_CTRL_PLE_GAP 0x4020
2075	#define VMX_VMCS32_CTRL_PLE_WINDOW 0x4022
2076
2077	/** 32-bits read-only fields. */
2078	#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
2079	#define VMX_VMCS32_RO_EXIT_REASON 0x4402
2080	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
2081	#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
2082	#define VMX_VMCS32_RO_IDT_VECTORING_INFO 0x4408
2083	#define VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE 0x440a
2084	#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440c
2085	#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440e
2086
2087	/** 32-bit guest-state fields. */
2088	#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
2089	#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
2090	#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
2091	#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
2092	#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
2093	#define VMX_VMCS32_GUEST_GS_LIMIT 0x480a
2094	#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480c
2095	#define VMX_VMCS32_GUEST_TR_LIMIT 0x480e
2096	#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
2097	#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
2098	#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
2099	#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
2100	#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
2101	#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481a
2102	#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481c
2103	#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481e
2104	#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
2105	#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
2106	#define VMX_VMCS32_GUEST_INT_STATE 0x4824
2107	#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
2108	#define VMX_VMCS32_GUEST_SMBASE 0x4828
2109	#define VMX_VMCS32_GUEST_SYSENTER_CS 0x482a
2110	#define VMX_VMCS32_PREEMPT_TIMER_VALUE 0x482e
2111
2112	/** 32-bit host-state fields. */
2113	#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
2114
2115	/** Natural-width control fields. */
2116	#define VMX_VMCS_CTRL_CR0_MASK 0x6000
2117	#define VMX_VMCS_CTRL_CR4_MASK 0x6002
2118	#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
2119	#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
2120	#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
2121	#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600a
2122	#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600c
2123	#define VMX_VMCS_CTRL_CR3_TARGET_VAL3 0x600e
2124
2125	/** Natural-width read-only data fields. */
2126	#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
2127	#define VMX_VMCS_RO_IO_RCX 0x6402
2128	#define VMX_VMCS_RO_IO_RSI 0x6404
2129	#define VMX_VMCS_RO_IO_RDI 0x6406
2130	#define VMX_VMCS_RO_IO_RIP 0x6408
2131	#define VMX_VMCS_RO_GUEST_LINEAR_ADDR 0x640a
2132
2133	/** Natural-width guest-state fields. */
2134	#define VMX_VMCS_GUEST_CR0 0x6800
2135	#define VMX_VMCS_GUEST_CR3 0x6802
2136	#define VMX_VMCS_GUEST_CR4 0x6804
2137	#define VMX_VMCS_GUEST_ES_BASE 0x6806
2138	#define VMX_VMCS_GUEST_CS_BASE 0x6808
2139	#define VMX_VMCS_GUEST_SS_BASE 0x680a
2140	#define VMX_VMCS_GUEST_DS_BASE 0x680c
2141	#define VMX_VMCS_GUEST_FS_BASE 0x680e
2142	#define VMX_VMCS_GUEST_GS_BASE 0x6810
2143	#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
2144	#define VMX_VMCS_GUEST_TR_BASE 0x6814
2145	#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
2146	#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
2147	#define VMX_VMCS_GUEST_DR7 0x681a
2148	#define VMX_VMCS_GUEST_RSP 0x681c
2149	#define VMX_VMCS_GUEST_RIP 0x681e
2150	#define VMX_VMCS_GUEST_RFLAGS 0x6820
2151	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS 0x6822
2152	#define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824
2153	#define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826
2154	#define VMX_VMCS_GUEST_S_CET 0x6828
2155	#define VMX_VMCS_GUEST_SSP 0x682a
2156	#define VMX_VMCS_GUEST_INTR_SSP_TABLE_ADDR 0x682c
2157
2158	/** Natural-width host-state fields. */
2159	#define VMX_VMCS_HOST_CR0 0x6c00
2160	#define VMX_VMCS_HOST_CR3 0x6c02
2161	#define VMX_VMCS_HOST_CR4 0x6c04
2162	#define VMX_VMCS_HOST_FS_BASE 0x6c06
2163	#define VMX_VMCS_HOST_GS_BASE 0x6c08
2164	#define VMX_VMCS_HOST_TR_BASE 0x6c0a
2165	#define VMX_VMCS_HOST_GDTR_BASE 0x6c0c
2166	#define VMX_VMCS_HOST_IDTR_BASE 0x6c0e
2167	#define VMX_VMCS_HOST_SYSENTER_ESP 0x6c10
2168	#define VMX_VMCS_HOST_SYSENTER_EIP 0x6c12
2169	#define VMX_VMCS_HOST_RSP 0x6c14
2170	#define VMX_VMCS_HOST_RIP 0x6c16
2171	#define VMX_VMCS_HOST_S_CET 0x6c18
2172	#define VMX_VMCS_HOST_SSP 0x6c1a
2173	#define VMX_VMCS_HOST_INTR_SSP_TABLE_ADDR 0x6c1c
2174
2175	#define VMX_VMCS16_GUEST_SEG_SEL(a_iSegReg) (VMX_VMCS16_GUEST_ES_SEL + (a_iSegReg) * 2)
2176	#define VMX_VMCS_GUEST_SEG_BASE(a_iSegReg) (VMX_VMCS_GUEST_ES_BASE + (a_iSegReg) * 2)
2177	#define VMX_VMCS32_GUEST_SEG_LIMIT(a_iSegReg) (VMX_VMCS32_GUEST_ES_LIMIT + (a_iSegReg) * 2)
2178	#define VMX_VMCS32_GUEST_SEG_ACCESS_RIGHTS(a_iSegReg) (VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS + (a_iSegReg) * 2)
2179
2180	/**
2181	* VMCS field.
2182	* In accordance with the VT-x spec.
2183	*/
2184	typedef union
2185	{
2186	struct
2187	{
2188	/** The access type; 0=full, 1=high of 64-bit fields. */
2189	uint32_t fAccessType : 1;
2190	/** The index. */
2191	uint32_t u8Index : 8;
2192	/** The type; 0=control, 1=VM-exit info, 2=guest-state, 3=host-state. */
2193	uint32_t u2Type : 2;
2194	/** Reserved (MBZ). */
2195	uint32_t u1Reserved0 : 1;
2196	/** The width; 0=16-bit, 1=64-bit, 2=32-bit, 3=natural-width. */
2197	uint32_t u2Width : 2;
2198	/** Reserved (MBZ). */
2199	uint32_t u18Reserved0 : 18;
2200	} n;
2201
2202	/* The unsigned integer view. */
2203	uint32_t u;
2204	} VMXVMCSFIELD;
2205	AssertCompileSize(VMXVMCSFIELD, 4);
2206	/** Pointer to a VMCS field. */
2207	typedef VMXVMCSFIELD *PVMXVMCSFIELD;
2208	/** Pointer to a const VMCS field. */
2209	typedef const VMXVMCSFIELD *PCVMXVMCSFIELD;
2210
2211	/** VMCS field: Mask of reserved bits (bits 63:15 MBZ), bit 12 is not included! */
2212	#define VMX_VMCSFIELD_RSVD_MASK UINT64_C(0xffffffffffff8000)
2213
2214	/** Bits fields for a VMCS field. */
2215	#define VMX_BF_VMCSFIELD_ACCESS_TYPE_SHIFT 0
2216	#define VMX_BF_VMCSFIELD_ACCESS_TYPE_MASK UINT32_C(0x00000001)
2217	#define VMX_BF_VMCSFIELD_INDEX_SHIFT 1
2218	#define VMX_BF_VMCSFIELD_INDEX_MASK UINT32_C(0x000003fe)
2219	#define VMX_BF_VMCSFIELD_TYPE_SHIFT 10
2220	#define VMX_BF_VMCSFIELD_TYPE_MASK UINT32_C(0x00000c00)
2221	#define VMX_BF_VMCSFIELD_RSVD_12_SHIFT 12
2222	#define VMX_BF_VMCSFIELD_RSVD_12_MASK UINT32_C(0x00001000)
2223	#define VMX_BF_VMCSFIELD_WIDTH_SHIFT 13
2224	#define VMX_BF_VMCSFIELD_WIDTH_MASK UINT32_C(0x00006000)
2225	#define VMX_BF_VMCSFIELD_RSVD_15_31_SHIFT 15
2226	#define VMX_BF_VMCSFIELD_RSVD_15_31_MASK UINT32_C(0xffff8000)
2227	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCSFIELD_, UINT32_C(0), UINT32_MAX,
2228	(ACCESS_TYPE, INDEX, TYPE, RSVD_12, WIDTH, RSVD_15_31));
2229
2230	/**
2231	* VMCS field encoding: Access type.
2232	* In accordance with the VT-x spec.
2233	*/
2234	typedef enum
2235	{
2236	VMXVMCSFIELDACCESS_FULL = 0,
2237	VMXVMCSFIELDACCESS_HIGH
2238	} VMXVMCSFIELDACCESS;
2239	AssertCompileSize(VMXVMCSFIELDACCESS, 4);
2240	/** VMCS field encoding type: Full. */
2241	#define VMX_VMCSFIELD_ACCESS_FULL 0
2242	/** VMCS field encoding type: High. */
2243	#define VMX_VMCSFIELD_ACCESS_HIGH 1
2244
2245	/**
2246	* VMCS field encoding: Type.
2247	* In accordance with the VT-x spec.
2248	*/
2249	typedef enum
2250	{
2251	VMXVMCSFIELDTYPE_CONTROL = 0,
2252	VMXVMCSFIELDTYPE_VMEXIT_INFO,
2253	VMXVMCSFIELDTYPE_GUEST_STATE,
2254	VMXVMCSFIELDTYPE_HOST_STATE
2255	} VMXVMCSFIELDTYPE;
2256	AssertCompileSize(VMXVMCSFIELDTYPE, 4);
2257	/** VMCS field encoding type: Control. */
2258	#define VMX_VMCSFIELD_TYPE_CONTROL 0
2259	/** VMCS field encoding type: VM-exit information / read-only fields. */
2260	#define VMX_VMCSFIELD_TYPE_VMEXIT_INFO 1
2261	/** VMCS field encoding type: Guest-state. */
2262	#define VMX_VMCSFIELD_TYPE_GUEST_STATE 2
2263	/** VMCS field encoding type: Host-state. */
2264	#define VMX_VMCSFIELD_TYPE_HOST_STATE 3
2265
2266	/**
2267	* VMCS field encoding: Width.
2268	* In accordance with the VT-x spec.
2269	*/
2270	typedef enum
2271	{
2272	VMXVMCSFIELDWIDTH_16BIT = 0,
2273	VMXVMCSFIELDWIDTH_64BIT,
2274	VMXVMCSFIELDWIDTH_32BIT,
2275	VMXVMCSFIELDWIDTH_NATURAL
2276	} VMXVMCSFIELDWIDTH;
2277	AssertCompileSize(VMXVMCSFIELDWIDTH, 4);
2278	/** VMCS field encoding width: 16-bit. */
2279	#define VMX_VMCSFIELD_WIDTH_16BIT 0
2280	/** VMCS field encoding width: 64-bit. */
2281	#define VMX_VMCSFIELD_WIDTH_64BIT 1
2282	/** VMCS field encoding width: 32-bit. */
2283	#define VMX_VMCSFIELD_WIDTH_32BIT 2
2284	/** VMCS field encoding width: Natural width. */
2285	#define VMX_VMCSFIELD_WIDTH_NATURAL 3
2286	/** @} */
2287
2288
2289	/** @name VM-entry instruction length.
2290	* @{ */
2291	/** The maximum valid value for VM-entry instruction length while injecting a
2292	* software interrupt, software exception or privileged software exception. */
2293	#define VMX_ENTRY_INSTR_LEN_MAX 15
2294	/** @} */
2295
2296
2297	/** @name VM-entry register masks.
2298	* @{ */
2299	/** CR0 bits ignored on VM-entry while loading guest CR0 (ET, CD, NW, bits 6:15,
2300	* bit 17 and bits 19:28). */
2301	#define VMX_ENTRY_GUEST_CR0_IGNORE_MASK UINT64_C(0x7ffaffd0)
2302	/** DR7 bits set here are always cleared on VM-entry while loading guest DR7 (bit
2303	* 12, bits 14:15). */
2304	#define VMX_ENTRY_GUEST_DR7_MBZ_MASK UINT64_C(0xd000)
2305	/** DR7 bits set here are always set on VM-entry while loading guest DR7 (bit
2306	* 10). */
2307	#define VMX_ENTRY_GUEST_DR7_MB1_MASK UINT64_C(0x400)
2308	/** @} */
2309
2310
2311	/** @name VM-exit register masks.
2312	* @{ */
2313	/** CR0 bits ignored on VM-exit while loading host CR0 (ET, CD, NW, bits 6:15,
2314	* bit 17, bits 19:28 and bits 32:63). */
2315	#define VMX_EXIT_HOST_CR0_IGNORE_MASK UINT64_C(0xffffffff7ffaffd0)
2316	/** @} */
2317
2318
2319	/** @name Pin-based VM-execution controls.
2320	* @{
2321	*/
2322	/** External interrupt exiting. */
2323	#define VMX_PIN_CTLS_EXT_INT_EXIT RT_BIT(0)
2324	/** NMI exiting. */
2325	#define VMX_PIN_CTLS_NMI_EXIT RT_BIT(3)
2326	/** Virtual NMIs. */
2327	#define VMX_PIN_CTLS_VIRT_NMI RT_BIT(5)
2328	/** Activate VMX preemption timer. */
2329	#define VMX_PIN_CTLS_PREEMPT_TIMER RT_BIT(6)
2330	/** Process interrupts with the posted-interrupt notification vector. */
2331	#define VMX_PIN_CTLS_POSTED_INT RT_BIT(7)
2332	/** Default1 class when true capability MSRs are not supported. */
2333	#define VMX_PIN_CTLS_DEFAULT1 UINT32_C(0x00000016)
2334
2335	/** Bit fields for MSR_IA32_VMX_PINBASED_CTLS and Pin-based VM-execution
2336	* controls field in the VMCS. */
2337	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT 0
2338	#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_MASK UINT32_C(0x00000001)
2339	#define VMX_BF_PIN_CTLS_RSVD_1_2_SHIFT 1
2340	#define VMX_BF_PIN_CTLS_RSVD_1_2_MASK UINT32_C(0x00000006)
2341	#define VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT 3
2342	#define VMX_BF_PIN_CTLS_NMI_EXIT_MASK UINT32_C(0x00000008)
2343	#define VMX_BF_PIN_CTLS_RSVD_4_SHIFT 4
2344	#define VMX_BF_PIN_CTLS_RSVD_4_MASK UINT32_C(0x00000010)
2345	#define VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT 5
2346	#define VMX_BF_PIN_CTLS_VIRT_NMI_MASK UINT32_C(0x00000020)
2347	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT 6
2348	#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_MASK UINT32_C(0x00000040)
2349	#define VMX_BF_PIN_CTLS_POSTED_INT_SHIFT 7
2350	#define VMX_BF_PIN_CTLS_POSTED_INT_MASK UINT32_C(0x00000080)
2351	#define VMX_BF_PIN_CTLS_RSVD_8_31_SHIFT 8
2352	#define VMX_BF_PIN_CTLS_RSVD_8_31_MASK UINT32_C(0xffffff00)
2353	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PIN_CTLS_, UINT32_C(0), UINT32_MAX,
2354	(EXT_INT_EXIT, RSVD_1_2, NMI_EXIT, RSVD_4, VIRT_NMI, PREEMPT_TIMER, POSTED_INT, RSVD_8_31));
2355	/** @} */
2356
2357
2358	/** @name Processor-based VM-execution controls.
2359	* @{
2360	*/
2361	/** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
2362	#define VMX_PROC_CTLS_INT_WINDOW_EXIT RT_BIT(2)
2363	/** Use timestamp counter offset. */
2364	#define VMX_PROC_CTLS_USE_TSC_OFFSETTING RT_BIT(3)
2365	/** VM-exit when executing the HLT instruction. */
2366	#define VMX_PROC_CTLS_HLT_EXIT RT_BIT(7)
2367	/** VM-exit when executing the INVLPG instruction. */
2368	#define VMX_PROC_CTLS_INVLPG_EXIT RT_BIT(9)
2369	/** VM-exit when executing the MWAIT instruction. */
2370	#define VMX_PROC_CTLS_MWAIT_EXIT RT_BIT(10)
2371	/** VM-exit when executing the RDPMC instruction. */
2372	#define VMX_PROC_CTLS_RDPMC_EXIT RT_BIT(11)
2373	/** VM-exit when executing the RDTSC/RDTSCP instruction. */
2374	#define VMX_PROC_CTLS_RDTSC_EXIT RT_BIT(12)
2375	/** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the
2376	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2377	#define VMX_PROC_CTLS_CR3_LOAD_EXIT RT_BIT(15)
2378	/** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the
2379	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2380	#define VMX_PROC_CTLS_CR3_STORE_EXIT RT_BIT(16)
2381	/** Whether the secondary processor based VM-execution controls are used. */
2382	#define VMX_PROC_CTLS_USE_TERTIARY_CTLS RT_BIT(17)
2383	/** VM-exit on CR8 loads. */
2384	#define VMX_PROC_CTLS_CR8_LOAD_EXIT RT_BIT(19)
2385	/** VM-exit on CR8 stores. */
2386	#define VMX_PROC_CTLS_CR8_STORE_EXIT RT_BIT(20)
2387	/** Use TPR shadow. */
2388	#define VMX_PROC_CTLS_USE_TPR_SHADOW RT_BIT(21)
2389	/** VM-exit when virtual NMI blocking is disabled. */
2390	#define VMX_PROC_CTLS_NMI_WINDOW_EXIT RT_BIT(22)
2391	/** VM-exit when executing a MOV DRx instruction. */
2392	#define VMX_PROC_CTLS_MOV_DR_EXIT RT_BIT(23)
2393	/** VM-exit when executing IO instructions. */
2394	#define VMX_PROC_CTLS_UNCOND_IO_EXIT RT_BIT(24)
2395	/** Use IO bitmaps. */
2396	#define VMX_PROC_CTLS_USE_IO_BITMAPS RT_BIT(25)
2397	/** Monitor trap flag. */
2398	#define VMX_PROC_CTLS_MONITOR_TRAP_FLAG RT_BIT(27)
2399	/** Use MSR bitmaps. */
2400	#define VMX_PROC_CTLS_USE_MSR_BITMAPS RT_BIT(28)
2401	/** VM-exit when executing the MONITOR instruction. */
2402	#define VMX_PROC_CTLS_MONITOR_EXIT RT_BIT(29)
2403	/** VM-exit when executing the PAUSE instruction. */
2404	#define VMX_PROC_CTLS_PAUSE_EXIT RT_BIT(30)
2405	/** Whether the secondary processor based VM-execution controls are used. */
2406	#define VMX_PROC_CTLS_USE_SECONDARY_CTLS RT_BIT(31)
2407	/** Default1 class when true-capability MSRs are not supported. */
2408	#define VMX_PROC_CTLS_DEFAULT1 UINT32_C(0x0401e172)
2409
2410	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS and Processor-based VM-execution
2411	* controls field in the VMCS. */
2412	#define VMX_BF_PROC_CTLS_RSVD_0_1_SHIFT 0
2413	#define VMX_BF_PROC_CTLS_RSVD_0_1_MASK UINT32_C(0x00000003)
2414	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT 2
2415	#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_MASK UINT32_C(0x00000004)
2416	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT 3
2417	#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_MASK UINT32_C(0x00000008)
2418	#define VMX_BF_PROC_CTLS_RSVD_4_6_SHIFT 4
2419	#define VMX_BF_PROC_CTLS_RSVD_4_6_MASK UINT32_C(0x00000070)
2420	#define VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT 7
2421	#define VMX_BF_PROC_CTLS_HLT_EXIT_MASK UINT32_C(0x00000080)
2422	#define VMX_BF_PROC_CTLS_RSVD_8_SHIFT 8
2423	#define VMX_BF_PROC_CTLS_RSVD_8_MASK UINT32_C(0x00000100)
2424	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT 9
2425	#define VMX_BF_PROC_CTLS_INVLPG_EXIT_MASK UINT32_C(0x00000200)
2426	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT 10
2427	#define VMX_BF_PROC_CTLS_MWAIT_EXIT_MASK UINT32_C(0x00000400)
2428	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT 11
2429	#define VMX_BF_PROC_CTLS_RDPMC_EXIT_MASK UINT32_C(0x00000800)
2430	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT 12
2431	#define VMX_BF_PROC_CTLS_RDTSC_EXIT_MASK UINT32_C(0x00001000)
2432	#define VMX_BF_PROC_CTLS_RSVD_13_14_SHIFT 13
2433	#define VMX_BF_PROC_CTLS_RSVD_13_14_MASK UINT32_C(0x00006000)
2434	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT 15
2435	#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK UINT32_C(0x00008000)
2436	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT 16
2437	#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK UINT32_C(0x00010000)
2438	#define VMX_BF_PROC_CTLS_USE_TERTIARY_CTLS_SHIFT 17
2439	#define VMX_BF_PROC_CTLS_USE_TERTIARY_CTLS_MASK UINT32_C(0x00020000)
2440	#define VMX_BF_PROC_CTLS_RSVD_18_SHIFT 18
2441	#define VMX_BF_PROC_CTLS_RSVD_18_MASK UINT32_C(0x00040000)
2442	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT 19
2443	#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_MASK UINT32_C(0x00080000)
2444	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT 20
2445	#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_MASK UINT32_C(0x00100000)
2446	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT 21
2447	#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_MASK UINT32_C(0x00200000)
2448	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT 22
2449	#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_MASK UINT32_C(0x00400000)
2450	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT 23
2451	#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_MASK UINT32_C(0x00800000)
2452	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT 24
2453	#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_MASK UINT32_C(0x01000000)
2454	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT 25
2455	#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_MASK UINT32_C(0x02000000)
2456	#define VMX_BF_PROC_CTLS_RSVD_26_SHIFT 26
2457	#define VMX_BF_PROC_CTLS_RSVD_26_MASK UINT32_C(0x4000000)
2458	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT 27
2459	#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_MASK UINT32_C(0x08000000)
2460	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT 28
2461	#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_MASK UINT32_C(0x10000000)
2462	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT 29
2463	#define VMX_BF_PROC_CTLS_MONITOR_EXIT_MASK UINT32_C(0x20000000)
2464	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT 30
2465	#define VMX_BF_PROC_CTLS_PAUSE_EXIT_MASK UINT32_C(0x40000000)
2466	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT 31
2467	#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_MASK UINT32_C(0x80000000)
2468	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS_, UINT32_C(0), UINT32_MAX,
2469	(RSVD_0_1, INT_WINDOW_EXIT, USE_TSC_OFFSETTING, RSVD_4_6, HLT_EXIT, RSVD_8, INVLPG_EXIT,
2470	MWAIT_EXIT, RDPMC_EXIT, RDTSC_EXIT, RSVD_13_14, CR3_LOAD_EXIT, CR3_STORE_EXIT, USE_TERTIARY_CTLS,
2471	RSVD_18, CR8_LOAD_EXIT, CR8_STORE_EXIT, USE_TPR_SHADOW, NMI_WINDOW_EXIT, MOV_DR_EXIT, UNCOND_IO_EXIT,
2472	USE_IO_BITMAPS, RSVD_26, MONITOR_TRAP_FLAG, USE_MSR_BITMAPS, MONITOR_EXIT, PAUSE_EXIT,
2473	USE_SECONDARY_CTLS));
2474	/** @} */
2475
2476
2477	/** @name Secondary Processor-based VM-execution controls.
2478	* @{
2479	*/
2480	/** Virtualize APIC accesses. */
2481	#define VMX_PROC_CTLS2_VIRT_APIC_ACCESS RT_BIT(0)
2482	/** EPT supported/enabled. */
2483	#define VMX_PROC_CTLS2_EPT RT_BIT(1)
2484	/** Descriptor table instructions cause VM-exits. */
2485	#define VMX_PROC_CTLS2_DESC_TABLE_EXIT RT_BIT(2)
2486	/** RDTSCP supported/enabled. */
2487	#define VMX_PROC_CTLS2_RDTSCP RT_BIT(3)
2488	/** Virtualize x2APIC mode. */
2489	#define VMX_PROC_CTLS2_VIRT_X2APIC_MODE RT_BIT(4)
2490	/** VPID supported/enabled. */
2491	#define VMX_PROC_CTLS2_VPID RT_BIT(5)
2492	/** VM-exit when executing the WBINVD instruction. */
2493	#define VMX_PROC_CTLS2_WBINVD_EXIT RT_BIT(6)
2494	/** Unrestricted guest execution. */
2495	#define VMX_PROC_CTLS2_UNRESTRICTED_GUEST RT_BIT(7)
2496	/** APIC register virtualization. */
2497	#define VMX_PROC_CTLS2_APIC_REG_VIRT RT_BIT(8)
2498	/** Virtual-interrupt delivery. */
2499	#define VMX_PROC_CTLS2_VIRT_INT_DELIVERY RT_BIT(9)
2500	/** A specified number of pause loops cause a VM-exit. */
2501	#define VMX_PROC_CTLS2_PAUSE_LOOP_EXIT RT_BIT(10)
2502	/** VM-exit when executing RDRAND instructions. */
2503	#define VMX_PROC_CTLS2_RDRAND_EXIT RT_BIT(11)
2504	/** Enables INVPCID instructions. */
2505	#define VMX_PROC_CTLS2_INVPCID RT_BIT(12)
2506	/** Enables VMFUNC instructions. */
2507	#define VMX_PROC_CTLS2_VMFUNC RT_BIT(13)
2508	/** Enables VMCS shadowing. */
2509	#define VMX_PROC_CTLS2_VMCS_SHADOWING RT_BIT(14)
2510	/** Enables ENCLS VM-exits. */
2511	#define VMX_PROC_CTLS2_ENCLS_EXIT RT_BIT(15)
2512	/** VM-exit when executing RDSEED. */
2513	#define VMX_PROC_CTLS2_RDSEED_EXIT RT_BIT(16)
2514	/** Enables page-modification logging. */
2515	#define VMX_PROC_CTLS2_PML RT_BIT(17)
2516	/** Controls whether EPT-violations may cause \#VE instead of exits. */
2517	#define VMX_PROC_CTLS2_EPT_XCPT_VE RT_BIT(18)
2518	/** Conceal VMX non-root operation from Intel processor trace (PT). */
2519	#define VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT RT_BIT(19)
2520	/** Enables XSAVES/XRSTORS instructions. */
2521	#define VMX_PROC_CTLS2_XSAVES_XRSTORS RT_BIT(20)
2522	/** Enables supervisor/user mode based EPT execute permission for linear
2523	* addresses. */
2524	#define VMX_PROC_CTLS2_MODE_BASED_EPT_PERM RT_BIT(22)
2525	/** Enables EPT write permissions to be specified at granularity of 128 bytes. */
2526	#define VMX_PROC_CTLS2_SPP_EPT RT_BIT(23)
2527	/** Intel PT output addresses are treated as guest-physical addresses and
2528	* translated using EPT. */
2529	#define VMX_PROC_CTLS2_PT_EPT RT_BIT(24)
2530	/** Use TSC scaling. */
2531	#define VMX_PROC_CTLS2_TSC_SCALING RT_BIT(25)
2532	/** Enables TPAUSE, UMONITOR and UMWAIT instructions. */
2533	#define VMX_PROC_CTLS2_USER_WAIT_PAUSE RT_BIT(26)
2534	/** Enables consulting ENCLV-exiting bitmap when executing ENCLV. */
2535	#define VMX_PROC_CTLS2_ENCLV_EXIT RT_BIT(28)
2536
2537	/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS2 and Secondary processor-based
2538	* VM-execution controls field in the VMCS. */
2539	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT 0
2540	#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_MASK UINT32_C(0x00000001)
2541	#define VMX_BF_PROC_CTLS2_EPT_SHIFT 1
2542	#define VMX_BF_PROC_CTLS2_EPT_MASK UINT32_C(0x00000002)
2543	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT 2
2544	#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_MASK UINT32_C(0x00000004)
2545	#define VMX_BF_PROC_CTLS2_RDTSCP_SHIFT 3
2546	#define VMX_BF_PROC_CTLS2_RDTSCP_MASK UINT32_C(0x00000008)
2547	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT 4
2548	#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_MASK UINT32_C(0x00000010)
2549	#define VMX_BF_PROC_CTLS2_VPID_SHIFT 5
2550	#define VMX_BF_PROC_CTLS2_VPID_MASK UINT32_C(0x00000020)
2551	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT 6
2552	#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_MASK UINT32_C(0x00000040)
2553	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT 7
2554	#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_MASK UINT32_C(0x00000080)
2555	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT 8
2556	#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_MASK UINT32_C(0x00000100)
2557	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT 9
2558	#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_MASK UINT32_C(0x00000200)
2559	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT 10
2560	#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_MASK UINT32_C(0x00000400)
2561	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT 11
2562	#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_MASK UINT32_C(0x00000800)
2563	#define VMX_BF_PROC_CTLS2_INVPCID_SHIFT 12
2564	#define VMX_BF_PROC_CTLS2_INVPCID_MASK UINT32_C(0x00001000)
2565	#define VMX_BF_PROC_CTLS2_VMFUNC_SHIFT 13
2566	#define VMX_BF_PROC_CTLS2_VMFUNC_MASK UINT32_C(0x00002000)
2567	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT 14
2568	#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_MASK UINT32_C(0x00004000)
2569	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_SHIFT 15
2570	#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_MASK UINT32_C(0x00008000)
2571	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT 16
2572	#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_MASK UINT32_C(0x00010000)
2573	#define VMX_BF_PROC_CTLS2_PML_SHIFT 17
2574	#define VMX_BF_PROC_CTLS2_PML_MASK UINT32_C(0x00020000)
2575	#define VMX_BF_PROC_CTLS2_EPT_VE_SHIFT 18
2576	#define VMX_BF_PROC_CTLS2_EPT_VE_MASK UINT32_C(0x00040000)
2577	#define VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_SHIFT 19
2578	#define VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x00080000)
2579	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT 20
2580	#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_MASK UINT32_C(0x00100000)
2581	#define VMX_BF_PROC_CTLS2_RSVD_21_SHIFT 21
2582	#define VMX_BF_PROC_CTLS2_RSVD_21_MASK UINT32_C(0x00200000)
2583	#define VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_SHIFT 22
2584	#define VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_MASK UINT32_C(0x00400000)
2585	#define VMX_BF_PROC_CTLS2_SPP_EPT_SHIFT 23
2586	#define VMX_BF_PROC_CTLS2_SPP_EPT_MASK UINT32_C(0x00800000)
2587	#define VMX_BF_PROC_CTLS2_PT_EPT_SHIFT 24
2588	#define VMX_BF_PROC_CTLS2_PT_EPT_MASK UINT32_C(0x01000000)
2589	#define VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT 25
2590	#define VMX_BF_PROC_CTLS2_TSC_SCALING_MASK UINT32_C(0x02000000)
2591	#define VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_SHIFT 26
2592	#define VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_MASK UINT32_C(0x04000000)
2593	#define VMX_BF_PROC_CTLS2_RSVD_27_SHIFT 27
2594	#define VMX_BF_PROC_CTLS2_RSVD_27_MASK UINT32_C(0x08000000)
2595	#define VMX_BF_PROC_CTLS2_ENCLV_EXIT_SHIFT 28
2596	#define VMX_BF_PROC_CTLS2_ENCLV_EXIT_MASK UINT32_C(0x10000000)
2597	#define VMX_BF_PROC_CTLS2_RSVD_29_31_SHIFT 29
2598	#define VMX_BF_PROC_CTLS2_RSVD_29_31_MASK UINT32_C(0xe0000000)
2599
2600	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS2_, UINT32_C(0), UINT32_MAX,
2601	(VIRT_APIC_ACCESS, EPT, DESC_TABLE_EXIT, RDTSCP, VIRT_X2APIC_MODE, VPID, WBINVD_EXIT,
2602	UNRESTRICTED_GUEST, APIC_REG_VIRT, VIRT_INT_DELIVERY, PAUSE_LOOP_EXIT, RDRAND_EXIT, INVPCID, VMFUNC,
2603	VMCS_SHADOWING, ENCLS_EXIT, RDSEED_EXIT, PML, EPT_VE, CONCEAL_VMX_FROM_PT, XSAVES_XRSTORS, RSVD_21,
2604	MODE_BASED_EPT_PERM, SPP_EPT, PT_EPT, TSC_SCALING, USER_WAIT_PAUSE, RSVD_27, ENCLV_EXIT,
2605	RSVD_29_31));
2606	/** @} */
2607
2608
2609	/** @name Tertiary Processor-based VM-execution controls.
2610	* @{
2611	*/
2612	/** VM-exit when executing LOADIWKEY. */
2613	#define VMX_PROC_CTLS3_LOADIWKEY_EXIT RT_BIT_64(0)
2614
2615	/** Bit fields for Tertiary processor-based VM-execution controls field in the VMCS. */
2616	#define VMX_BF_PROC_CTLS3_LOADIWKEY_EXIT_SHIFT 0
2617	#define VMX_BF_PROC_CTLS3_LOADIWKEY_EXIT_MASK UINT64_C(0x0000000000000001)
2618	#define VMX_BF_PROC_CTLS3_RSVD_1_63_SHIFT 1
2619	#define VMX_BF_PROC_CTLS3_RSVD_1_63_MASK UINT64_C(0xfffffffffffffffe)
2620
2621	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS3_, UINT64_C(0), UINT64_MAX,
2622	(LOADIWKEY_EXIT, RSVD_1_63));
2623	/** @} */
2624
2625
2626	/** @name VM-entry controls.
2627	* @{
2628	*/
2629	/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2630	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2631	#define VMX_ENTRY_CTLS_LOAD_DEBUG RT_BIT(2)
2632	/** 64-bit guest mode. Must be 0 for CPUs that don't support AMD64. */
2633	#define VMX_ENTRY_CTLS_IA32E_MODE_GUEST RT_BIT(9)
2634	/** In SMM mode after VM-entry. */
2635	#define VMX_ENTRY_CTLS_ENTRY_TO_SMM RT_BIT(10)
2636	/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
2637	#define VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON RT_BIT(11)
2638	/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
2639	#define VMX_ENTRY_CTLS_LOAD_PERF_MSR RT_BIT(13)
2640	/** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
2641	#define VMX_ENTRY_CTLS_LOAD_PAT_MSR RT_BIT(14)
2642	/** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
2643	#define VMX_ENTRY_CTLS_LOAD_EFER_MSR RT_BIT(15)
2644	/** Whether the guest IA32_BNDCFGS MSR is loaded on VM-entry. */
2645	#define VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR RT_BIT(16)
2646	/** Whether to conceal VMX from Intel PT (Processor Trace). */
2647	#define VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT RT_BIT(17)
2648	/** Whether the guest IA32_RTIT MSR is loaded on VM-entry. */
2649	#define VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR RT_BIT(18)
2650	/** Whether the guest CET-related MSRs and SPP are loaded on VM-entry. */
2651	#define VMX_ENTRY_CTLS_LOAD_CET_STATE RT_BIT(20)
2652	/** Whether the guest IA32_PKRS MSR is loaded on VM-entry. */
2653	#define VMX_ENTRY_CTLS_LOAD_PKRS_MSR RT_BIT(22)
2654	/** Default1 class when true-capability MSRs are not supported. */
2655	#define VMX_ENTRY_CTLS_DEFAULT1 UINT32_C(0x000011ff)
2656
2657	/** Bit fields for MSR_IA32_VMX_ENTRY_CTLS and VM-entry controls field in the
2658	* VMCS. */
2659	#define VMX_BF_ENTRY_CTLS_RSVD_0_1_SHIFT 0
2660	#define VMX_BF_ENTRY_CTLS_RSVD_0_1_MASK UINT32_C(0x00000003)
2661	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT 2
2662	#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK UINT32_C(0x00000004)
2663	#define VMX_BF_ENTRY_CTLS_RSVD_3_8_SHIFT 3
2664	#define VMX_BF_ENTRY_CTLS_RSVD_3_8_MASK UINT32_C(0x000001f8)
2665	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT 9
2666	#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK UINT32_C(0x00000200)
2667	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_SHIFT 10
2668	#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK UINT32_C(0x00000400)
2669	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_SHIFT 11
2670	#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK UINT32_C(0x00000800)
2671	#define VMX_BF_ENTRY_CTLS_RSVD_12_SHIFT 12
2672	#define VMX_BF_ENTRY_CTLS_RSVD_12_MASK UINT32_C(0x00001000)
2673	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_SHIFT 13
2674	#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00002000)
2675	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT 14
2676	#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00004000)
2677	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT 15
2678	#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00008000)
2679	#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_SHIFT 16
2680	#define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_MASK UINT32_C(0x00010000)
2681	#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_FROM_PT_SHIFT 17
2682	#define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x00020000)
2683	#define VMX_BF_ENTRY_CTLS_LOAD_RTIT_CTL_MSR_SHIFT 18
2684	#define VMX_BF_ENTRY_CTLS_LOAD_RTIT_CTL_MSR_MASK UINT32_C(0x00040000)
2685	#define VMX_BF_ENTRY_CTLS_RSVD_19_SHIFT 19
2686	#define VMX_BF_ENTRY_CTLS_RSVD_19_MASK UINT32_C(0x00080000)
2687	#define VMX_BF_ENTRY_CTLS_LOAD_CET_SHIFT 20
2688	#define VMX_BF_ENTRY_CTLS_LOAD_CET_MASK UINT32_C(0x00100000)
2689	#define VMX_BF_ENTRY_CTLS_RSVD_21_SHIFT 21
2690	#define VMX_BF_ENTRY_CTLS_RSVD_21_MASK UINT32_C(0x00200000)
2691	#define VMX_BF_ENTRY_CTLS_LOAD_PKRS_MSR_SHIFT 22
2692	#define VMX_BF_ENTRY_CTLS_LOAD_PKRS_MSR_MASK UINT32_C(0x00400000)
2693	#define VMX_BF_ENTRY_CTLS_RSVD_23_31_SHIFT 23
2694	#define VMX_BF_ENTRY_CTLS_RSVD_23_31_MASK UINT32_C(0xff800000)
2695
2696	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_CTLS_, UINT32_C(0), UINT32_MAX,
2697	(RSVD_0_1, LOAD_DEBUG, RSVD_3_8, IA32E_MODE_GUEST, ENTRY_SMM, DEACTIVATE_DUAL_MON, RSVD_12,
2698	LOAD_PERF_MSR, LOAD_PAT_MSR, LOAD_EFER_MSR, LOAD_BNDCFGS_MSR, CONCEAL_VMX_FROM_PT,
2699	LOAD_RTIT_CTL_MSR, RSVD_19, LOAD_CET, RSVD_21, LOAD_PKRS_MSR, RSVD_23_31));
2700	/** @} */
2701
2702
2703	/** @name VM-exit controls.
2704	* @{
2705	*/
2706	/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
2707	* 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
2708	#define VMX_EXIT_CTLS_SAVE_DEBUG RT_BIT(2)
2709	/** Return to long mode after a VM-exit. */
2710	#define VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE RT_BIT(9)
2711	/** Whether the host IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
2712	#define VMX_EXIT_CTLS_LOAD_PERF_MSR RT_BIT(12)
2713	/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
2714	#define VMX_EXIT_CTLS_ACK_EXT_INT RT_BIT(15)
2715	/** Whether the guest IA32_PAT MSR is saved on VM-exit. */
2716	#define VMX_EXIT_CTLS_SAVE_PAT_MSR RT_BIT(18)
2717	/** Whether the host IA32_PAT MSR is loaded on VM-exit. */
2718	#define VMX_EXIT_CTLS_LOAD_PAT_MSR RT_BIT(19)
2719	/** Whether the guest IA32_EFER MSR is saved on VM-exit. */
2720	#define VMX_EXIT_CTLS_SAVE_EFER_MSR RT_BIT(20)
2721	/** Whether the host IA32_EFER MSR is loaded on VM-exit. */
2722	#define VMX_EXIT_CTLS_LOAD_EFER_MSR RT_BIT(21)
2723	/** Whether the value of the VMX preemption timer is saved on every VM-exit. */
2724	#define VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER RT_BIT(22)
2725	/** Whether IA32_BNDCFGS MSR is cleared on VM-exit. */
2726	#define VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR RT_BIT(23)
2727	/** Whether to conceal VMX from Intel PT. */
2728	#define VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT RT_BIT(24)
2729	/** Whether IA32_RTIT_CTL MSR is cleared on VM-exit. */
2730	#define VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR RT_BIT(25)
2731	/** Whether CET-related MSRs and SPP are loaded on VM-exit. */
2732	#define VMX_EXIT_CTLS_LOAD_CET_STATE RT_BIT(28)
2733	/** Whether the host IA32_PKRS MSR is loaded on VM-exit. */
2734	#define VMX_EXIT_CTLS_LOAD_PKRS_MSR RT_BIT(29)
2735	/** Default1 class when true-capability MSRs are not supported. */
2736	#define VMX_EXIT_CTLS_DEFAULT1 UINT32_C(0x00036dff)
2737
2738	/** Bit fields for MSR_IA32_VMX_EXIT_CTLS and VM-exit controls field in the
2739	* VMCS. */
2740	#define VMX_BF_EXIT_CTLS_RSVD_0_1_SHIFT 0
2741	#define VMX_BF_EXIT_CTLS_RSVD_0_1_MASK UINT32_C(0x00000003)
2742	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT 2
2743	#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK UINT32_C(0x00000004)
2744	#define VMX_BF_EXIT_CTLS_RSVD_3_8_SHIFT 3
2745	#define VMX_BF_EXIT_CTLS_RSVD_3_8_MASK UINT32_C(0x000001f8)
2746	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT 9
2747	#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_MASK UINT32_C(0x00000200)
2748	#define VMX_BF_EXIT_CTLS_RSVD_10_11_SHIFT 10
2749	#define VMX_BF_EXIT_CTLS_RSVD_10_11_MASK UINT32_C(0x00000c00)
2750	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_SHIFT 12
2751	#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_MASK UINT32_C(0x00001000)
2752	#define VMX_BF_EXIT_CTLS_RSVD_13_14_SHIFT 13
2753	#define VMX_BF_EXIT_CTLS_RSVD_13_14_MASK UINT32_C(0x00006000)
2754	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT 15
2755	#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_MASK UINT32_C(0x00008000)
2756	#define VMX_BF_EXIT_CTLS_RSVD_16_17_SHIFT 16
2757	#define VMX_BF_EXIT_CTLS_RSVD_16_17_MASK UINT32_C(0x00030000)
2758	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT 18
2759	#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_MASK UINT32_C(0x00040000)
2760	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT 19
2761	#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_MASK UINT32_C(0x00080000)
2762	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT 20
2763	#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_MASK UINT32_C(0x00100000)
2764	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT 21
2765	#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_MASK UINT32_C(0x00200000)
2766	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT 22
2767	#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_MASK UINT32_C(0x00400000)
2768	#define VMX_BF_EXIT_CTLS_CLEAR_BNDCFGS_MSR_SHIFT 23
2769	#define VMX_BF_EXIT_CTLS_CLEAR_BNDCFGS_MSR_MASK UINT32_C(0x00800000)
2770	#define VMX_BF_EXIT_CTLS_CONCEAL_VMX_FROM_PT_SHIFT 24
2771	#define VMX_BF_EXIT_CTLS_CONCEAL_VMX_FROM_PT_MASK UINT32_C(0x01000000)
2772	#define VMX_BF_EXIT_CTLS_CLEAR_RTIT_CTL_MSR_SHIFT 25
2773	#define VMX_BF_EXIT_CTLS_CLEAR_RTIT_CTL_MSR_MASK UINT32_C(0x02000000)
2774	#define VMX_BF_EXIT_CTLS_RSVD_26_27_SHIFT 26
2775	#define VMX_BF_EXIT_CTLS_RSVD_26_27_MASK UINT32_C(0x0c000000)
2776	#define VMX_BF_EXIT_CTLS_LOAD_CET_SHIFT 28
2777	#define VMX_BF_EXIT_CTLS_LOAD_CET_MASK UINT32_C(0x10000000)
2778	#define VMX_BF_EXIT_CTLS_LOAD_PKRS_MSR_SHIFT 29
2779	#define VMX_BF_EXIT_CTLS_LOAD_PKRS_MSR_MASK UINT32_C(0x20000000)
2780	#define VMX_BF_EXIT_CTLS_RSVD_30_31_SHIFT 30
2781	#define VMX_BF_EXIT_CTLS_RSVD_30_31_MASK UINT32_C(0xc0000000)
2782	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_CTLS_, UINT32_C(0), UINT32_MAX,
2783	(RSVD_0_1, SAVE_DEBUG, RSVD_3_8, HOST_ADDR_SPACE_SIZE, RSVD_10_11, LOAD_PERF_MSR, RSVD_13_14,
2784	ACK_EXT_INT, RSVD_16_17, SAVE_PAT_MSR, LOAD_PAT_MSR, SAVE_EFER_MSR, LOAD_EFER_MSR,
2785	SAVE_PREEMPT_TIMER, CLEAR_BNDCFGS_MSR, CONCEAL_VMX_FROM_PT, CLEAR_RTIT_CTL_MSR, RSVD_26_27,
2786	LOAD_CET, LOAD_PKRS_MSR, RSVD_30_31));
2787	/** @} */
2788
2789
2790	/** @name VM-exit reason.
2791	* @{
2792	*/
2793	#define VMX_EXIT_REASON_BASIC(a) ((a) & 0xffff)
2794	#define VMX_EXIT_REASON_HAS_ENTRY_FAILED(a) (((a) >> 31) & 1)
2795	#define VMX_EXIT_REASON_ENTRY_FAILED RT_BIT(31)
2796
2797	/** Bit fields for VM-exit reason. */
2798	/** The exit reason. */
2799	#define VMX_BF_EXIT_REASON_BASIC_SHIFT 0
2800	#define VMX_BF_EXIT_REASON_BASIC_MASK UINT32_C(0x0000ffff)
2801	/** Bits 16:26 are reseved and MBZ. */
2802	#define VMX_BF_EXIT_REASON_RSVD_16_26_SHIFT 16
2803	#define VMX_BF_EXIT_REASON_RSVD_16_26_MASK UINT32_C(0x07ff0000)
2804	/** Whether the VM-exit was incident to enclave mode. */
2805	#define VMX_BF_EXIT_REASON_ENCLAVE_MODE_SHIFT 27
2806	#define VMX_BF_EXIT_REASON_ENCLAVE_MODE_MASK UINT32_C(0x08000000)
2807	/** Pending MTF (Monitor Trap Flag) during VM-exit (only applicable in SMM mode). */
2808	#define VMX_BF_EXIT_REASON_SMM_PENDING_MTF_SHIFT 28
2809	#define VMX_BF_EXIT_REASON_SMM_PENDING_MTF_MASK UINT32_C(0x10000000)
2810	/** VM-exit from VMX root operation (only possible with SMM). */
2811	#define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_SHIFT 29
2812	#define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_MASK UINT32_C(0x20000000)
2813	/** Bit 30 is reserved and MBZ. */
2814	#define VMX_BF_EXIT_REASON_RSVD_30_SHIFT 30
2815	#define VMX_BF_EXIT_REASON_RSVD_30_MASK UINT32_C(0x40000000)
2816	/** Whether VM-entry failed (currently only happens during loading guest-state
2817	* or MSRs or machine check exceptions). */
2818	#define VMX_BF_EXIT_REASON_ENTRY_FAILED_SHIFT 31
2819	#define VMX_BF_EXIT_REASON_ENTRY_FAILED_MASK UINT32_C(0x80000000)
2820	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_REASON_, UINT32_C(0), UINT32_MAX,
2821	(BASIC, RSVD_16_26, ENCLAVE_MODE, SMM_PENDING_MTF, VMX_ROOT_MODE, RSVD_30, ENTRY_FAILED));
2822	/** @} */
2823
2824
2825	/** @name VM-entry interruption information.
2826	* @{
2827	*/
2828	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2829	#define VMX_ENTRY_INT_INFO_VECTOR(a) ((a) & 0xff)
2830	#define VMX_ENTRY_INT_INFO_TYPE_SHIFT 8
2831	#define VMX_ENTRY_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2832	#define VMX_ENTRY_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2833	#define VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2834	#define VMX_ENTRY_INT_INFO_NMI_UNBLOCK_IRET 12
2835	#define VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2836	#define VMX_ENTRY_INT_INFO_VALID RT_BIT(31)
2837	#define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2838	/** Construct an VM-entry interruption information field from a VM-exit interruption
2839	* info value (same except that bit 12 is reserved). */
2840	#define VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12))
2841	/** Construct a VM-entry interruption information field from an IDT-vectoring
2842	* information field (same except that bit 12 is reserved). */
2843	#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a) ((a) & ~RT_BIT(12))
2844	/** If the VM-entry interruption information field indicates a page-fault. */
2845	#define VMX_ENTRY_INT_INFO_IS_XCPT_PF(a) (((a) & ( VMX_BF_ENTRY_INT_INFO_VALID_MASK \
2846	\| VMX_BF_ENTRY_INT_INFO_TYPE_MASK \
2847	\| VMX_BF_ENTRY_INT_INFO_VECTOR_MASK)) \
2848	== ( RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1) \
2849	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_HW_XCPT) \
2850	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_PF)))
2851	/** If the VM-entry interruption information field indicates an external
2852	* interrupt. */
2853	#define VMX_ENTRY_INT_INFO_IS_EXT_INT(a) (((a) & ( VMX_BF_ENTRY_INT_INFO_VALID_MASK \
2854	\| VMX_BF_ENTRY_INT_INFO_TYPE_MASK)) \
2855	== ( RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1) \
2856	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_EXT_INT)))
2857	/** If the VM-entry interruption information field indicates an NMI. */
2858	#define VMX_ENTRY_INT_INFO_IS_XCPT_NMI(a) (((a) & ( VMX_BF_ENTRY_INT_INFO_VALID_MASK \
2859	\| VMX_BF_ENTRY_INT_INFO_TYPE_MASK \
2860	\| VMX_BF_ENTRY_INT_INFO_VECTOR_MASK)) \
2861	== ( RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1) \
2862	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_ENTRY_INT_INFO_TYPE_NMI) \
2863	\| RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_NMI)))
2864
2865	/** Bit fields for VM-entry interruption information. */
2866	/** The VM-entry interruption vector. */
2867	#define VMX_BF_ENTRY_INT_INFO_VECTOR_SHIFT 0
2868	#define VMX_BF_ENTRY_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2869	/** The VM-entry interruption type (see VMX_ENTRY_INT_INFO_TYPE_XXX). */
2870	#define VMX_BF_ENTRY_INT_INFO_TYPE_SHIFT 8
2871	#define VMX_BF_ENTRY_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2872	/** Whether this event has an error code. */
2873	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_SHIFT 11
2874	#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2875	/** Bits 12:30 are reserved and MBZ. */
2876	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_SHIFT 12
2877	#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_MASK UINT32_C(0x7ffff000)
2878	/** Whether this VM-entry interruption info is valid. */
2879	#define VMX_BF_ENTRY_INT_INFO_VALID_SHIFT 31
2880	#define VMX_BF_ENTRY_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2881	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_INT_INFO_, UINT32_C(0), UINT32_MAX,
2882	(VECTOR, TYPE, ERR_CODE_VALID, RSVD_12_30, VALID));
2883	/** @} */
2884
2885
2886	/** @name VM-entry exception error code.
2887	* @{ */
2888	/** Error code valid mask. */
2889	/** @todo r=ramshankar: Intel spec. 26.2.1.3 "VM-Entry Control Fields" states that
2890	* bits 31:15 MBZ. However, Intel spec. 6.13 "Error Code" states "To keep the
2891	* stack aligned for doubleword pushes, the upper half of the error code is
2892	* reserved" which implies bits 31:16 MBZ (and not 31:15) which is what we
2893	* use below. */
2894	#define VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK UINT32_C(0xffff)
2895	/** @} */
2896
2897	/** @name VM-entry interruption information types.
2898	* @{
2899	*/
2900	#define VMX_ENTRY_INT_INFO_TYPE_EXT_INT 0
2901	#define VMX_ENTRY_INT_INFO_TYPE_RSVD 1
2902	#define VMX_ENTRY_INT_INFO_TYPE_NMI 2
2903	#define VMX_ENTRY_INT_INFO_TYPE_HW_XCPT 3
2904	#define VMX_ENTRY_INT_INFO_TYPE_SW_INT 4
2905	#define VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT 5
2906	#define VMX_ENTRY_INT_INFO_TYPE_SW_XCPT 6
2907	#define VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT 7
2908	/** @} */
2909
2910
2911	/** @name VM-entry interruption information vector types for
2912	* VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT.
2913	* @{ */
2914	#define VMX_ENTRY_INT_INFO_VECTOR_MTF 0
2915	/** @} */
2916
2917
2918	/** @name VM-exit interruption information.
2919	* @{
2920	*/
2921	#define VMX_EXIT_INT_INFO_VECTOR(a) ((a) & 0xff)
2922	#define VMX_EXIT_INT_INFO_TYPE_SHIFT 8
2923	#define VMX_EXIT_INT_INFO_TYPE(a) (((a) >> 8) & 7)
2924	#define VMX_EXIT_INT_INFO_ERROR_CODE_VALID RT_BIT(11)
2925	#define VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
2926	#define VMX_EXIT_INT_INFO_NMI_UNBLOCK_IRET 12
2927	#define VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
2928	#define VMX_EXIT_INT_INFO_VALID RT_BIT(31)
2929	#define VMX_EXIT_INT_INFO_IS_VALID(a) (((a) >> 31) & 1)
2930
2931	/** If the VM-exit interruption information field indicates an page-fault. */
2932	#define VMX_EXIT_INT_INFO_IS_XCPT_PF(a) (((a) & ( VMX_BF_EXIT_INT_INFO_VALID_MASK \
2933	\| VMX_BF_EXIT_INT_INFO_TYPE_MASK \
2934	\| VMX_BF_EXIT_INT_INFO_VECTOR_MASK)) \
2935	== ( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1) \
2936	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT) \
2937	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_PF)))
2938	/** If the VM-exit interruption information field indicates an double-fault. */
2939	#define VMX_EXIT_INT_INFO_IS_XCPT_DF(a) (((a) & ( VMX_BF_EXIT_INT_INFO_VALID_MASK \
2940	\| VMX_BF_EXIT_INT_INFO_TYPE_MASK \
2941	\| VMX_BF_EXIT_INT_INFO_VECTOR_MASK)) \
2942	== ( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1) \
2943	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT) \
2944	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_DF)))
2945	/** If the VM-exit interruption information field indicates an NMI. */
2946	#define VMX_EXIT_INT_INFO_IS_XCPT_NMI(a) (((a) & ( VMX_BF_EXIT_INT_INFO_VALID_MASK \
2947	\| VMX_BF_EXIT_INT_INFO_TYPE_MASK \
2948	\| VMX_BF_EXIT_INT_INFO_VECTOR_MASK)) \
2949	== ( RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VALID, 1) \
2950	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_NMI) \
2951	\| RT_BF_MAKE(VMX_BF_EXIT_INT_INFO_VECTOR, X86_XCPT_NMI)))
2952
2953
2954	/** Bit fields for VM-exit interruption infomration. */
2955	/** The VM-exit interruption vector. */
2956	#define VMX_BF_EXIT_INT_INFO_VECTOR_SHIFT 0
2957	#define VMX_BF_EXIT_INT_INFO_VECTOR_MASK UINT32_C(0x000000ff)
2958	/** The VM-exit interruption type (see VMX_EXIT_INT_INFO_TYPE_XXX). */
2959	#define VMX_BF_EXIT_INT_INFO_TYPE_SHIFT 8
2960	#define VMX_BF_EXIT_INT_INFO_TYPE_MASK UINT32_C(0x00000700)
2961	/** Whether this event has an error code. */
2962	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_SHIFT 11
2963	#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
2964	/** Whether NMI-unblocking due to IRET is active. */
2965	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_SHIFT 12
2966	#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_MASK UINT32_C(0x00001000)
2967	/** Bits 13:30 is reserved (MBZ). */
2968	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_SHIFT 13
2969	#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
2970	/** Whether this VM-exit interruption info is valid. */
2971	#define VMX_BF_EXIT_INT_INFO_VALID_SHIFT 31
2972	#define VMX_BF_EXIT_INT_INFO_VALID_MASK UINT32_C(0x80000000)
2973	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_INT_INFO_, UINT32_C(0), UINT32_MAX,
2974	(VECTOR, TYPE, ERR_CODE_VALID, NMI_UNBLOCK_IRET, RSVD_13_30, VALID));
2975	/** @} */
2976
2977
2978	/** @name VM-exit interruption information types.
2979	* @{
2980	*/
2981	#define VMX_EXIT_INT_INFO_TYPE_EXT_INT 0
2982	#define VMX_EXIT_INT_INFO_TYPE_NMI 2
2983	#define VMX_EXIT_INT_INFO_TYPE_HW_XCPT 3
2984	#define VMX_EXIT_INT_INFO_TYPE_SW_INT 4
2985	#define VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT 5
2986	#define VMX_EXIT_INT_INFO_TYPE_SW_XCPT 6
2987	#define VMX_EXIT_INT_INFO_TYPE_UNUSED 7
2988	/** @} */
2989
2990
2991	/** @name VM-exit instruction identity.
2992	*
2993	* These are found in VM-exit instruction information fields for certain
2994	* instructions.
2995	* @{ */
2996	typedef uint32_t VMXINSTRID;
2997	/** Whether the instruction ID field is valid. */
2998	#define VMXINSTRID_VALID RT_BIT_32(31)
2999	/** Whether the instruction's primary operand in the Mod R/M byte (bits 0:3) is a
3000	* read or write. */
3001	#define VMXINSTRID_MODRM_PRIMARY_OP_W RT_BIT_32(30)
3002	/** Gets whether the instruction ID is valid or not. */
3003	#define VMXINSTRID_IS_VALID(a) (((a) >> 31) & 1)
3004	#define VMXINSTRID_IS_MODRM_PRIMARY_OP_W(a) (((a) >> 30) & 1)
3005	/** Gets the instruction ID. */
3006	#define VMXINSTRID_GET_ID(a) ((a) & ~(VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W))
3007	/** No instruction ID info. */
3008	#define VMXINSTRID_NONE 0
3009
3010	/** The OR'd rvalues are from the VT-x spec (valid bit is VBox specific): */
3011	#define VMXINSTRID_SGDT (0x0 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
3012	#define VMXINSTRID_SIDT (0x1 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
3013	#define VMXINSTRID_LGDT (0x2 \| VMXINSTRID_VALID)
3014	#define VMXINSTRID_LIDT (0x3 \| VMXINSTRID_VALID)
3015
3016	#define VMXINSTRID_SLDT (0x0 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
3017	#define VMXINSTRID_STR (0x1 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
3018	#define VMXINSTRID_LLDT (0x2 \| VMXINSTRID_VALID)
3019	#define VMXINSTRID_LTR (0x3 \| VMXINSTRID_VALID)
3020
3021	/** The following IDs are used internally (some for logging, others for conveying
3022	* the ModR/M primary operand write bit): */
3023	#define VMXINSTRID_VMLAUNCH (0x10 \| VMXINSTRID_VALID)
3024	#define VMXINSTRID_VMRESUME (0x11 \| VMXINSTRID_VALID)
3025	#define VMXINSTRID_VMREAD (0x12 \| VMXINSTRID_VALID)
3026	#define VMXINSTRID_VMWRITE (0x13 \| VMXINSTRID_VALID \| VMXINSTRID_MODRM_PRIMARY_OP_W)
3027	#define VMXINSTRID_IO_IN (0x14 \| VMXINSTRID_VALID)
3028	#define VMXINSTRID_IO_INS (0x15 \| VMXINSTRID_VALID)
3029	#define VMXINSTRID_IO_OUT (0x16 \| VMXINSTRID_VALID)
3030	#define VMXINSTRID_IO_OUTS (0x17 \| VMXINSTRID_VALID)
3031	#define VMXINSTRID_MOV_TO_DRX (0x18 \| VMXINSTRID_VALID)
3032	#define VMXINSTRID_MOV_FROM_DRX (0x19 \| VMXINSTRID_VALID)
3033	/** @} */
3034
3035
3036	/** @name IDT-vectoring information.
3037	* @{
3038	*/
3039	#define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff)
3040	#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
3041	#define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> 8) & 7)
3042	#define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11)
3043	#define VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1)
3044	#define VMX_IDT_VECTORING_INFO_IS_VALID(a) (((a) >> 31) & 1)
3045	#define VMX_IDT_VECTORING_INFO_VALID RT_BIT(31)
3046
3047	/** Construct an IDT-vectoring information field from an VM-entry interruption
3048	* information field (same except that bit 12 is reserved). */
3049	#define VMX_IDT_VECTORING_INFO_FROM_ENTRY_INT_INFO(a) ((a) & ~RT_BIT(12))
3050	/** If the IDT-vectoring information field indicates a page-fault. */
3051	#define VMX_IDT_VECTORING_INFO_IS_XCPT_PF(a) (((a) & ( VMX_BF_IDT_VECTORING_INFO_VALID_MASK \
3052	\| VMX_BF_IDT_VECTORING_INFO_TYPE_MASK \
3053	\| VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK)) \
3054	== ( RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1) \
3055	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT) \
3056	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, X86_XCPT_PF)))
3057	/** If the IDT-vectoring information field indicates an NMI. */
3058	#define VMX_IDT_VECTORING_INFO_IS_XCPT_NMI(a) (((a) & ( VMX_BF_IDT_VECTORING_INFO_VALID_MASK \
3059	\| VMX_BF_IDT_VECTORING_INFO_TYPE_MASK \
3060	\| VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK)) \
3061	== ( RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VALID, 1) \
3062	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_TYPE, VMX_IDT_VECTORING_INFO_TYPE_NMI) \
3063	\| RT_BF_MAKE(VMX_BF_IDT_VECTORING_INFO_VECTOR, X86_XCPT_NMI)))
3064
3065
3066	/** Bit fields for IDT-vectoring information. */
3067	/** The IDT-vectoring info vector. */
3068	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_SHIFT 0
3069	#define VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK UINT32_C(0x000000ff)
3070	/** The IDT-vectoring info type (see VMX_IDT_VECTORING_INFO_TYPE_XXX). */
3071	#define VMX_BF_IDT_VECTORING_INFO_TYPE_SHIFT 8
3072	#define VMX_BF_IDT_VECTORING_INFO_TYPE_MASK UINT32_C(0x00000700)
3073	/** Whether the event has an error code. */
3074	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_SHIFT 11
3075	#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_MASK UINT32_C(0x00000800)
3076	/** Bit 12 is undefined. */
3077	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_SHIFT 12
3078	#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_MASK UINT32_C(0x00001000)
3079	/** Bits 13:30 is reserved (MBZ). */
3080	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_SHIFT 13
3081	#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_MASK UINT32_C(0x7fffe000)
3082	/** Whether this IDT-vectoring info is valid. */
3083	#define VMX_BF_IDT_VECTORING_INFO_VALID_SHIFT 31
3084	#define VMX_BF_IDT_VECTORING_INFO_VALID_MASK UINT32_C(0x80000000)
3085	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_IDT_VECTORING_INFO_, UINT32_C(0), UINT32_MAX,
3086	(VECTOR, TYPE, ERR_CODE_VALID, UNDEF_12, RSVD_13_30, VALID));
3087	/** @} */
3088
3089
3090	/** @name IDT-vectoring information vector types.
3091	* @{
3092	*/
3093	#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
3094	#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
3095	#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
3096	#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
3097	#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
3098	#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
3099	#define VMX_IDT_VECTORING_INFO_TYPE_UNUSED 7
3100	/** @} */
3101
3102
3103	/** @name TPR threshold.
3104	* @{ */
3105	/** Mask of the TPR threshold field (bits 31:4 MBZ). */
3106	#define VMX_TPR_THRESHOLD_MASK UINT32_C(0xf)
3107
3108	/** Bit fields for TPR threshold. */
3109	#define VMX_BF_TPR_THRESHOLD_TPR_SHIFT 0
3110	#define VMX_BF_TPR_THRESHOLD_TPR_MASK UINT32_C(0x0000000f)
3111	#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_SHIFT 4
3112	#define VMX_BF_TPR_THRESHOLD_RSVD_4_31_MASK UINT32_C(0xfffffff0)
3113	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_TPR_THRESHOLD_, UINT32_C(0), UINT32_MAX,
3114	(TPR, RSVD_4_31));
3115	/** @} */
3116
3117
3118	/** @name Guest-activity states.
3119	* @{
3120	*/
3121	/** The logical processor is active. */
3122	#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
3123	/** The logical processor is inactive, because it executed a HLT instruction. */
3124	#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
3125	/** The logical processor is inactive, because of a triple fault or other serious error. */
3126	#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
3127	/** The logical processor is inactive, because it's waiting for a startup-IPI */
3128	#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
3129	/** @} */
3130
3131
3132	/** @name Guest-interruptibility states.
3133	* @{
3134	*/
3135	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_STI RT_BIT(0)
3136	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS RT_BIT(1)
3137	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI RT_BIT(2)
3138	#define VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI RT_BIT(3)
3139	#define VMX_VMCS_GUEST_INT_STATE_ENCLAVE RT_BIT(4)
3140
3141	/** Mask of the guest-interruptibility state field (bits 31:5 MBZ). */
3142	#define VMX_VMCS_GUEST_INT_STATE_MASK UINT32_C(0x1f)
3143	/** @} */
3144
3145
3146	/** @name Exit qualification for debug exceptions.
3147	* @{
3148	*/
3149	/** Hardware breakpoint 0 was met. */
3150	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP0 RT_BIT_64(0)
3151	/** Hardware breakpoint 1 was met. */
3152	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP1 RT_BIT_64(1)
3153	/** Hardware breakpoint 2 was met. */
3154	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP2 RT_BIT_64(2)
3155	/** Hardware breakpoint 3 was met. */
3156	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP3 RT_BIT_64(3)
3157	/** Debug register access detected. */
3158	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BD RT_BIT_64(13)
3159	/** A debug exception would have been triggered by single-step execution mode. */
3160	#define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BS RT_BIT_64(14)
3161	/** Mask of all valid bits. */
3162	#define VMX_VMCS_EXIT_QUAL_VALID_MASK ( VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP0 \
3163	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP1 \
3164	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP2 \
3165	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP3 \
3166	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BD \
3167	\| VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BS)
3168
3169	/** Bit fields for Exit qualifications due to debug exceptions. */
3170	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP0_SHIFT 0
3171	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP0_MASK UINT64_C(0x0000000000000001)
3172	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP1_SHIFT 1
3173	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP1_MASK UINT64_C(0x0000000000000002)
3174	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP2_SHIFT 2
3175	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP2_MASK UINT64_C(0x0000000000000004)
3176	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP3_SHIFT 3
3177	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP3_MASK UINT64_C(0x0000000000000008)
3178	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_4_12_SHIFT 4
3179	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_4_12_MASK UINT64_C(0x0000000000001ff0)
3180	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BD_SHIFT 13
3181	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BD_MASK UINT64_C(0x0000000000002000)
3182	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BS_SHIFT 14
3183	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BS_MASK UINT64_C(0x0000000000004000)
3184	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_15_63_SHIFT 15
3185	#define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_15_63_MASK UINT64_C(0xffffffffffff8000)
3186	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_DEBUG_XCPT_, UINT64_C(0), UINT64_MAX,
3187	(BP0, BP1, BP2, BP3, RSVD_4_12, BD, BS, RSVD_15_63));
3188	/** @} */
3189
3190	/** @name Exit qualification for Mov DRx.
3191	* @{
3192	*/
3193	/** 0-2: Debug register number */
3194	#define VMX_EXIT_QUAL_DRX_REGISTER(a) ((a) & 7)
3195	/** 3: Reserved; cleared to 0. */
3196	#define VMX_EXIT_QUAL_DRX_RES1(a) (((a) >> 3) & 1)
3197	/** 4: Direction of move (0 = write, 1 = read) */
3198	#define VMX_EXIT_QUAL_DRX_DIRECTION(a) (((a) >> 4) & 1)
3199	/** 5-7: Reserved; cleared to 0. */
3200	#define VMX_EXIT_QUAL_DRX_RES2(a) (((a) >> 5) & 7)
3201	/** 8-11: General purpose register number. */
3202	#define VMX_EXIT_QUAL_DRX_GENREG(a) (((a) >> 8) & 0xf)
3203
3204	/** Bit fields for Exit qualification due to Mov DRx. */
3205	#define VMX_BF_EXIT_QUAL_DRX_REGISTER_SHIFT 0
3206	#define VMX_BF_EXIT_QUAL_DRX_REGISTER_MASK UINT64_C(0x0000000000000007)
3207	#define VMX_BF_EXIT_QUAL_DRX_RSVD_1_SHIFT 3
3208	#define VMX_BF_EXIT_QUAL_DRX_RSVD_1_MASK UINT64_C(0x0000000000000008)
3209	#define VMX_BF_EXIT_QUAL_DRX_DIRECTION_SHIFT 4
3210	#define VMX_BF_EXIT_QUAL_DRX_DIRECTION_MASK UINT64_C(0x0000000000000010)
3211	#define VMX_BF_EXIT_QUAL_DRX_RSVD_5_7_SHIFT 5
3212	#define VMX_BF_EXIT_QUAL_DRX_RSVD_5_7_MASK UINT64_C(0x00000000000000e0)
3213	#define VMX_BF_EXIT_QUAL_DRX_GENREG_SHIFT 8
3214	#define VMX_BF_EXIT_QUAL_DRX_GENREG_MASK UINT64_C(0x0000000000000f00)
3215	#define VMX_BF_EXIT_QUAL_DRX_RSVD_12_63_SHIFT 12
3216	#define VMX_BF_EXIT_QUAL_DRX_RSVD_12_63_MASK UINT64_C(0xfffffffffffff000)
3217	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_DRX_, UINT64_C(0), UINT64_MAX,
3218	(REGISTER, RSVD_1, DIRECTION, RSVD_5_7, GENREG, RSVD_12_63));
3219	/** @} */
3220
3221
3222	/** @name Exit qualification for debug exceptions types.
3223	* @{
3224	*/
3225	#define VMX_EXIT_QUAL_DRX_DIRECTION_WRITE 0
3226	#define VMX_EXIT_QUAL_DRX_DIRECTION_READ 1
3227	/** @} */
3228
3229
3230	/** @name Exit qualification for control-register accesses.
3231	* @{
3232	*/
3233	/** 0-3: Control register number (0 for CLTS & LMSW) */
3234	#define VMX_EXIT_QUAL_CRX_REGISTER(a) ((a) & 0xf)
3235	/** 4-5: Access type. */
3236	#define VMX_EXIT_QUAL_CRX_ACCESS(a) (((a) >> 4) & 3)
3237	/** 6: LMSW operand type memory (1 for memory, 0 for register). */
3238	#define VMX_EXIT_QUAL_CRX_LMSW_OP_MEM(a) (((a) >> 6) & 1)
3239	/** 7: Reserved; cleared to 0. */
3240	#define VMX_EXIT_QUAL_CRX_RES1(a) (((a) >> 7) & 1)
3241	/** 8-11: General purpose register number (0 for CLTS & LMSW). */
3242	#define VMX_EXIT_QUAL_CRX_GENREG(a) (((a) >> 8) & 0xf)
3243	/** 12-15: Reserved; cleared to 0. */
3244	#define VMX_EXIT_QUAL_CRX_RES2(a) (((a) >> 12) & 0xf)
3245	/** 16-31: LMSW source data (else 0). */
3246	#define VMX_EXIT_QUAL_CRX_LMSW_DATA(a) (((a) >> 16) & 0xffff)
3247
3248	/** Bit fields for Exit qualification for control-register accesses. */
3249	#define VMX_BF_EXIT_QUAL_CRX_REGISTER_SHIFT 0
3250	#define VMX_BF_EXIT_QUAL_CRX_REGISTER_MASK UINT64_C(0x000000000000000f)
3251	#define VMX_BF_EXIT_QUAL_CRX_ACCESS_SHIFT 4
3252	#define VMX_BF_EXIT_QUAL_CRX_ACCESS_MASK UINT64_C(0x0000000000000030)
3253	#define VMX_BF_EXIT_QUAL_CRX_LMSW_OP_SHIFT 6
3254	#define VMX_BF_EXIT_QUAL_CRX_LMSW_OP_MASK UINT64_C(0x0000000000000040)
3255	#define VMX_BF_EXIT_QUAL_CRX_RSVD_7_SHIFT 7
3256	#define VMX_BF_EXIT_QUAL_CRX_RSVD_7_MASK UINT64_C(0x0000000000000080)
3257	#define VMX_BF_EXIT_QUAL_CRX_GENREG_SHIFT 8
3258	#define VMX_BF_EXIT_QUAL_CRX_GENREG_MASK UINT64_C(0x0000000000000f00)
3259	#define VMX_BF_EXIT_QUAL_CRX_RSVD_12_15_SHIFT 12
3260	#define VMX_BF_EXIT_QUAL_CRX_RSVD_12_15_MASK UINT64_C(0x000000000000f000)
3261	#define VMX_BF_EXIT_QUAL_CRX_LMSW_DATA_SHIFT 16
3262	#define VMX_BF_EXIT_QUAL_CRX_LMSW_DATA_MASK UINT64_C(0x00000000ffff0000)
3263	#define VMX_BF_EXIT_QUAL_CRX_RSVD_32_63_SHIFT 32
3264	#define VMX_BF_EXIT_QUAL_CRX_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
3265	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_CRX_, UINT64_C(0), UINT64_MAX,
3266	(REGISTER, ACCESS, LMSW_OP, RSVD_7, GENREG, RSVD_12_15, LMSW_DATA, RSVD_32_63));
3267	/** @} */
3268
3269
3270	/** @name Exit qualification for control-register access types.
3271	* @{
3272	*/
3273	#define VMX_EXIT_QUAL_CRX_ACCESS_WRITE 0
3274	#define VMX_EXIT_QUAL_CRX_ACCESS_READ 1
3275	#define VMX_EXIT_QUAL_CRX_ACCESS_CLTS 2
3276	#define VMX_EXIT_QUAL_CRX_ACCESS_LMSW 3
3277	/** @} */
3278
3279
3280	/** @name Exit qualification for task switch.
3281	* @{
3282	*/
3283	#define VMX_EXIT_QUAL_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)
3284	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)
3285	/** Task switch caused by a call instruction. */
3286	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL 0
3287	/** Task switch caused by an iret instruction. */
3288	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET 1
3289	/** Task switch caused by a jmp instruction. */
3290	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP 2
3291	/** Task switch caused by an interrupt gate. */
3292	#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT 3
3293
3294	/** Bit fields for Exit qualification for task switches. */
3295	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS_SHIFT 0
3296	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS_MASK UINT64_C(0x000000000000ffff)
3297	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_16_29_SHIFT 16
3298	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_16_29_MASK UINT64_C(0x000000003fff0000)
3299	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE_SHIFT 30
3300	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE_MASK UINT64_C(0x00000000c0000000)
3301	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_32_63_SHIFT 32
3302	#define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
3303	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_TASK_SWITCH_, UINT64_C(0), UINT64_MAX,
3304	(NEW_TSS, RSVD_16_29, SOURCE, RSVD_32_63));
3305	/** @} */
3306
3307
3308	/** @name Exit qualification for EPT violations.
3309	* @{
3310	*/
3311	/** Set if acess causing the violation was a data read. */
3312	#define VMX_EXIT_QUAL_EPT_ACCESS_READ RT_BIT_64(0)
3313	/** Set if acess causing the violation was a data write. */
3314	#define VMX_EXIT_QUAL_EPT_ACCESS_WRITE RT_BIT_64(1)
3315	/** Set if the violation was caused by an instruction fetch. */
3316	#define VMX_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH RT_BIT_64(2)
3317	/** AND of the read bit of all EPT structures. */
3318	#define VMX_EXIT_QUAL_EPT_ENTRY_READ RT_BIT_64(3)
3319	/** AND of the write bit of all EPT structures. */
3320	#define VMX_EXIT_QUAL_EPT_ENTRY_WRITE RT_BIT_64(4)
3321	/** AND of the execute bit of all EPT structures. */
3322	#define VMX_EXIT_QUAL_EPT_ENTRY_EXECUTE RT_BIT_64(5)
3323	/** And of the execute bit of all EPT structures for user-mode addresses
3324	* (requires mode-based execute control). */
3325	#define VMX_EXIT_QUAL_EPT_ENTRY_EXECUTE_USER RT_BIT_64(6)
3326	/** Set if the guest linear address field is valid. */
3327	#define VMX_EXIT_QUAL_EPT_LINEAR_ADDR_VALID RT_BIT_64(7)
3328	/** If bit 7 is one: (reserved otherwise)
3329	* 1 - violation due to physical address access.
3330	* 0 - violation caused by page walk or access/dirty bit updates.
3331	*/
3332	#define VMX_EXIT_QUAL_EPT_LINEAR_TO_PHYS_ADDR RT_BIT_64(8)
3333	/** If bit 7, 8 and advanced VM-exit info. for EPT is one: (reserved otherwise)
3334	* 1 - linear address is user-mode address.
3335	* 0 - linear address is supervisor-mode address.
3336	*/
3337	#define VMX_EXIT_QUAL_EPT_LINEAR_ADDR_USER RT_BIT_64(9)
3338	/** If bit 7, 8 and advanced VM-exit info. for EPT is one: (reserved otherwise)
3339	* 1 - linear address translates to read-only page.
3340	* 0 - linear address translates to read-write page.
3341	*/
3342	#define VMX_EXIT_QUAL_EPT_LINEAR_ADDR_RO RT_BIT_64(10)
3343	/** If bit 7, 8 and advanced VM-exit info. for EPT is one: (reserved otherwise)
3344	* 1 - linear address translates to executable-disabled page.
3345	* 0 - linear address translates to executable page.
3346	*/
3347	#define VMX_EXIT_QUAL_EPT_LINEAR_ADDR_XD RT_BIT_64(11)
3348	/** NMI unblocking due to IRET. */
3349	#define VMX_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET RT_BIT_64(12)
3350	/** Set if acess causing the violation was a shadow-stack access. */
3351	#define VMX_EXIT_QUAL_EPT_ACCESS_SHW_STACK RT_BIT_64(13)
3352	/** If supervisor-shadow stack is enabled: (reserved otherwise)
3353	* 1 - supervisor shadow-stack access allowed.
3354	* 0 - supervisor shadow-stack access disallowed.
3355	*/
3356	#define VMX_EXIT_QUAL_EPT_ENTRY_SHW_STACK_SUPER RT_BIT_64(14)
3357	/** Set if access is related to trace output by Intel PT (reserved otherwise). */
3358	#define VMX_EXIT_QUAL_EPT_ACCESS_PT_TRACE RT_BIT_64(16)
3359
3360	/** Checks whether NMI unblocking due to IRET. */
3361	#define VMX_EXIT_QUAL_EPT_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1)
3362
3363	/** Bit fields for Exit qualification for EPT violations. */
3364	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_READ_SHIFT 0
3365	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_READ_MASK UINT64_C(0x0000000000000001)
3366	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE_SHIFT 1
3367	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_WRITE_MASK UINT64_C(0x0000000000000002)
3368	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH_SHIFT 2
3369	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_INSTR_FETCH_MASK UINT64_C(0x0000000000000004)
3370	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_READ_SHIFT 3
3371	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_READ_MASK UINT64_C(0x0000000000000008)
3372	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE_SHIFT 4
3373	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_WRITE_MASK UINT64_C(0x0000000000000010)
3374	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE_SHIFT 5
3375	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE_MASK UINT64_C(0x0000000000000020)
3376	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE_USER_SHIFT 6
3377	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_EXECUTE_USER_MASK UINT64_C(0x0000000000000040)
3378	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID_SHIFT 7
3379	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_VALID_MASK UINT64_C(0x0000000000000080)
3380	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_TO_PHYS_ADDR_SHIFT 8
3381	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_TO_PHYS_ADDR_MASK UINT64_C(0x0000000000000100)
3382	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_USER_SHIFT 9
3383	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_USER_MASK UINT64_C(0x0000000000000200)
3384	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_RO_SHIFT 10
3385	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_RO_MASK UINT64_C(0x0000000000000400)
3386	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_XD_SHIFT 11
3387	#define VMX_BF_EXIT_QUAL_EPT_LINEAR_ADDR_XD_MASK UINT64_C(0x0000000000000800)
3388	#define VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET_SHIFT 12
3389	#define VMX_BF_EXIT_QUAL_EPT_NMI_UNBLOCK_IRET_MASK UINT64_C(0x0000000000001000)
3390	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_SHW_STACK_SHIFT 13
3391	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_SHW_STACK_MASK UINT64_C(0x0000000000002000)
3392	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_SHW_STACK_SUPER_SHIFT 14
3393	#define VMX_BF_EXIT_QUAL_EPT_ENTRY_SHW_STACK_SUPER_MASK UINT64_C(0x0000000000004000)
3394	#define VMX_BF_EXIT_QUAL_EPT_RSVD_15_SHIFT 15
3395	#define VMX_BF_EXIT_QUAL_EPT_RSVD_15_MASK UINT64_C(0x0000000000008000)
3396	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_PT_TRACE_SHIFT 16
3397	#define VMX_BF_EXIT_QUAL_EPT_ACCESS_PT_TRACE_MASK UINT64_C(0x0000000000010000)
3398	#define VMX_BF_EXIT_QUAL_EPT_RSVD_17_63_SHIFT 17
3399	#define VMX_BF_EXIT_QUAL_EPT_RSVD_17_63_MASK UINT64_C(0xfffffffffffe0000)
3400	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_EPT_, UINT64_C(0), UINT64_MAX,
3401	(ACCESS_READ, ACCESS_WRITE, ACCESS_INSTR_FETCH, ENTRY_READ, ENTRY_WRITE, ENTRY_EXECUTE,
3402	ENTRY_EXECUTE_USER, LINEAR_ADDR_VALID, LINEAR_TO_PHYS_ADDR, LINEAR_ADDR_USER, LINEAR_ADDR_RO,
3403	LINEAR_ADDR_XD, NMI_UNBLOCK_IRET, ACCESS_SHW_STACK, ENTRY_SHW_STACK_SUPER, RSVD_15,
3404	ACCESS_PT_TRACE, RSVD_17_63));
3405	/** @} */
3406
3407
3408	/** @name Exit qualification for I/O instructions.
3409	* @{
3410	*/
3411	/** 0-2: IO operation size 0(=1 byte), 1(=2 bytes) and 3(=4 bytes). */
3412	#define VMX_EXIT_QUAL_IO_SIZE(a) ((a) & 7)
3413	/** 3: IO operation direction. */
3414	#define VMX_EXIT_QUAL_IO_DIRECTION(a) (((a) >> 3) & 1)
3415	/** 4: String IO operation (INS / OUTS). */
3416	#define VMX_EXIT_QUAL_IO_IS_STRING(a) (((a) >> 4) & 1)
3417	/** 5: Repeated IO operation. */
3418	#define VMX_EXIT_QUAL_IO_IS_REP(a) (((a) >> 5) & 1)
3419	/** 6: Operand encoding. */
3420	#define VMX_EXIT_QUAL_IO_ENCODING(a) (((a) >> 6) & 1)
3421	/** 16-31: IO Port (0-0xffff). */
3422	#define VMX_EXIT_QUAL_IO_PORT(a) (((a) >> 16) & 0xffff)
3423
3424	/** Bit fields for Exit qualification for I/O instructions. */
3425	#define VMX_BF_EXIT_QUAL_IO_WIDTH_SHIFT 0
3426	#define VMX_BF_EXIT_QUAL_IO_WIDTH_MASK UINT64_C(0x0000000000000007)
3427	#define VMX_BF_EXIT_QUAL_IO_DIRECTION_SHIFT 3
3428	#define VMX_BF_EXIT_QUAL_IO_DIRECTION_MASK UINT64_C(0x0000000000000008)
3429	#define VMX_BF_EXIT_QUAL_IO_IS_STRING_SHIFT 4
3430	#define VMX_BF_EXIT_QUAL_IO_IS_STRING_MASK UINT64_C(0x0000000000000010)
3431	#define VMX_BF_EXIT_QUAL_IO_IS_REP_SHIFT 5
3432	#define VMX_BF_EXIT_QUAL_IO_IS_REP_MASK UINT64_C(0x0000000000000020)
3433	#define VMX_BF_EXIT_QUAL_IO_ENCODING_SHIFT 6
3434	#define VMX_BF_EXIT_QUAL_IO_ENCODING_MASK UINT64_C(0x0000000000000040)
3435	#define VMX_BF_EXIT_QUAL_IO_RSVD_7_15_SHIFT 7
3436	#define VMX_BF_EXIT_QUAL_IO_RSVD_7_15_MASK UINT64_C(0x000000000000ff80)
3437	#define VMX_BF_EXIT_QUAL_IO_PORT_SHIFT 16
3438	#define VMX_BF_EXIT_QUAL_IO_PORT_MASK UINT64_C(0x00000000ffff0000)
3439	#define VMX_BF_EXIT_QUAL_IO_RSVD_32_63_SHIFT 32
3440	#define VMX_BF_EXIT_QUAL_IO_RSVD_32_63_MASK UINT64_C(0xffffffff00000000)
3441	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_IO_, UINT64_C(0), UINT64_MAX,
3442	(WIDTH, DIRECTION, IS_STRING, IS_REP, ENCODING, RSVD_7_15, PORT, RSVD_32_63));
3443	/** @} */
3444
3445
3446	/** @name Exit qualification for I/O instruction types.
3447	* @{
3448	*/
3449	#define VMX_EXIT_QUAL_IO_DIRECTION_OUT 0
3450	#define VMX_EXIT_QUAL_IO_DIRECTION_IN 1
3451	/** @} */
3452
3453
3454	/** @name Exit qualification for I/O instruction encoding.
3455	* @{
3456	*/
3457	#define VMX_EXIT_QUAL_IO_ENCODING_DX 0
3458	#define VMX_EXIT_QUAL_IO_ENCODING_IMM 1
3459	/** @} */
3460
3461
3462	/** @name Exit qualification for APIC-access VM-exits from linear and
3463	* guest-physical accesses.
3464	* @{
3465	*/
3466	/** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of
3467	* access within the APIC page. */
3468	#define VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)
3469	/** 12-15: Access type. */
3470	#define VMX_EXIT_QUAL_APIC_ACCESS_TYPE(a) (((a) & 0xf000) >> 12)
3471	/* Rest reserved. */
3472
3473	/** Bit fields for Exit qualification for APIC-access VM-exits. */
3474	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_SHIFT 0
3475	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_MASK UINT64_C(0x0000000000000fff)
3476	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_SHIFT 12
3477	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_MASK UINT64_C(0x000000000000f000)
3478	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_SHIFT 16
3479	#define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_MASK UINT64_C(0xffffffffffff0000)
3480	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_APIC_ACCESS_, UINT64_C(0), UINT64_MAX,
3481	(OFFSET, TYPE, RSVD_16_63));
3482	/** @} */
3483
3484
3485	/** @name Exit qualification for linear address APIC-access types.
3486	* @{
3487	*/
3488	/** Linear access for a data read during instruction execution. */
3489	#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
3490	/** Linear access for a data write during instruction execution. */
3491	#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
3492	/** Linear access for an instruction fetch. */
3493	#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
3494	/** Linear read/write access during event delivery. */
3495	#define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY 3
3496	/** Physical read/write access during event delivery. */
3497	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
3498	/** Physical access for an instruction fetch or during instruction execution. */
3499	#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
3500
3501	/**
3502	* APIC-access type.
3503	* In accordance with the VT-x spec.
3504	*/
3505	typedef enum
3506	{
3507	VMXAPICACCESS_LINEAR_READ = VMX_APIC_ACCESS_TYPE_LINEAR_READ,
3508	VMXAPICACCESS_LINEAR_WRITE = VMX_APIC_ACCESS_TYPE_LINEAR_WRITE,
3509	VMXAPICACCESS_LINEAR_INSTR_FETCH = VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH,
3510	VMXAPICACCESS_LINEAR_EVENT_DELIVERY = VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY,
3511	VMXAPICACCESS_PHYSICAL_EVENT_DELIVERY = VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY,
3512	VMXAPICACCESS_PHYSICAL_INSTR = VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR
3513	} VMXAPICACCESS;
3514	AssertCompileSize(VMXAPICACCESS, 4);
3515	/** @} */
3516
3517
3518	/** @name VMX_BF_XXTR_INSINFO_XXX - VMX_EXIT_XDTR_ACCESS instruction information.
3519	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
3520	* @{
3521	*/
3522	/** Address calculation scaling field (powers of two). */
3523	#define VMX_BF_XDTR_INSINFO_SCALE_SHIFT 0
3524	#define VMX_BF_XDTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
3525	/** Bits 2 thru 6 are undefined. */
3526	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_SHIFT 2
3527	#define VMX_BF_XDTR_INSINFO_UNDEF_2_6_MASK UINT32_C(0x0000007c)
3528	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
3529	* @remarks anyone's guess why this is a 3 bit field... */
3530	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_SHIFT 7
3531	#define VMX_BF_XDTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
3532	/** Bit 10 is defined as zero. */
3533	#define VMX_BF_XDTR_INSINFO_ZERO_10_SHIFT 10
3534	#define VMX_BF_XDTR_INSINFO_ZERO_10_MASK UINT32_C(0x00000400)
3535	/** Operand size, either (1=)32-bit or (0=)16-bit, but get this, it's undefined
3536	* for exits from 64-bit code as the operand size there is fixed. */
3537	#define VMX_BF_XDTR_INSINFO_OP_SIZE_SHIFT 11
3538	#define VMX_BF_XDTR_INSINFO_OP_SIZE_MASK UINT32_C(0x00000800)
3539	/** Bits 12 thru 14 are undefined. */
3540	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_SHIFT 12
3541	#define VMX_BF_XDTR_INSINFO_UNDEF_12_14_MASK UINT32_C(0x00007000)
3542	/** Applicable segment register (X86_SREG_XXX values). */
3543	#define VMX_BF_XDTR_INSINFO_SREG_SHIFT 15
3544	#define VMX_BF_XDTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
3545	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
3546	#define VMX_BF_XDTR_INSINFO_INDEX_REG_SHIFT 18
3547	#define VMX_BF_XDTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
3548	/** Is VMX_BF_XDTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
3549	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_SHIFT 22
3550	#define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
3551	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
3552	#define VMX_BF_XDTR_INSINFO_BASE_REG_SHIFT 23
3553	#define VMX_BF_XDTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
3554	/** Is VMX_XDTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
3555	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_SHIFT 27
3556	#define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
3557	/** The instruction identity (VMX_XDTR_INSINFO_II_XXX values). */
3558	#define VMX_BF_XDTR_INSINFO_INSTR_ID_SHIFT 28
3559	#define VMX_BF_XDTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
3560	#define VMX_XDTR_INSINFO_II_SGDT 0 /*< Instruction ID: SGDT /
3561	#define VMX_XDTR_INSINFO_II_SIDT 1 /*< Instruction ID: SIDT /
3562	#define VMX_XDTR_INSINFO_II_LGDT 2 /*< Instruction ID: LGDT /
3563	#define VMX_XDTR_INSINFO_II_LIDT 3 /*< Instruction ID: LIDT /
3564	/** Bits 30 & 31 are undefined. */
3565	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_SHIFT 30
3566	#define VMX_BF_XDTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
3567	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_XDTR_INSINFO_, UINT32_C(0), UINT32_MAX,
3568	(SCALE, UNDEF_2_6, ADDR_SIZE, ZERO_10, OP_SIZE, UNDEF_12_14, SREG, INDEX_REG, HAS_INDEX_REG,
3569	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
3570	/** @} */
3571
3572
3573	/** @name VMX_BF_YYTR_INSINFO_XXX - VMX_EXIT_TR_ACCESS instruction information.
3574	* Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
3575	* This is similar to VMX_BF_XDTR_INSINFO_XXX.
3576	* @{
3577	*/
3578	/** Address calculation scaling field (powers of two). */
3579	#define VMX_BF_YYTR_INSINFO_SCALE_SHIFT 0
3580	#define VMX_BF_YYTR_INSINFO_SCALE_MASK UINT32_C(0x00000003)
3581	/** Bit 2 is undefined. */
3582	#define VMX_BF_YYTR_INSINFO_UNDEF_2_SHIFT 2
3583	#define VMX_BF_YYTR_INSINFO_UNDEF_2_MASK UINT32_C(0x00000004)
3584	/** Register operand 1. Undefined if VMX_YYTR_INSINFO_HAS_REG1 is clear. */
3585	#define VMX_BF_YYTR_INSINFO_REG1_SHIFT 3
3586	#define VMX_BF_YYTR_INSINFO_REG1_MASK UINT32_C(0x00000078)
3587	/** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
3588	* @remarks anyone's guess why this is a 3 bit field... */
3589	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_SHIFT 7
3590	#define VMX_BF_YYTR_INSINFO_ADDR_SIZE_MASK UINT32_C(0x00000380)
3591	/** Is VMX_YYTR_INSINFO_REG1_XXX valid (=1) or not (=0). */
3592	#define VMX_BF_YYTR_INSINFO_HAS_REG1_SHIFT 10
3593	#define VMX_BF_YYTR_INSINFO_HAS_REG1_MASK UINT32_C(0x00000400)
3594	/** Bits 11 thru 14 are undefined. */
3595	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_SHIFT 11
3596	#define VMX_BF_YYTR_INSINFO_UNDEF_11_14_MASK UINT32_C(0x00007800)
3597	/** Applicable segment register (X86_SREG_XXX values). */
3598	#define VMX_BF_YYTR_INSINFO_SREG_SHIFT 15
3599	#define VMX_BF_YYTR_INSINFO_SREG_MASK UINT32_C(0x00038000)
3600	/** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
3601	#define VMX_BF_YYTR_INSINFO_INDEX_REG_SHIFT 18
3602	#define VMX_BF_YYTR_INSINFO_INDEX_REG_MASK UINT32_C(0x003c0000)
3603	/** Is VMX_YYTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
3604	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_SHIFT 22
3605	#define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_MASK UINT32_C(0x00400000)
3606	/** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
3607	#define VMX_BF_YYTR_INSINFO_BASE_REG_SHIFT 23
3608	#define VMX_BF_YYTR_INSINFO_BASE_REG_MASK UINT32_C(0x07800000)
3609	/** Is VMX_YYTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
3610	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_SHIFT 27
3611	#define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_MASK UINT32_C(0x08000000)
3612	/** The instruction identity (VMX_YYTR_INSINFO_II_XXX values) */
3613	#define VMX_BF_YYTR_INSINFO_INSTR_ID_SHIFT 28
3614	#define VMX_BF_YYTR_INSINFO_INSTR_ID_MASK UINT32_C(0x30000000)
3615	#define VMX_YYTR_INSINFO_II_SLDT 0 /*< Instruction ID: SLDT /
3616	#define VMX_YYTR_INSINFO_II_STR 1 /*< Instruction ID: STR /
3617	#define VMX_YYTR_INSINFO_II_LLDT 2 /*< Instruction ID: LLDT /
3618	#define VMX_YYTR_INSINFO_II_LTR 3 /*< Instruction ID: LTR /
3619	/** Bits 30 & 31 are undefined. */
3620	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_SHIFT 30
3621	#define VMX_BF_YYTR_INSINFO_UNDEF_30_31_MASK UINT32_C(0xc0000000)
3622	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_YYTR_INSINFO_, UINT32_C(0), UINT32_MAX,
3623	(SCALE, UNDEF_2, REG1, ADDR_SIZE, HAS_REG1, UNDEF_11_14, SREG, INDEX_REG, HAS_INDEX_REG,
3624	BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
3625	/** @} */
3626
3627
3628	/** @name Format of Pending-Debug-Exceptions.
3629	* Bits 4-11, 13, 15 and 17-63 are reserved.
3630	* Similar to DR6 except bit 12 (breakpoint enabled) and bit 16 (RTM) are both
3631	* possibly valid here but not in DR6.
3632	* @{
3633	*/
3634	/** Hardware breakpoint 0 was met. */
3635	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 RT_BIT_64(0)
3636	/** Hardware breakpoint 1 was met. */
3637	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 RT_BIT_64(1)
3638	/** Hardware breakpoint 2 was met. */
3639	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 RT_BIT_64(2)
3640	/** Hardware breakpoint 3 was met. */
3641	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 RT_BIT_64(3)
3642	/** At least one data or IO breakpoint was hit. */
3643	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP RT_BIT_64(12)
3644	/** A debug exception would have been triggered by single-step execution mode. */
3645	#define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS RT_BIT_64(14)
3646	/** A debug exception occurred inside an RTM region. */
3647	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM RT_BIT_64(16)
3648	/** Mask of valid bits. */
3649	#define VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 \
3650	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 \
3651	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 \
3652	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 \
3653	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
3654	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
3655	\| VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
3656	#define VMX_VMCS_GUEST_PENDING_DEBUG_RTM_MASK ( VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
3657	\| VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
3658	\| VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
3659	/** Bit fields for Pending debug exceptions. */
3660	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_SHIFT 0
3661	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_MASK UINT64_C(0x0000000000000001)
3662	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_SHIFT 1
3663	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_MASK UINT64_C(0x0000000000000002)
3664	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_SHIFT 2
3665	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_MASK UINT64_C(0x0000000000000004)
3666	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_SHIFT 3
3667	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_MASK UINT64_C(0x0000000000000008)
3668	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_SHIFT 4
3669	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_MASK UINT64_C(0x0000000000000ff0)
3670	#define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_SHIFT 12
3671	#define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_MASK UINT64_C(0x0000000000001000)
3672	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_SHIFT 13
3673	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_MASK UINT64_C(0x0000000000002000)
3674	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_SHIFT 14
3675	#define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_MASK UINT64_C(0x0000000000004000)
3676	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_SHIFT 15
3677	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_MASK UINT64_C(0x0000000000008000)
3678	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_SHIFT 16
3679	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_MASK UINT64_C(0x0000000000010000)
3680	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_SHIFT 17
3681	#define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_MASK UINT64_C(0xfffffffffffe0000)
3682	RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_PENDING_DBG_XCPT_, UINT64_C(0), UINT64_MAX,
3683	(BP0, BP1, BP2, BP3, RSVD_4_11, EN_BP, RSVD_13, BS, RSVD_15, RTM, RSVD_17_63));
3684	/** @} */
3685
3686
3687	/**
3688	* VM-exit auxiliary information.
3689	*
3690	* This includes information that isn't necessarily stored in the guest-CPU
3691	* context but provided as part of VM-exits.
3692	*/
3693	typedef struct
3694	{
3695	/** The VM-exit reason. */
3696	uint32_t uReason;
3697	/** The Exit qualification field. */
3698	uint64_t u64Qual;
3699	/** The Guest-linear address field. */
3700	uint64_t u64GuestLinearAddr;
3701	/** The Guest-physical address field. */
3702	uint64_t u64GuestPhysAddr;
3703	/** The guest pending-debug exceptions. */
3704	uint64_t u64GuestPendingDbgXcpts;
3705	/** The VM-exit instruction length. */
3706	uint32_t cbInstr;
3707	/** The VM-exit instruction information. */
3708	VMXEXITINSTRINFO InstrInfo;
3709	/** VM-exit interruption information. */
3710	uint32_t uExitIntInfo;
3711	/** VM-exit interruption error code. */
3712	uint32_t uExitIntErrCode;
3713	/** IDT-vectoring information. */
3714	uint32_t uIdtVectoringInfo;
3715	/** IDT-vectoring error code. */
3716	uint32_t uIdtVectoringErrCode;
3717	} VMXEXITAUX;
3718	/** Pointer to a VMXEXITAUX struct. */
3719	typedef VMXEXITAUX *PVMXEXITAUX;
3720	/** Pointer to a const VMXEXITAUX struct. */
3721	typedef const VMXEXITAUX *PCVMXEXITAUX;
3722
3723
3724	/** @defgroup grp_hm_vmx_virt VMX virtualization.
3725	* @{
3726	*/
3727
3728	/** @name Virtual VMX MSR - Miscellaneous data.
3729	* @{ */
3730	/** Number of CR3-target values supported. */
3731	#define VMX_V_CR3_TARGET_COUNT 4
3732	/** Activity states supported. */
3733	#define VMX_V_GUEST_ACTIVITY_STATE_MASK (VMX_VMCS_GUEST_ACTIVITY_HLT \| VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN)
3734	/** VMX preemption-timer shift (Core i7-2600 taken as reference). */
3735	#define VMX_V_PREEMPT_TIMER_SHIFT 5
3736	/** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
3737	#define VMX_V_AUTOMSR_COUNT_MAX 0
3738	/** SMM MSEG revision ID. */
3739	#define VMX_V_MSEG_REV_ID 0
3740	/** @} */
3741
3742	/** @name VMX_V_VMCS_STATE_XXX - Virtual VMCS launch state.
3743	* @{ */
3744	/** VMCS launch state clear. */
3745	#define VMX_V_VMCS_LAUNCH_STATE_CLEAR RT_BIT(0)
3746	/** VMCS launch state active. */
3747	#define VMX_V_VMCS_LAUNCH_STATE_ACTIVE RT_BIT(1)
3748	/** VMCS launch state current. */
3749	#define VMX_V_VMCS_LAUNCH_STATE_CURRENT RT_BIT(2)
3750	/** VMCS launch state launched. */
3751	#define VMX_V_VMCS_LAUNCH_STATE_LAUNCHED RT_BIT(3)
3752	/** The mask of valid VMCS launch states. */
3753	#define VMX_V_VMCS_LAUNCH_STATE_MASK ( VMX_V_VMCS_LAUNCH_STATE_CLEAR \
3754	\| VMX_V_VMCS_LAUNCH_STATE_ACTIVE \
3755	\| VMX_V_VMCS_LAUNCH_STATE_CURRENT \
3756	\| VMX_V_VMCS_LAUNCH_STATE_LAUNCHED)
3757	/** @} */
3758
3759	/** CR0 bits set here must always be set when in VMX operation. */
3760	#define VMX_V_CR0_FIXED0 (X86_CR0_PE \| X86_CR0_NE \| X86_CR0_PG)
3761	/** CR0 bits set here must always be set when in VMX non-root operation with
3762	* unrestricted-guest control enabled. */
3763	#define VMX_V_CR0_FIXED0_UX (X86_CR0_NE)
3764	/** CR0 bits cleared here must always be cleared when in VMX operation. */
3765	#define VMX_V_CR0_FIXED1 UINT32_C(0xffffffff)
3766	/** CR4 bits set here must always be set when in VMX operation. */
3767	#define VMX_V_CR4_FIXED0 (X86_CR4_VMXE)
3768
3769	/** Virtual VMCS revision ID. Bump this arbitarily chosen identifier if incompatible
3770	* changes to the layout of VMXVVMCS is done. Bit 31 MBZ. */
3771	#define VMX_V_VMCS_REVISION_ID UINT32_C(0x40000001)
3772	AssertCompile(!(VMX_V_VMCS_REVISION_ID & RT_BIT(31)));
3773
3774	/** The size of the virtual VMCS region (we use the maximum allowed size to avoid
3775	* complications when teleporation may be implemented). */
3776	#define VMX_V_VMCS_SIZE X86_PAGE_4K_SIZE
3777	/** The size of the virtual VMCS region (in pages). */
3778	#define VMX_V_VMCS_PAGES 1
3779
3780	/** The size of the virtual shadow VMCS region. */
3781	#define VMX_V_SHADOW_VMCS_SIZE VMX_V_VMCS_SIZE
3782	/** The size of the virtual shadow VMCS region (in pages). */
3783	#define VMX_V_SHADOW_VMCS_PAGES VMX_V_VMCS_PAGES
3784
3785	/** The size of the Virtual-APIC page (in bytes). */
3786	#define VMX_V_VIRT_APIC_SIZE X86_PAGE_4K_SIZE
3787	/** The size of the Virtual-APIC page (in pages). */
3788	#define VMX_V_VIRT_APIC_PAGES 1
3789
3790	/** The size of the VMREAD/VMWRITE bitmap (in bytes). */
3791	#define VMX_V_VMREAD_VMWRITE_BITMAP_SIZE X86_PAGE_4K_SIZE
3792	/** The size of the VMREAD/VMWRITE-bitmap (in pages). */
3793	#define VMX_V_VMREAD_VMWRITE_BITMAP_PAGES 1
3794
3795	/** The size of the MSR bitmap (in bytes). */
3796	#define VMX_V_MSR_BITMAP_SIZE X86_PAGE_4K_SIZE
3797	/** The size of the MSR bitmap (in pages). */
3798	#define VMX_V_MSR_BITMAP_PAGES 1
3799
3800	/** The size of I/O bitmap A (in bytes). */
3801	#define VMX_V_IO_BITMAP_A_SIZE X86_PAGE_4K_SIZE
3802	/** The size of I/O bitmap A (in pages). */
3803	#define VMX_V_IO_BITMAP_A_PAGES 1
3804
3805	/** The size of I/O bitmap B (in bytes). */
3806	#define VMX_V_IO_BITMAP_B_SIZE X86_PAGE_4K_SIZE
3807	/** The size of I/O bitmap B (in pages). */
3808	#define VMX_V_IO_BITMAP_B_PAGES 1
3809
3810	/** The size of the auto-load/store MSR area (in bytes). */
3811	#define VMX_V_AUTOMSR_AREA_SIZE ((512 * (VMX_V_AUTOMSR_COUNT_MAX + 1)) * sizeof(VMXAUTOMSR))
3812	/* Assert that the size is page aligned or adjust the VMX_V_AUTOMSR_AREA_PAGES macro below. */
3813	AssertCompile(RT_ALIGN_Z(VMX_V_AUTOMSR_AREA_SIZE, X86_PAGE_4K_SIZE) == VMX_V_AUTOMSR_AREA_SIZE);
3814	/** The size of the auto-load/store MSR area (in pages). */
3815	#define VMX_V_AUTOMSR_AREA_PAGES ((VMX_V_AUTOMSR_AREA_SIZE) >> X86_PAGE_4K_SHIFT)
3816
3817	/** The highest index value used for supported virtual VMCS field encoding. */
3818	#define VMX_V_VMCS_MAX_INDEX RT_BF_GET(VMX_VMCS64_CTRL_ENCLV_EXITING_BITMAP_HIGH, VMX_BF_VMCSFIELD_INDEX)
3819
3820	/**
3821	* Virtual VM-exit information.
3822	*
3823	* This is a convenience structure that bundles some VM-exit information related
3824	* fields together.
3825	*/
3826	typedef struct
3827	{
3828	/** The VM-exit reason. */
3829	uint32_t uReason;
3830	/** The VM-exit instruction length. */
3831	uint32_t cbInstr;
3832	/** The VM-exit instruction information. */
3833	VMXEXITINSTRINFO InstrInfo;
3834	/** The VM-exit instruction ID. */
3835	VMXINSTRID uInstrId;
3836
3837	/** The Exit qualification field. */
3838	uint64_t u64Qual;
3839	/** The Guest-linear address field. */
3840	uint64_t u64GuestLinearAddr;
3841	/** The Guest-physical address field. */
3842	uint64_t u64GuestPhysAddr;
3843	/** The guest pending-debug exceptions. */
3844	uint64_t u64GuestPendingDbgXcpts;
3845	/** The effective guest-linear address if @a InstrInfo indicates a memory-based
3846	* instruction VM-exit. */
3847	RTGCPTR GCPtrEffAddr;
3848	} VMXVEXITINFO;
3849	/** Pointer to the VMXVEXITINFO struct. */
3850	typedef VMXVEXITINFO *PVMXVEXITINFO;
3851	/** Pointer to a const VMXVEXITINFO struct. */
3852	typedef const VMXVEXITINFO *PCVMXVEXITINFO;
3853	AssertCompileMemberAlignment(VMXVEXITINFO, u64Qual, 8);
3854
3855	/**
3856	* Virtual VM-exit information for events.
3857	*
3858	* This is a convenience structure that bundles some event-based VM-exit information
3859	* related fields together that are not included in VMXVEXITINFO.
3860	*
3861	* This is kept as a separate structure and not included in VMXVEXITINFO, to make it
3862	* easier to distinguish that IEM VM-exit handlers will set one or more of the
3863	* following fields in the virtual VMCS. Including it in the VMXVEXITINFO will not
3864	* make it ovbious which fields may get set (or cleared).
3865	*/
3866	typedef struct
3867	{
3868	/** VM-exit interruption information. */
3869	uint32_t uExitIntInfo;
3870	/** VM-exit interruption error code. */
3871	uint32_t uExitIntErrCode;
3872	/** IDT-vectoring information. */
3873	uint32_t uIdtVectoringInfo;
3874	/** IDT-vectoring error code. */
3875	uint32_t uIdtVectoringErrCode;
3876	} VMXVEXITEVENTINFO;
3877	/** Pointer to the VMXVEXITEVENTINFO struct. */
3878	typedef VMXVEXITEVENTINFO *PVMXVEXITEVENTINFO;
3879	/** Pointer to a const VMXVEXITEVENTINFO struct. */
3880	typedef const VMXVEXITEVENTINFO *PCVMXVEXITEVENTINFO;
3881
3882	/**
3883	* Virtual VMCS.
3884	*
3885	* This is our custom format. Relevant fields from this VMCS will be merged into the
3886	* actual/shadow VMCS when we execute nested-guest code using hardware-assisted
3887	* VMX.
3888	*
3889	* The first 8 bytes must be in accordance with the Intel VT-x spec.
3890	* See Intel spec. 24.2 "Format of the VMCS Region".
3891	*
3892	* The offset and size of the VMCS state field (@a fVmcsState) is also fixed (not by
3893	* the Intel spec. but for our own requirements) as we use it to offset into guest
3894	* memory.
3895	*
3896	* Although the guest is supposed to access the VMCS only through the execution of
3897	* VMX instructions (VMREAD, VMWRITE etc.), since the VMCS may reside in guest
3898	* memory (e.g, active but not current VMCS), for saved-states compatibility, and
3899	* for teleportation purposes, any newly added fields should be added to the
3900	* appropriate reserved sections or at the end of the structure.
3901	*
3902	* We always treat natural-width fields as 64-bit in our implementation since
3903	* it's easier, allows for teleporation in the future and does not affect guest
3904	* software.
3905	*
3906	* @note Any fields that are added or modified here, make sure to update the
3907	* corresponding fields in IEM (g_aoffVmcsMap), the corresponding saved
3908	* state structure in CPUM (g_aVmxHwvirtVmcs) and bump the SSM version.
3909	* Also consider updating CPUMIsGuestVmxVmcsFieldValid and cpumR3InfoVmxVmcs.
3910	*/
3911	#pragma pack(1)
3912	typedef struct
3913	{
3914	/** @name Header.
3915	* @{
3916	*/
3917	VMXVMCSREVID u32VmcsRevId; /*< 0x000 - VMX VMCS revision identifier. /
3918	VMXABORT enmVmxAbort; /*< 0x004 - VMX-abort indicator. /
3919	uint8_t fVmcsState; /*< 0x008 - VMCS launch state, see VMX_V_VMCS_LAUNCH_STATE_XXX. /
3920	uint8_t au8Padding0[3]; /*< 0x009 - Reserved for future. /
3921	uint32_t au32Reserved0[12]; /*< 0x00c - Reserved for future. /
3922	/** @} */
3923
3924	/** @name Read-only fields.
3925	* @{ */
3926	/** 16-bit fields. */
3927	uint16_t u16Reserved0[14]; /*< 0x03c - Reserved for future. /
3928
3929	/** 32-bit fields. */
3930	uint32_t u32RoVmInstrError; /*< 0x058 - VM-instruction error. /
3931	uint32_t u32RoExitReason; /*< 0x05c - VM-exit reason. /
3932	uint32_t u32RoExitIntInfo; /*< 0x060 - VM-exit interruption information. /
3933	uint32_t u32RoExitIntErrCode; /*< 0x064 - VM-exit interruption error code. /
3934	uint32_t u32RoIdtVectoringInfo; /*< 0x068 - IDT-vectoring information. /
3935	uint32_t u32RoIdtVectoringErrCode; /*< 0x06c - IDT-vectoring error code. /
3936	uint32_t u32RoExitInstrLen; /*< 0x070 - VM-exit instruction length. /
3937	uint32_t u32RoExitInstrInfo; /*< 0x074 - VM-exit instruction information. /
3938	uint32_t au32RoReserved2[16]; /*< 0x078 - Reserved for future. /
3939
3940	/** 64-bit fields. */
3941	RTUINT64U u64RoGuestPhysAddr; /*< 0x0b8 - Guest-physical address. /
3942	RTUINT64U au64Reserved1[8]; /*< 0x0c0 - Reserved for future. /
3943
3944	/** Natural-width fields. */
3945	RTUINT64U u64RoExitQual; /*< 0x100 - Exit qualification. /
3946	RTUINT64U u64RoIoRcx; /*< 0x108 - I/O RCX. /
3947	RTUINT64U u64RoIoRsi; /*< 0x110 - I/O RSI. /
3948	RTUINT64U u64RoIoRdi; /*< 0x118 - I/O RDI. /
3949	RTUINT64U u64RoIoRip; /*< 0x120 - I/O RIP. /
3950	RTUINT64U u64RoGuestLinearAddr; /*< 0x128 - Guest-linear address. /
3951	RTUINT64U au64Reserved5[16]; /*< 0x130 - Reserved for future. /
3952	/** @} */
3953
3954	/** @name Control fields.
3955	* @{ */
3956	/** 16-bit fields. */
3957	uint16_t u16Vpid; /*< 0x1b0 - Virtual processor ID. /
3958	uint16_t u16PostIntNotifyVector; /*< 0x1b2 - Posted interrupt notify vector. /
3959	uint16_t u16EptpIndex; /*< 0x1b4 - EPTP index. /
3960	uint16_t au16Reserved0[13]; /*< 0x1b6 - Reserved for future. /
3961
3962	/** 32-bit fields. */
3963	uint32_t u32PinCtls; /*< 0x1d0 - Pin-based VM-execution controls. /
3964	uint32_t u32ProcCtls; /*< 0x1d4 - Processor-based VM-execution controls. /
3965	uint32_t u32XcptBitmap; /*< 0x1d8 - Exception bitmap. /
3966	uint32_t u32XcptPFMask; /*< 0x1dc - Page-fault exception error mask. /
3967	uint32_t u32XcptPFMatch; /*< 0x1e0 - Page-fault exception error match. /
3968	uint32_t u32Cr3TargetCount; /*< 0x1e4 - CR3-target count. /
3969	uint32_t u32ExitCtls; /*< 0x1e8 - VM-exit controls. /
3970	uint32_t u32ExitMsrStoreCount; /*< 0x1ec - VM-exit MSR store count. /
3971	uint32_t u32ExitMsrLoadCount; /*< 0x1f0 - VM-exit MSR load count. /
3972	uint32_t u32EntryCtls; /*< 0x1f4 - VM-entry controls. /
3973	uint32_t u32EntryMsrLoadCount; /*< 0x1f8 - VM-entry MSR load count. /
3974	uint32_t u32EntryIntInfo; /*< 0x1fc - VM-entry interruption information. /
3975	uint32_t u32EntryXcptErrCode; /*< 0x200 - VM-entry exception error code. /
3976	uint32_t u32EntryInstrLen; /*< 0x204 - VM-entry instruction length. /
3977	uint32_t u32TprThreshold; /*< 0x208 - TPR-threshold. /
3978	uint32_t u32ProcCtls2; /*< 0x20c - Secondary-processor based VM-execution controls. /
3979	uint32_t u32PleGap; /*< 0x210 - Pause-loop exiting Gap. /
3980	uint32_t u32PleWindow; /*< 0x214 - Pause-loop exiting Window. /
3981	uint32_t au32Reserved1[16]; /*< 0x218 - Reserved for future. /
3982
3983	/** 64-bit fields. */
3984	RTUINT64U u64AddrIoBitmapA; /*< 0x258 - I/O bitmap A address. /
3985	RTUINT64U u64AddrIoBitmapB; /*< 0x260 - I/O bitmap B address. /
3986	RTUINT64U u64AddrMsrBitmap; /*< 0x268 - MSR bitmap address. /
3987	RTUINT64U u64AddrExitMsrStore; /*< 0x270 - VM-exit MSR-store area address. /
3988	RTUINT64U u64AddrExitMsrLoad; /*< 0x278 - VM-exit MSR-load area address. /
3989	RTUINT64U u64AddrEntryMsrLoad; /*< 0x280 - VM-entry MSR-load area address. /
3990	RTUINT64U u64ExecVmcsPtr; /*< 0x288 - Executive-VMCS pointer. /
3991	RTUINT64U u64AddrPml; /*< 0x290 - Page-modification log address (PML). /
3992	RTUINT64U u64TscOffset; /*< 0x298 - TSC offset. /
3993	RTUINT64U u64AddrVirtApic; /*< 0x2a0 - Virtual-APIC address. /
3994	RTUINT64U u64AddrApicAccess; /*< 0x2a8 - APIC-access address. /
3995	RTUINT64U u64AddrPostedIntDesc; /*< 0x2b0 - Posted-interrupt descriptor address. /
3996	RTUINT64U u64VmFuncCtls; /*< 0x2b8 - VM-functions control. /
3997	RTUINT64U u64EptPtr; /*< 0x2c0 - EPT pointer. /
3998	RTUINT64U u64EoiExitBitmap0; /*< 0x2c8 - EOI-exit bitmap 0. /
3999	RTUINT64U u64EoiExitBitmap1; /*< 0x2d0 - EOI-exit bitmap 1. /
4000	RTUINT64U u64EoiExitBitmap2; /*< 0x2d8 - EOI-exit bitmap 2. /
4001	RTUINT64U u64EoiExitBitmap3; /*< 0x2e0 - EOI-exit bitmap 3. /
4002	RTUINT64U u64AddrEptpList; /*< 0x2e8 - EPTP-list address. /
4003	RTUINT64U u64AddrVmreadBitmap; /*< 0x2f0 - VMREAD-bitmap address. /
4004	RTUINT64U u64AddrVmwriteBitmap; /*< 0x2f8 - VMWRITE-bitmap address. /
4005	RTUINT64U u64AddrXcptVeInfo; /*< 0x300 - Virtualization-exception information address. /
4006	RTUINT64U u64XssExitBitmap; /*< 0x308 - XSS-exiting bitmap. /
4007	RTUINT64U u64EnclsExitBitmap; /*< 0x310 - ENCLS-exiting bitmap address. /
4008	RTUINT64U u64SppTablePtr; /*< 0x318 - Sub-page-permission-table pointer (SPPTP). /
4009	RTUINT64U u64TscMultiplier; /*< 0x320 - TSC multiplier. /
4010	RTUINT64U u64ProcCtls3; /*< 0x328 - Tertiary-Processor based VM-execution controls. /
4011	RTUINT64U u64EnclvExitBitmap; /*< 0x330 - ENCLV-exiting bitmap. /
4012	RTUINT64U au64Reserved0[13]; /*< 0x338 - Reserved for future. /
4013
4014	/** Natural-width fields. */
4015	RTUINT64U u64Cr0Mask; /*< 0x3a0 - CR0 guest/host Mask. /
4016	RTUINT64U u64Cr4Mask; /*< 0x3a8 - CR4 guest/host Mask. /
4017	RTUINT64U u64Cr0ReadShadow; /*< 0x3b0 - CR0 read shadow. /
4018	RTUINT64U u64Cr4ReadShadow; /*< 0x3b8 - CR4 read shadow. /
4019	RTUINT64U u64Cr3Target0; /*< 0x3c0 - CR3-target value 0. /
4020	RTUINT64U u64Cr3Target1; /*< 0x3c8 - CR3-target value 1. /
4021	RTUINT64U u64Cr3Target2; /*< 0x3d0 - CR3-target value 2. /
4022	RTUINT64U u64Cr3Target3; /*< 0x3d8 - CR3-target value 3. /
4023	RTUINT64U au64Reserved4[32]; /*< 0x3e0 - Reserved for future. /
4024	/** @} */
4025
4026	/** @name Host-state fields.
4027	* @{ */
4028	/** 16-bit fields. */
4029	/* Order of [Es..Gs] fields below must match [X86_SREG_ES..X86_SREG_GS]. */
4030	RTSEL HostEs; /*< 0x4e0 - Host ES selector. /
4031	RTSEL HostCs; /*< 0x4e2 - Host CS selector. /
4032	RTSEL HostSs; /*< 0x4e4 - Host SS selector. /
4033	RTSEL HostDs; /*< 0x4e6 - Host DS selector. /
4034	RTSEL HostFs; /*< 0x4e8 - Host FS selector. /
4035	RTSEL HostGs; /*< 0x4ea - Host GS selector. /
4036	RTSEL HostTr; /*< 0x4ec - Host TR selector. /
4037	uint16_t au16Reserved2[13]; /*< 0x4ee - Reserved for future. /
4038
4039	/** 32-bit fields. */
4040	uint32_t u32HostSysenterCs; /*< 0x508 - Host SYSENTER CS. /
4041	uint32_t au32Reserved4[11]; /*< 0x50c - Reserved for future. /
4042
4043	/** 64-bit fields. */
4044	RTUINT64U u64HostPatMsr; /*< 0x538 - Host PAT MSR. /
4045	RTUINT64U u64HostEferMsr; /*< 0x540 - Host EFER MSR. /
4046	RTUINT64U u64HostPerfGlobalCtlMsr; /*< 0x548 - Host global performance-control MSR. /
4047	RTUINT64U u64HostPkrsMsr; /*< 0x550 - Host PKRS MSR. /
4048	RTUINT64U au64Reserved3[15]; /*< 0x558 - Reserved for future. /
4049
4050	/** Natural-width fields. */
4051	RTUINT64U u64HostCr0; /*< 0x5d0 - Host CR0. /
4052	RTUINT64U u64HostCr3; /*< 0x5d8 - Host CR3. /
4053	RTUINT64U u64HostCr4; /*< 0x5e0 - Host CR4. /
4054	RTUINT64U u64HostFsBase; /*< 0x5e8 - Host FS base. /
4055	RTUINT64U u64HostGsBase; /*< 0x5f0 - Host GS base. /
4056	RTUINT64U u64HostTrBase; /*< 0x5f8 - Host TR base. /
4057	RTUINT64U u64HostGdtrBase; /*< 0x600 - Host GDTR base. /
4058	RTUINT64U u64HostIdtrBase; /*< 0x608 - Host IDTR base. /
4059	RTUINT64U u64HostSysenterEsp; /*< 0x610 - Host SYSENTER ESP base. /
4060	RTUINT64U u64HostSysenterEip; /*< 0x618 - Host SYSENTER ESP base. /
4061	RTUINT64U u64HostRsp; /*< 0x620 - Host RSP. /
4062	RTUINT64U u64HostRip; /*< 0x628 - Host RIP. /
4063	RTUINT64U u64HostSCetMsr; /*< 0x630 - Host S_CET MSR. /
4064	RTUINT64U u64HostSsp; /*< 0x638 - Host SSP. /
4065	RTUINT64U u64HostIntrSspTableAddrMsr; /*< 0x640 - Host Interrupt SSP table address MSR. /
4066	RTUINT64U au64Reserved7[29]; /*< 0x648 - Reserved for future. /
4067	/** @} */
4068
4069	/** @name Guest-state fields.
4070	* @{ */
4071	/** 16-bit fields. */
4072	/* Order of [Es..Gs] fields below must match [X86_SREG_ES..X86_SREG_GS]. */
4073	RTSEL GuestEs; /*< 0x730 - Guest ES selector. /
4074	RTSEL GuestCs; /*< 0x732 - Guest ES selector. /
4075	RTSEL GuestSs; /*< 0x734 - Guest ES selector. /
4076	RTSEL GuestDs; /*< 0x736 - Guest ES selector. /
4077	RTSEL GuestFs; /*< 0x738 - Guest ES selector. /
4078	RTSEL GuestGs; /*< 0x73a - Guest ES selector. /
4079	RTSEL GuestLdtr; /*< 0x73c - Guest LDTR selector. /
4080	RTSEL GuestTr; /*< 0x73e - Guest TR selector. /
4081	uint16_t u16GuestIntStatus; /*< 0x740 - Guest interrupt status (virtual-interrupt delivery). /
4082	uint16_t u16PmlIndex; /*< 0x742 - PML index. /
4083	uint16_t au16Reserved1[14]; /*< 0x744 - Reserved for future. /
4084
4085	/** 32-bit fields. */
4086	/* Order of [Es..Gs] fields below must match [X86_SREG_ES..X86_SREG_GS]. */
4087	uint32_t u32GuestEsLimit; /*< 0x760 - Guest ES limit. /
4088	uint32_t u32GuestCsLimit; /*< 0x764 - Guest CS limit. /
4089	uint32_t u32GuestSsLimit; /*< 0x768 - Guest SS limit. /
4090	uint32_t u32GuestDsLimit; /*< 0x76c - Guest DS limit. /
4091	uint32_t u32GuestFsLimit; /*< 0x770 - Guest FS limit. /
4092	uint32_t u32GuestGsLimit; /*< 0x774 - Guest GS limit. /
4093	uint32_t u32GuestLdtrLimit; /*< 0x778 - Guest LDTR limit. /
4094	uint32_t u32GuestTrLimit; /*< 0x77c - Guest TR limit. /
4095	uint32_t u32GuestGdtrLimit; /*< 0x780 - Guest GDTR limit. /
4096	uint32_t u32GuestIdtrLimit; /*< 0x784 - Guest IDTR limit. /
4097	uint32_t u32GuestEsAttr; /*< 0x788 - Guest ES attributes. /
4098	uint32_t u32GuestCsAttr; /*< 0x78c - Guest CS attributes. /
4099	uint32_t u32GuestSsAttr; /*< 0x790 - Guest SS attributes. /
4100	uint32_t u32GuestDsAttr; /*< 0x794 - Guest DS attributes. /
4101	uint32_t u32GuestFsAttr; /*< 0x798 - Guest FS attributes. /
4102	uint32_t u32GuestGsAttr; /*< 0x79c - Guest GS attributes. /
4103	uint32_t u32GuestLdtrAttr; /*< 0x7a0 - Guest LDTR attributes. /
4104	uint32_t u32GuestTrAttr; /*< 0x7a4 - Guest TR attributes. /
4105	uint32_t u32GuestIntrState; /*< 0x7a8 - Guest interruptibility state. /
4106	uint32_t u32GuestActivityState; /*< 0x7ac - Guest activity state. /
4107	uint32_t u32GuestSmBase; /*< 0x7b0 - Guest SMBASE. /
4108	uint32_t u32GuestSysenterCS; /*< 0x7b4 - Guest SYSENTER CS. /
4109	uint32_t u32PreemptTimer; /*< 0x7b8 - Preemption timer value. /
4110	uint32_t au32Reserved3[11]; /*< 0x7bc - Reserved for future. /
4111
4112	/** 64-bit fields. */
4113	RTUINT64U u64VmcsLinkPtr; /*< 0x7e8 - VMCS link pointer. /
4114	RTUINT64U u64GuestDebugCtlMsr; /*< 0x7f0 - Guest debug-control MSR. /
4115	RTUINT64U u64GuestPatMsr; /*< 0x7f8 - Guest PAT MSR. /
4116	RTUINT64U u64GuestEferMsr; /*< 0x800 - Guest EFER MSR. /
4117	RTUINT64U u64GuestPerfGlobalCtlMsr; /*< 0x808 - Guest global performance-control MSR. /
4118	RTUINT64U u64GuestPdpte0; /*< 0x810 - Guest PDPTE 0. /
4119	RTUINT64U u64GuestPdpte1; /*< 0x818 - Guest PDPTE 0. /
4120	RTUINT64U u64GuestPdpte2; /*< 0x820 - Guest PDPTE 1. /
4121	RTUINT64U u64GuestPdpte3; /*< 0x828 - Guest PDPTE 2. /
4122	RTUINT64U u64GuestBndcfgsMsr; /*< 0x830 - Guest Bounds config MPX MSR (Intel Memory Protection Extensions). /
4123	RTUINT64U u64GuestRtitCtlMsr; /*< 0x838 - Guest RTIT control MSR (Intel Real Time Instruction Trace). /
4124	RTUINT64U u64GuestPkrsMsr; /*< 0x840 - Guest PKRS MSR. /
4125	RTUINT64U au64Reserved2[31]; /*< 0x848 - Reserved for future. /
4126
4127	/** Natural-width fields. */
4128	RTUINT64U u64GuestCr0; /*< 0x940 - Guest CR0. /
4129	RTUINT64U u64GuestCr3; /*< 0x948 - Guest CR3. /
4130	RTUINT64U u64GuestCr4; /*< 0x950 - Guest CR4. /
4131	RTUINT64U u64GuestEsBase; /*< 0x958 - Guest ES base. /
4132	RTUINT64U u64GuestCsBase; /*< 0x960 - Guest CS base. /
4133	RTUINT64U u64GuestSsBase; /*< 0x968 - Guest SS base. /
4134	RTUINT64U u64GuestDsBase; /*< 0x970 - Guest DS base. /
4135	RTUINT64U u64GuestFsBase; /*< 0x978 - Guest FS base. /
4136	RTUINT64U u64GuestGsBase; /*< 0x980 - Guest GS base. /
4137	RTUINT64U u64GuestLdtrBase; /*< 0x988 - Guest LDTR base. /
4138	RTUINT64U u64GuestTrBase; /*< 0x990 - Guest TR base. /
4139	RTUINT64U u64GuestGdtrBase; /*< 0x998 - Guest GDTR base. /
4140	RTUINT64U u64GuestIdtrBase; /*< 0x9a0 - Guest IDTR base. /
4141	RTUINT64U u64GuestDr7; /*< 0x9a8 - Guest DR7. /
4142	RTUINT64U u64GuestRsp; /*< 0x9b0 - Guest RSP. /
4143	RTUINT64U u64GuestRip; /*< 0x9b8 - Guest RIP. /
4144	RTUINT64U u64GuestRFlags; /*< 0x9c0 - Guest RFLAGS. /
4145	RTUINT64U u64GuestPendingDbgXcpts; /*< 0x9c8 - Guest pending debug exceptions. /
4146	RTUINT64U u64GuestSysenterEsp; /*< 0x9d0 - Guest SYSENTER ESP. /
4147	RTUINT64U u64GuestSysenterEip; /*< 0x9d8 - Guest SYSENTER EIP. /
4148	RTUINT64U u64GuestSCetMsr; /*< 0x9e0 - Guest S_CET MSR. /
4149	RTUINT64U u64GuestSsp; /*< 0x9e8 - Guest SSP. /
4150	RTUINT64U u64GuestIntrSspTableAddrMsr; /*< 0x9f0 - Guest Interrupt SSP table address MSR. /
4151	RTUINT64U au64Reserved6[29]; /*< 0x9f8 - Reserved for future. /
4152	/** @} */
4153
4154	/** 0xae0 - Padding / reserved for future use. */
4155	uint8_t abPadding[X86_PAGE_4K_SIZE - 0xae0];
4156	} VMXVVMCS;
4157	#pragma pack()
4158	/** Pointer to the VMXVVMCS struct. */
4159	typedef VMXVVMCS *PVMXVVMCS;
4160	/** Pointer to a const VMXVVMCS struct. */
4161	typedef const VMXVVMCS *PCVMXVVMCS;
4162	AssertCompileSize(VMXVVMCS, X86_PAGE_4K_SIZE);
4163	AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(uint8_t));
4164	AssertCompileMemberOffset(VMXVVMCS, enmVmxAbort, 0x004);
4165	AssertCompileMemberOffset(VMXVVMCS, fVmcsState, 0x008);
4166	AssertCompileMemberOffset(VMXVVMCS, u32RoVmInstrError, 0x058);
4167	AssertCompileMemberOffset(VMXVVMCS, u64RoGuestPhysAddr, 0x0b8);
4168	AssertCompileMemberOffset(VMXVVMCS, u64RoExitQual, 0x100);
4169	AssertCompileMemberOffset(VMXVVMCS, u16Vpid, 0x1b0);
4170	AssertCompileMemberOffset(VMXVVMCS, u32PinCtls, 0x1d0);
4171	AssertCompileMemberOffset(VMXVVMCS, u64AddrIoBitmapA, 0x258);
4172	AssertCompileMemberOffset(VMXVVMCS, u64Cr0Mask, 0x3a0);
4173	AssertCompileMemberOffset(VMXVVMCS, HostEs, 0x4e0);
4174	AssertCompileMemberOffset(VMXVVMCS, u32HostSysenterCs, 0x508);
4175	AssertCompileMemberOffset(VMXVVMCS, u64HostPatMsr, 0x538);
4176	AssertCompileMemberOffset(VMXVVMCS, u64HostCr0, 0x5d0);
4177	AssertCompileMemberOffset(VMXVVMCS, GuestEs, 0x730);
4178	AssertCompileMemberOffset(VMXVVMCS, u32GuestEsLimit, 0x760);
4179	AssertCompileMemberOffset(VMXVVMCS, u64VmcsLinkPtr, 0x7e8);
4180	AssertCompileMemberOffset(VMXVVMCS, u64GuestCr0, 0x940);
4181
4182	/**
4183	* Virtual VMX-instruction and VM-exit diagnostics.
4184	*
4185	* These are not the same as VM instruction errors that are enumerated in the Intel
4186	* spec. These are purely internal, fine-grained definitions used for diagnostic
4187	* purposes and are not reported to guest software under the VM-instruction error
4188	* field in its VMCS.
4189	*
4190	* @note Members of this enum are used as array indices, so no gaps are allowed.
4191	* Please update g_apszVmxVDiagDesc when you add new fields to this enum.
4192	*/
4193	typedef enum
4194	{
4195	/* Internal processing errors. */
4196	kVmxVDiag_None = 0,
4197	kVmxVDiag_Ipe_1,
4198	kVmxVDiag_Ipe_2,
4199	kVmxVDiag_Ipe_3,
4200	kVmxVDiag_Ipe_4,
4201	kVmxVDiag_Ipe_5,
4202	kVmxVDiag_Ipe_6,
4203	kVmxVDiag_Ipe_7,
4204	kVmxVDiag_Ipe_8,
4205	kVmxVDiag_Ipe_9,
4206	kVmxVDiag_Ipe_10,
4207	kVmxVDiag_Ipe_11,
4208	kVmxVDiag_Ipe_12,
4209	kVmxVDiag_Ipe_13,
4210	kVmxVDiag_Ipe_14,
4211	kVmxVDiag_Ipe_15,
4212	kVmxVDiag_Ipe_16,
4213	/* VMXON. */
4214	kVmxVDiag_Vmxon_A20M,
4215	kVmxVDiag_Vmxon_Cpl,
4216	kVmxVDiag_Vmxon_Cr0Fixed0,
4217	kVmxVDiag_Vmxon_Cr0Fixed1,
4218	kVmxVDiag_Vmxon_Cr4Fixed0,
4219	kVmxVDiag_Vmxon_Cr4Fixed1,
4220	kVmxVDiag_Vmxon_Intercept,
4221	kVmxVDiag_Vmxon_LongModeCS,
4222	kVmxVDiag_Vmxon_MsrFeatCtl,
4223	kVmxVDiag_Vmxon_PtrAbnormal,
4224	kVmxVDiag_Vmxon_PtrAlign,
4225	kVmxVDiag_Vmxon_PtrMap,
4226	kVmxVDiag_Vmxon_PtrReadPhys,
4227	kVmxVDiag_Vmxon_PtrWidth,
4228	kVmxVDiag_Vmxon_RealOrV86Mode,
4229	kVmxVDiag_Vmxon_ShadowVmcs,
4230	kVmxVDiag_Vmxon_VmxAlreadyRoot,
4231	kVmxVDiag_Vmxon_Vmxe,
4232	kVmxVDiag_Vmxon_VmcsRevId,
4233	kVmxVDiag_Vmxon_VmxRootCpl,
4234	/* VMXOFF. */
4235	kVmxVDiag_Vmxoff_Cpl,
4236	kVmxVDiag_Vmxoff_Intercept,
4237	kVmxVDiag_Vmxoff_LongModeCS,
4238	kVmxVDiag_Vmxoff_RealOrV86Mode,
4239	kVmxVDiag_Vmxoff_Vmxe,
4240	kVmxVDiag_Vmxoff_VmxRoot,
4241	/* VMPTRLD. */
4242	kVmxVDiag_Vmptrld_Cpl,
4243	kVmxVDiag_Vmptrld_LongModeCS,
4244	kVmxVDiag_Vmptrld_PtrAbnormal,
4245	kVmxVDiag_Vmptrld_PtrAlign,
4246	kVmxVDiag_Vmptrld_PtrMap,
4247	kVmxVDiag_Vmptrld_PtrReadPhys,
4248	kVmxVDiag_Vmptrld_PtrVmxon,
4249	kVmxVDiag_Vmptrld_PtrWidth,
4250	kVmxVDiag_Vmptrld_RealOrV86Mode,
4251	kVmxVDiag_Vmptrld_RevPtrReadPhys,
4252	kVmxVDiag_Vmptrld_ShadowVmcs,
4253	kVmxVDiag_Vmptrld_VmcsRevId,
4254	kVmxVDiag_Vmptrld_VmxRoot,
4255	/* VMPTRST. */
4256	kVmxVDiag_Vmptrst_Cpl,
4257	kVmxVDiag_Vmptrst_LongModeCS,
4258	kVmxVDiag_Vmptrst_PtrMap,
4259	kVmxVDiag_Vmptrst_RealOrV86Mode,
4260	kVmxVDiag_Vmptrst_VmxRoot,
4261	/* VMCLEAR. */
4262	kVmxVDiag_Vmclear_Cpl,
4263	kVmxVDiag_Vmclear_LongModeCS,
4264	kVmxVDiag_Vmclear_PtrAbnormal,
4265	kVmxVDiag_Vmclear_PtrAlign,
4266	kVmxVDiag_Vmclear_PtrMap,
4267	kVmxVDiag_Vmclear_PtrReadPhys,
4268	kVmxVDiag_Vmclear_PtrVmxon,
4269	kVmxVDiag_Vmclear_PtrWidth,
4270	kVmxVDiag_Vmclear_RealOrV86Mode,
4271	kVmxVDiag_Vmclear_VmxRoot,
4272	/* VMWRITE. */
4273	kVmxVDiag_Vmwrite_Cpl,
4274	kVmxVDiag_Vmwrite_FieldInvalid,
4275	kVmxVDiag_Vmwrite_FieldRo,
4276	kVmxVDiag_Vmwrite_LinkPtrInvalid,
4277	kVmxVDiag_Vmwrite_LongModeCS,
4278	kVmxVDiag_Vmwrite_PtrInvalid,
4279	kVmxVDiag_Vmwrite_PtrMap,
4280	kVmxVDiag_Vmwrite_RealOrV86Mode,
4281	kVmxVDiag_Vmwrite_VmxRoot,
4282	/* VMREAD. */
4283	kVmxVDiag_Vmread_Cpl,
4284	kVmxVDiag_Vmread_FieldInvalid,
4285	kVmxVDiag_Vmread_LinkPtrInvalid,
4286	kVmxVDiag_Vmread_LongModeCS,
4287	kVmxVDiag_Vmread_PtrInvalid,
4288	kVmxVDiag_Vmread_PtrMap,
4289	kVmxVDiag_Vmread_RealOrV86Mode,
4290	kVmxVDiag_Vmread_VmxRoot,
4291	/* INVVPID. */
4292	kVmxVDiag_Invvpid_Cpl,
4293	kVmxVDiag_Invvpid_DescRsvd,
4294	kVmxVDiag_Invvpid_LongModeCS,
4295	kVmxVDiag_Invvpid_RealOrV86Mode,
4296	kVmxVDiag_Invvpid_TypeInvalid,
4297	kVmxVDiag_Invvpid_Type0InvalidAddr,
4298	kVmxVDiag_Invvpid_Type0InvalidVpid,
4299	kVmxVDiag_Invvpid_Type1InvalidVpid,
4300	kVmxVDiag_Invvpid_Type3InvalidVpid,
4301	kVmxVDiag_Invvpid_VmxRoot,
4302	/* INVEPT. */
4303	kVmxVDiag_Invept_Cpl,
4304	kVmxVDiag_Invept_DescRsvd,
4305	kVmxVDiag_Invept_EptpInvalid,
4306	kVmxVDiag_Invept_LongModeCS,
4307	kVmxVDiag_Invept_RealOrV86Mode,
4308	kVmxVDiag_Invept_TypeInvalid,
4309	kVmxVDiag_Invept_VmxRoot,
4310	/* VMLAUNCH/VMRESUME. */
4311	kVmxVDiag_Vmentry_AddrApicAccess,
4312	kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic,
4313	kVmxVDiag_Vmentry_AddrApicAccessHandlerReg,
4314	kVmxVDiag_Vmentry_AddrEntryMsrLoad,
4315	kVmxVDiag_Vmentry_AddrExitMsrLoad,
4316	kVmxVDiag_Vmentry_AddrExitMsrStore,
4317	kVmxVDiag_Vmentry_AddrIoBitmapA,
4318	kVmxVDiag_Vmentry_AddrIoBitmapB,
4319	kVmxVDiag_Vmentry_AddrMsrBitmap,
4320	kVmxVDiag_Vmentry_AddrVirtApicPage,
4321	kVmxVDiag_Vmentry_AddrVmcsLinkPtr,
4322	kVmxVDiag_Vmentry_AddrVmreadBitmap,
4323	kVmxVDiag_Vmentry_AddrVmwriteBitmap,
4324	kVmxVDiag_Vmentry_ApicRegVirt,
4325	kVmxVDiag_Vmentry_BlocKMovSS,
4326	kVmxVDiag_Vmentry_Cpl,
4327	kVmxVDiag_Vmentry_Cr3TargetCount,
4328	kVmxVDiag_Vmentry_EntryCtlsAllowed1,
4329	kVmxVDiag_Vmentry_EntryCtlsDisallowed0,
4330	kVmxVDiag_Vmentry_EntryInstrLen,
4331	kVmxVDiag_Vmentry_EntryInstrLenZero,
4332	kVmxVDiag_Vmentry_EntryIntInfoErrCodePe,
4333	kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec,
4334	kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd,
4335	kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd,
4336	kVmxVDiag_Vmentry_EptpAccessDirty,
4337	kVmxVDiag_Vmentry_EptpPageWalkLength,
4338	kVmxVDiag_Vmentry_EptpMemType,
4339	kVmxVDiag_Vmentry_EptpRsvd,
4340	kVmxVDiag_Vmentry_ExitCtlsAllowed1,
4341	kVmxVDiag_Vmentry_ExitCtlsDisallowed0,
4342	kVmxVDiag_Vmentry_GuestActStateHlt,
4343	kVmxVDiag_Vmentry_GuestActStateRsvd,
4344	kVmxVDiag_Vmentry_GuestActStateShutdown,
4345	kVmxVDiag_Vmentry_GuestActStateSsDpl,
4346	kVmxVDiag_Vmentry_GuestActStateStiMovSs,
4347	kVmxVDiag_Vmentry_GuestCr0Fixed0,
4348	kVmxVDiag_Vmentry_GuestCr0Fixed1,
4349	kVmxVDiag_Vmentry_GuestCr0PgPe,
4350	kVmxVDiag_Vmentry_GuestCr3,
4351	kVmxVDiag_Vmentry_GuestCr4Fixed0,
4352	kVmxVDiag_Vmentry_GuestCr4Fixed1,
4353	kVmxVDiag_Vmentry_GuestDebugCtl,
4354	kVmxVDiag_Vmentry_GuestDr7,
4355	kVmxVDiag_Vmentry_GuestEferMsr,
4356	kVmxVDiag_Vmentry_GuestEferMsrRsvd,
4357	kVmxVDiag_Vmentry_GuestGdtrBase,
4358	kVmxVDiag_Vmentry_GuestGdtrLimit,
4359	kVmxVDiag_Vmentry_GuestIdtrBase,
4360	kVmxVDiag_Vmentry_GuestIdtrLimit,
4361	kVmxVDiag_Vmentry_GuestIntStateEnclave,
4362	kVmxVDiag_Vmentry_GuestIntStateExtInt,
4363	kVmxVDiag_Vmentry_GuestIntStateNmi,
4364	kVmxVDiag_Vmentry_GuestIntStateRFlagsSti,
4365	kVmxVDiag_Vmentry_GuestIntStateRsvd,
4366	kVmxVDiag_Vmentry_GuestIntStateSmi,
4367	kVmxVDiag_Vmentry_GuestIntStateStiMovSs,
4368	kVmxVDiag_Vmentry_GuestIntStateVirtNmi,
4369	kVmxVDiag_Vmentry_GuestPae,
4370	kVmxVDiag_Vmentry_GuestPatMsr,
4371	kVmxVDiag_Vmentry_GuestPcide,
4372	kVmxVDiag_Vmentry_GuestPdpte,
4373	kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf,
4374	kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf,
4375	kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd,
4376	kVmxVDiag_Vmentry_GuestPndDbgXcptRtm,
4377	kVmxVDiag_Vmentry_GuestRip,
4378	kVmxVDiag_Vmentry_GuestRipRsvd,
4379	kVmxVDiag_Vmentry_GuestRFlagsIf,
4380	kVmxVDiag_Vmentry_GuestRFlagsRsvd,
4381	kVmxVDiag_Vmentry_GuestRFlagsVm,
4382	kVmxVDiag_Vmentry_GuestSegAttrCsDefBig,
4383	kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs,
4384	kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs,
4385	kVmxVDiag_Vmentry_GuestSegAttrCsDplZero,
4386	kVmxVDiag_Vmentry_GuestSegAttrCsType,
4387	kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead,
4388	kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs,
4389	kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs,
4390	kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs,
4391	kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs,
4392	kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs,
4393	kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs,
4394	kVmxVDiag_Vmentry_GuestSegAttrDplRplCs,
4395	kVmxVDiag_Vmentry_GuestSegAttrDplRplDs,
4396	kVmxVDiag_Vmentry_GuestSegAttrDplRplEs,
4397	kVmxVDiag_Vmentry_GuestSegAttrDplRplFs,
4398	kVmxVDiag_Vmentry_GuestSegAttrDplRplGs,
4399	kVmxVDiag_Vmentry_GuestSegAttrDplRplSs,
4400	kVmxVDiag_Vmentry_GuestSegAttrGranCs,
4401	kVmxVDiag_Vmentry_GuestSegAttrGranDs,
4402	kVmxVDiag_Vmentry_GuestSegAttrGranEs,
4403	kVmxVDiag_Vmentry_GuestSegAttrGranFs,
4404	kVmxVDiag_Vmentry_GuestSegAttrGranGs,
4405	kVmxVDiag_Vmentry_GuestSegAttrGranSs,
4406	kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType,
4407	kVmxVDiag_Vmentry_GuestSegAttrLdtrGran,
4408	kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent,
4409	kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd,
4410	kVmxVDiag_Vmentry_GuestSegAttrLdtrType,
4411	kVmxVDiag_Vmentry_GuestSegAttrPresentCs,
4412	kVmxVDiag_Vmentry_GuestSegAttrPresentDs,
4413	kVmxVDiag_Vmentry_GuestSegAttrPresentEs,
4414	kVmxVDiag_Vmentry_GuestSegAttrPresentFs,
4415	kVmxVDiag_Vmentry_GuestSegAttrPresentGs,
4416	kVmxVDiag_Vmentry_GuestSegAttrPresentSs,
4417	kVmxVDiag_Vmentry_GuestSegAttrRsvdCs,
4418	kVmxVDiag_Vmentry_GuestSegAttrRsvdDs,
4419	kVmxVDiag_Vmentry_GuestSegAttrRsvdEs,
4420	kVmxVDiag_Vmentry_GuestSegAttrRsvdFs,
4421	kVmxVDiag_Vmentry_GuestSegAttrRsvdGs,
4422	kVmxVDiag_Vmentry_GuestSegAttrRsvdSs,
4423	kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl,
4424	kVmxVDiag_Vmentry_GuestSegAttrSsDplZero,
4425	kVmxVDiag_Vmentry_GuestSegAttrSsType,
4426	kVmxVDiag_Vmentry_GuestSegAttrTrDescType,
4427	kVmxVDiag_Vmentry_GuestSegAttrTrGran,
4428	kVmxVDiag_Vmentry_GuestSegAttrTrPresent,
4429	kVmxVDiag_Vmentry_GuestSegAttrTrRsvd,
4430	kVmxVDiag_Vmentry_GuestSegAttrTrType,
4431	kVmxVDiag_Vmentry_GuestSegAttrTrUnusable,
4432	kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs,
4433	kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs,
4434	kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs,
4435	kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs,
4436	kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs,
4437	kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs,
4438	kVmxVDiag_Vmentry_GuestSegAttrV86Cs,
4439	kVmxVDiag_Vmentry_GuestSegAttrV86Ds,
4440	kVmxVDiag_Vmentry_GuestSegAttrV86Es,
4441	kVmxVDiag_Vmentry_GuestSegAttrV86Fs,
4442	kVmxVDiag_Vmentry_GuestSegAttrV86Gs,
4443	kVmxVDiag_Vmentry_GuestSegAttrV86Ss,
4444	kVmxVDiag_Vmentry_GuestSegBaseCs,
4445	kVmxVDiag_Vmentry_GuestSegBaseDs,
4446	kVmxVDiag_Vmentry_GuestSegBaseEs,
4447	kVmxVDiag_Vmentry_GuestSegBaseFs,
4448	kVmxVDiag_Vmentry_GuestSegBaseGs,
4449	kVmxVDiag_Vmentry_GuestSegBaseLdtr,
4450	kVmxVDiag_Vmentry_GuestSegBaseSs,
4451	kVmxVDiag_Vmentry_GuestSegBaseTr,
4452	kVmxVDiag_Vmentry_GuestSegBaseV86Cs,
4453	kVmxVDiag_Vmentry_GuestSegBaseV86Ds,
4454	kVmxVDiag_Vmentry_GuestSegBaseV86Es,
4455	kVmxVDiag_Vmentry_GuestSegBaseV86Fs,
4456	kVmxVDiag_Vmentry_GuestSegBaseV86Gs,
4457	kVmxVDiag_Vmentry_GuestSegBaseV86Ss,
4458	kVmxVDiag_Vmentry_GuestSegLimitV86Cs,
4459	kVmxVDiag_Vmentry_GuestSegLimitV86Ds,
4460	kVmxVDiag_Vmentry_GuestSegLimitV86Es,
4461	kVmxVDiag_Vmentry_GuestSegLimitV86Fs,
4462	kVmxVDiag_Vmentry_GuestSegLimitV86Gs,
4463	kVmxVDiag_Vmentry_GuestSegLimitV86Ss,
4464	kVmxVDiag_Vmentry_GuestSegSelCsSsRpl,
4465	kVmxVDiag_Vmentry_GuestSegSelLdtr,
4466	kVmxVDiag_Vmentry_GuestSegSelTr,
4467	kVmxVDiag_Vmentry_GuestSysenterEspEip,
4468	kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs,
4469	kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys,
4470	kVmxVDiag_Vmentry_VmcsLinkPtrRevId,
4471	kVmxVDiag_Vmentry_VmcsLinkPtrShadow,
4472	kVmxVDiag_Vmentry_HostCr0Fixed0,
4473	kVmxVDiag_Vmentry_HostCr0Fixed1,
4474	kVmxVDiag_Vmentry_HostCr3,
4475	kVmxVDiag_Vmentry_HostCr4Fixed0,
4476	kVmxVDiag_Vmentry_HostCr4Fixed1,
4477	kVmxVDiag_Vmentry_HostCr4Pae,
4478	kVmxVDiag_Vmentry_HostCr4Pcide,
4479	kVmxVDiag_Vmentry_HostCsTr,
4480	kVmxVDiag_Vmentry_HostEferMsr,
4481	kVmxVDiag_Vmentry_HostEferMsrRsvd,
4482	kVmxVDiag_Vmentry_HostGuestLongMode,
4483	kVmxVDiag_Vmentry_HostGuestLongModeNoCpu,
4484	kVmxVDiag_Vmentry_HostLongMode,
4485	kVmxVDiag_Vmentry_HostPatMsr,
4486	kVmxVDiag_Vmentry_HostRip,
4487	kVmxVDiag_Vmentry_HostRipRsvd,
4488	kVmxVDiag_Vmentry_HostSel,
4489	kVmxVDiag_Vmentry_HostSegBase,
4490	kVmxVDiag_Vmentry_HostSs,
4491	kVmxVDiag_Vmentry_HostSysenterEspEip,
4492	kVmxVDiag_Vmentry_IoBitmapAPtrReadPhys,
4493	kVmxVDiag_Vmentry_IoBitmapBPtrReadPhys,
4494	kVmxVDiag_Vmentry_LongModeCS,
4495	kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys,
4496	kVmxVDiag_Vmentry_MsrLoad,
4497	kVmxVDiag_Vmentry_MsrLoadCount,
4498	kVmxVDiag_Vmentry_MsrLoadPtrReadPhys,
4499	kVmxVDiag_Vmentry_MsrLoadRing3,
4500	kVmxVDiag_Vmentry_MsrLoadRsvd,
4501	kVmxVDiag_Vmentry_NmiWindowExit,
4502	kVmxVDiag_Vmentry_PinCtlsAllowed1,
4503	kVmxVDiag_Vmentry_PinCtlsDisallowed0,
4504	kVmxVDiag_Vmentry_ProcCtlsAllowed1,
4505	kVmxVDiag_Vmentry_ProcCtlsDisallowed0,
4506	kVmxVDiag_Vmentry_ProcCtls2Allowed1,
4507	kVmxVDiag_Vmentry_ProcCtls2Disallowed0,
4508	kVmxVDiag_Vmentry_PtrInvalid,
4509	kVmxVDiag_Vmentry_PtrShadowVmcs,
4510	kVmxVDiag_Vmentry_RealOrV86Mode,
4511	kVmxVDiag_Vmentry_SavePreemptTimer,
4512	kVmxVDiag_Vmentry_TprThresholdRsvd,
4513	kVmxVDiag_Vmentry_TprThresholdVTpr,
4514	kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys,
4515	kVmxVDiag_Vmentry_VirtIntDelivery,
4516	kVmxVDiag_Vmentry_VirtNmi,
4517	kVmxVDiag_Vmentry_VirtX2ApicTprShadow,
4518	kVmxVDiag_Vmentry_VirtX2ApicVirtApic,
4519	kVmxVDiag_Vmentry_VmcsClear,
4520	kVmxVDiag_Vmentry_VmcsLaunch,
4521	kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys,
4522	kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys,
4523	kVmxVDiag_Vmentry_VmxRoot,
4524	kVmxVDiag_Vmentry_Vpid,
4525	kVmxVDiag_Vmexit_HostPdpte,
4526	kVmxVDiag_Vmexit_MsrLoad,
4527	kVmxVDiag_Vmexit_MsrLoadCount,
4528	kVmxVDiag_Vmexit_MsrLoadPtrReadPhys,
4529	kVmxVDiag_Vmexit_MsrLoadRing3,
4530	kVmxVDiag_Vmexit_MsrLoadRsvd,
4531	kVmxVDiag_Vmexit_MsrStore,
4532	kVmxVDiag_Vmexit_MsrStoreCount,
4533	kVmxVDiag_Vmexit_MsrStorePtrReadPhys,
4534	kVmxVDiag_Vmexit_MsrStorePtrWritePhys,
4535	kVmxVDiag_Vmexit_MsrStoreRing3,
4536	kVmxVDiag_Vmexit_MsrStoreRsvd,
4537	kVmxVDiag_Vmexit_VirtApicPagePtrWritePhys,
4538	/* Last member for determining array index limit. */
4539	kVmxVDiag_End
4540	} VMXVDIAG;
4541	AssertCompileSize(VMXVDIAG, 4);
4542
4543	/** @} */
4544
4545	/** @} */
4546
4547	#endif /* !VBOX_INCLUDED_vmm_hm_vmx_h */
4548

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source: vbox/trunk/include/VBox/vmm/hm_vmx.h@ 96601

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