VirtualBox

source: vbox/trunk/include/VBox/dis.h@ 41742

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DISOPPARAM: s/scale/uScale/ + doc
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1/** @file
2 * DIS - The VirtualBox Disassembler.
3 */
4
5/*
6 * Copyright (C) 2006-2012 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.215389.xyz. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_dis_h
27#define ___VBox_dis_h
28
29#include <VBox/types.h>
30#include <VBox/disopcode.h>
31#include <iprt/assert.h>
32
33
34RT_C_DECLS_BEGIN
35
36
37/**
38 * CPU mode flags (DISCPUSTATE::mode).
39 */
40typedef enum DISCPUMODE
41{
42 DISCPUMODE_INVALID = 0,
43 DISCPUMODE_16BIT,
44 DISCPUMODE_32BIT,
45 DISCPUMODE_64BIT,
46 /** hack forcing the size of the enum to 32-bits. */
47 DISCPUMODE_MAKE_32BIT_HACK = 0x7fffffff
48} DISCPUMODE;
49
50/** @name Prefix byte flags (DISCPUSTATE::fPrefix).
51 * @{
52 */
53#define DISPREFIX_NONE UINT8_C(0x00)
54/** non-default address size. */
55#define DISPREFIX_ADDRSIZE UINT8_C(0x01)
56/** non-default operand size. */
57#define DISPREFIX_OPSIZE UINT8_C(0x02)
58/** lock prefix. */
59#define DISPREFIX_LOCK UINT8_C(0x04)
60/** segment prefix. */
61#define DISPREFIX_SEG UINT8_C(0x08)
62/** rep(e) prefix (not a prefix, but we'll treat is as one). */
63#define DISPREFIX_REP UINT8_C(0x10)
64/** rep(e) prefix (not a prefix, but we'll treat is as one). */
65#define DISPREFIX_REPNE UINT8_C(0x20)
66/** REX prefix (64 bits) */
67#define DISPREFIX_REX UINT8_C(0x40)
68/** @} */
69
70/** @name 64 bits prefix byte flags (DISCPUSTATE::fRexPrefix).
71 * Requires VBox/disopcode.h.
72 * @{
73 */
74#define DISPREFIX_REX_OP_2_FLAGS(a) (a - OP_PARM_REX_START)
75#define DISPREFIX_REX_FLAGS DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX)
76#define DISPREFIX_REX_FLAGS_B DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_B)
77#define DISPREFIX_REX_FLAGS_X DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_X)
78#define DISPREFIX_REX_FLAGS_XB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_XB)
79#define DISPREFIX_REX_FLAGS_R DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_R)
80#define DISPREFIX_REX_FLAGS_RB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RB)
81#define DISPREFIX_REX_FLAGS_RX DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RX)
82#define DISPREFIX_REX_FLAGS_RXB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RXB)
83#define DISPREFIX_REX_FLAGS_W DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_W)
84#define DISPREFIX_REX_FLAGS_WB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WB)
85#define DISPREFIX_REX_FLAGS_WX DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WX)
86#define DISPREFIX_REX_FLAGS_WXB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WXB)
87#define DISPREFIX_REX_FLAGS_WR DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WR)
88#define DISPREFIX_REX_FLAGS_WRB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRB)
89#define DISPREFIX_REX_FLAGS_WRX DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRX)
90#define DISPREFIX_REX_FLAGS_WRXB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRXB)
91/** @} */
92
93/** @name Operand type (DISOPCODE::fOpType).
94 * @{
95 */
96#define DISOPTYPE_INVALID RT_BIT_32(0)
97#define DISOPTYPE_HARMLESS RT_BIT_32(1)
98#define DISOPTYPE_CONTROLFLOW RT_BIT_32(2)
99#define DISOPTYPE_POTENTIALLY_DANGEROUS RT_BIT_32(3)
100#define DISOPTYPE_DANGEROUS RT_BIT_32(4)
101#define DISOPTYPE_PORTIO RT_BIT_32(5)
102#define DISOPTYPE_PRIVILEGED RT_BIT_32(6)
103#define DISOPTYPE_PRIVILEGED_NOTRAP RT_BIT_32(7)
104#define DISOPTYPE_UNCOND_CONTROLFLOW RT_BIT_32(8)
105#define DISOPTYPE_RELATIVE_CONTROLFLOW RT_BIT_32(9)
106#define DISOPTYPE_COND_CONTROLFLOW RT_BIT_32(10)
107#define DISOPTYPE_INTERRUPT RT_BIT_32(11)
108#define DISOPTYPE_ILLEGAL RT_BIT_32(12)
109#define DISOPTYPE_RRM_DANGEROUS RT_BIT_32(14) /**< Some additional dangerous ones when recompiling raw r0. */
110#define DISOPTYPE_RRM_DANGEROUS_16 RT_BIT_32(15) /**< Some additional dangerous ones when recompiling 16-bit raw r0. */
111#define DISOPTYPE_RRM_MASK (DISOPTYPE_RRM_DANGEROUS | DISOPTYPE_RRM_DANGEROUS_16)
112#define DISOPTYPE_INHIBIT_IRQS RT_BIT_32(16) /**< Will or can inhibit irqs (sti, pop ss, mov ss) */
113#define DISOPTYPE_PORTIO_READ RT_BIT_32(17)
114#define DISOPTYPE_PORTIO_WRITE RT_BIT_32(18)
115#define DISOPTYPE_INVALID_64 RT_BIT_32(19) /**< Invalid in 64 bits mode */
116#define DISOPTYPE_ONLY_64 RT_BIT_32(20) /**< Only valid in 64 bits mode */
117#define DISOPTYPE_DEFAULT_64_OP_SIZE RT_BIT_32(21) /**< Default 64 bits operand size */
118#define DISOPTYPE_FORCED_64_OP_SIZE RT_BIT_32(22) /**< Forced 64 bits operand size; regardless of prefix bytes */
119#define DISOPTYPE_REXB_EXTENDS_OPREG RT_BIT_32(23) /**< REX.B extends the register field in the opcode byte */
120#define DISOPTYPE_MOD_FIXED_11 RT_BIT_32(24) /**< modrm.mod is always 11b */
121#define DISOPTYPE_FORCED_32_OP_SIZE_X86 RT_BIT_32(25) /**< Forced 32 bits operand size; regardless of prefix bytes (only in 16 & 32 bits mode!) */
122#define DISOPTYPE_ALL UINT32_C(0xffffffff)
123/** @} */
124
125/** @name Parameter usage flags.
126 * @{
127 */
128#define DISUSE_BASE RT_BIT_64(0)
129#define DISUSE_INDEX RT_BIT_64(1)
130#define DISUSE_SCALE RT_BIT_64(2)
131#define DISUSE_REG_GEN8 RT_BIT_64(3)
132#define DISUSE_REG_GEN16 RT_BIT_64(4)
133#define DISUSE_REG_GEN32 RT_BIT_64(5)
134#define DISUSE_REG_GEN64 RT_BIT_64(6)
135#define DISUSE_REG_FP RT_BIT_64(7)
136#define DISUSE_REG_MMX RT_BIT_64(8)
137#define DISUSE_REG_XMM RT_BIT_64(9)
138#define DISUSE_REG_CR RT_BIT_64(10)
139#define DISUSE_REG_DBG RT_BIT_64(11)
140#define DISUSE_REG_SEG RT_BIT_64(12)
141#define DISUSE_REG_TEST RT_BIT_64(13)
142#define DISUSE_DISPLACEMENT8 RT_BIT_64(14)
143#define DISUSE_DISPLACEMENT16 RT_BIT_64(15)
144#define DISUSE_DISPLACEMENT32 RT_BIT_64(16)
145#define DISUSE_DISPLACEMENT64 RT_BIT_64(17)
146#define DISUSE_RIPDISPLACEMENT32 RT_BIT_64(18)
147#define DISUSE_IMMEDIATE8 RT_BIT_64(19)
148#define DISUSE_IMMEDIATE8_REL RT_BIT_64(20)
149#define DISUSE_IMMEDIATE16 RT_BIT_64(21)
150#define DISUSE_IMMEDIATE16_REL RT_BIT_64(22)
151#define DISUSE_IMMEDIATE32 RT_BIT_64(23)
152#define DISUSE_IMMEDIATE32_REL RT_BIT_64(24)
153#define DISUSE_IMMEDIATE64 RT_BIT_64(25)
154#define DISUSE_IMMEDIATE64_REL RT_BIT_64(26)
155#define DISUSE_IMMEDIATE_ADDR_0_32 RT_BIT_64(27)
156#define DISUSE_IMMEDIATE_ADDR_16_32 RT_BIT_64(28)
157#define DISUSE_IMMEDIATE_ADDR_0_16 RT_BIT_64(29)
158#define DISUSE_IMMEDIATE_ADDR_16_16 RT_BIT_64(30)
159/** DS:ESI */
160#define DISUSE_POINTER_DS_BASED RT_BIT_64(31)
161/** ES:EDI */
162#define DISUSE_POINTER_ES_BASED RT_BIT_64(32)
163#define DISUSE_IMMEDIATE16_SX8 RT_BIT_64(33)
164#define DISUSE_IMMEDIATE32_SX8 RT_BIT_64(34)
165#define DISUSE_IMMEDIATE64_SX8 RT_BIT_64(36)
166
167/** Mask of immediate use flags. */
168#define DISUSE_IMMEDIATE ( DISUSE_IMMEDIATE8 \
169 | DISUSE_IMMEDIATE16 \
170 | DISUSE_IMMEDIATE32 \
171 | DISUSE_IMMEDIATE64 \
172 | DISUSE_IMMEDIATE8_REL \
173 | DISUSE_IMMEDIATE16_REL \
174 | DISUSE_IMMEDIATE32_REL \
175 | DISUSE_IMMEDIATE64_REL \
176 | DISUSE_IMMEDIATE_ADDR_0_32 \
177 | DISUSE_IMMEDIATE_ADDR_16_32 \
178 | DISUSE_IMMEDIATE_ADDR_0_16 \
179 | DISUSE_IMMEDIATE_ADDR_16_16 \
180 | DISUSE_IMMEDIATE16_SX8 \
181 | DISUSE_IMMEDIATE32_SX8 \
182 | DISUSE_IMMEDIATE64_SX8)
183/** Check if the use flags indicates an effective address. */
184#define DISUSE_IS_EFFECTIVE_ADDR(a_fUseFlags) (!!( (a_fUseFlags) \
185 & ( DISUSE_BASE \
186 | DISUSE_INDEX \
187 | DISUSE_DISPLACEMENT32 \
188 | DISUSE_DISPLACEMENT64 \
189 | DISUSE_DISPLACEMENT16 \
190 | DISUSE_DISPLACEMENT8 \
191 | DISUSE_RIPDISPLACEMENT32) ))
192/** @} */
193
194/** @name 64-bit general register indexes.
195 * This matches the AMD64 register encoding. It is found used in
196 * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen.
197 * @note Safe to assume same values as the 16-bit and 32-bit general registers.
198 * @{
199 */
200#define DISGREG_RAX UINT8_C(0)
201#define DISGREG_RCX UINT8_C(1)
202#define DISGREG_RDX UINT8_C(2)
203#define DISGREG_RBX UINT8_C(3)
204#define DISGREG_RSP UINT8_C(4)
205#define DISGREG_RBP UINT8_C(5)
206#define DISGREG_RSI UINT8_C(6)
207#define DISGREG_RDI UINT8_C(7)
208#define DISGREG_R8 UINT8_C(8)
209#define DISGREG_R9 UINT8_C(9)
210#define DISGREG_R10 UINT8_C(10)
211#define DISGREG_R11 UINT8_C(11)
212#define DISGREG_R12 UINT8_C(12)
213#define DISGREG_R13 UINT8_C(13)
214#define DISGREG_R14 UINT8_C(14)
215#define DISGREG_R15 UINT8_C(15)
216/** @} */
217
218/** @name 32-bit general register indexes.
219 * This matches the AMD64 register encoding. It is found used in
220 * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen.
221 * @note Safe to assume same values as the 16-bit and 64-bit general registers.
222 * @{
223 */
224#define DISGREG_EAX UINT8_C(0)
225#define DISGREG_ECX UINT8_C(1)
226#define DISGREG_EDX UINT8_C(2)
227#define DISGREG_EBX UINT8_C(3)
228#define DISGREG_ESP UINT8_C(4)
229#define DISGREG_EBP UINT8_C(5)
230#define DISGREG_ESI UINT8_C(6)
231#define DISGREG_EDI UINT8_C(7)
232#define DISGREG_R8D UINT8_C(8)
233#define DISGREG_R9D UINT8_C(9)
234#define DISGREG_R10D UINT8_C(10)
235#define DISGREG_R11D UINT8_C(11)
236#define DISGREG_R12D UINT8_C(12)
237#define DISGREG_R13D UINT8_C(13)
238#define DISGREG_R14D UINT8_C(14)
239#define DISGREG_R15D UINT8_C(15)
240/** @} */
241
242/** @name 16-bit general register indexes.
243 * This matches the AMD64 register encoding. It is found used in
244 * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen.
245 * @note Safe to assume same values as the 32-bit and 64-bit general registers.
246 * @{
247 */
248#define DISGREG_AX UINT8_C(0)
249#define DISGREG_CX UINT8_C(1)
250#define DISGREG_DX UINT8_C(2)
251#define DISGREG_BX UINT8_C(3)
252#define DISGREG_SP UINT8_C(4)
253#define DISGREG_BP UINT8_C(5)
254#define DISGREG_SI UINT8_C(6)
255#define DISGREG_DI UINT8_C(7)
256#define DISGREG_R8W UINT8_C(8)
257#define DISGREG_R9W UINT8_C(9)
258#define DISGREG_R10W UINT8_C(10)
259#define DISGREG_R11W UINT8_C(11)
260#define DISGREG_R12W UINT8_C(12)
261#define DISGREG_R13W UINT8_C(13)
262#define DISGREG_R14W UINT8_C(14)
263#define DISGREG_R15W UINT8_C(15)
264/** @} */
265
266/** @name 8-bit general register indexes.
267 * This mostly (?) matches the AMD64 register encoding. It is found used in
268 * DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen.
269 * @{
270 */
271#define DISGREG_AL UINT8_C(0)
272#define DISGREG_CL UINT8_C(1)
273#define DISGREG_DL UINT8_C(2)
274#define DISGREG_BL UINT8_C(3)
275#define DISGREG_AH UINT8_C(4)
276#define DISGREG_CH UINT8_C(5)
277#define DISGREG_DH UINT8_C(6)
278#define DISGREG_BH UINT8_C(7)
279#define DISGREG_R8B UINT8_C(8)
280#define DISGREG_R9B UINT8_C(9)
281#define DISGREG_R10B UINT8_C(10)
282#define DISGREG_R11B UINT8_C(11)
283#define DISGREG_R12B UINT8_C(12)
284#define DISGREG_R13B UINT8_C(13)
285#define DISGREG_R14B UINT8_C(14)
286#define DISGREG_R15B UINT8_C(15)
287#define DISGREG_SPL UINT8_C(16)
288#define DISGREG_BPL UINT8_C(17)
289#define DISGREG_SIL UINT8_C(18)
290#define DISGREG_DIL UINT8_C(19)
291/** @} */
292
293/** @name Segment registerindexes.
294 * This matches the AMD64 register encoding. It is found used in
295 * DISOPPARAM::base.reg_seg.
296 * @{
297 */
298typedef enum
299{
300 DISSELREG_ES = 0,
301 DISSELREG_CS = 1,
302 DISSELREG_SS = 2,
303 DISSELREG_DS = 3,
304 DISSELREG_FS = 4,
305 DISSELREG_GS = 5,
306 /** The usual 32-bit paranoia. */
307 DIS_SEGREG_32BIT_HACK = 0x7fffffff
308} DISSELREG;
309/** @} */
310
311/** @name FPU register indexes.
312 * This matches the AMD64 register encoding. It is found used in
313 * DISOPPARAM::base.reg_fp.
314 * @{
315 */
316#define DISFPREG_ST0 UINT8_C(0)
317#define DISFPREG_ST1 UINT8_C(1)
318#define DISFPREG_ST2 UINT8_C(2)
319#define DISFPREG_ST3 UINT8_C(3)
320#define DISFPREG_ST4 UINT8_C(4)
321#define DISFPREG_ST5 UINT8_C(5)
322#define DISFPREG_ST6 UINT8_C(6)
323#define DISFPREG_ST7 UINT8_C(7)
324/** @} */
325
326/** @name Control register indexes.
327 * This matches the AMD64 register encoding. It is found used in
328 * DISOPPARAM::base.reg_ctrl.
329 * @{
330 */
331#define DISCREG_CR0 UINT8_C(0)
332#define DISCREG_CR1 UINT8_C(1)
333#define DISCREG_CR2 UINT8_C(2)
334#define DISCREG_CR3 UINT8_C(3)
335#define DISCREG_CR4 UINT8_C(4)
336#define DISCREG_CR8 UINT8_C(8)
337/** @} */
338
339/** @name Debug register indexes.
340 * This matches the AMD64 register encoding. It is found used in
341 * DISOPPARAM::base.reg_dbg.
342 * @{
343 */
344#define DISDREG_DR0 UINT8_C(0)
345#define DISDREG_DR1 UINT8_C(1)
346#define DISDREG_DR2 UINT8_C(2)
347#define DISDREG_DR3 UINT8_C(3)
348#define DISDREG_DR4 UINT8_C(4)
349#define DISDREG_DR5 UINT8_C(5)
350#define DISDREG_DR6 UINT8_C(6)
351#define DISDREG_DR7 UINT8_C(7)
352/** @} */
353
354/** @name MMX register indexes.
355 * This matches the AMD64 register encoding. It is found used in
356 * DISOPPARAM::base.reg_mmx.
357 * @{
358 */
359#define DISMREG_MMX0 UINT8_C(0)
360#define DISMREG_MMX1 UINT8_C(1)
361#define DISMREG_MMX2 UINT8_C(2)
362#define DISMREG_MMX3 UINT8_C(3)
363#define DISMREG_MMX4 UINT8_C(4)
364#define DISMREG_MMX5 UINT8_C(5)
365#define DISMREG_MMX6 UINT8_C(6)
366#define DISMREG_MMX7 UINT8_C(7)
367/** @} */
368
369/** @name SSE register indexes.
370 * This matches the AMD64 register encoding. It is found used in
371 * DISOPPARAM::base.reg_xmm.
372 * @{
373 */
374#define DISXREG_XMM0 UINT8_C(0)
375#define DISXREG_XMM1 UINT8_C(1)
376#define DISXREG_XMM2 UINT8_C(2)
377#define DISXREG_XMM3 UINT8_C(3)
378#define DISXREG_XMM4 UINT8_C(4)
379#define DISXREG_XMM5 UINT8_C(5)
380#define DISXREG_XMM6 UINT8_C(6)
381#define DISXREG_XMM7 UINT8_C(7)
382/** @} */
383
384
385/**
386 * Operand Parameter.
387 */
388typedef struct DISOPPARAM
389{
390 /** Immediate value or address, if used. */
391 uint64_t uValue;
392 /** A combination of DISUSE_XXX. */
393 uint64_t fUse;
394 union
395 {
396 int64_t i64;
397 int32_t i32;
398 int32_t i16;
399 int32_t i8;
400 uint64_t u64;
401 uint32_t u32;
402 uint32_t u16;
403 uint32_t u8;
404 } uDisp;
405 /** Copy of the corresponding DISOPCODE::fParam1 / DISOPCODE::fParam2 /
406 * DISOPCODE::fParam3. */
407 uint32_t fParam;
408
409 union
410 {
411 /** DISGREG_XXX. */
412 uint8_t reg_gen;
413 /** DISFPREG_XXX */
414 uint8_t reg_fp;
415 /** DISMREG_XXX. */
416 uint8_t reg_mmx;
417 /** DISXREG_XXX. */
418 uint8_t reg_xmm;
419 /** DISSELREG_XXX. */
420 uint8_t reg_seg;
421 /** TR0-TR7 (no defines for these). */
422 uint8_t reg_test;
423 /** DISCREG_XXX */
424 uint8_t reg_ctrl;
425 /** DISDREG_XXX */
426 uint8_t reg_dbg;
427 } base;
428 union
429 {
430 /** DISGREG_XXX. */
431 uint8_t reg_gen;
432 } index;
433
434 /** 2, 4 or 8, if DISUSE_SCALE is set in fUse. */
435 uint8_t uScale;
436 /** Parameter size. */
437 uint8_t cb;
438} DISOPPARAM;
439AssertCompileSize(DISOPPARAM, 32);
440/** Pointer to opcode parameter. */
441typedef DISOPPARAM *PDISOPPARAM;
442/** Pointer to opcode parameter. */
443typedef const DISOPPARAM *PCDISOPPARAM;
444
445
446/**
447 * Opcode descriptor.
448 */
449typedef struct DISOPCODE
450{
451#ifndef DIS_CORE_ONLY
452 const char *pszOpcode;
453#endif
454 /** Parameter \#1 parser index. */
455 uint8_t idxParse1;
456 /** Parameter \#2 parser index. */
457 uint8_t idxParse2;
458 /** Parameter \#3 parser index. */
459 uint8_t idxParse3;
460 /** Unused padding. */
461 uint8_t uUnused;
462 /** The opcode identifier. This DIS specific, @see grp_dis_opcodes and
463 * VBox/disopcode.h. */
464 uint16_t uOpcode;
465 /** Parameter \#1 info, @see grp_dis_opparam. */
466 uint16_t fParam1;
467 /** Parameter \#2 info, @see grp_dis_opparam. */
468 uint16_t fParam2;
469 /** Parameter \#3 info, @see grp_dis_opparam. */
470 uint16_t fParam3;
471 /** Operand type flags, DISOPTYPE_XXX. */
472 uint32_t fOpType;
473} DISOPCODE;
474/** Pointer to const opcode. */
475typedef const struct DISOPCODE *PCDISOPCODE;
476
477
478/**
479 * Callback for reading opcode bytes.
480 *
481 * @param pDisState Pointer to the CPU state. The primary user argument
482 * can be retrived from DISCPUSTATE::pvUser. If
483 * more is required these can be passed in the
484 * subsequent slots.
485 * @param pbDst Pointer to output buffer.
486 * @param uSrcAddr The address to start reading at.
487 * @param cbToRead The number of bytes to read.
488 */
489typedef DECLCALLBACK(int) FNDISREADBYTES(PDISCPUSTATE pDisState, uint8_t *pbDst, RTUINTPTR uSrcAddr, uint32_t cbToRead);
490/** Pointer to a opcode byte reader. */
491typedef FNDISREADBYTES *PFNDISREADBYTES;
492
493/** Parser callback.
494 * @remark no DECLCALLBACK() here because it's considered to be internal (really, I'm too lazy to update all the functions). */
495typedef unsigned FNDISPARSE(RTUINTPTR pu8CodeBlock, PCDISOPCODE pOp, PDISOPPARAM pParam, PDISCPUSTATE pCpu);
496/** Pointer to a disassembler parser function. */
497typedef FNDISPARSE *PFNDISPARSE;
498/** Pointer to a const disassembler parser function pointer. */
499typedef PFNDISPARSE const *PCPFNDISPARSE;
500
501/**
502 * The diassembler state and result.
503 */
504typedef struct DISCPUSTATE
505{
506 /* Because of pvUser2, put the less frequently used bits at the top for
507 now. (Might be better off in the middle?) */
508 DISOPPARAM Param3;
509 DISOPPARAM Param2;
510 DISOPPARAM Param1;
511
512 /* off: 0x060 (96) */
513 /** ModRM fields. */
514 union
515 {
516 /** Bitfield view */
517 struct
518 {
519 unsigned Rm : 4;
520 unsigned Reg : 4;
521 unsigned Mod : 2;
522 } Bits;
523 /** unsigned view */
524 unsigned u;
525 } ModRM;
526 /** SIB fields. */
527 union
528 {
529 /** Bitfield view */
530 struct
531 {
532 unsigned Base : 4;
533 unsigned Index : 4;
534 unsigned Scale : 2;
535 } Bits;
536 /** unsigned view */
537 unsigned u;
538 } SIB;
539 int32_t i32SibDisp;
540
541 /* off: 0x06c (108) */
542 /** The CPU mode (DISCPUMODE). */
543 uint8_t uCpuMode;
544 /** The addressing mode (DISCPUMODE). */
545 uint8_t uAddrMode;
546 /** The operand mode (DISCPUMODE). */
547 uint8_t uOpMode;
548 /** Per instruction prefix settings. */
549 uint8_t fPrefix;
550 /* off: 0x070 (112) */
551 /** REX prefix value (64 bits only). */
552 uint8_t fRexPrefix;
553 /** Segment prefix value (DISSELREG). */
554 uint8_t idxSegPrefix;
555 /** Last prefix byte (for SSE2 extension tables). */
556 uint8_t bLastPrefix;
557 /** First opcode byte of instruction. */
558 uint8_t bOpCode;
559 /* off: 0x074 (116) */
560 /** The size of the prefix bytes. */
561 uint8_t cbPrefix;
562 /** The instruction size. */
563 uint8_t cbInstr;
564 uint8_t abUnused[2];
565 /* off: 0x078 (120) */
566 /** Return code set by a worker function like the opcode bytes readers. */
567 int32_t rc;
568 /** Internal: instruction filter */
569 uint32_t fFilter;
570 /* off: 0x080 (128) */
571 /** Internal: pointer to disassembly function table */
572 PCPFNDISPARSE pfnDisasmFnTable;
573#if ARCH_BITS == 32
574 uint32_t uPtrPadding1;
575#endif
576 /** Pointer to the current instruction. */
577 PCDISOPCODE pCurInstr;
578#if ARCH_BITS == 32
579 uint32_t uPtrPadding2;
580#endif
581 /* off: 0x090 (144) */
582 /** The address of the instruction. */
583 RTUINTPTR uInstrAddr;
584 /* off: 0x098 (152) */
585 /** Optional read function */
586 PFNDISREADBYTES pfnReadBytes;
587#if ARCH_BITS == 32
588 uint32_t uPadding3;
589#endif
590 /* off: 0x0a0 (160) */
591 /** The instruction bytes. */
592 uint8_t abInstr[16];
593 /* off: 0x0b0 (176) */
594 /** User data supplied as an argument to the APIs. */
595 void *pvUser;
596#if ARCH_BITS == 32
597 uint32_t uPadding4;
598#endif
599 /** User data that can be set prior to calling the API.
600 * @deprecated Please don't use this any more. */
601 void *pvUser2;
602#if ARCH_BITS == 32
603 uint32_t uPadding5;
604#endif
605} DISCPUSTATE;
606
607
608
609DISDECL(int) DISInstrToStr(void const *pvInstr, DISCPUMODE enmCpuMode,
610 PDISCPUSTATE pCpu, uint32_t *pcbInstr, char *pszOutput, size_t cbOutput);
611DISDECL(int) DISInstrToStrWithReader(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, PFNDISREADBYTES pfnReadBytes, void *pvUser,
612 PDISCPUSTATE pCpu, uint32_t *pcbInstr, char *pszOutput, size_t cbOutput);
613DISDECL(int) DISInstrToStrEx(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode,
614 PFNDISREADBYTES pfnReadBytes, void *pvUser, uint32_t uFilter,
615 PDISCPUSTATE pCpu, uint32_t *pcbInstr, char *pszOutput, size_t cbOutput);
616
617DISDECL(int) DISInstr(void const *pvInstr, DISCPUMODE enmCpuMode, PDISCPUSTATE pCpu, uint32_t *pcbInstr);
618DISDECL(int) DISInstrWithReader(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, PFNDISREADBYTES pfnReadBytes, void *pvUser,
619 PDISCPUSTATE pCpu, uint32_t *pcbInstr);
620DISDECL(int) DISInstEx(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, uint32_t uFilter,
621 PFNDISREADBYTES pfnReadBytes, void *pvUser,
622 PDISCPUSTATE pCpu, uint32_t *pcbInstr);
623
624DISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, PDISOPPARAM pParam);
625DISDECL(DISSELREG) DISDetectSegReg(PDISCPUSTATE pCpu, PDISOPPARAM pParam);
626DISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu);
627
628
629
630/** @name Flags returned by DISQueryParamVal (DISQPVPARAMVAL::flags).
631 * @{
632 */
633#define DISQPV_FLAG_8 UINT8_C(0x01)
634#define DISQPV_FLAG_16 UINT8_C(0x02)
635#define DISQPV_FLAG_32 UINT8_C(0x04)
636#define DISQPV_FLAG_64 UINT8_C(0x08)
637#define DISQPV_FLAG_FARPTR16 UINT8_C(0x10)
638#define DISQPV_FLAG_FARPTR32 UINT8_C(0x20)
639/** @} */
640
641/** @name Types returned by DISQueryParamVal (DISQPVPARAMVAL::flags).
642 * @{ */
643#define DISQPV_TYPE_REGISTER UINT8_C(1)
644#define DISQPV_TYPE_ADDRESS UINT8_C(2)
645#define DISQPV_TYPE_IMMEDIATE UINT8_C(3)
646/** @} */
647
648typedef struct
649{
650 union
651 {
652 uint8_t val8;
653 uint16_t val16;
654 uint32_t val32;
655 uint64_t val64;
656
657 struct
658 {
659 uint16_t sel;
660 uint32_t offset;
661 } farptr;
662 } val;
663
664 uint8_t type;
665 uint8_t size;
666 uint8_t flags;
667} DISQPVPARAMVAL;
668/** Pointer to opcode parameter value. */
669typedef DISQPVPARAMVAL *PDISQPVPARAMVAL;
670
671/** Indicates which parameter DISQueryParamVal should operate on. */
672typedef enum DISQPVWHICH
673{
674 DISQPVWHICH_DST = 1,
675 DISQPVWHICH_SRC,
676 DISQPVWHAT_32_BIT_HACK = 0x7fffffff
677} DISQPVWHICH;
678DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, PDISOPPARAM pParam, PDISQPVPARAMVAL pParamVal, DISQPVWHICH parmtype);
679
680DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, PDISOPPARAM pParam, void **ppReg, size_t *pcbSize);
681DISDECL(int) DISFetchReg8(PCCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal);
682DISDECL(int) DISFetchReg16(PCCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal);
683DISDECL(int) DISFetchReg32(PCCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal);
684DISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal);
685DISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal);
686DISDECL(int) DISFetchRegSegEx(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal, PCPUMSELREGHID *ppSelHidReg);
687DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8);
688DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg32, uint16_t val16);
689DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32);
690DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64);
691DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DISSELREG sel, RTSEL val);
692DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg);
693DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg);
694DISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg);
695DISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg);
696
697
698/**
699 * Try resolve an address into a symbol name.
700 *
701 * For use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
702 *
703 * @returns VBox status code.
704 * @retval VINF_SUCCESS on success, pszBuf contains the full symbol name.
705 * @retval VINF_BUFFER_OVERFLOW if pszBuf is too small the symbol name. The
706 * content of pszBuf is truncated and zero terminated.
707 * @retval VERR_SYMBOL_NOT_FOUND if no matching symbol was found for the address.
708 *
709 * @param pCpu Pointer to the disassembler CPU state.
710 * @param u32Sel The selector value. Use DIS_FMT_SEL_IS_REG, DIS_FMT_SEL_GET_VALUE,
711 * DIS_FMT_SEL_GET_REG to access this.
712 * @param uAddress The segment address.
713 * @param pszBuf Where to store the symbol name
714 * @param cchBuf The size of the buffer.
715 * @param poff If not a perfect match, then this is where the offset from the return
716 * symbol to the specified address is returned.
717 * @param pvUser The user argument.
718 */
719typedef DECLCALLBACK(int) FNDISGETSYMBOL(PCDISCPUSTATE pCpu, uint32_t u32Sel, RTUINTPTR uAddress, char *pszBuf, size_t cchBuf, RTINTPTR *poff, void *pvUser);
720/** Pointer to a FNDISGETSYMBOL(). */
721typedef FNDISGETSYMBOL *PFNDISGETSYMBOL;
722
723/**
724 * Checks if the FNDISGETSYMBOL argument u32Sel is a register or not.
725 */
726#define DIS_FMT_SEL_IS_REG(u32Sel) ( !!((u32Sel) & RT_BIT(31)) )
727
728/**
729 * Extracts the selector value from the FNDISGETSYMBOL argument u32Sel.
730 * @returns Selector value.
731 */
732#define DIS_FMT_SEL_GET_VALUE(u32Sel) ( (RTSEL)(u32Sel) )
733
734/**
735 * Extracts the register number from the FNDISGETSYMBOL argument u32Sel.
736 * @returns USE_REG_CS, USE_REG_SS, USE_REG_DS, USE_REG_ES, USE_REG_FS or USE_REG_FS.
737 */
738#define DIS_FMT_SEL_GET_REG(u32Sel) ( ((u32Sel) >> 16) & 0xf )
739
740/** @internal */
741#define DIS_FMT_SEL_FROM_REG(uReg) ( ((uReg) << 16) | RT_BIT(31) | 0xffff )
742/** @internal */
743#define DIS_FMT_SEL_FROM_VALUE(Sel) ( (Sel) & 0xffff )
744
745
746/** @name Flags for use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
747 * @{
748 */
749/** Put the address to the right. */
750#define DIS_FMT_FLAGS_ADDR_RIGHT RT_BIT_32(0)
751/** Put the address to the left. */
752#define DIS_FMT_FLAGS_ADDR_LEFT RT_BIT_32(1)
753/** Put the address in comments.
754 * For some assemblers this implies placing it to the right. */
755#define DIS_FMT_FLAGS_ADDR_COMMENT RT_BIT_32(2)
756/** Put the instruction bytes to the right of the disassembly. */
757#define DIS_FMT_FLAGS_BYTES_RIGHT RT_BIT_32(3)
758/** Put the instruction bytes to the left of the disassembly. */
759#define DIS_FMT_FLAGS_BYTES_LEFT RT_BIT_32(4)
760/** Put the instruction bytes in comments.
761 * For some assemblers this implies placing the bytes to the right. */
762#define DIS_FMT_FLAGS_BYTES_COMMENT RT_BIT_32(5)
763/** Put the bytes in square brackets. */
764#define DIS_FMT_FLAGS_BYTES_BRACKETS RT_BIT_32(6)
765/** Put spaces between the bytes. */
766#define DIS_FMT_FLAGS_BYTES_SPACED RT_BIT_32(7)
767/** Display the relative +/- offset of branch instructions that uses relative addresses,
768 * and put the target address in parenthesis. */
769#define DIS_FMT_FLAGS_RELATIVE_BRANCH RT_BIT_32(8)
770/** Strict assembly. The assembly should, when ever possible, make the
771 * assembler reproduce the exact same binary. (Refers to the yasm
772 * strict keyword.) */
773#define DIS_FMT_FLAGS_STRICT RT_BIT_32(9)
774/** Checks if the given flags are a valid combination. */
775#define DIS_FMT_FLAGS_IS_VALID(fFlags) \
776 ( !((fFlags) & ~UINT32_C(0x000003ff)) \
777 && ((fFlags) & (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT)) != (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT) \
778 && ( !((fFlags) & DIS_FMT_FLAGS_ADDR_COMMENT) \
779 || (fFlags & (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT)) ) \
780 && ((fFlags) & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT)) != (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT) \
781 && ( !((fFlags) & (DIS_FMT_FLAGS_BYTES_COMMENT | DIS_FMT_FLAGS_BYTES_BRACKETS)) \
782 || (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT)) ) \
783 )
784/** @} */
785
786DISDECL(size_t) DISFormatYasm( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
787DISDECL(size_t) DISFormatYasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
788DISDECL(size_t) DISFormatMasm( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
789DISDECL(size_t) DISFormatMasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
790DISDECL(size_t) DISFormatGas( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
791DISDECL(size_t) DISFormatGasEx( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
792
793/** @todo DISAnnotate(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, register reader, memory reader); */
794
795DISDECL(bool) DISFormatYasmIsOddEncoding(PDISCPUSTATE pCpu);
796
797
798RT_C_DECLS_END
799
800#endif
801
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