dis.h@ 41728

Last change on this file since 41728 was 41728, checked in by vboxsync, 13 years ago
DIS: register macro name adjustments - part two.
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1	/** @file
2	* DIS - The VirtualBox Disassembler.
3	*/
4
5	/*
6	* Copyright (C) 2006-2012 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.215389.xyz. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_dis_h
27	#define ___VBox_dis_h
28
29	#include <VBox/types.h>
30	#include <VBox/disopcode.h>
31	#include <iprt/assert.h>
32
33
34	RT_C_DECLS_BEGIN
35
36
37	/**
38	* CPU mode flags (DISCPUSTATE::mode).
39	*/
40	typedef enum DISCPUMODE
41	{
42	DISCPUMODE_INVALID = 0,
43	DISCPUMODE_16BIT,
44	DISCPUMODE_32BIT,
45	DISCPUMODE_64BIT,
46	/** hack forcing the size of the enum to 32-bits. */
47	DISCPUMODE_MAKE_32BIT_HACK = 0x7fffffff
48	} DISCPUMODE;
49
50	/** @name Prefix byte flags (DISCPUSTATE::prefix_rex).
51	* @{
52	*/
53	#define DISPREFIX_NONE UINT8_C(0x00)
54	/** non-default address size. */
55	#define DISPREFIX_ADDRSIZE UINT8_C(0x01)
56	/** non-default operand size. */
57	#define DISPREFIX_OPSIZE UINT8_C(0x02)
58	/** lock prefix. */
59	#define DISPREFIX_LOCK UINT8_C(0x04)
60	/** segment prefix. */
61	#define DISPREFIX_SEG UINT8_C(0x08)
62	/** rep(e) prefix (not a prefix, but we'll treat is as one). */
63	#define DISPREFIX_REP UINT8_C(0x10)
64	/** rep(e) prefix (not a prefix, but we'll treat is as one). */
65	#define DISPREFIX_REPNE UINT8_C(0x20)
66	/** REX prefix (64 bits) */
67	#define DISPREFIX_REX UINT8_C(0x40)
68	/** @} */
69
70	/** @name 64 bits prefix byte flags (DISCPUSTATE::prefix_rex).
71	* Requires VBox/disopcode.h.
72	* @{
73	*/
74	#define DISPREFIX_REX_OP_2_FLAGS(a) (a - OP_PARM_REX_START)
75	#define DISPREFIX_REX_FLAGS DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX)
76	#define DISPREFIX_REX_FLAGS_B DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_B)
77	#define DISPREFIX_REX_FLAGS_X DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_X)
78	#define DISPREFIX_REX_FLAGS_XB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_XB)
79	#define DISPREFIX_REX_FLAGS_R DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_R)
80	#define DISPREFIX_REX_FLAGS_RB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RB)
81	#define DISPREFIX_REX_FLAGS_RX DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RX)
82	#define DISPREFIX_REX_FLAGS_RXB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RXB)
83	#define DISPREFIX_REX_FLAGS_W DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_W)
84	#define DISPREFIX_REX_FLAGS_WB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WB)
85	#define DISPREFIX_REX_FLAGS_WX DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WX)
86	#define DISPREFIX_REX_FLAGS_WXB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WXB)
87	#define DISPREFIX_REX_FLAGS_WR DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WR)
88	#define DISPREFIX_REX_FLAGS_WRB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRB)
89	#define DISPREFIX_REX_FLAGS_WRX DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRX)
90	#define DISPREFIX_REX_FLAGS_WRXB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRXB)
91	/** @} */
92
93	/** @name Operand type.
94	* @{
95	*/
96	#define DISOPTYPE_INVALID RT_BIT_32(0)
97	#define DISOPTYPE_HARMLESS RT_BIT_32(1)
98	#define DISOPTYPE_CONTROLFLOW RT_BIT_32(2)
99	#define DISOPTYPE_POTENTIALLY_DANGEROUS RT_BIT_32(3)
100	#define DISOPTYPE_DANGEROUS RT_BIT_32(4)
101	#define DISOPTYPE_PORTIO RT_BIT_32(5)
102	#define DISOPTYPE_PRIVILEGED RT_BIT_32(6)
103	#define DISOPTYPE_PRIVILEGED_NOTRAP RT_BIT_32(7)
104	#define DISOPTYPE_UNCOND_CONTROLFLOW RT_BIT_32(8)
105	#define DISOPTYPE_RELATIVE_CONTROLFLOW RT_BIT_32(9)
106	#define DISOPTYPE_COND_CONTROLFLOW RT_BIT_32(10)
107	#define DISOPTYPE_INTERRUPT RT_BIT_32(11)
108	#define DISOPTYPE_ILLEGAL RT_BIT_32(12)
109	#define DISOPTYPE_RRM_DANGEROUS RT_BIT_32(14) /*< Some additional dangerous ones when recompiling raw r0. /
110	#define DISOPTYPE_RRM_DANGEROUS_16 RT_BIT_32(15) /*< Some additional dangerous ones when recompiling 16-bit raw r0. /
111	#define DISOPTYPE_RRM_MASK (DISOPTYPE_RRM_DANGEROUS \| DISOPTYPE_RRM_DANGEROUS_16)
112	#define DISOPTYPE_INHIBIT_IRQS RT_BIT_32(16) /*< Will or can inhibit irqs (sti, pop ss, mov ss) /
113	#define DISOPTYPE_PORTIO_READ RT_BIT_32(17)
114	#define DISOPTYPE_PORTIO_WRITE RT_BIT_32(18)
115	#define DISOPTYPE_INVALID_64 RT_BIT_32(19) /*< Invalid in 64 bits mode /
116	#define DISOPTYPE_ONLY_64 RT_BIT_32(20) /*< Only valid in 64 bits mode /
117	#define DISOPTYPE_DEFAULT_64_OP_SIZE RT_BIT_32(21) /*< Default 64 bits operand size /
118	#define DISOPTYPE_FORCED_64_OP_SIZE RT_BIT_32(22) /*< Forced 64 bits operand size; regardless of prefix bytes /
119	#define DISOPTYPE_REXB_EXTENDS_OPREG RT_BIT_32(23) /*< REX.B extends the register field in the opcode byte /
120	#define DISOPTYPE_MOD_FIXED_11 RT_BIT_32(24) /*< modrm.mod is always 11b /
121	#define DISOPTYPE_FORCED_32_OP_SIZE_X86 RT_BIT_32(25) /*< Forced 32 bits operand size; regardless of prefix bytes (only in 16 & 32 bits mode!) /
122	#define DISOPTYPE_ALL UINT32_C(0xffffffff)
123	/** @} */
124
125	/** @name Parameter usage flags.
126	* @{
127	*/
128	#define DISUSE_BASE RT_BIT_64(0)
129	#define DISUSE_INDEX RT_BIT_64(1)
130	#define DISUSE_SCALE RT_BIT_64(2)
131	#define DISUSE_REG_GEN8 RT_BIT_64(3)
132	#define DISUSE_REG_GEN16 RT_BIT_64(4)
133	#define DISUSE_REG_GEN32 RT_BIT_64(5)
134	#define DISUSE_REG_GEN64 RT_BIT_64(6)
135	#define DISUSE_REG_FP RT_BIT_64(7)
136	#define DISUSE_REG_MMX RT_BIT_64(8)
137	#define DISUSE_REG_XMM RT_BIT_64(9)
138	#define DISUSE_REG_CR RT_BIT_64(10)
139	#define DISUSE_REG_DBG RT_BIT_64(11)
140	#define DISUSE_REG_SEG RT_BIT_64(12)
141	#define DISUSE_REG_TEST RT_BIT_64(13)
142	#define DISUSE_DISPLACEMENT8 RT_BIT_64(14)
143	#define DISUSE_DISPLACEMENT16 RT_BIT_64(15)
144	#define DISUSE_DISPLACEMENT32 RT_BIT_64(16)
145	#define DISUSE_DISPLACEMENT64 RT_BIT_64(17)
146	#define DISUSE_RIPDISPLACEMENT32 RT_BIT_64(18)
147	#define DISUSE_IMMEDIATE8 RT_BIT_64(19)
148	#define DISUSE_IMMEDIATE8_REL RT_BIT_64(20)
149	#define DISUSE_IMMEDIATE16 RT_BIT_64(21)
150	#define DISUSE_IMMEDIATE16_REL RT_BIT_64(22)
151	#define DISUSE_IMMEDIATE32 RT_BIT_64(23)
152	#define DISUSE_IMMEDIATE32_REL RT_BIT_64(24)
153	#define DISUSE_IMMEDIATE64 RT_BIT_64(25)
154	#define DISUSE_IMMEDIATE64_REL RT_BIT_64(26)
155	#define DISUSE_IMMEDIATE_ADDR_0_32 RT_BIT_64(27)
156	#define DISUSE_IMMEDIATE_ADDR_16_32 RT_BIT_64(28)
157	#define DISUSE_IMMEDIATE_ADDR_0_16 RT_BIT_64(29)
158	#define DISUSE_IMMEDIATE_ADDR_16_16 RT_BIT_64(30)
159	/** DS:ESI */
160	#define DISUSE_POINTER_DS_BASED RT_BIT_64(31)
161	/** ES:EDI */
162	#define DISUSE_POINTER_ES_BASED RT_BIT_64(32)
163	#define DISUSE_IMMEDIATE16_SX8 RT_BIT_64(33)
164	#define DISUSE_IMMEDIATE32_SX8 RT_BIT_64(34)
165	#define DISUSE_IMMEDIATE64_SX8 RT_BIT_64(36)
166
167	/** Mask of immediate use flags. */
168	#define DISUSE_IMMEDIATE ( DISUSE_IMMEDIATE8 \
169	\| DISUSE_IMMEDIATE16 \
170	\| DISUSE_IMMEDIATE32 \
171	\| DISUSE_IMMEDIATE64 \
172	\| DISUSE_IMMEDIATE8_REL \
173	\| DISUSE_IMMEDIATE16_REL \
174	\| DISUSE_IMMEDIATE32_REL \
175	\| DISUSE_IMMEDIATE64_REL \
176	\| DISUSE_IMMEDIATE_ADDR_0_32 \
177	\| DISUSE_IMMEDIATE_ADDR_16_32 \
178	\| DISUSE_IMMEDIATE_ADDR_0_16 \
179	\| DISUSE_IMMEDIATE_ADDR_16_16 \
180	\| DISUSE_IMMEDIATE16_SX8 \
181	\| DISUSE_IMMEDIATE32_SX8 \
182	\| DISUSE_IMMEDIATE64_SX8)
183	/** Check if the use flags indicates an effective address. */
184	#define DISUSE_IS_EFFECTIVE_ADDR(a_fUseFlags) (!!( (a_fUseFlags) \
185	& ( DISUSE_BASE \
186	\| DISUSE_INDEX \
187	\| DISUSE_DISPLACEMENT32 \
188	\| DISUSE_DISPLACEMENT64 \
189	\| DISUSE_DISPLACEMENT16 \
190	\| DISUSE_DISPLACEMENT8 \
191	\| DISUSE_RIPDISPLACEMENT32) ))
192	/** @} */
193
194	/** @name 64-bit general register indexes.
195	* This matches the AMD64 register encoding. It is found used in
196	* DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen.
197	* @note Safe to assume same values as the 16-bit and 32-bit general registers.
198	* @{
199	*/
200	#define DISGREG_RAX UINT8_C(0)
201	#define DISGREG_RCX UINT8_C(1)
202	#define DISGREG_RDX UINT8_C(2)
203	#define DISGREG_RBX UINT8_C(3)
204	#define DISGREG_RSP UINT8_C(4)
205	#define DISGREG_RBP UINT8_C(5)
206	#define DISGREG_RSI UINT8_C(6)
207	#define DISGREG_RDI UINT8_C(7)
208	#define DISGREG_R8 UINT8_C(8)
209	#define DISGREG_R9 UINT8_C(9)
210	#define DISGREG_R10 UINT8_C(10)
211	#define DISGREG_R11 UINT8_C(11)
212	#define DISGREG_R12 UINT8_C(12)
213	#define DISGREG_R13 UINT8_C(13)
214	#define DISGREG_R14 UINT8_C(14)
215	#define DISGREG_R15 UINT8_C(15)
216	/** @} */
217
218	/** @name 32-bit general register indexes.
219	* This matches the AMD64 register encoding. It is found used in
220	* DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen.
221	* @note Safe to assume same values as the 16-bit and 64-bit general registers.
222	* @{
223	*/
224	#define DISGREG_EAX UINT8_C(0)
225	#define DISGREG_ECX UINT8_C(1)
226	#define DISGREG_EDX UINT8_C(2)
227	#define DISGREG_EBX UINT8_C(3)
228	#define DISGREG_ESP UINT8_C(4)
229	#define DISGREG_EBP UINT8_C(5)
230	#define DISGREG_ESI UINT8_C(6)
231	#define DISGREG_EDI UINT8_C(7)
232	#define DISGREG_R8D UINT8_C(8)
233	#define DISGREG_R9D UINT8_C(9)
234	#define DISGREG_R10D UINT8_C(10)
235	#define DISGREG_R11D UINT8_C(11)
236	#define DISGREG_R12D UINT8_C(12)
237	#define DISGREG_R13D UINT8_C(13)
238	#define DISGREG_R14D UINT8_C(14)
239	#define DISGREG_R15D UINT8_C(15)
240	/** @} */
241
242	/** @name 16-bit general register indexes.
243	* This matches the AMD64 register encoding. It is found used in
244	* DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen.
245	* @note Safe to assume same values as the 32-bit and 64-bit general registers.
246	* @{
247	*/
248	#define DISGREG_AX UINT8_C(0)
249	#define DISGREG_CX UINT8_C(1)
250	#define DISGREG_DX UINT8_C(2)
251	#define DISGREG_BX UINT8_C(3)
252	#define DISGREG_SP UINT8_C(4)
253	#define DISGREG_BP UINT8_C(5)
254	#define DISGREG_SI UINT8_C(6)
255	#define DISGREG_DI UINT8_C(7)
256	#define DISGREG_R8W UINT8_C(8)
257	#define DISGREG_R9W UINT8_C(9)
258	#define DISGREG_R10W UINT8_C(10)
259	#define DISGREG_R11W UINT8_C(11)
260	#define DISGREG_R12W UINT8_C(12)
261	#define DISGREG_R13W UINT8_C(13)
262	#define DISGREG_R14W UINT8_C(14)
263	#define DISGREG_R15W UINT8_C(15)
264	/** @} */
265
266	/** @name 8-bit general register indexes.
267	* This mostly (?) matches the AMD64 register encoding. It is found used in
268	* DISOPPARAM::base.reg_gen and DISOPPARAM::index.reg_gen.
269	* @{
270	*/
271	#define DISGREG_AL UINT8_C(0)
272	#define DISGREG_CL UINT8_C(1)
273	#define DISGREG_DL UINT8_C(2)
274	#define DISGREG_BL UINT8_C(3)
275	#define DISGREG_AH UINT8_C(4)
276	#define DISGREG_CH UINT8_C(5)
277	#define DISGREG_DH UINT8_C(6)
278	#define DISGREG_BH UINT8_C(7)
279	#define DISGREG_R8B UINT8_C(8)
280	#define DISGREG_R9B UINT8_C(9)
281	#define DISGREG_R10B UINT8_C(10)
282	#define DISGREG_R11B UINT8_C(11)
283	#define DISGREG_R12B UINT8_C(12)
284	#define DISGREG_R13B UINT8_C(13)
285	#define DISGREG_R14B UINT8_C(14)
286	#define DISGREG_R15B UINT8_C(15)
287	#define DISGREG_SPL UINT8_C(16)
288	#define DISGREG_BPL UINT8_C(17)
289	#define DISGREG_SIL UINT8_C(18)
290	#define DISGREG_DIL UINT8_C(19)
291	/** @} */
292
293	/** @name Segment registerindexes.
294	* This matches the AMD64 register encoding. It is found used in
295	* DISOPPARAM::base.reg_seg.
296	* @{
297	*/
298	typedef enum
299	{
300	DISSELREG_ES = 0,
301	DISSELREG_CS = 1,
302	DISSELREG_SS = 2,
303	DISSELREG_DS = 3,
304	DISSELREG_FS = 4,
305	DISSELREG_GS = 5,
306	/** The usual 32-bit paranoia. */
307	DIS_SEGREG_32BIT_HACK = 0x7fffffff
308	} DISSELREG;
309	/** @} */
310
311	/** @name FPU register indexes.
312	* This matches the AMD64 register encoding. It is found used in
313	* DISOPPARAM::base.reg_fp.
314	* @{
315	*/
316	#define DISFPREG_ST0 UINT8_C(0)
317	#define DISFPREG_ST1 UINT8_C(1)
318	#define DISFPREG_ST2 UINT8_C(2)
319	#define DISFPREG_ST3 UINT8_C(3)
320	#define DISFPREG_ST4 UINT8_C(4)
321	#define DISFPREG_ST5 UINT8_C(5)
322	#define DISFPREG_ST6 UINT8_C(6)
323	#define DISFPREG_ST7 UINT8_C(7)
324	/** @} */
325
326	/** @name Control register indexes.
327	* This matches the AMD64 register encoding. It is found used in
328	* DISOPPARAM::base.reg_ctrl.
329	* @{
330	*/
331	#define DISCREG_CR0 UINT8_C(0)
332	#define DISCREG_CR1 UINT8_C(1)
333	#define DISCREG_CR2 UINT8_C(2)
334	#define DISCREG_CR3 UINT8_C(3)
335	#define DISCREG_CR4 UINT8_C(4)
336	#define DISCREG_CR8 UINT8_C(8)
337	/** @} */
338
339	/** @name Debug register indexes.
340	* This matches the AMD64 register encoding. It is found used in
341	* DISOPPARAM::base.reg_dbg.
342	* @{
343	*/
344	#define DISDREG_DR0 UINT8_C(0)
345	#define DISDREG_DR1 UINT8_C(1)
346	#define DISDREG_DR2 UINT8_C(2)
347	#define DISDREG_DR3 UINT8_C(3)
348	#define DISDREG_DR4 UINT8_C(4)
349	#define DISDREG_DR5 UINT8_C(5)
350	#define DISDREG_DR6 UINT8_C(6)
351	#define DISDREG_DR7 UINT8_C(7)
352	/** @} */
353
354	/** @name MMX register indexes.
355	* This matches the AMD64 register encoding. It is found used in
356	* DISOPPARAM::base.reg_mmx.
357	* @{
358	*/
359	#define DISMREG_MMX0 UINT8_C(0)
360	#define DISMREG_MMX1 UINT8_C(1)
361	#define DISMREG_MMX2 UINT8_C(2)
362	#define DISMREG_MMX3 UINT8_C(3)
363	#define DISMREG_MMX4 UINT8_C(4)
364	#define DISMREG_MMX5 UINT8_C(5)
365	#define DISMREG_MMX6 UINT8_C(6)
366	#define DISMREG_MMX7 UINT8_C(7)
367	/** @} */
368
369	/** @name SSE register indexes.
370	* This matches the AMD64 register encoding. It is found used in
371	* DISOPPARAM::base.reg_xmm.
372	* @{
373	*/
374	#define DISXREG_XMM0 UINT8_C(0)
375	#define DISXREG_XMM1 UINT8_C(1)
376	#define DISXREG_XMM2 UINT8_C(2)
377	#define DISXREG_XMM3 UINT8_C(3)
378	#define DISXREG_XMM4 UINT8_C(4)
379	#define DISXREG_XMM5 UINT8_C(5)
380	#define DISXREG_XMM6 UINT8_C(6)
381	#define DISXREG_XMM7 UINT8_C(7)
382	/** @} */
383
384	/** Used by DISQueryParamVal & EMIQueryParamVal
385	* @{
386	*/
387	#define PARAM_VAL8 RT_BIT(0)
388	#define PARAM_VAL16 RT_BIT(1)
389	#define PARAM_VAL32 RT_BIT(2)
390	#define PARAM_VAL64 RT_BIT(3)
391	#define PARAM_VALFARPTR16 RT_BIT(4)
392	#define PARAM_VALFARPTR32 RT_BIT(5)
393
394	#define PARMTYPE_REGISTER 1
395	#define PARMTYPE_ADDRESS 2
396	#define PARMTYPE_IMMEDIATE 3
397
398	typedef struct
399	{
400	uint32_t type;
401	uint32_t size;
402	uint64_t flags;
403
404	union
405	{
406	uint8_t val8;
407	uint16_t val16;
408	uint32_t val32;
409	uint64_t val64;
410
411	struct
412	{
413	uint16_t sel;
414	uint32_t offset;
415	} farptr;
416	} val;
417
418	} OP_PARAMVAL;
419	/** Pointer to opcode parameter value. */
420	typedef OP_PARAMVAL *POP_PARAMVAL;
421
422	typedef enum
423	{
424	PARAM_DEST,
425	PARAM_SOURCE
426	} PARAM_TYPE;
427
428	/** @} */
429
430	/**
431	* Operand Parameter.
432	*/
433	typedef struct DISOPPARAM
434	{
435	uint64_t parval;
436	/** A combination of DISUSE_XXX. */
437	uint64_t fUse;
438	union
439	{
440	int64_t i64;
441	int32_t i32;
442	int32_t i16;
443	int32_t i8;
444	uint64_t u64;
445	uint32_t u32;
446	uint32_t u16;
447	uint32_t u8;
448	} uDisp;
449	int32_t param;
450
451	union
452	{
453	/** DISGREG_XXX. */
454	uint8_t reg_gen;
455	/** DISFPREG_XXX */
456	uint8_t reg_fp;
457	/** DISMREG_XXX. */
458	uint8_t reg_mmx;
459	/** DISXREG_XXX. */
460	uint8_t reg_xmm;
461	/** DISSELREG_XXX. */
462	uint8_t reg_seg;
463	/** TR0-TR7 (no defines for these). */
464	uint8_t reg_test;
465	/** DISCREG_XXX */
466	uint8_t reg_ctrl;
467	/** DISDREG_XXX */
468	uint8_t reg_dbg;
469	} base;
470	union
471	{
472	/** DISGREG_XXX. */
473	uint8_t reg_gen;
474	} index;
475
476	/** 2, 4 or 8. */
477	uint8_t scale;
478	/** Parameter size. */
479	uint8_t cb;
480	} DISOPPARAM;
481	AssertCompileSize(DISOPPARAM, 32);
482	/** Pointer to opcode parameter. */
483	typedef DISOPPARAM *PDISOPPARAM;
484	/** Pointer to opcode parameter. */
485	typedef const DISOPPARAM *PCOP_PARAMETER;
486
487
488	/** Pointer to const opcode. */
489	typedef const struct DISOPCODE *PCDISOPCODE;
490
491	/**
492	* Callback for reading opcode bytes.
493	*
494	* @param pDisState Pointer to the CPU state. The primary user argument
495	* can be retrived from DISCPUSTATE::apvUserData[0]. If
496	* more is required these can be passed in the
497	* subsequent slots.
498	* @param pbDst Pointer to output buffer.
499	* @param uSrcAddr The address to start reading at.
500	* @param cbToRead The number of bytes to read.
501	*/
502	typedef DECLCALLBACK(int) FNDISREADBYTES(PDISCPUSTATE pDisState, uint8_t *pbDst, RTUINTPTR uSrcAddr, uint32_t cbToRead);
503	/** Pointer to a opcode byte reader. */
504	typedef FNDISREADBYTES *PFNDISREADBYTES;
505
506	/** Parser callback.
507	* @remark no DECLCALLBACK() here because it's considered to be internal (really, I'm too lazy to update all the functions). */
508	typedef unsigned FNDISPARSE(RTUINTPTR pu8CodeBlock, PCDISOPCODE pOp, PDISOPPARAM pParam, PDISCPUSTATE pCpu);
509	typedef FNDISPARSE *PFNDISPARSE;
510	typedef PFNDISPARSE const *PCPFNDISPARSE;
511
512	typedef struct DISCPUSTATE
513	{
514	/* Because of apvUserData[1] and apvUserData[2], put the less frequently
515	used bits at the top for now. (Might be better off in the middle?) */
516	DISOPPARAM param3;
517	DISOPPARAM param2;
518	DISOPPARAM param1;
519
520	/* off: 0x060 (96) */
521	/** ModRM fields. */
522	union
523	{
524	/** Bitfield view */
525	struct
526	{
527	unsigned Rm : 4;
528	unsigned Reg : 4;
529	unsigned Mod : 2;
530	} Bits;
531	/** unsigned view */
532	unsigned u;
533	} ModRM;
534	/** SIB fields. */
535	union
536	{
537	/** Bitfield view */
538	struct
539	{
540	unsigned Base : 4;
541	unsigned Index : 4;
542	unsigned Scale : 2;
543	} Bits;
544	/** unsigned view */
545	unsigned u;
546	} SIB;
547	int32_t i32SibDisp;
548
549	/* off: 0x06c (108) */
550	/** The CPU mode (DISCPUMODE). */
551	uint8_t mode;
552	/** The addressing mode (DISCPUMODE). */
553	uint8_t addrmode;
554	/** The operand mode (DISCPUMODE). */
555	uint8_t opmode;
556	/** Per instruction prefix settings. */
557	uint8_t prefix;
558	/* off: 0x070 (112) */
559	/** REX prefix value (64 bits only). */
560	uint8_t prefix_rex;
561	/** Segment prefix value (DISSELREG). */
562	uint8_t idxSegPrefix;
563	/** Last prefix byte (for SSE2 extension tables). */
564	uint8_t lastprefix;
565	/** First opcode byte of instruction. */
566	uint8_t opcode;
567	/* off: 0x074 (116) */
568	/** The size of the prefix bytes. */
569	uint8_t cbPrefix;
570	/** The instruction size. */
571	uint8_t opsize;
572	uint8_t abUnused[2];
573	/* off: 0x078 (120) */
574	/** Return code set by a worker function like the opcode bytes readers. */
575	int32_t rc;
576	/** Internal: instruction filter */
577	uint32_t fFilter;
578	/* off: 0x080 (128) */
579	/** Internal: pointer to disassembly function table */
580	PCPFNDISPARSE pfnDisasmFnTable;
581	#if ARCH_BITS == 32
582	uint32_t uPtrPadding1;
583	#endif
584	/** Pointer to the current instruction. */
585	PCDISOPCODE pCurInstr;
586	#if ARCH_BITS == 32
587	uint32_t uPtrPadding2;
588	#endif
589	/* off: 0x090 (144) */
590	/** The address of the instruction. */
591	RTUINTPTR uInstrAddr;
592	/* off: 0x098 (152) */
593	/** Optional read function */
594	PFNDISREADBYTES pfnReadBytes;
595	#if ARCH_BITS == 32
596	uint32_t uPadding3;
597	#endif
598	/* off: 0x0a0 (160) */
599	/** The instruction bytes. */
600	uint8_t abInstr[16];
601	/* off: 0x0b0 (176) */
602	/** User data slots for the read callback. The first entry is used for the
603	* pvUser argument, the rest are up for grabs.
604	* @remarks This must come last so that we can memset everything before this. */
605	void *apvUserData[3];
606	#if ARCH_BITS == 32
607	uint32_t auPadding4[3];
608	#endif
609	} DISCPUSTATE;
610
611
612	/**
613	* Opcode descriptor.
614	*/
615	typedef struct DISOPCODE
616	{
617	#ifndef DIS_CORE_ONLY
618	const char *pszOpcode;
619	#endif
620	uint8_t idxParse1;
621	uint8_t idxParse2;
622	uint8_t idxParse3;
623	uint8_t uUnused;
624	uint16_t opcode;
625	uint16_t param1;
626	uint16_t param2;
627	uint16_t param3;
628	uint32_t optype;
629	} DISOPCODE;
630
631
632	DISDECL(int) DISInstrToStr(void const *pvInstr, DISCPUMODE enmCpuMode,
633	PDISCPUSTATE pCpu, uint32_t pcbInstr, char pszOutput, size_t cbOutput);
634	DISDECL(int) DISInstrToStrWithReader(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, PFNDISREADBYTES pfnReadBytes, void *pvUser,
635	PDISCPUSTATE pCpu, uint32_t pcbInstr, char pszOutput, size_t cbOutput);
636	DISDECL(int) DISInstrToStrEx(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode,
637	PFNDISREADBYTES pfnReadBytes, void *pvUser, uint32_t uFilter,
638	PDISCPUSTATE pCpu, uint32_t pcbInstr, char pszOutput, size_t cbOutput);
639
640	DISDECL(int) DISInstr(void const pvInstr, DISCPUMODE enmCpuMode, PDISCPUSTATE pCpu, uint32_t pcbInstr);
641	DISDECL(int) DISInstrWithReader(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, PFNDISREADBYTES pfnReadBytes, void *pvUser,
642	PDISCPUSTATE pCpu, uint32_t *pcbInstr);
643	DISDECL(int) DISInstEx(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, uint32_t uFilter,
644	PFNDISREADBYTES pfnReadBytes, void *pvUser,
645	PDISCPUSTATE pCpu, uint32_t *pcbInstr);
646
647	DISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, PDISOPPARAM pParam);
648	DISDECL(DISSELREG) DISDetectSegReg(PDISCPUSTATE pCpu, PDISOPPARAM pParam);
649	DISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu);
650
651	DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, PDISOPPARAM pParam, POP_PARAMVAL pParamVal, PARAM_TYPE parmtype);
652	DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, PDISOPPARAM pParam, void *ppReg, size_t pcbSize);
653
654	DISDECL(int) DISFetchReg8(PCCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal);
655	DISDECL(int) DISFetchReg16(PCCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal);
656	DISDECL(int) DISFetchReg32(PCCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal);
657	DISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal);
658	DISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal);
659	DISDECL(int) DISFetchRegSegEx(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL pVal, PCPUMSELREGHID ppSelHidReg);
660	DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8);
661	DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg32, uint16_t val16);
662	DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32);
663	DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64);
664	DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DISSELREG sel, RTSEL val);
665	DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg);
666	DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg);
667	DISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg);
668	DISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg);
669
670
671	/**
672	* Try resolve an address into a symbol name.
673	*
674	* For use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
675	*
676	* @returns VBox status code.
677	* @retval VINF_SUCCESS on success, pszBuf contains the full symbol name.
678	* @retval VINF_BUFFER_OVERFLOW if pszBuf is too small the symbol name. The
679	* content of pszBuf is truncated and zero terminated.
680	* @retval VERR_SYMBOL_NOT_FOUND if no matching symbol was found for the address.
681	*
682	* @param pCpu Pointer to the disassembler CPU state.
683	* @param u32Sel The selector value. Use DIS_FMT_SEL_IS_REG, DIS_FMT_SEL_GET_VALUE,
684	* DIS_FMT_SEL_GET_REG to access this.
685	* @param uAddress The segment address.
686	* @param pszBuf Where to store the symbol name
687	* @param cchBuf The size of the buffer.
688	* @param poff If not a perfect match, then this is where the offset from the return
689	* symbol to the specified address is returned.
690	* @param pvUser The user argument.
691	*/
692	typedef DECLCALLBACK(int) FNDISGETSYMBOL(PCDISCPUSTATE pCpu, uint32_t u32Sel, RTUINTPTR uAddress, char pszBuf, size_t cchBuf, RTINTPTR poff, void *pvUser);
693	/** Pointer to a FNDISGETSYMBOL(). */
694	typedef FNDISGETSYMBOL *PFNDISGETSYMBOL;
695
696	/**
697	* Checks if the FNDISGETSYMBOL argument u32Sel is a register or not.
698	*/
699	#define DIS_FMT_SEL_IS_REG(u32Sel) ( !!((u32Sel) & RT_BIT(31)) )
700
701	/**
702	* Extracts the selector value from the FNDISGETSYMBOL argument u32Sel.
703	* @returns Selector value.
704	*/
705	#define DIS_FMT_SEL_GET_VALUE(u32Sel) ( (RTSEL)(u32Sel) )
706
707	/**
708	* Extracts the register number from the FNDISGETSYMBOL argument u32Sel.
709	* @returns USE_REG_CS, USE_REG_SS, USE_REG_DS, USE_REG_ES, USE_REG_FS or USE_REG_FS.
710	*/
711	#define DIS_FMT_SEL_GET_REG(u32Sel) ( ((u32Sel) >> 16) & 0xf )
712
713	/** @internal */
714	#define DIS_FMT_SEL_FROM_REG(uReg) ( ((uReg) << 16) \| RT_BIT(31) \| 0xffff )
715	/** @internal */
716	#define DIS_FMT_SEL_FROM_VALUE(Sel) ( (Sel) & 0xffff )
717
718
719	/** @name Flags for use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
720	* @{
721	*/
722	/** Put the address to the right. */
723	#define DIS_FMT_FLAGS_ADDR_RIGHT RT_BIT_32(0)
724	/** Put the address to the left. */
725	#define DIS_FMT_FLAGS_ADDR_LEFT RT_BIT_32(1)
726	/** Put the address in comments.
727	* For some assemblers this implies placing it to the right. */
728	#define DIS_FMT_FLAGS_ADDR_COMMENT RT_BIT_32(2)
729	/** Put the instruction bytes to the right of the disassembly. */
730	#define DIS_FMT_FLAGS_BYTES_RIGHT RT_BIT_32(3)
731	/** Put the instruction bytes to the left of the disassembly. */
732	#define DIS_FMT_FLAGS_BYTES_LEFT RT_BIT_32(4)
733	/** Put the instruction bytes in comments.
734	* For some assemblers this implies placing the bytes to the right. */
735	#define DIS_FMT_FLAGS_BYTES_COMMENT RT_BIT_32(5)
736	/** Put the bytes in square brackets. */
737	#define DIS_FMT_FLAGS_BYTES_BRACKETS RT_BIT_32(6)
738	/** Put spaces between the bytes. */
739	#define DIS_FMT_FLAGS_BYTES_SPACED RT_BIT_32(7)
740	/** Display the relative +/- offset of branch instructions that uses relative addresses,
741	* and put the target address in parenthesis. */
742	#define DIS_FMT_FLAGS_RELATIVE_BRANCH RT_BIT_32(8)
743	/** Strict assembly. The assembly should, when ever possible, make the
744	* assembler reproduce the exact same binary. (Refers to the yasm
745	* strict keyword.) */
746	#define DIS_FMT_FLAGS_STRICT RT_BIT_32(9)
747	/** Checks if the given flags are a valid combination. */
748	#define DIS_FMT_FLAGS_IS_VALID(fFlags) \
749	( !((fFlags) & ~UINT32_C(0x000003ff)) \
750	&& ((fFlags) & (DIS_FMT_FLAGS_ADDR_RIGHT \| DIS_FMT_FLAGS_ADDR_LEFT)) != (DIS_FMT_FLAGS_ADDR_RIGHT \| DIS_FMT_FLAGS_ADDR_LEFT) \
751	&& ( !((fFlags) & DIS_FMT_FLAGS_ADDR_COMMENT) \
752	\|\| (fFlags & (DIS_FMT_FLAGS_ADDR_RIGHT \| DIS_FMT_FLAGS_ADDR_LEFT)) ) \
753	&& ((fFlags) & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_BYTES_LEFT)) != (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_BYTES_LEFT) \
754	&& ( !((fFlags) & (DIS_FMT_FLAGS_BYTES_COMMENT \| DIS_FMT_FLAGS_BYTES_BRACKETS)) \
755	\|\| (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_BYTES_LEFT)) ) \
756	)
757	/** @} */
758
759	DISDECL(size_t) DISFormatYasm( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
760	DISDECL(size_t) DISFormatYasmEx(PCDISCPUSTATE pCpu, char pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void pvUser);
761	DISDECL(size_t) DISFormatMasm( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
762	DISDECL(size_t) DISFormatMasmEx(PCDISCPUSTATE pCpu, char pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void pvUser);
763	DISDECL(size_t) DISFormatGas( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
764	DISDECL(size_t) DISFormatGasEx( PCDISCPUSTATE pCpu, char pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void pvUser);
765
766	/** @todo DISAnnotate(PCDISCPUSTATE pCpu, char pszBuf, size_t cchBuf, register reader, memory reader); /
767
768	DISDECL(bool) DISFormatYasmIsOddEncoding(PDISCPUSTATE pCpu);
769
770
771	RT_C_DECLS_END
772
773	#endif
774

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source: vbox/trunk/include/VBox/dis.h@ 41728

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